Semiconductor device manufacturing methods

Abstract

This application discloses a method for manufacturing a semiconductor device, comprising: forming a shallow trench isolation structure on a substrate; forming a well of a first conductivity type in a first device region and a second sub-region of the substrate; forming a well of a second conductivity type in a second device region and a first sub-region of the substrate; forming a first gate dielectric layer on the first device region, the first sub-region, the second sub-region, and the second device region of the substrate; forming a channel threshold adjustment region for adjusting a threshold voltage in the wells of the first and second sub-regions, wherein during the formation of the channel threshold adjustment region, the first gate dielectric layer on the first and second sub-regions is removed and the substrate tops of the first and second sub-regions are lower than the substrate tops of the first and second device regions; forming a CMOS gate dielectric layer on the first and second sub-regions of the substrate; forming a second gate dielectric layer on the second device region of the substrate; and forming a gate structure, a source region, and a drain region. This application can flexibly adapt to the precise requirements of medium-voltage applications.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to methods for manufacturing semiconductor devices. Background Technology

[0002] In the field of semiconductor device manufacturing, to improve the fabrication efficiency, integration level, and circuit functionality of semiconductor devices, different types of devices are often integrated onto the same wafer for fabrication. Taking metal-oxide-semiconductor field-effect transistors (MOSFETs, referred to as "MOS" in this application) as an example, chips with different functional circuits can be formed by fabricating MOS devices with different operating voltages on the same substrate.

[0003] In related technologies, dual-gate (DG) processes are commonly used to integrate high-voltage and low-voltage MOS devices. However, this approach cannot meet the needs of medium-voltage applications. If the integration of medium-voltage MOS devices is required, an independent well injection process and a complete gate fabrication process must be introduced, and multiple photolithography masks must be redesigned, significantly increasing process complexity and production costs.

[0004] To reduce production costs and simplify process complexity, related technologies integrate low-voltage MOS devices, complementary metal-oxide-semiconductor (CMOS) devices, and high-voltage MOS devices based on dual-gate processes. The CMOS devices, including N-type and P-type MOS devices, directly reuse the well injection parameters of the corresponding high-voltage or low-voltage MOS devices, and add a well injection step to adjust the threshold voltage, thus meeting the application requirements for low, medium, and high operating voltages. However, this method is limited by the inherent depth and concentration parameters of the well injection in low-voltage and high-voltage MOS devices. Key parameters such as the threshold voltage and saturation current of the CMOS devices are locked to a fixed value, making it difficult to flexibly adapt to the precise requirements of medium-voltage applications and prone to reliability issues or performance redundancy. Summary of the Invention

[0005] This application provides a method for manufacturing a semiconductor device that is not limited by the well implantation depth and concentration of the first MOS device and the second MOS device. It allows for flexible adjustment of key parameters such as the threshold voltage and saturation current of the CMOS device, and flexibly adapts to the precise voltage application requirements within the operating voltage range of the first MOS device and the second MOS device.

[0006] In view of this, this application provides a method for manufacturing a semiconductor device, comprising the following steps:

[0007] S1, a shallow trench isolation structure is formed on the substrate, the shallow trench isolation structure separating a first device region, a CMOS device region, and a second device region, the first device region being the formation region of a first MOS device on the substrate, the CMOS device region being the formation region of a CMOS device on the substrate, which includes a first sub-region and a second sub-region, the second device region being the formation region of a second MOS device on the substrate, the operating voltage of the first MOS device being greater than the operating voltage of the CMOS device, and the operating voltage of the CMOS device being greater than the operating voltage of the second MOS device;

[0008] S2, a first conductivity type well is formed in the first device region and the second sub-region of the substrate;

[0009] S3, a second conductivity type well is formed in the second device region and the first sub-region of the substrate;

[0010] S4, a first gate dielectric layer is formed on the first device region, the first sub-region, the second sub-region, and the second device region of the substrate;

[0011] S5, a channel threshold adjustment region for adjusting the threshold voltage is formed in the well of the first sub-region and the second sub-region; during the formation of the channel threshold adjustment region, the first gate dielectric layer on the first sub-region and the second sub-region is removed and the top of the substrate of the first sub-region and the second sub-region is lower than the top of the substrate of the first device region and the second device region.

[0012] S6, a CMOS gate dielectric layer is formed on the first and second sub-regions of the substrate;

[0013] S7, Remove the first gate dielectric layer on the second device region of the substrate;

[0014] S8, a second gate dielectric layer is formed on the second device region of the substrate;

[0015] S9, forming the gate structure of the first MOS device, the CMOS device and the second MOS device;

[0016] S10, forming the source and drain regions of the first MOS device, the CMOS device, and the second MOS device.

[0017] Optionally, the method for forming the channel threshold adjustment region includes:

[0018] S51 uses a patterned mask for photolithography to form a photoresist pattern on the substrate that exposes the first gate dielectric layer on the first sub-region and the second sub-region.

[0019] S52 uses the photoresist pattern as a mask, the exposed first gate dielectric layer as an ion implantation buffer layer, and performs impurity ion implantation on the substrate to form an initial channel threshold adjustment region in the first and second sub-regions.

[0020] S53, remove the first gate dielectric layer on the first sub-region and the second sub-region;

[0021] S54, remove a portion of the substrate from the first sub-region and the second sub-region. The thickness of the substrate removed is less than the depth of the initial channel threshold adjustment region (301). The channel threshold adjustment region is formed within the well of the first sub-region and the second sub-region. After the channel threshold adjustment region is formed, the photoresist pattern is removed.

[0022] Optionally, the thickness of the substrate removed is greater than the thickness of the CMOS gate dielectric layer.

[0023] Optionally, the impurity ion is of type P, the energy range of the impurity ion implantation is 5 keV-100 keV, and the implantation dose range is 1.0 × 10⁻⁶. 11 -5.0×10 13 cm -2 The injection angle is 0°-45°.

[0024] Optionally, the first conductivity type is N-type, and the second conductivity type ion is P-type.

[0025] Optionally, the first conductivity type is P-type and the second conductivity type is N-type.

[0026] Optionally, the thickness of the CMOS gate dielectric layer is less than the thickness of the first gate dielectric layer, and the thickness of the second gate dielectric layer is less than the thickness of the CMOS gate dielectric layer.

[0027] Optionally, the method for forming the gate structure includes: forming a gate structure on a first device region, a first sub-region, a second sub-region, and a second device region of a substrate, and after the gate structure is formed, removing the first gate dielectric layer, the CMOS gate dielectric layer, and the second gate dielectric layer outside the gate structure formation region.

[0028] Optionally, it further includes forming a sidewall on the periphery of the gate structure.

[0029] Optionally, the sidewalls include a first layer of sidewalls and a second layer of sidewalls from the outside to the inside.

[0030] Optionally, the method for forming the source and drain regions includes: forming source and drain regions of a second conductivity type in a first device region and a second sub-region of the substrate; and forming source and drain regions of a first conductivity type in a second device region and a second sub-region of the substrate.

[0031] Optionally, it further includes: forming drift regions for the first MOS device, the CMOS device, and the second MOS device.

[0032] Optionally, the method for forming the drift region includes: forming a drift region of a second conductivity type in a first device region and a second sub-region of the substrate; and forming a drift region of a first conductivity type in the second device region and the first sub-region of the substrate.

[0033] The technical solution of this application has at least the following advantages:

[0034] (1) When fabricating a first device, a CMOS device and a second device with different operating voltages on the same substrate, this application forms a first conductivity type well in the first device region and the second sub-region of the substrate, and forms a second conductivity type well in the second device region and the first sub-region of the substrate. This allows the MOS device of the second conductivity type in the CMOS device to directly reuse the well injection parameters of the first device, and the MOS device of the first conductivity type in the CMOS device to directly reuse the well injection parameters of the second device. By forming a channel threshold adjustment region for adjusting the threshold voltage in the wells of the first sub-region and the second sub-region, and removing the first gate dielectric layer on the first sub-region and the second sub-region during the formation of the channel threshold adjustment region, and making the top of the substrate of the first sub-region and the second sub-region lower than the top of the substrate of the first device region and the second device region, the key parameters such as the threshold voltage and saturation current of the CMOS device can be flexibly adjusted without being limited by the well injection depth and concentration of the first MOS device and the second MOS device. This allows for flexible adaptation to the precise voltage application requirements within the operating voltage range of the first MOS device and the second MOS device.

[0035] (2) Based on the existing dual-gate process, this application can add a CMOS device with adjustable key parameters by adding only one pattern mask for forming the channel threshold adjustment region. There is no need to introduce an independent trap injection process and a complete gate fabrication process, which greatly reduces the process steps and production costs. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0037] Figure 1 This is a process flow diagram of a semiconductor device manufacturing method provided in an exemplary embodiment of this application;

[0038] Figure 2This is a schematic cross-sectional view of a semiconductor device manufacturing method provided in an exemplary embodiment of this application after the formation of a well;

[0039] Figure 3 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after the formation of the initial channel threshold adjustment region;

[0040] Figure 4 This is a schematic cross-sectional view of a semiconductor device manufacturing method provided in an exemplary embodiment of this application after forming a channel threshold adjustment region;

[0041] Figure 5 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after the gate structure has been formed;

[0042] Figure 6 This is a schematic cross-sectional view of a semiconductor device manufacturing method provided in an exemplary embodiment of this application after the drift region has been formed;

[0043] Figure 7 This is a schematic cross-sectional view of the semiconductor device manufacturing method provided in an exemplary embodiment of this application after the source and drain regions have been formed;

[0044] The numbers in the diagram represent:

[0045] 100. Substrate;

[0046] 110. First device region; 111. Well of first conductivity type; 112. Drift region of second conductivity type; 113. Source / drain region of second conductivity type;

[0047] 120. CMOS device area; 121. First sub-region; 122. Second sub-region; 123. Initial channel threshold adjustment region; 124. Channel threshold adjustment region;

[0048] 130. Second device region; 131. Well of second conductivity type; 132. Drift region of first conductivity type; 133. Source / drain region of first conductivity type;

[0049] 140. Shallow trench isolation structure;

[0050] 210, First gate dielectric layer; 220, CMOS gate dielectric layer; 230, Second gate dielectric layer;

[0051] 300. Gate structure;

[0052] 400, Side wall; 410, First side wall; 420, Second side wall. Detailed Implementation

[0053] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0054] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0055] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0056] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0057] The following is combined with Figures 1 to 7 This describes an embodiment of the present application.

[0058] refer to Figure 1 The illustration shows an embodiment of this application, providing a method for manufacturing a semiconductor device, comprising:

[0059] S1, a shallow trench isolation structure 140 is formed on the substrate 100. The shallow trench isolation structure 140 separates a first device region 110, a CMOS device region 120, and a second device region 130. The first device region 110 is the formation area of ​​a first MOS device on the substrate 100. The CMOS device region 120 is the formation area of ​​a CMOS device on the substrate 100, which includes a first sub-region 121 and a second sub-region 122. The second device region 130 is the formation area of ​​a second MOS device on the substrate 100. The operating voltage of the first MOS device is greater than the operating voltage of the CMOS device, and the operating voltage of the CMOS device is greater than the operating voltage of the second MOS device.

[0060] For example, substrate 100 can be silicon substrate 100, germanium (Ge) substrate 100, gallium arsenide (GaAs) substrate 100, or other materials suitable for semiconductor device fabrication. The shallow trench isolation structure 140 formed on substrate 100 is typically achieved using a shallow trench isolation (STI) process. The first MOS device can be a high-voltage (HV) MOS device, the CMOS device can be a medium-voltage (MV) MOS device, and the second MOS device can be a low-voltage (LV) MOS device.

[0061] S2, a first conductivity type well 111 is formed in the first device region 110 and the second sub-region 122 of the substrate 100.

[0062] For example, forming a well 111 of a first conductivity type within the first device region 110 and the second sub-region 122 of the substrate 100 can be achieved through a combination of thermal oxidation, photolithography, etching, and ion implantation. For instance, a pad oxide layer is first formed on the substrate 100 using a thermal oxidation process, followed by a photoresist patterning process. Then, dry etching is used to etch away the portion of the pad oxide layer not protected by the photoresist, exposing the first device region 110 and the second sub-region 122 on the substrate 100 as ion implantation windows. Impurity ions of the first conductivity type are then implanted into the substrate 100, forming the well 111 of the first conductivity type within the first device region 110 and the second sub-region 122 of the substrate 100. After ion implantation, the pad oxide layer is typically removed using an etching process.

[0063] It should be noted that the first conductivity type can be either N-type or P-type.

[0064] For example, the impurity ion of the first conductivity type can be an N-type impurity ion, such as a phosphorus ion (P ion). + ), arsenic ions (As + ), antimony ions (Sb) +These can also be p-type impurity ions, such as boron ions and gallium ions (Ga). + Indium ions (In) + )wait.

[0065] S3, a second conductivity type well 131 is formed in the second device region 130 and the first sub-region 121 of the substrate 100.

[0066] For example, forming a trap 131 of a second conductivity type within the substrate 100 of the second device region 130 and the first sub-region 121 of the substrate 100 can also be achieved through a combination of thermal oxidation, photolithography, etching, and ion implantation. It should be noted that the second conductivity type can be P-type or N-type. When the first conductivity type is N-type, the second conductivity type ion is P-type; when the first conductivity type is P-type, the second conductivity type is N-type.

[0067] S4, a first gate dielectric layer 210 is formed on the first device region 110, the first sub-region 121, the second sub-region 122, and the second device region 130 of the substrate 100.

[0068] For example, a first gate dielectric layer 210 is typically grown on the first device region 110, the first sub-region 121, the second sub-region 122, and the second device region 130 of the substrate 100 using a thermal oxidation process.

[0069] S5, a channel threshold adjustment region 124 for adjusting the threshold voltage is formed in the well of the first sub-region 121 and the second sub-region 122. During the formation of the channel threshold adjustment region 124, the first gate dielectric layer 210 on the first sub-region 121 and the second sub-region 122 is removed and the top of the substrate 100 of the first sub-region 121 and the second sub-region 122 is lower than the top of the substrate 100 of the first device region 110 and the second device region 130.

[0070] In some embodiments, the method for forming the channel threshold adjustment region 124 includes:

[0071] S51, a photolithography is performed using a patterned mask to form a photoresist pattern on the substrate 100 that exposes the first gate dielectric layer on the first sub-region 121 and the second sub-region 122;

[0072] S52, using the photoresist pattern as a mask, the exposed first gate dielectric layer is used as an ion implantation buffer layer to implant impurity ions into the substrate 100, forming an initial channel threshold adjustment region 123 in the well of the first sub-region 121 and the second sub-region 122.

[0073] S53, remove the first gate dielectric layer 210 on the first sub-region 121 and the second sub-region 122;

[0074] S54, a portion of the substrate 100 in the first sub-region 121 and the second sub-region 122 is removed. The thickness of the substrate 100 removed is less than the depth of the initial channel threshold adjustment region 123. A channel threshold adjustment region 124 is formed in the well of the first sub-region 121 and the second sub-region 122. After the channel threshold adjustment region 124 is formed, the photoresist pattern is removed.

[0075] By implanting impurity ions into the substrate 100 to form an initial channel threshold adjustment region 123 and selectively removing portions of the substrate 100 in the first sub-region 121 and the second sub-region 122, it is beneficial to optimize the doping concentration of the channel threshold adjustment region 124. At the same time, it optimizes the height difference between the tops of the substrates 100 in the first sub-region 121 and the second sub-region 122 and the tops of the substrates 100 in the first device region 110 and the second device region 130. On the one hand, it is beneficial to flexibly adjust key parameters such as the threshold voltage and saturation current of the CMOS device, without being limited by the well implantation depth and concentration of the first MOS device and the second MOS device. It can flexibly adapt to the precise voltage application requirements within the operating voltage range of the first MOS device and the second MOS device. On the other hand, it is beneficial to reduce the parasitic capacitance between the CMOS device and the first MOS device and the second MOS device, reduce the switching loss of the semiconductor device, improve the switching speed of the device, and at the same time, it is beneficial to reduce the channel length modulation effect of the CMOS device, thereby improving the reliability and stability of the semiconductor.

[0076] For example, an etching process is typically used to remove the first gate dielectric layer and a portion of the substrate 100 on the first sub-region 121 and the second sub-region 122.

[0077] In some embodiments, the thickness of the substrate 100 removed in step S54 is greater than the thickness of the CMOS gate dielectric layer 220.

[0078] In some embodiments, the impurity ion type in step S52 is P-type, the energy range of impurity ion implantation is 5 keV-100 keV, and the implantation dose range is 1.0 × 10⁻⁶. 11 -5.0×10 13 The implantation angle is 0°-45°. By implanting P-type impurity ions into the substrate 100 to form an initial channel threshold adjustment region 123, the threshold voltage of the N-type MOS device in the CMOS device can be increased, while the threshold voltage of the P-type MOS device in the CMOS device can be decreased.

[0079] For example, the energy range of impurity ion implantation can be 5 keV, 10 keV, 20 keV, 50 keV, 70 keV, 100 keV, etc., and the implantation dose range can be 1.0 × 10⁻⁶. 11 2.0×1012 5.0×10 13 The injection angle can be 0°, 5°, 15°, 25°, 35°, 45°, etc.

[0080] S6, a CMOS gate dielectric layer 220 is formed on the first sub-region 121 and the second sub-region 122 of the substrate 100.

[0081] For example, a thermal oxidation process is typically used to form a CMOS gate dielectric layer 220 on a first sub-region 121 and a second sub-region 122 of a substrate 100.

[0082] In some embodiments, the thickness of the CMOS gate dielectric layer 220 is smaller than that of the first gate dielectric layer 210.

[0083] S7, remove the first gate dielectric layer 210 on the second device region 130 of the substrate 100.

[0084] For example, photolithography and etching processes are typically used to remove the first gate dielectric layer 210 on the second device region 130 of the substrate 100. For instance, a photoresist pattern is first formed on the substrate 100 by photolithography, exposing the first gate dielectric layer 210 on the second device region 130. Using the photoresist pattern as a mask, dry etching is performed, and the first gate dielectric layer 210 on the second device region 130 is removed.

[0085] S8, a second gate dielectric layer 230 is formed on the second device region 130 of the substrate 100.

[0086] For example, a second gate dielectric layer 230 is typically formed on the second device region 130 of the substrate 100 using a thermal oxidation process.

[0087] In some embodiments, the thickness of the second gate dielectric layer 230 is less than the thickness of the CMOS gate dielectric layer 220.

[0088] S9 forms the gate structure 300 of the first MOS device, the CMOS device, and the second MOS device.

[0089] In some embodiments, the method of forming the gate structure 300 includes: forming the gate structure 300 on the first device region 110, the first sub-region 121, the second sub-region 122, and the second device region 130 of the substrate 100; and after the gate structure 300 is formed, removing the first gate dielectric layer 210, the CMOS gate dielectric layer, and the second gate dielectric layer outside the forming region of the gate structure 300.

[0090] For example, the formation of the gate structure 300 on the first device region 110, the first sub-region 121, the second sub-region 122, and the second device region 130 of the substrate 100 can be achieved through a deposition-photolithography-etching combination process. For instance, a polysilicon layer is first deposited on the substrate 100 using a deposition process, followed by a photolithography process to form a photoresist pattern. The photoresist pattern protects the polysilicon in the target gate region. Then, dry etching is used to etch the polysilicon layer portion not protected by the photoresist pattern, thereby forming the gate structure 300. After the gate structure 300 is formed, the first gate dielectric layer 210, the CMOS gate dielectric layer, and the second gate dielectric layer outside the region where the gate structure 300 is formed can be removed by an etching process.

[0091] In some embodiments, after the gate structure 300 is formed, the method further includes forming a sidewall 400 on the periphery of the gate structure 300.

[0092] In some embodiments, the sidewall 400 includes a first sidewall 410 and a second sidewall 420 from the outside to the inside.

[0093] In some embodiments, after the gate structure 300 is formed, the method further includes: forming a drift region for the first MOS device, the CMOS device, and the second MOS device.

[0094] In some embodiments, the method of forming a drift region includes: forming a drift region 112 of a second conductivity type in a first device region 110 and a second sub-region 122 of a substrate 100; and forming a drift region 132 of a first conductivity type in a second device region 130 and a first sub-region 121 of the substrate 100.

[0095] For example, the formation of a drift region 112 of a second conductivity type in the first device region 110 and the second sub-region 122 of the substrate 100, and the formation of a drift region 132 of a first conductivity type in the second device region 130 and the first sub-region 121 of the substrate 100, can both be achieved using a selective light-doped ion implantation process.

[0096] S10 forms the source and drain regions of the first MOS device, the CMOS device, and the second MOS device.

[0097] In some embodiments, the method of forming source and drain regions includes: forming source and drain regions 113 of a second conductivity type in a first device region 110 and a second sub-region 122 of substrate 100; and forming source and drain regions 133 of a first conductivity type in a second device region 130 and a second sub-region 122 of substrate 100.

[0098] For example, forming a source and drain region of the second conductivity type in the first device region 110 and the second sub-region 122 of the substrate 100, and forming a source and drain region of the first conductivity type in the second device region 130 and the second sub-region 122 of the substrate 100, can both be achieved using a selective heavy doping source and drain implantation process.

[0099] Related technologies integrate low-voltage MOS devices, complementary metal-oxide-semiconductor (CMOS) devices, and high-voltage MOS devices based on dual-gate processes. The CMOS devices, including N-type and P-type MOS devices, directly reuse the well injection parameters of the corresponding high-voltage or low-voltage MOS devices, and add a well injection step to adjust the threshold voltage, thus meeting the application requirements for low, medium, and high operating voltages. However, this method is limited by the inherent depth and concentration parameters of the well injection in low-voltage and high-voltage MOS devices. Key parameters such as the threshold voltage and saturation current of the CMOS devices are locked to a fixed value, making it difficult to flexibly adapt to the precise requirements of medium-voltage applications and prone to insufficient reliability or performance redundancy.

[0100] This application, based on existing dual-gate technology, fabricates a first device, a CMOS device, and a second device with different operating voltages on the same substrate. By forming a first conductivity type well in the first device region and the second sub-region of the substrate, and forming a second conductivity type well in the substrate of the second device region and the first sub-region, the MOS device of the second conductivity type in the CMOS device can directly reuse the well injection parameters of the first device, and the MOS device of the first conductivity type in the CMOS device can directly reuse the well injection parameters of the second device. By forming a channel threshold adjustment region to adjust the threshold voltage in the wells of the first and second sub-regions, and by removing the first gate dielectric layer on the first and second sub-regions during the formation of the channel threshold adjustment region, and by ensuring that the top of the substrates of the first and second sub-regions is lower than the top of the substrates of the first and second device regions, key parameters such as the threshold voltage and saturation current of the CMOS device can be flexibly adjusted without being limited by the well injection depth and concentration of the first and second MOS devices. This allows for flexible adaptation to the precise voltage application requirements within the operating voltage range of the first and second MOS devices. Furthermore, this application adds only one patterned mask for forming the channel threshold adjustment region to the existing dual-gate process, thereby adding a CMOS device with adjustable key parameters. This eliminates the need for an independent trap implantation process and a complete gate fabrication process, significantly reducing process steps and production costs.

[0101] The technical effects of this application will be illustrated below with specific simulation test data.

[0102] To ensure the accuracy of the process simulation, the inventors first conducted a comparative verification between CMOS process simulation and actual testing. In the comparative verification, the NMOS device adopted a 3.3V process node with a gate oxide (GOX) + P-well (PW) + N-type lightly doped drain (NLDD) process scheme, while the PMOS device adopted a 3.3V process node with a GOX + N-well (NW) + P-type lightly doped drain (PLDD) process scheme. The manufacturing process and electrical performance of the CMOS device were simulated using TCAD (Technology Computer-Aided Design) software. The key parameters of the CMOS device, such as the threshold voltage and drain current, were simulated and tested, and compared with the actual silicon wafer test data. The results are shown in Table 1.

[0103] Table 1

[0104]

[0105] To verify the effectiveness of threshold voltage regulation in CMOS devices, the inventors, based on existing 5V process node MOS devices (first MOS devices) and 1.2V process node MOS devices (second MOS devices), used the manufacturing methods provided in Examples 1-5 and Comparative Examples 1-2. They simulated the manufacturing process and electrical performance of semiconductor devices under different process schemes using TCAD (Technology Computer-Aided Design) software, and conducted simulation tests on key parameters such as threshold voltage and drain current of CMOS devices. The results are shown in Tables 2 and 3.

[0106] Example 1

[0107] This embodiment provides a method for manufacturing a semiconductor device, including:

[0108] S1, a shallow trench isolation structure 140 is formed on the substrate 100. The shallow trench isolation structure 140 separates a first device region 110, a CMOS device region 120, and a second device region 130. The first device region 110 is the formation area of ​​a first MOS device on the substrate 100. The CMOS device region 120 is the formation area of ​​a CMOS device on the substrate 100, which includes a first sub-region 121 and a second sub-region 122. The second device region 130 is the formation area of ​​a second MOS device on the substrate 100. The operating voltage of the first MOS device is greater than the operating voltage of the CMOS device, and the operating voltage of the CMOS device is greater than the operating voltage of the second MOS device.

[0109] In this embodiment, a silicon substrate is used as the substrate, the first MOS device operates at 5V, the CMOS device operates at 3.3V, and the second MOS device operates at 1.2V.

[0110] S2, a first conductivity type well 111 is formed in the first device region 110 and the second sub-region 122 of the substrate 100.

[0111] In this embodiment, the first conductivity type well 111 is a P-well. The well injection parameters when forming the P-well in the first device region 110 and the second sub-region 122 of the substrate 100 are borrowed from the P-well injection parameters of the first MOS device process platform.

[0112] S3, a second conductivity type well 131 is formed in the second device region 130 and the first sub-region 121 of the substrate 100.

[0113] In this embodiment, the second conductivity type of well 131 is an N-well. The well injection parameters when forming the N-well in the second device region 130 and the first sub-region 121 of the substrate 100 are borrowed from the N-well injection parameters of the second MOS device process platform.

[0114] S4, a first gate dielectric layer 210 is formed on the first device region 110, the first sub-region 121, the second sub-region 122, and the second device region 130 of the substrate 100.

[0115] S5, a channel threshold adjustment region 124 for adjusting the threshold voltage is formed in the well of the first sub-region 121 and the second sub-region 122. During the formation of the channel threshold adjustment region 124, the first gate dielectric layer 210 on the first sub-region 121 and the second sub-region 122 is removed and the top of the substrate 100 of the first sub-region 121 and the second sub-region 122 is lower than the top of the substrate 100 of the first device region 110 and the second device region 130.

[0116] In this embodiment, the method for forming the channel threshold adjustment region 124 includes:

[0117] S51, a photolithography is performed using a patterned mask to form a photoresist pattern on the substrate 100 that exposes the first gate dielectric layer on the first sub-region 121 and the second sub-region 122;

[0118] S52, using the photoresist pattern as a mask, the exposed first gate dielectric layer is used as an ion implantation buffer layer to implant P-type impurity ions into the substrate 100, forming an initial channel threshold adjustment region 123 in the well of the first sub-region 121 and the second sub-region 122.

[0119] S53, remove the first gate dielectric layer 210 on the first sub-region 121 and the second sub-region 122;

[0120] S54, a portion of the substrate 100 in the first sub-region 121 and the second sub-region 122 is removed. The thickness of the substrate 100 removed is less than the depth of the initial channel threshold adjustment region 123. A channel threshold adjustment region 124 is formed in the well of the first sub-region 121 and the second sub-region 122. After the channel threshold adjustment region 124 is formed, the photoresist pattern is removed.

[0121] In this embodiment, the impurity ion in step S52 is boron ion, the energy of impurity ion implantation is 13 keV, the implantation dose is 8.3e12, and the implantation angle is 0°; the thickness of the substrate removed in step S54 is 20 nm.

[0122] S6, a CMOS gate dielectric layer 220 is formed on the first sub-region 121 and the second sub-region 122 of the substrate 100.

[0123] In this embodiment, the CMOS gate dielectric layer is a 3.3V gate oxide layer.

[0124] S7, remove the first gate dielectric layer 210 on the second device region 130 of the substrate 100.

[0125] S8, a second gate dielectric layer 230 is formed on the second device region 130 of the substrate 100.

[0126] S9 forms the gate structure 300 of the first MOS device, the CMOS device, and the second MOS device.

[0127] In this embodiment, the method for forming the gate structure 300 includes: forming the gate structure 300 on the first device region 110, the first sub-region 121, the second sub-region 122, and the second device region 130 of the substrate 100; and after the gate structure 300 is formed, the first gate dielectric layer 210, the CMOS gate dielectric layer, and the second gate dielectric layer outside the forming region of the gate structure 300 are removed.

[0128] S10 forms the source and drain regions of the first MOS device, the CMOS device, and the second MOS device.

[0129] In this embodiment, the method for forming the source and drain regions includes: forming an N-type source / drain region 113 in the first device region 110 and the second sub-region 122 of the substrate 100; and forming a P-type source / drain region 133 in the second device region 130 and the second sub-region 122 of the substrate 100.

[0130] Example 2:

[0131] The only difference between this embodiment and Embodiment 1 is that the energy of impurity ion implantation in step S52 is 16 keV and the implantation dose is 6.1e12; the thickness of the substrate removed in step S54 is 30 nm.

[0132] Example 3

[0133] The only difference between this embodiment and Embodiment 1 is that the energy of impurity ion implantation in step S52 is 19 keV and the implantation dose is 4.0e12; the thickness of the substrate removed in step S54 is 40 nm.

[0134] Example 4

[0135] The only difference between this embodiment and Embodiment 1 is that the energy of impurity ion implantation in step S52 is 21 keV and the implantation dose is 2.9e12; the thickness of the substrate removed in step S54 is 50 nm.

[0136] Example 5

[0137] The only difference between this embodiment and Embodiment 1 is that the energy of impurity ion implantation in step S52 is 24 keV and the implantation dose is 2.0e12; the thickness of the substrate removed in step S54 is 60 nm.

[0138] Comparative Example 1

[0139] The only difference between this comparative example and Example 1 is that the energy of impurity ion implantation in step S52 is 10 keV and the implantation dose is 6.0e12; step S54 is omitted.

[0140] Comparative Example 2

[0141] The only difference between this comparative example and Example 1 is that steps S52 and S54 are omitted.

[0142] Table 2

[0143]

[0144] Table 3

[0145]

[0146] As can be seen from Tables 2 and 3, when the NMOS device in the CMOS device directly reuses the P-well implantation parameters of the first MOS device, and the PMOS device directly reuses the N-well implantation parameters of the second MOS device, and only P-type ion implantation is performed, the threshold voltage of the CMOS device is limited to 0.82V. However, by applying the method provided in this application, through P-type ion implantation and partial removal of the substrate, the key parameters such as the threshold voltage and saturation current of the CMOS device can be flexibly adjusted.

[0147] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: S1, a shallow trench isolation structure is formed on the substrate, the shallow trench isolation structure separating a first device region, a CMOS device region, and a second device region, the first device region being the formation region of a first MOS device on the substrate, the CMOS device region being the formation region of a CMOS device on the substrate, which includes a first sub-region and a second sub-region, the second device region being the formation region of a second MOS device on the substrate, the operating voltage of the first MOS device being greater than the operating voltage of the CMOS device, and the operating voltage of the CMOS device being greater than the operating voltage of the second MOS device; S2, a first conductivity type well is formed in the first device region and the second sub-region of the substrate; S3, a second conductivity type well is formed in the second device region and the first sub-region of the substrate; S4, a first gate dielectric layer is formed on the first device region, the first sub-region, the second sub-region, and the second device region of the substrate; S5, a channel threshold adjustment region for adjusting the threshold voltage is formed in the well of the first sub-region and the second sub-region. During the formation of the channel threshold adjustment region, the first gate dielectric layer on the first sub-region and the second sub-region is removed and the substrate top of the first sub-region and the second sub-region is lower than the substrate top of the first device region and the second device region. S6, a CMOS gate dielectric layer is formed on the first and second sub-regions of the substrate; S7, Remove the first gate dielectric layer on the second device region of the substrate; S8, a second gate dielectric layer is formed on the second device region of the substrate; S9, forming the gate structure of the first MOS device, the CMOS device and the second MOS device; S10, forming the source and drain regions of the first MOS device, the CMOS device, and the second MOS device.

2. The manufacturing method according to claim 1, characterized in that, The method for forming the channel threshold adjustment region includes: S51 uses a patterned mask for photolithography to form a photoresist pattern on the substrate that exposes the first gate dielectric layer on the first sub-region and the second sub-region. S52 uses the photoresist pattern as a mask, the exposed first gate dielectric layer as an ion implantation buffer layer, and performs impurity ion implantation on the substrate to form an initial channel threshold adjustment region in the first and second sub-regions. S53, remove the first gate dielectric layer on the first sub-region and the second sub-region; S54, remove a portion of the substrate from the first and second sub-regions, the thickness of the removed substrate being less than the depth of the initial channel threshold adjustment region, and form the channel threshold adjustment region within the wells of the first and second sub-regions. After the channel threshold adjustment region is formed, the photoresist pattern is removed.

3. The manufacturing method according to claim 2, characterized in that, The thickness of the substrate removed is greater than the thickness of the CMOS gate dielectric layer.

4. The manufacturing method according to claim 2, characterized in that, The impurity ions are P-type, the implantation energy range is 5 keV-100 keV, and the implantation dose range is 1.0 × 10⁻⁶. 11 -5.0×10 13 cm -2 The injection angle is 0°-45°.

5. The manufacturing method according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type.

6. The manufacturing method according to claim 1, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type.

7. The manufacturing method according to claim 1, characterized in that, The thickness of the CMOS gate dielectric layer is less than the thickness of the first gate dielectric layer, and the thickness of the second gate dielectric layer is less than the thickness of the CMOS gate dielectric layer.

8. The manufacturing method according to claim 1, characterized in that, The method for forming the gate structure includes: forming a gate structure (104) on a first device region, a first sub-region, a second sub-region, and a second device region of a substrate; after the gate structure is formed, the first gate dielectric layer, the CMOS gate dielectric layer, and the second gate dielectric layer outside the gate structure forming region are removed.

9. The manufacturing method according to claim 1, characterized in that, Also includes: Sidewalls are formed on the periphery of the gate structure.

10. The manufacturing method according to claim 9, characterized in that, The side walls, from the outside to the inside, include a first side wall and a second side wall.

11. The manufacturing method according to claim 1, characterized in that, The method for forming the source and drain regions includes: forming a source and drain region of a second conductivity type in a first device region and a second sub-region of the substrate; and forming a source and drain region of a first conductivity type in a second device region and a second sub-region of the substrate.

12. The manufacturing method according to claim 1, characterized in that, Also includes: Between steps S9 and S10, drift regions are formed for the first MOS device, the CMOS device, and the second MOS device.

13. The manufacturing method according to claim 12, characterized in that, The method for forming the drift region includes: forming a drift region of a second conductivity type in a first device region and a second sub-region of the substrate; and forming a drift region of a first conductivity type in the second device region and the first sub-region of the substrate.

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