Semiconductor device manufacturing methods

Abstract

This invention provides a method for manufacturing a semiconductor device. The method includes: providing a substrate including first and second device regions; sequentially forming a first gate material layer, an insulating dielectric layer, and a second gate material layer; forming a second well region using a mask pattern and etching the second gate material layer and the insulating dielectric layer in the second device region; forming a first device gate stack and performing light doping implantation; forming a first sidewall structure; forming a second device gate structure using a photolithography pattern and removing the second gate material layer in the first device region; and forming a second sidewall structure and exposing the upper surface of the first gate material layer. This invention achieves a thickened sidewall structure without adding an additional photomask, significantly improving the breakdown voltage of high-voltage devices and reducing leakage risk, thus realizing efficient integration and cost optimization of high-voltage devices and logic devices in advanced processes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Technology

[0002] With the continuous evolution of complementary metal-oxide-semiconductor (CMOS) integrated circuit manufacturing processes, process nodes are becoming increasingly advanced, and device integration is continuously improving. In advanced processes, in order to pursue higher speeds and smaller feature sizes, the thickness of gate materials (such as polysilicon) and sidewall (spacer) thicknesses are both showing a continuous trend of thinning.

[0003] However, this thinning trend presents significant challenges in integrated circuits that include high-voltage devices such as 5V CMOS. For example... Figure 1 The diagram shows a cross-sectional view of a high-voltage CMOS device (HV-CMOS) and a logic CMOS device integrated on the same substrate in the prior art (taking an N-channel as an example). A high-voltage P-type well 102 and a logic P-type well 202 are defined on the substrate 100 via shallow trench isolation 101. The high-voltage CMOS device includes a thicker high-voltage gate insulating dielectric layer 104, and the logic CMOS device includes a thinner logic gate insulating dielectric layer 204. A gate material layer 105 is formed on top of both. A high-voltage N-type lightly doped drain (LDD) 103 and a logic N-type lightly doped drain 206 are formed on both sides below the gate material layer 105. Sidewall dielectric layers 108 are formed on the sidewalls of the gate material layer 105, and the sidewall dielectric layers 108 of the high-voltage CMOS device and the logic CMOS device have the same thickness. An N-type heavily doped region 109 is formed on the outer side of the sidewall dielectric layer 108, and a metal silicide 111 is formed on top of the heavily doped region 109 and the gate material layer 105.

[0004] In the aforementioned advanced process structure, the reduction in the thickness of the gate material layer 105 limits the maximum energy during high-voltage CMOS self-aligned lightly doped drain 103 implantation, thereby limiting the width of the overlap region between the gate material layer 105 and the lightly doped drain 103 (e.g., Figure 1 The width x is indicated in the middle. Simultaneously, the thinning of the sidewall dielectric layer 108 directly shortens the horizontal distance from the heavily doped region 109 to the edge of the gate material layer 105 (e.g., the width x). Figure 1 The limited overlap width x and distance y (as indicated in the text) together lead to a decrease in the breakdown voltage (BV) of high-voltage CMOS devices, severely affecting the reliability of the devices under high-voltage operating environments.

[0005] In existing technologies, to improve the performance of high-voltage CMOS devices, it is typically necessary to thicken the sidewalls of the high-voltage device separately by adding additional photomasks or complex process steps to increase the aforementioned distance y. However, this not only increases production costs and prolongs the manufacturing cycle but may also negatively impact the performance of logic devices. Therefore, how to thicken the sidewalls of high-voltage CMOS devices in advanced processes without increasing additional process costs to improve their breakdown voltage is a pressing technical problem to be solved in current semiconductor integration processes. Summary of the Invention

[0006] The technical problem this invention aims to solve is that in advanced manufacturing processes, thinning of the gate material and sidewall thickness limits the breakdown voltage of high-voltage devices, while existing methods of thickening the sidewalls increase the cost of additional photomasks and processes. To address this problem, this invention provides a method for manufacturing a semiconductor device.

[0007] A method for manufacturing a semiconductor device, comprising:

[0008] Step 1: Provide a substrate, the substrate including a first device region and a second device region, wherein a first well region is formed in the first device region;

[0009] Step 2: Sequentially form a first gate material layer, an insulating dielectric layer, and a second gate material layer on the substrate;

[0010] Step 3: Form a mask pattern, use the mask pattern to perform ion implantation on the second device region to form a second well region, and etch away the second gate material layer and the insulating dielectric layer located in the second device region;

[0011] Step 4: Etch the second gate material layer, the insulating dielectric layer, and the first gate material layer located in the first device region to form a first device gate stack;

[0012] Step 5: Perform lightly doped drain implantation in the first device region to form the first lightly doped region;

[0013] Step 6: Deposit a first sidewall dielectric layer on the substrate and etch it to form a first sidewall structure on the sidewall of the first device gate stack;

[0014] Step 7: Form a photolithography pattern. The photolithography pattern falls on the first sidewall structure at the edge of the first device region. Use the photolithography pattern to etch the first gate material layer located in the second device region to form the second device gate structure. At the same time, etch away all the second gate material layer located in the first device region.

[0015] Step 8: Perform lightly doped drain implantation in the second device region to form a second lightly doped region;

[0016] Step 9: Deposit a second sidewall dielectric layer on the substrate and etch it to form a second sidewall structure, while exposing the upper surface of the middle of the first gate material layer in the first device region.

[0017] Preferably, in step one, an isolation structure is formed on the substrate, and the first device region and the second device region are defined by the isolation structure.

[0018] Preferably, in step two, before forming the first gate material layer, a first gate insulating dielectric layer is formed in the first device region, and a second gate insulating dielectric layer is formed in the second device region.

[0019] Preferably, in step two, the first gate material layer and the second gate material layer are made of polycrystalline silicon.

[0020] Preferably, in step two, the thickness of the first gate material layer is 400 angstroms to 1200 angstroms.

[0021] Preferably, in step two, the thickness of the second gate material layer is 0.8 to 1.0 times the thickness of the first gate material layer.

[0022] Preferably, in step six, the thickness of the first sidewall dielectric layer is greater than twice the photolithography offset error.

[0023] Preferably, in step six, the thickness of the first sidewall medium layer is greater than 400 angstroms.

[0024] Preferably, in step eight, the second lightly doped region includes an ultra-shallow junction lightly doped drain structure.

[0025] Preferably, in step eight, the second lightly doped region includes a halo implantation structure.

[0026] Preferably, in step eight, the second lightly doped region includes a pocket implantation structure.

[0027] Preferably, in step nine, the second sidewall structure is formed on the outside of the first sidewall structure, the top and inside of the first sidewall structure, and the outside of the second device gate structure.

[0028] Preferably, after step nine, the method further includes step ten: performing heavy doping implantation to form a heavily doped region.

[0029] Preferably, in step ten, a metal silicide is also formed on the upper surface between the exposed silicon surface and the first gate material layer in the first device region.

[0030] Preferably, the first device region is used to form a high-voltage complementary metal-oxide-semiconductor device.

[0031] Preferably, the second device region is used to form a logic complementary metal-oxide-semiconductor device.

[0032] As described above, the method for manufacturing the semiconductor device of the present invention has the following beneficial effects:

[0033] This disclosure introduces a second gate material layer as an auxiliary gate, thickening the gate stack of the high-voltage device without adding an additional photomask. This allows for higher-energy lightly doped drain implantation and forms a thicker sidewall structure. The thickened sidewalls increase the horizontal distance from the heavily doped region to the gate edge, significantly improving the breakdown voltage and reliability of the high-voltage device. Simultaneously, by utilizing a shared etching step with the logic well implantation mask and cleverly leveraging the sidewall thickness to ensure complete removal of the auxiliary gate, a high degree of integration between the high-voltage device and logic device processes is achieved, reducing production costs and enhancing the product's market competitiveness. Attached Figure Description

[0034] Figure 1 The diagram shows a cross-sectional structure of a semiconductor device in the prior art.

[0035] Figure 2 The diagram shows a process flow diagram of the semiconductor device manufacturing method of the present invention;

[0036] Figure 3 The diagram shows a cross-sectional structure after the formation of the second gate material layer in the manufacturing method of the semiconductor device of the present invention;

[0037] Figure 4 The diagram shows a cross-sectional structure after etching the second gate material layer of the second device region in the semiconductor device manufacturing method of the present invention.

[0038] Figure 5 The diagram shows a cross-sectional structure after the first device gate stack is formed in the semiconductor device manufacturing method of the present invention;

[0039] Figure 6 The diagram shows a cross-sectional structure after the formation of the first lightly doped region in the manufacturing method of the semiconductor device of the present invention.

[0040] Figure 7 The diagram shows a cross-sectional structure after the first sidewall structure is formed in the manufacturing method of the semiconductor device of the present invention;

[0041] Figure 8 The diagram shows a cross-sectional view of the semiconductor device after the second device gate structure is formed in the manufacturing method of the present invention.

[0042] Figure 9 The diagram shows a cross-sectional view of the semiconductor device manufacturing method of the present invention after the second sidewall structure is formed.

[0043] Figure 10 The diagram shows a cross-sectional structure of the semiconductor device after metal silicide formation in the manufacturing method of the present invention. Detailed Implementation

[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0045] like Figure 2 As shown, a method for manufacturing a semiconductor device includes:

[0046] Step 1: Provide a substrate 100, which includes a first device region and a second device region, wherein a first well region 102 is formed in the first device region.

[0047] In some embodiments, in step one, an isolation structure 101 is formed on the substrate 100, and a first device region and a second device region are defined by the isolation structure 101.

[0048] In some embodiments, the first device region is used to form a high-voltage complementary metal-oxide-semiconductor device.

[0049] In some embodiments, the second device region is used to form a logic complementary metal-oxide-semiconductor device.

[0050] Substrate 100 is a silicon substrate, which may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The active layer and bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0051] A shallow trench isolation process is implemented on substrate 100, for example, by sequentially growing a front oxide layer and a silicon nitride layer, performing photolithography and etching to form trenches, then filling the trenches with an insulating material such as silicon oxide, and removing excess oxide by chemical mechanical polishing, thereby forming isolation structure 101. Isolation structure 101 effectively isolates different active regions, preventing leakage and electrical crosstalk between adjacent devices. A first well region 102, such as a high-voltage P-type well or a high-voltage N-type well, is formed in the first device region using an ion implantation process.

[0052] Step 2: Sequentially form a first gate material layer 105, an insulating dielectric layer 151, and a second gate material layer 152 on the substrate 100.

[0053] In some embodiments, in step two, before forming the first gate material layer 105, a first gate insulating dielectric layer 104 is formed in the first device region, and a second gate insulating dielectric layer 204 is formed in the second device region.

[0054] In some embodiments, in step two, the first gate material layer 105 and the second gate material layer 152 are made of polycrystalline silicon.

[0055] In some embodiments, in step two, the thickness of the first gate material layer 105 is 400 angstroms to 1200 angstroms.

[0056] In some embodiments, in step two, the thickness of the second gate material layer 152 is 0.8 to 1.0 times the thickness of the first gate material layer 105.

[0057] Continue to refer to Figure 3The first gate insulating dielectric layer 104 can be formed using a thermal oxidation process, an in-situ vapor growth process, or a decoupled plasma nitriding process. To support high-voltage operation, the first gate insulating dielectric layer 104 has a relatively large thickness. The second gate insulating dielectric layer 204 can have a smaller thickness than the first gate insulating dielectric layer 104, and its material can include silicon dioxide, silicon oxynitride, or high-dielectric-constant materials such as hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, or silicates of these materials. High-dielectric-constant materials can be formed using atomic layer deposition processes to ensure atomic-level thickness control and excellent uniformity. In addition to polycrystalline silicon, the first gate material layer 105 and the second gate material layer 152 can also include amorphous silicon, metallic materials, or metal silicides. The metallic material can be selected from tungsten, titanium, tantalum, titanium nitride, tantalum nitride, aluminum, or alloys thereof. The first gate material layer 105 can have a multilayer structure, for example, a layer of metal silicide overlying polycrystalline silicon to reduce gate resistance. The deposition of the first gate material layer 105 and the second gate material layer 152 can be achieved using low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD). The insulating dielectric layer 151 can be made of materials such as silicon oxide, silicon nitride, or silicon oxynitride, and formed by LCVD or PECVD. The second gate material layer 152 serves as an auxiliary gate, thickening the gate structure of the high-voltage device, which is beneficial for increasing the energy of self-aligned lightly doped drain injection in subsequent processes. Setting the thickness of the second gate material layer 152 to 0.8 to 1.0 times the thickness of the first gate material layer 105 ensures that the second gate material layer 152 on the high-voltage device can be etched away simultaneously during subsequent etching of the logic device gate, thereby simplifying the process flow.

[0058] Step 3: Form a mask pattern 501, use the mask pattern 501 to perform ion implantation on the second device region to form a second well region 202, and etch away the second gate material layer 152 and insulating dielectric layer 151 located in the second device region.

[0059] like Figure 4 As shown, a mask pattern 501, such as a photoresist layer, is formed through a photolithography process. Ion implantation is then performed on the second device region using the mask pattern 501 to form a second well region 202, such as a logic P-type well or a logic N-type well. Without removing the photoresist, or by etching before implantation, the second gate material layer 152 and the insulating dielectric layer 151 in the open area of ​​the second device region are etched away using the same mask pattern 501. This post-well implantation method allows the implantation and etching processes to share the same mask photolithography step, eliminating the need for additional photomasks, effectively reducing manufacturing costs and shortening the production cycle.

[0060] Step 4: Etch the second gate material layer 152, the insulating dielectric layer 151 and the first gate material layer 105 located in the first device region to form the first device gate stack.

[0061] like Figure 5 As shown, a photoresist pattern 502 is formed by photolithography and development. An anisotropic dry etching process, such as reactive ion etching, is used, employing a reactive gas containing chlorine, hydrogen bromide, oxygen, or fluorocarbons to sequentially etch the second gate material layer 152, the insulating dielectric layer 151, and the first gate material layer 105 of the first device region. The etching process requires a high selectivity for the first gate insulating dielectric layer 104 to avoid damaging the surface of the underlying substrate 100. After etching, residual photoresist pattern 502 and polymer can be removed by plasma ashing and wet cleaning. The formed first device gate stack has a large overall thickness, which can serve as an effective barrier layer for subsequent high-energy ion implantation, protecting the underlying channel region from impurity penetration.

[0062] Step 5: Perform lightly doped drain implantation in the first device region to form the first lightly doped region 103.

[0063] like Figure 6 As shown, a photoresist pattern 503 is formed by photolithography to cover the second device region, and a self-aligned high-voltage lightly doped drain implantation is performed in the first device region to form a first lightly doped region 103. The formation of the first lightly doped region 103 helps to establish an electric field gradient at the gate edge, thereby improving the reliability of the device. The implantation process can be self-aligned, using the first device gate stack as a mask. The implanted impurities can include phosphorus, arsenic, or boron, and the implantation energy and dose can be set according to the required junction depth. The implantation can be performed with a certain tilt angle to control the lateral diffusion distance of the impurities below the gate. The depth and concentration distribution of the first lightly doped region 103 directly affect the breakdown voltage and hot carrier effect of the first device. Since a second gate material layer 152 is introduced into the first device region as an auxiliary gate, the overall gate structure is thickened, so a higher implantation energy can be used for lightly doped drain implantation. High-energy implantation can optimize the junction depth and impurity distribution of the lightly doped region 103, thereby improving the breakdown voltage and hot carrier reliability of the high-voltage device.

[0064] Step 6: Deposit a first sidewall dielectric layer 107 on the substrate 100 and etch it to form a first sidewall structure 107 on the sidewall of the first device gate stack.

[0065] In some embodiments, in step six, the thickness of the first sidewall dielectric layer 107 is greater than twice the photolithography offset error.

[0066] In some embodiments, in step six, the thickness of the first sidewall medium layer 107 is greater than 400 angstroms.

[0067] like Figure 7 As shown, the first sidewall dielectric layer 107 can be made of silicon oxide, silicon nitride, or a stacked structure thereof, and can be formed using a conformal deposition process, such as low-pressure chemical vapor deposition or atomic layer deposition. Subsequently, anisotropic dry etching is performed. By adjusting the fluorine-to-carbon ratio and bias power, high-speed removal of the dielectric at the horizontal plane is achieved while retaining the dielectric at the sidewall, forming the first sidewall structure 107 on the sidewall of the first device gate stack. Since the first device gate structure is thickened, the height and thickness of the first sidewall structure 107 can also be increased accordingly. The thickened first sidewall structure 107 can further increase the horizontal distance from the subsequent heavily doped region to the gate edge, which significantly promotes the improvement of the breakdown voltage of high-voltage devices and reduces leakage current.

[0068] Step 7: Forming a photolithography pattern 504. The edge of the photolithography pattern 504 falls on the first sidewall structure 107. The first gate material layer 105 located in the second device region is etched using the photolithography pattern 504 to form the second device gate structure. At the same time, the second gate material layer 152 located in the first device region is completely etched away.

[0069] like Figure 8 As shown, a photolithographic pattern 504 is formed through photolithography. Since the thickness of the first sidewall structure 107 is greater than twice the photolithographic overlay error, this ensures that the edge of the photolithographic pattern 504 falls precisely on the first sidewall structure 107 within the first device region. Simultaneously with etching the first gate material layer 105 of the second device region to form the logic device gate structure, the second gate material layer 152 on the main gate of the first device region is completely etched away. This design results in a unique, symmetrical gate structure for the high-voltage device: the central region of the gate structure contains only the first gate insulating dielectric layer 104 and the first gate material layer 105, while the two side edge regions of the gate structure contain the first gate insulating dielectric layer 104, the first gate material layer 105, the insulating dielectric layer 151, and the subsequently formed multilayer sidewall structure. This structure retains the thickened sidewalls while removing the auxiliary gate, avoiding parasitic capacitance or leakage problems that might be caused by residual auxiliary gates. The width of the second device gate structure is typically smaller than the width of the first device gate stack to achieve higher logic operation speeds.

[0070] Step 8: Perform lightly doped drain implantation in the second device region to form the second lightly doped region 206.

[0071] In some embodiments, in step eight, the second lightly doped region 206 includes an ultra-shallow junction lightly doped drain structure.

[0072] In some embodiments, in step eight, the second lightly doped region 206 includes a halo implantation structure.

[0073] In some embodiments, in step eight, the second lightly doped region 206 includes a pocket implantation structure.

[0074] like Figure 9 As shown, ion implantation is performed in the second device region to form a second lightly doped region 206. Ultra-shallow junction lightly doped drain structures are typically formed using extremely low implantation energy to suppress short-channel effects. Halo implantation or pocket implantation uses impurities of the same conductivity type as the second well region 202 for large-angle tilting implantation, forming a locally high-concentration region at the channel edge, thereby effectively controlling the expansion of the depletion layer and improving the switching speed and overall electrical performance of the logic device. These implantation steps can be combined multiple times according to the performance specifications of the logic device.

[0075] Step 9: Deposit a second sidewall dielectric layer 108 on the substrate 100 and etch it to form the second sidewall structure 108, while exposing the upper surface of the middle of the first gate material layer 105 in the first device region.

[0076] In some embodiments, in step nine, the second sidewall structure 108 is formed on the outside of the first sidewall structure 107, on the top and inside of the first sidewall structure 107, and on the outside of the second device gate structure.

[0077] Continue to refer to Figure 9 A second sidewall dielectric layer 108 is deposited and etched to form the second sidewall structure 108. The second sidewall dielectric layer 108 can use a different insulating material than the first sidewall dielectric layer 107 to achieve a good etch selectivity. The second sidewall dielectric layer 108 can include a single-layer, double-layer, or multi-layer stacked structure. Commonly used material combinations include stacks of silicon oxide and silicon nitride, for example, depositing a thin silicon oxide buffer layer followed by a thicker silicon nitride layer. This combination helps to relieve stress and improve etch selectivity. The deposition process can be formed using conformal deposition processes, such as low-pressure chemical vapor deposition or atomic layer deposition. In the first device region, the second sidewall structure 108 covers the outer side and top of the first sidewall structure 107 and the inner side of the insulating dielectric layer 151, together forming a multi-layer sidewall structure of the high-voltage device. At the same time, the etching process exposes the upper surface of the middle of the first gate material layer 105 in the first device region, providing a window for subsequent contact formation.

[0078] In some embodiments, after step nine, the method further includes step ten, performing heavy doping implantation to form a heavily doped region 109.

[0079] In some embodiments, in step ten, a metal silicide 111 is also formed on the upper surface between the exposed silicon surface and the first gate material layer 105 in the first device region.

[0080] like Figure 10As shown, N-type or P-type heavy doping is selectively implanted to form heavily doped regions 109, which serve as the source and drain of the device. After implantation, an activation annealing process, such as rapid thermal annealing, spike annealing, or laser annealing, is performed. The annealing process activates the implanted impurity atoms and repairs lattice damage generated during etching and implantation. Before forming the metal silicide, the exposed silicon surface and the upper surface of the first gate material layer 105 are typically cleaned to remove native oxides and surface contaminants. Next, one or more metal layers are deposited over the substrate 100. The material of the metal layer can be selected from nickel, cobalt, titanium, tungsten, platinum, erbium, palladium, or alloys of these metals. The deposition process can be physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In some embodiments, a capping layer, such as titanium nitride or tantalum nitride, can also be deposited over the metal layer to prevent oxidation of the metal layer and limit surface migration of metal atoms during subsequent heat treatment. A subsequent heat treatment process induces the deposited metal layer to react with the exposed silicon material beneath, thereby forming a metal silicide 111 on the upper surface between the exposed source / drain silicon surface and the first gate material layer 105 in the first device region. The heat treatment process may include rapid thermal annealing, spike annealing, or millisecond-level laser annealing. In some embodiments, the silicide reaction can be accomplished through a two-step annealing process. The first annealing is performed at a lower temperature, causing the metal to react with silicon to form a metal-rich silicide phase. Then, an unreacted metal layer and any existing capping layers are selectively removed using a wet etching process, while retaining the formed metal silicide 111. The wet etching may employ a mixed solution of sulfuric acid and hydrogen peroxide, a mixed solution of ammonia and hydrogen peroxide, or a mixed solution of hydrochloric acid and hydrogen peroxide. After removing the unreacted metal, a second annealing at a higher temperature can be performed to convert the metal-rich silicide phase into a stable silicide phase with lower resistivity. This self-aligned silicide process forms metal silicide 111 only on the middle surface of the main gate and the surface of the source / drain regions of the high-voltage device. Combined with the aforementioned special symmetrical gate structure and thickened sidewalls, this layout can effectively reduce the contact resistance between the gate and the source / drain, and improve the drive current of the device. At the same time, due to the physical isolation effect of the sidewall structure, the metal silicide 111 is strictly confined to a specific area, avoiding the metal silicide 111 from being too close to the channel edge or bridging short circuits along the sidewall surface, thereby reducing the risk of leakage current and improving the overall reliability of the device.

[0081] This invention relates to doping processes for various conductivity types to form complementary metal-oxide-semiconductor (CMOS) structures. The doping types primarily include N-type doping and P-type doping. For N-type doping, the impurity atoms used can be selected from phosphorus, arsenic, antimony, or combinations thereof. For P-type doping, the impurity atoms used can be selected from boron, boron fluoride, indium, gallium, or combinations thereof. Specifically, when the first and second devices are configured as N-channel CMOS devices, the first well region 102 and the second well region 202 are P-type doped, while the first lightly doped region 103, the second lightly doped region 206, and the heavily doped region 109 are N-type doped. In this configuration, by introducing a high concentration of N-type impurities into the P-type well region, N-type sources and drains can be formed.

[0082] Conversely, when the first and second devices are configured as P-channel metal-oxide-semiconductor devices, the first well region 102 and the second well region 202 are N-type doped, while the first lightly doped region 103, the second lightly doped region 206, and the heavily doped region 109 are P-type doped. In this configuration, P-type sources and drains can be formed by introducing a high concentration of P-type impurities into the N-type well regions. To integrate N-channel and P-channel devices on the same substrate 100, a dual-well process can be employed. For example, during the formation of the first and second device regions, multiple ion implantations can be selectively performed using masks to form mutually isolated N-type and P-type wells in different regions of the substrate 100.

[0083] Furthermore, for halo injection or pocket injection involved in the second device, the doping type is typically the same as the conductivity type of the well region, but opposite to the conductivity type of the source / drain region. For example, in N-channel logic devices, halo injection uses P-type impurities. By forming a localized high-concentration P-type region at the channel edge, the short-channel effect and punch-through effect caused by device size reduction can be effectively suppressed. The doping concentration and distribution profile of the first lightly doped region 103 and the second lightly doped region 206 can be differentiated according to the voltage withstand requirements of the device. The first lightly doped region 103 of high-voltage devices typically has a lower doping concentration and a deeper junction depth to increase the depletion layer width and reduce the peak electric field; while the second lightly doped region 206 of logic devices aims for a higher doping concentration and a shallower junction depth to reduce parasitic resistance and improve switching speed.

[0084] By precisely controlling the doping type and impurity distribution in different regions, this invention can simultaneously optimize the reliability of high-voltage devices and the electrical performance of logic devices without adding an additional photomask. The method provided by this invention enables the integration of high-voltage devices and logic devices with different sidewall thicknesses onto the same chip. This process integration scheme does not require additional photomask steps; by simply adjusting the deposition and etching sequence of the gate material layer and sidewall layers, the breakdown characteristics of high-voltage devices can be effectively optimized while maintaining the advanced process advantages of logic devices. This method can be widely applied in the manufacture of power management chips, display driver chips, and various mixed-signal integrated circuits.

[0085] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0086] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, At least including: Step 1: Provide a substrate, the substrate including a first device region and a second device region, wherein a first well region is formed in the first device region; Step 2: Sequentially form a first gate material layer, an insulating dielectric layer, and a second gate material layer on the substrate; Step 3: Form a mask pattern, use the mask pattern to perform ion implantation on the second device region to form a second well region, and etch away the second gate material layer and the insulating dielectric layer located in the second device region; Step 4: Etch the second gate material layer, the insulating dielectric layer, and the first gate material layer located in the first device region to form a first device gate stack; Step 5: Perform lightly doped drain implantation in the first device region to form the first lightly doped region; Step 6: Deposit a first sidewall dielectric layer on the substrate and etch it to form a first sidewall structure on the sidewall of the first device gate stack; Step 7: Form a photolithography pattern. The photolithography pattern falls on the first sidewall structure at the edge of the first device region. Use the photolithography pattern to etch the first gate material layer located in the second device region to form the second device gate structure. At the same time, etch away all the second gate material layer located in the first device region. Step 8: Perform lightly doped drain implantation in the second device region to form a second lightly doped region; Step 9: Deposit a second sidewall dielectric layer on the substrate and etch it to form a second sidewall structure, while exposing the upper surface of the middle of the first gate material layer in the first device region.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step one, an isolation structure is formed on the substrate, and the first device region and the second device region are defined by the isolation structure.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step two, before forming the first gate material layer, a first gate insulating dielectric layer is formed in the first device region, and a second gate insulating dielectric layer is formed in the second device region.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step two, the first gate material layer and the second gate material layer are made of polycrystalline silicon.

5. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step two, the thickness of the first gate material layer is 400 angstroms to 1200 angstroms.

6. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step two, the thickness of the second gate material layer is 0.8 to 1.0 times the thickness of the first gate material layer.

7. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step six, the thickness of the first sidewall dielectric layer is greater than twice the photolithography offset error.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that: In step six, the thickness of the first sidewall medium layer is greater than 400 angstroms.

9. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step eight, the second lightly doped region includes an ultra-shallow junction lightly doped drain structure.

10. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step eight, the second lightly doped region includes a halo implantation structure.

11. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step eight, the second lightly doped region includes a pocket implantation structure.

12. The method for manufacturing a semiconductor device according to claim 1, characterized in that: In step nine, the second sidewall structure is formed on the outside of the first sidewall structure, the top and inside of the first sidewall structure, and the outside of the second device gate structure.

13. The method for manufacturing a semiconductor device according to claim 1, characterized in that: After step nine, the method further includes step ten: performing heavy doping implantation to form a heavily doped region.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that: In step ten, a metal silicide is also formed on the upper surface between the exposed silicon surface and the first gate material layer in the first device region.

15. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The first device region is used to form a high-voltage complementary metal-oxide-semiconductor device.

16. The method for manufacturing a semiconductor device according to claim 1, characterized in that: The second device region is used to form a logic complementary metal-oxide-semiconductor device.

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