Semiconductor structure and manufacturing method

Abstract

This invention discloses a semiconductor structure including a substrate, a transistor element, a first back gate, a second back gate, and a dielectric layer. The substrate has a front side and a back side opposite to each other. The transistor element is located on the front side. The transistor element includes a first drift region and a second drift region. The first drift region and the second drift region are located within the substrate. The first back gate is located on the back side. The first back gate extends into the first drift region. The second back gate is located on the back side. The second back gate extends into the second drift region. The dielectric layer is located between the first back gate and the substrate, and between the second back gate and the substrate.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and particularly to a semiconductor structure having a back electrode and a method for manufacturing the same. Background Technology

[0002] Transistors are widely used in various electronic products. With technological advancements, the size of electronic components continues to shrink, making it increasingly difficult to improve the breakdown voltage and reduce the on-resistance of transistors. Therefore, improving the breakdown voltage and reducing the on-resistance of transistors remains a continuous goal. Summary of the Invention

[0003] This invention provides a semiconductor structure and its manufacturing method, which can improve the breakdown voltage of transistor elements and reduce the on-resistance of transistor elements.

[0004] This invention proposes a semiconductor structure including a substrate, a transistor element, a first back gate, a second back gate, and a dielectric layer. The substrate has a front side and a back side opposite to each other. The transistor element is located on the front side. The transistor element includes a first drift region and a second drift region. The first drift region and the second drift region are located within the substrate. The first back gate is located on the back side. The first back gate extends into the first drift region. The second back gate is located on the back side. The second back gate extends into the second drift region. The dielectric layer is located between the first back gate and the substrate, and between the second back gate and the substrate.

[0005] According to an embodiment of the present invention, the semiconductor structure described above may further include a conductive layer. The conductive layer is located on the first back gate and the second back electrode. The conductive layer is electrically connected to the first back gate and the second back electrode.

[0006] According to an embodiment of the present invention, in the above-described semiconductor structure, the transistor element may further include a gate and a gate dielectric layer. The gate is located on the front side. The gate is located above a portion of the first drift region and a portion of the second drift region. The gate dielectric layer is located between the gate and the substrate.

[0007] According to an embodiment of the present invention, in the above-described semiconductor structure, the first back electrode may have a first protrusion extending into a first drift region. The second back electrode may have a second protrusion extending into a second drift region.

[0008] According to an embodiment of the present invention, in the above-described semiconductor structure, the gate may have a first sidewall and a second sidewall opposite to each other. The first sidewall may be located directly above the first drift region. The second sidewall may be located directly above the second drift region. The first protrusion may have a third sidewall away from the second protrusion. The second protrusion may have a fourth sidewall away from the first protrusion.

[0009] According to an embodiment of the present invention, in the above semiconductor structure, the third sidewall does not extend beyond the first sidewall, and the fourth sidewall does not extend beyond the second sidewall.

[0010] According to an embodiment of the present invention, in the above semiconductor structure, the third sidewall can be aligned with the first sidewall, and the fourth sidewall can be aligned with the second sidewall.

[0011] According to an embodiment of the present invention, in the above semiconductor structure, the third sidewall may extend beyond the first sidewall, and the fourth sidewall may extend beyond the second sidewall.

[0012] According to an embodiment of the present invention, in the above semiconductor structure, the transistor element may further include a first isolation structure and a second isolation structure. The first isolation structure is located in a first drift region. The second isolation structure is located in a second drift region. The gate is located above a portion of the first isolation structure and a portion of the second isolation structure.

[0013] According to an embodiment of the present invention, in the above-described semiconductor structure, the transistor element may further include a first doped region and a second doped region. The first doped region is located in a first drift region. The second doped region is located in a second drift region. A first isolation structure and a second isolation structure may be located between the first doped region and the second doped region.

[0014] According to an embodiment of the present invention, in the above-described semiconductor structure, the transistor element may further include a first well region and a second well region. The first well region and the second well region are located in the substrate on both sides of the gate. The first drift region and the second drift region may be located between the first well region and the second well region.

[0015] According to one embodiment of the present invention, in the above semiconductor structure, the transistor element may further include a first doped region and a second doped region. The first doped region is located in a first well region. The second doped region is located in a second well region.

[0016] According to one embodiment of the present invention, in the above semiconductor structure, the transistor element may further include a third well region. The first drift region, the second drift region, the first well region, and the second well region may be located in the third well region.

[0017] According to one embodiment of the present invention, in the above semiconductor structure, the transistor element may be mirror-symmetric.

[0018] This invention proposes a method for manufacturing a semiconductor structure, comprising the following steps: A substrate is provided. The substrate has a front side and a back side opposite to each other. A transistor element is formed on the front side. The transistor element includes a first drift region and a second drift region. The first drift region and the second drift region are located in the substrate. A first back gate and a second back gate are formed on the back side. The first back gate extends into the first drift region. The second back gate extends into the second drift region. A first dielectric layer is formed between the first back gate and the substrate, and between the second back gate and the substrate.

[0019] According to an embodiment of the present invention, in the method for manufacturing the above-described semiconductor structure, the method for forming the first dielectric layer may include the following steps: Patterning the back surface to form a first recess and a second recess. The first recess exposes a first drift region. The second recess exposes a second drift region. A first dielectric layer is conventionally formed on the back surface and in the first and second recesses.

[0020] According to an embodiment of the present invention, in the method for manufacturing the above-described semiconductor structure, the first recess may extend into the first drift region. The second recess may extend into the second drift region.

[0021] According to an embodiment of the present invention, in the method for manufacturing the above-described semiconductor structure, the method for forming the first back gate and the second back gate may include the following steps: A second dielectric layer is formed on a first dielectric layer. The second dielectric layer may fill a first recess and a second recess. The first back gate and the second back gate are formed in the second dielectric layer. A portion of the first back gate may be located in the first recess. A portion of the second back gate may be located in the second recess.

[0022] According to an embodiment of the present invention, the method for manufacturing the above-described semiconductor structure may further include the following step: forming a conductive layer on a first back gate and a second back gate. The conductive layer is electrically connected to the first back gate and the second back gate.

[0023] According to an embodiment of the present invention, in the method for manufacturing the above-described semiconductor structure, the method for forming a conductive layer may include the following steps: forming a third dielectric layer on a second dielectric layer, a first back gate, and a second back gate; and forming a conductive layer in the third dielectric layer.

[0024] Based on the above, in the semiconductor structure and manufacturing method proposed in this invention, the first back gate extends into the first drift region, and the second back gate extends into the second drift region. Therefore, the breakdown voltage of the transistor element and the on-resistance of the transistor element can be increased and reduced by using the first back gate and the second back electrode.

[0025] To make the above-mentioned features and advantages of the present invention readily apparent, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0026] Figures 1A to 1H This is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention;

[0027] Figure 2 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention;

[0028] Figure 3 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention.

[0029] Symbol Explanation

[0030] 10: Semiconductor Structure

[0031] 100: Base

[0032] 102, 104: Drift Zone

[0033] 106,132: Gate

[0034] 108, 134: Gate dielectric layer

[0035] 110, 112, 118, 120: Doped regions

[0036] 114, 116, 122, 140: Tunnel area

[0037] 124, 126, 128, 130, 142: Metal silicide layers

[0038] 136: Lightly doped drain region

[0039] 138: Source / Drain Region

[0040] 144, 146: Spacer wall

[0041] 148, 162, 166, 168, 176: Dielectric layer

[0042] 150, 152, 154, 156, 158: Contact Window

[0043] 160, 170: Through holes

[0044] 164: Internal Wiring Structure

[0045] 172, 174: Back gate

[0046] 178, 180: Conductive layer

[0047] IS1, IS2, IS3, IS4, IS5, IS6, IS7: Isolation Structure

[0048] P1, P2: Protrusions

[0049] R1: Zone 1

[0050] R2: Second Zone

[0051] R3, R4: Depression

[0052] S1: Front

[0053] S2: Back

[0054] SW1, SW2, SW3, SW4: Sidewalls

[0055] T1, T2: Transistor components Detailed Implementation

[0056] The following description provides detailed examples and accompanying drawings, but these examples are not intended to limit the scope of the invention. For ease of understanding, the same components will be designated with the same symbols in the following description. Furthermore, the drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, the dimensions of various features may be increased or decreased arbitrarily for clarity of explanation.

[0057] Figures 1A to 1H This is a cross-sectional view of the manufacturing process of a semiconductor structure according to some embodiments of the present invention. Figure 2 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention. Figure 3 This is a cross-sectional view of a semiconductor structure according to other embodiments of the present invention.

[0058] Please refer to Figure 1A A substrate 100 is provided. The substrate 100 has a front side S1 and a back side S2 opposite to each other. In some embodiments, the substrate 100 may include a first region R1 and a second region R2. In some embodiments, the first region R1 may be a component region having a high-voltage device, and the second region R2 may be a component region having a core device. In some embodiments, the threshold voltage of the high-voltage device may be higher than the threshold voltage of the core device. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon substrate.

[0059] Next, a transistor element T1 is formed on the front side S1. The transistor element T1 may be located in the first region R1. The transistor element T1 includes a drift region 102 and a drift region 104. The drift region 102 and the drift region 104 are located in the substrate 100. In addition, the transistor element T1 may also include an isolation structure IS1 and an isolation structure IS2. The isolation structure IS1 is located in the drift region 102. The isolation structure IS2 is located in the drift region 104. In some embodiments, the isolation structure IS1 and the isolation structure IS2 may be shallow trench isolation structures.

[0060] The transistor element T1 may further include a gate 106 and a gate dielectric layer 108. The gate 106 is located on the front side S1. The gate 106 is located above partial drift regions 102 and 104. The gate 106 is located above partial isolation structures IS1 and IS2. The gate 106 may have sidewalls SW1 and SW2 opposite to each other. Sidewall SW1 may be located directly above drift region 102. Sidewall SW2 may be located directly above drift region 104. In some embodiments, the gate 106 may be a polysilicon gate or a metal gate. The gate dielectric layer 108 is located between the gate 106 and the substrate 100. In some embodiments, the material of the gate 106 may be doped polysilicon, and the material of the gate dielectric layer 108 may be silicon oxide, but the invention is not limited thereto. In other embodiments, the gate 106 and the gate dielectric layer 108 may be formed using high-k metal gate (HKMG) technology.

[0061] Transistor device T1 may further include doped regions 110 and 112. In some embodiments, doped regions 110 and 112 may serve as source / drain regions. Doped region 110 is located in drift region 102. Doped region 112 is located in drift region 104. Isolation structures IS1 and IS2 may be located between doped regions 110 and 112. Transistor device T1 may further include well regions 114 and 116. Well regions 114 and 116 are located in the substrate 100 on both sides of gate 106. Drift regions 102 and 104 may be located between well regions 114 and 116. Transistor device T1 may further include doped regions 118 and 120. Doped region 118 is located in well region 114. Doped region 120 is located in well region 116. Transistor device T1 may further include well region 122. Drift region 102, drift region 104, trap region 114 and trap region 116 may be located in trap region 122.

[0062] The transistor element T1 may further include metal silicide layers 124, 126, 128, and 130. Metal silicide layers 124, 126, 128, and 130 are located on doped regions 110, 112, 118, and 120, respectively.

[0063] In some embodiments, a transistor T2 may be formed in the second region R2. The transistor T2 is located on the front side S1. The transistor T2 may be a planar transistor or a finned transistor. In this embodiment, the transistor T2 is exemplified as a planar transistor, but the invention is not limited thereto. The transistor T2 may include a gate 132, a gate dielectric layer 134, multiple lightly doped drain (LDD) regions 136, multiple source / drain regions 138, a well region 140, and multiple metal silicide layers 142. The gate 132 is located on the front side S1 of the substrate 100. In some embodiments, the gate 132 may be a polysilicon gate or a metal gate. The gate dielectric layer 134 is located between the gate 132 and the substrate 100. In some embodiments, the material of the gate 132 may be doped polysilicon, and the material of the gate dielectric layer 134 may be silicon oxide, but the invention is not limited thereto. In other embodiments, the gate 132 and the gate dielectric layer 134 may be formed using high dielectric metal gate (HKMG) technology. Multiple lightly doped drain regions 136 are located in the substrate 100 on both sides of the gate 132. Multiple source / drain regions 138 are located in the multiple lightly doped drain regions 136. The multiple lightly doped drain regions 136 and the multiple source / drain regions 138 are located in the well region 140. Multiple metal silicide layers 142 are located on the multiple source / drain regions 138.

[0064] In some embodiments, the substrate may further include isolation structures IS3, IS4, IS5, IS6, and IS7. A doped region 110 is located between isolation structures IS1 and IS3. A doped region 112 is located between isolation structures IS2 and IS4. A doped region 118 is located between isolation structures IS3 and IS5. A doped region 120 is located between isolation structures IS4 and IS6. Multiple doped regions 138 are located between isolation structures IS5 and IS7. In some embodiments, isolation structures IS3, IS4, IS5, IS6, and IS7 may be shallow trench isolation structures.

[0065] In some embodiments, a spacer wall 144 may be formed on the sidewalls SW1 and SW2 of the gate 106, and a spacer wall 146 may be formed on the sidewall of the gate 132. The spacer walls 144 and 146 may be a single-layer or multi-layer structure. In some embodiments, the materials of the spacer walls 144 and 146 are, for example, silicon oxide, silicon nitride, or a combination thereof.

[0066] Next, a dielectric layer 148 may be formed on the substrate 100. The dielectric layer 148 may be a single-layer structure or a multi-layer structure. In some embodiments, the material of the dielectric layer 148 is, for example, silicon oxide, silicon nitride, or a combination thereof.

[0067] Then, contact windows 150, 152, 154, 156, and a plurality of contact windows 158 can be formed in the dielectric layer 148. Contact windows 150, 152, 154, 156, and a plurality of contact windows 158 can be electrically connected to doped regions 110, 112, 118, 120, and a plurality of doped regions 138, respectively. The materials of contact windows 150, 152, 154, 156, and 158 are, for example, tungsten, titanium, titanium nitride, or combinations thereof.

[0068] Next, vias 160 can be formed in the substrate 100, the isolation structure IS5, and the dielectric layer 148. The via 160 can be used as a power via. In some embodiments, the material of the via 160 is, for example, titanium, titanium nitride, tungsten, aluminum, tantalum nitride, copper, cobalt, or a combination thereof.

[0069] Please refer to Figure 1B A back end of line (BEOL) dielectric layer 162 and a plurality of interconnect structures 164 can be formed on the dielectric layer 148. In some embodiments, the dielectric layer 162 may be a multilayer structure. The material of the dielectric layer 162 is, for example, silicon oxide, silicon nitride, or a combination thereof. The plurality of interconnect structures 164 are located in the dielectric layer 162. A portion of the plurality of interconnect structures 164 may be electrically connected to a contact window 150, a portion of the plurality of interconnect structures 164 may be electrically connected to a contact window 152, a portion of the plurality of interconnect structures 164 may be electrically connected to a contact window 154, a portion of the plurality of interconnect structures 164 may be electrically connected to a contact window 156, a portion of the plurality of interconnect structures 164 may be electrically connected to a plurality of contact windows 158, and a portion of the plurality of interconnect structures 164 may be electrically connected to a via 160. The material of the interconnect structure 164 is, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination thereof.

[0070] Please refer to Figure 1C A thinning process can be performed on the back side S2, thereby reducing the thickness of the substrate 100 and exposing the through-hole 160. In this way, the through-hole 160 can penetrate the substrate 100. In some embodiments, the thinning process is, for example, a grinding process or a chemical mechanical polishing process.

[0071] Please refer to Figure 1D The back surface S2 can be patterned to form recesses R3 and R4. Recess R3 exposes drift region 102. Recess R4 exposes drift region 104. Recess R3 extends into drift region 102. Recess R4 extends into drift region 104. In some embodiments, the back surface S2 can be patterned using photolithography and etching processes.

[0072] Please refer to Figure 1E A dielectric layer 166 may be conformally formed on the back surface S2 and in the recesses R3 and R4. In some embodiments, the material of the dielectric layer 166 is, for example, a metal oxide. In some embodiments, the dielectric layer 166 is formed by a method such as chemical vapor deposition or atomic layer deposition.

[0073] Next, a dielectric layer 168 may be formed on the dielectric layer 166. The dielectric layer 168 may fill recesses R3 and R4. In some embodiments, the material of the dielectric layer 168 is, for example, silicon oxide. In some embodiments, the dielectric layer 168 is formed by, for example, chemical vapor deposition.

[0074] Please refer to Figure 1F Vias 170 may be formed in dielectric layers 168 and 166. Vias 170 may be electrically connected to via 160. In some embodiments, the material of via 170 may be, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or a combination thereof.

[0075] Please refer to Figure 1G Back gate 172 and back gate 174 can be formed in dielectric layer 168. A portion of back gate 172 may be located in recess R3, forming protrusion P1. A portion of back gate 174 may be located in recess R4, forming protrusion P2. Thus, back gate 172 and back gate 174 can be formed on back surface S2. Back gate 172 extends into drift region 102. Back gate 174 extends into drift region 104. Using the above method, dielectric layer 166 can be formed between back gate 172 and substrate 100, and between back gate 174 and substrate 100. Protrusion P1 can directly contact dielectric layer 166. Protrusion P2 can directly contact dielectric layer 166. In some embodiments, the materials of back gate 172 and back gate 174 are, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or combinations thereof.

[0076] Please refer to Figure 1H A dielectric layer 176 may be formed on the dielectric layer 168, via 170, back gate 172, and back gate 174. In some embodiments, the material of the dielectric layer 176 is, for example, silicon oxide. In some embodiments, the dielectric layer 168 is formed by, for example, chemical vapor deposition.

[0077] Next, conductive layers 178 and 180 can be formed in dielectric layer 176. Thus, conductive layer 178 can be formed on back gate 172 and back gate 174, and conductive layer 180 can be formed on via 170. Conductive layer 178 is electrically connected to back gate 172 and back gate 174. Conductive layer 180 is electrically connected to via 170. In some embodiments, the materials of conductive layer 178 and conductive layer 180 are, for example, copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, or combinations thereof.

[0078] The following is through Figure 1H The semiconductor structure 10 of the above embodiment will be explained here. Furthermore, although the method for forming the semiconductor structure 10 is described using the above method as an example, the present invention is not limited thereto.

[0079] Please refer to Figure 1H The semiconductor structure 10 includes a substrate 100, a transistor element T1, a back gate 172, a back gate 174, and a dielectric layer 166. In some embodiments, the semiconductor structure 10 can be applied to a packaging structure for a three-dimensional integrated circuit (3D IC). The substrate 100 has a front side S1 and a back side S2 opposite to each other. In some embodiments, the substrate 100 may include a first region R1 and a second region R2. The transistor element T1 may be located in the first region R1. The transistor element T1 is located on the front side S1. In some embodiments, the transistor element T1 may be mirror-symmetric. For example, the transistor element T1 may be mirror-symmetric with respect to a central axis passing through the transistor element T1. The transistor element T1 includes a drift region 102 and a drift region 104. The drift region 102 and the drift region 104 are located in the substrate 100. In some embodiments, the semiconductor structure 10 may also include a transistor element T2. The transistor element T2 may be located in the second region R2. The transistor element T2 is located on the front side S1. Furthermore, transistors T1 and T2 have been described in detail in the above embodiments, and will not be repeated here.

[0080] A back gate 172 is located on the back surface S2. The back gate 172 extends into the drift region 102. A back gate 174 is located on the back surface S2. The back gate 174 extends into the drift region 104. The back electrode 172 may have a protrusion P1 extending into the drift region 102. The back electrode 174 may have a protrusion P2 extending into the drift region 104. The protrusion P1 may have a sidewall SW3 away from the protrusion P2. The protrusion P2 may have a sidewall SW4 away from the protrusion P1. In this embodiment, as... Figure 1H As shown, sidewall SW3 does not extend beyond sidewall SW1, and sidewall SW4 does not extend beyond sidewall SW2, but the present invention is not limited thereto. In other embodiments, such as Figure 2As shown, sidewall SW3 can be aligned with sidewall SW1, and sidewall SW4 can be aligned with sidewall SW2. In other embodiments, such as Figure 3 As shown, sidewall SW3 can extend beyond sidewall SW1, and sidewall SW4 can extend beyond sidewall SW2.

[0081] A dielectric layer 166 is located between the back gate 172 and the substrate 100, and between the back gate 174 and the substrate 100. The semiconductor structure 10 may also include a conductive layer 178. The conductive layer 178 is located on the back gate 172 and the back electrode 174. The conductive layer 178 is electrically connected to the back gate 172 and the back electrode 174. Furthermore, the remaining components in the semiconductor structure 10 can be described with reference to the above embodiments. In addition, the details of each component in the semiconductor structure 10 (e.g., materials and formation methods) have been described in detail in the above embodiments and will not be repeated here.

[0082] As can be seen from the above embodiments, in the semiconductor structure 10 and its manufacturing method, the back gate 172 extends into the drift region 102, and the back gate 174 extends into the drift region 104. Therefore, the breakdown voltage of the transistor element T1 and the on-resistance of the transistor element T1 can be increased and reduced by the back gate 172 and the back electrode 174.

[0083] In summary, in the semiconductor structure and manufacturing method of the above embodiments, the semiconductor structure includes a substrate, a transistor element, a first back gate, a second back gate, and a dielectric layer. The substrate has a front side and a back side opposite to each other. The transistor element is located on the front side. The transistor element includes a first drift region and a second drift region. The first drift region and the second drift region are located in the substrate. The first back gate is located on the back side. The first back gate extends into the first drift region. The second back gate is located on the back side. The second back gate extends into the second drift region. The dielectric layer is located between the first back gate and the substrate and between the second back gate and the substrate. Since the first back gate extends into the first drift region and the second back gate extends into the second drift region, the breakdown voltage of the transistor element and the on-resistance of the transistor element can be increased and reduced through the first back gate and the second back gate.

[0084] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A semiconductor structure, comprising: The base has a front and a back that are opposite to each other; A transistor element is located on the front side and includes a first drift region and a second drift region, wherein the first drift region and the second drift region are located in the substrate; A first back gate is located on the back side and extends into the first drift region; The second back gate is located on the back side and extends into the second drift region; as well as A dielectric layer is located between the first back gate and the substrate, and between the second back gate and the substrate.

2. The semiconductor structure as described in claim 1, further comprising: A conductive layer is located on the first back gate and the second back electrode, and is electrically connected to the first back gate and the second back electrode.

3. The semiconductor structure of claim 1, wherein the transistor element further comprises: The gate is located on the front side and above a portion of the first drift region and a portion of the second drift region; as well as A gate dielectric layer is located between the gate and the substrate.

4. The semiconductor structure as described in claim 3, wherein The first back electrode has a first protrusion extending into the first drift region, and The second back electrode has a second protrusion extending into the second drift region.

5. The semiconductor structure as claimed in claim 4, wherein... The gate has a first sidewall and a second sidewall that are opposite to each other. The first sidewall is located directly above the first drift region. The second sidewall is located directly above the second drift zone. The first protrusion has a third sidewall away from the second protrusion, and The second protrusion has a fourth sidewall that is away from the first protrusion.

6. The semiconductor structure as claimed in claim 5, wherein... The third sidewall does not extend beyond the first sidewall, and The fourth sidewall does not extend beyond the second sidewall.

7. The semiconductor structure as claimed in claim 5, wherein... The third sidewall is aligned with the first sidewall, and The fourth sidewall is aligned with the second sidewall.

8. The semiconductor structure as claimed in claim 5, wherein The third sidewall extends beyond the first sidewall, and The fourth sidewall extends beyond the second sidewall.

9. The semiconductor structure of claim 3, wherein the transistor element further comprises: The first isolation structure is located in the first drift region; as well as The second isolation structure is located in the second drift region, wherein The gate is located above a portion of the first isolation structure and a portion of the second isolation structure.

10. The semiconductor structure of claim 9, wherein the transistor element further comprises: The first doped region is located in the first drift region; as well as The second doped region is located in the second drift region, wherein the first isolation structure and the second isolation structure are located between the first doped region and the second doped region.

11. The semiconductor structure of claim 3, wherein the transistor element further comprises: The first well region and the second well region are located in the substrate on both sides of the gate, wherein the first drift region and the second drift region are located between the first well region and the second well region.

12. The semiconductor structure of claim 11, wherein the transistor element further comprises: The first doped region is located in the first well region; as well as The second doped region is located in the second well region.

13. The semiconductor structure of claim 11, wherein the transistor element further comprises: The third well region, wherein the first drift region, the second drift region, the first well region, and the second well region are located in the third well region.

14. The semiconductor structure of claim 1, wherein the transistor element is mirror-symmetric.

15. A method for manufacturing a semiconductor structure, comprising: A substrate is provided, wherein the substrate has a front side and a back side opposite to each other; A transistor element is formed on the front side, wherein the transistor element includes a first drift region and a second drift region, and the first drift region and the second drift region are located in the substrate; A first back gate and a second back gate are formed on the back side, wherein the first back gate extends into the first drift region, and the second back gate extends into the second drift region; and A first dielectric layer is formed between the first back gate and the substrate, and between the second back gate and the substrate.

16. The method for manufacturing a semiconductor structure as claimed in claim 15, wherein the method for forming the first dielectric layer comprises: The back surface is patterned to form a first recess and a second recess, wherein the first recess exposes the first drift region and the second recess exposes the second drift region; as well as The first dielectric layer is conventionally formed on the back surface and in the first and second recesses.

17. The method for manufacturing a semiconductor structure as described in claim 16, wherein... The first depression extends into the first drift region, and The second depression extends into the second drift region.

18. The method for manufacturing a semiconductor structure as claimed in claim 16, wherein the method for forming the first back gate and the second back gate comprises: A second dielectric layer is formed on the first dielectric layer, wherein the second dielectric layer fills the first recess and the second recess; as well as The first back gate and the second back gate are formed in the second dielectric layer, wherein a portion of the first back gate is located in the first recess and a portion of the second back gate is located in the second recess.

19. The method for manufacturing a semiconductor structure as described in claim 18, further comprising: A conductive layer is formed on the first back gate and the second back gate, wherein the conductive layer is electrically connected to the first back gate and the second back gate.

20. The method for manufacturing a semiconductor structure as claimed in claim 19, wherein the method for forming the conductive layer comprises: A third dielectric layer is formed on the second dielectric layer, the first back gate, and the second back gate; as well as The conductive layer is formed in the third dielectric layer.

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