Integrated circuit with gate plugs for inducing compression channel strain
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-23
- Publication Date
- 2026-08-14
Smart Images
Figure CN122579696A_ABST
Abstract
Description
Technical Field
[0001] The disclosed embodiments are in the field of advanced integrated circuit structure fabrication, and particularly in the field of integrated circuits that use gate plugs to induce compressive channel strain. Background Technology
[0002] For decades, the scaling of features in integrated circuits has been a driving force behind the ever-growing semiconductor industry. Scaling down features to increasingly smaller sizes enables increased density of functional units on the limited real estate of a semiconductor chip. For example, shrinking transistor size allows for the combination of an increased number of memory or logic devices on a single chip, facilitating the manufacture of products with increased capacity. However, this drive for ever-increasing capacity is not without its challenges. The need to optimize the performance of each device becomes increasingly important. The embodiments of this disclosure address these and other problems. Attached Figure Description
[0003] Figure 1A and Figure 1B This is a cross-sectional view of an integrated circuit (IC) structure according to an embodiment of the present disclosure.
[0004] Figure 2 Examples of computing devices according to various disclosed embodiments are illustrated.
[0005] Figure 3 Examples of interposers, including one or more of the disclosed embodiments, are illustrated. Detailed Implementation
[0006] In some embodiments, an integrated circuit is described that uses gate plugs to induce compressive channel strain. In the following description, numerous specific details, such as specific integration and material systems, are set forth in order to provide a thorough understanding of embodiments of this disclosure. It will be apparent to those skilled in the art that embodiments of this disclosure may be practiced without these specific details. In other instances, well-known features such as integrated circuit design layouts have not been described in detail so as not to unnecessarily obscure embodiments of this disclosure. Furthermore, it should be appreciated that the various embodiments illustrated in the drawings are illustrative representations and are not necessarily drawn to scale.
[0007] The following detailed description is illustrative in nature only and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as being more preferred or advantageous than other implementations. Furthermore, there is no intention to be bound by any express or implied theory presented in the foregoing technical field, background art, summary of the invention, or the following detailed description.
[0008] This specification includes references to "one embodiment" or "embodiment". The appearance of the phrase "in one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.
[0009] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure (including the appended claims): "Comprising". This term is open-ended. As used in the appended claims, this term does not exclude additional structures or operations.
[0010] "Configured to". Various units or components can be described or required to be "configured to" perform one or more tasks. In such a context, "configured to" is used to imply a structure by indicating that the unit or component includes a structure that performs those tasks or tasks during operation. Thus, a unit or component can be said to be configured to perform a task even when the specified unit or component is not currently operational (e.g., not on or active). The statement that a unit or circuit or component is "configured to" perform one or more tasks is not expressly intended to invoke 35 USC §112, sixth paragraph for that unit or component.
[0011] "First," "second," etc. As used in this article, these terms are used as labels preceding nouns and do not imply any type of order (e.g., spatial, temporal, logical, etc.).
[0012] "Coupled" - The following description means that elements, nodes, or features are "coupled" together. As used herein, unless otherwise expressly stated, "coupled" means that one element, node, or feature is directly or indirectly connected to (or directly or indirectly connected to) another element, node, or feature, and not necessarily in a mechanical way.
[0013] Additionally, certain terms may be used in the following description for reference only, and some terms are therefore not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” and “below” refer to orientation in the referenced figures. Terms such as “front,” “rear,” “rear,” “side,” “outer,” and “inner” describe the orientation or position, or both, of a part of a component within a consistent but arbitrary frame of reference that will become clear from the text of the component discussed in the reference description and the associated figures. Such terms may include the words specifically mentioned above, their derivatives, and words with similar meanings.
[0014] "Suppression"—as used in this article—is used to describe reducing or minimizing an effect. When a component or feature is described as suppressing an action, movement, or condition, it completely prevents the result or outcome or future state. Additionally, "suppression" can also refer to reducing or mitigating an outcome, performance, or effect that might otherwise occur. Therefore, when a component, element, or feature is described as suppressing a result or state, it does not necessarily mean that it completely prevents or eliminates the result or state.
[0015] The embodiments described herein pertain to front-end process (FEOL) semiconductor processing and structures. FEOL is the first part of integrated circuit (IC) fabrication, in which various devices (e.g., transistors, capacitors, resistors, etc.) are patterned in a semiconductor substrate or layer. FEOL typically covers everything up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).
[0016] The embodiments described herein pertain to back-to-the-line (BEOL) semiconductor processing and structures. BEOL is the second part of IC fabrication, where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, such as metallization layers or multiple metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal layers, and bonding areas for chip-to-package connections. During the fabrication phase of BEOL, contacts (pads), interconnect wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers can be added to the BEOL.
[0017] The embodiments described below are applicable to FEOL processing and structure, BEOL processing and structure, or both FEOL and BEOL processing and structure. Specifically, while an exemplary processing scheme can be illustrated using a FEOL processing scenario, such a method is also applicable to BEOL processing. Similarly, while an exemplary processing scheme can be illustrated using a BEOL processing scenario, such a method is also applicable to FEOL processing.
[0018] One or more embodiments can be implemented to realize 3D ferroelectric RAM (FRAM, FeRAM, or F-RAM), potentially increasing the monolithic integration of back-end logic plus memory in SoCs for future technology nodes. For context, FRAM is a random access memory built similarly to DRAM, but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility. Conventionally, both FRAM and DRAM are transistor (1T) / capacitor (1C) cell arrays, where each cell includes an access transistor coupled to a single capacitor at the front end. The capacitor may be coupled to a higher bit line (COB) in the stack in the semiconductor back end.
[0019] As described above, one performance problem faced by integrated circuit devices relates to insufficient transistor performance due to limited channel mobility. As described below, embodiments of this disclosure help improve such channel mobility by providing a fin trimmed isolation (FTI) plug (also referred to as a gate plug) that includes a compressed film to apply compressive strain in the active channel.
[0020] Among other things, the embodiments disclosed herein also help improve channel mobility and enhance transistor performance. The disclosed embodiments can also be patterned separately for NMOS and PMOS to make them compatible with CMOS processes. The disclosed embodiments are also applicable to any non-planar transistor, such as a FinFET, a fork-type transistor, or a gate-all-around (GAA) transistor.
[0021] Figure 1A and Figure 1B It is a cross-section of an IC structure according to various embodiments. Figure 1A Examples of GAA or fork-plate structures are illustrated, while Figure 1B An example of a FinFET structure is illustrated. Embodiments of this disclosure can also be used with any other suitable nonplanar transistor configuration.
[0022] exist Figure 1A In the example shown, device 100 includes a substrate layer 118 and a pair of epitaxial layers 109 coupled to the substrate layer 118. A pair of fin trimmed isolation (FTI) plugs 114 are coupled to the substrate layer 118 and include a compressed film. Gate spacer layers 104 are disposed between the respective FTI plugs 114 and their respective adjacent epitaxial layers 109.
[0023] exist Figure 1A (Illustration of GAA or fork-type example) In this example, a silicon channel 112 is arranged between two epitaxial layers 109 and coupled to a work function metal (WFM) 102, which in turn is coupled to a high-k dielectric material 110. Figure 1B(Illustrating a FinFET example) In this example, a channel 130 is disposed between two epitaxial layers 109. The epitaxial layers 109 are coupled to a contact metal region 108 and a dielectric layer 106. In some embodiments, the high-k dielectric material 110 includes HfO2, ZrO2, or TiO2.
[0024] exist Figure 1A and 1B In both cases, the compression film of the FTI plug 114 is adapted to apply a compressive strain 116 from the respective FTI plug 114 outward to their respective channels 112, 130. The FTI plug 114 may comprise any suitable compression material or combination of materials. For example, in some embodiments, the compression film comprises SiGe, SiO, SiN, or AlN.
[0025] In some embodiments, the compressive strain measured in channels 112, 130 will be negatively correlated with the distance between the FTI plug 114 and channels 112, 130. The closer the FTI plug is to the channel, the greater its ability to apply compressive strain in the channel.
[0026] In some embodiments, the thin film properties in the FTI plug near the PMOS device and the thin film properties in another FTI plug near the NMOS device can be different. For example, the PMOS-FTI plug can be tuned using relatively compressed materials such as SiGe, SiO, SiN, and AlN, and the NMOS-FTI can be composed of a stretched thin film.
[0027] Implementations of embodiments of the invention can be formed or performed on a substrate such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or a silicon-on-insulator substructure. In other implementations, alternative materials may be used to form the semiconductor substrate, which may or may not be bonded to silicon. These alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. While several examples of materials on which substrates can be formed are described herein, any material that can be used as the basis on which semiconductor devices can be built is within the spirit and scope of the invention.
[0028] Multiple transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs or simply MOS transistors), can be fabricated on a substrate. In various implementations of the invention, the MOS transistor can be a planar transistor, a non-planar transistor, or a combination of both. Non-planar transistors include FinFET transistors such as dual-gate and tri-gate transistors, and gate-around or all-around transistors such as nanoribbon and nanowire transistors. While the implementations described herein may only illustrate planar transistors, it should be noted that the invention can also be implemented using non-planar transistors.
[0029] Each MOS transistor includes a gate stack formed of at least two layers: a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include a single layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide (SiO2), and / or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using a high-k material, an annealing process may be performed on the gate dielectric layer to improve its quality.
[0030] A gate electrode layer is formed on the gate dielectric layer, and depending on whether the transistor is a PMOS or NMOS transistor, the gate electrode layer may consist of at least one P-type work function metal or an N-type work function metal. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, wherein one or more metal layers are work function metal layers and at least one metal layer is a filler metal layer.
[0031] For PMOS transistors, metals that can be used as gate electrodes include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides such as ruthenium oxide. A P-type metal layer enables the formation of PMOS gate electrodes with a work function between approximately 4.9 eV and approximately 5.2 eV. For NMOS transistors, metals that can be used as gate electrodes include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer enables the formation of NMOS gate electrodes with a work function between approximately 3.9 eV and approximately 4.2 eV.
[0032] In some implementations, the gate electrode may be composed of a U-shaped structure, the U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and excluding the sidewall portions substantially perpendicular to the top surface of the substrate. In yet another implementation of the invention, the gate electrode may be composed of a combination of U-shaped structures and planar non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.
[0033] In some implementations of the invention, a pair of sidewall spacers for mounting the gate stack can be formed on opposite sides of the gate stack. The sidewall spacers can be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and typically include deposition and etching steps. In alternative implementations, multiple pairs of spacers can be used; for example, two, three, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack.
[0034] As is known in the art, source and drain regions are formed within a substrate adjacent to the gate stack of each MOS transistor. Typically, either an implantation / diffusion process or an etching / deposition process is used to form the source and drain regions. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic are implanted into the substrate to form the source and drain regions. An annealing process, which activates the dopant and promotes its further diffusion into the substrate, typically follows the ion implantation process. In the latter process, the substrate is first etched to form trenches at the locations of the source and drain regions. An epitaxial deposition process is then performed to fill the trenches using the material used to form the source and drain regions. In some implementations, silicon alloys such as silicon-germanium or silicon carbide are used to form the source and drain regions. In some implementations, epitaxially deposited silicon alloys are in-situ doped with dopant such as boron, arsenic, or phosphorus. In other embodiments, one or more alternative semiconductor materials such as germanium or group III-V materials or alloys are used to form the source and drain regions. In another embodiment, one or more layers of metal and / or metal alloy may be used to form the source and drain regions.
[0035] One or more interlayer dielectrics (ILDs) are deposited over a MOS transistor. ILD layers can be formed using dielectric materials known for their suitability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that can be used include, but are not limited to, silicon dioxide (SiO2), carbon-doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicones such as silsesquioxanes, siloxanes, or organosilicon glasses. ILD layers may include pores or air gaps to further reduce their dielectric constant.
[0036] Figure 2 A computing device 200 according to one implementation of the invention is described. The computing device 200 houses a board 202. The board 202 may include multiple components, including but not limited to a processor 204 and at least one communication chip 206. The processor 204 is physically and electrically coupled to the board 202. In some implementations, at least one communication chip 206 is also physically and electrically coupled to the board 202. In other implementations, the communication chip 206 is part of the processor 204.
[0037] Depending on its application, computing device 200 may include other components that may or may not be physically and electrically coupled to board 202. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touch screen display, touch screen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (such as hard disk drives, optical discs (CDs), digital versatile optical discs (DVDs), etc.).
[0038] Communication chip 206 enables wireless communication for the transmission of data to and from computing device 200. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated apparatus does not contain any wires, although in some embodiments they may not contain any wires. Communication chip 206 can implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocol designated as 3G, 4G, 5G, and above. Computing device 200 may include multiple communication chips 206. For example, the first communication chip 206 can be dedicated to shorter-range wireless communication such as Wi-Fi and Bluetooth, and the second communication chip 206 can be dedicated to longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.
[0039] The processor 204 of the computing device 200 includes an integrated circuit die packaged within the processor 204. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices such as MOS-FET transistors constructed according to implementations of the invention. The term "processor" can refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.
[0040] The communication chip 206 also includes an integrated circuit die packaged within the communication chip 206. According to another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices such as a MOS-FET transistor constructed according to an implementation of the invention.
[0041] In another implementation, another component housed within the computing device 200 may comprise an integrated circuit die, which includes one or more devices such as a MOS-FET transistor constructed according to an implementation of the invention.
[0042] In various implementations, computing device 200 may be a laptop computer, netbook, notebook computer, ultrabook, smartphone, tablet computer, personal digital assistant (PDA), super mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other implementations, computing device 200 may be any other electronic device that processes data.
[0043] Figure 3 An interposer 300, comprising one or more embodiments of the invention, is described. The interposer 300 is an intermediary substrate used to bridge a first substrate 302 to a second substrate 304. The first substrate 302 may be, for example, an integrated circuit die. The second substrate 304 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Typically, the purpose of the interposer 300 is to extend connections to a wider pitch or to rewire connections to different connections. For example, the interposer 300 may couple an integrated circuit die to a ball grid array (BGA) 306, which may then be coupled to the second substrate 304. In some embodiments, the first and second substrates 302 / 304 are attached to opposite sides of the interposer 300. In other embodiments, the first and second substrates 302 / 304 are attached to the same side of the interposer 300. And in yet another embodiment, three or more substrates are interconnected via the interposer 300.
[0044] Intermediate layer 300 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymeric material such as polyimide. In another implementation, intermediate layer 300 may be formed of alternative rigid or flexible material, which may include the same materials described above for use with semiconductor substrates, such as silicon, germanium, and other group III-V and IV materials.
[0045] Interposer 300 may include metal interconnects 308 and vias 310, including but not limited to through-silicon vias (TSVs) 312. Interposer 300 may further include embedded devices 314, which may include both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on interposer 300. According to embodiments of the invention, the devices or processes disclosed herein can be used in the fabrication of interposer 300.
[0046] While specific embodiments have been described above, these embodiments are not intended to limit the scope of this disclosure, even though only a single embodiment is described with respect to a particular feature. Unless otherwise stated, the examples of features provided in the disclosure are intended to be illustrative and not restrictive. The above description is intended to cover alternatives, modifications, and equivalents as will be apparent to those skilled in the art who will benefit from this disclosure.
[0047] The scope of this disclosure includes any feature or combination of features, or any generalization thereof, disclosed herein (either explicitly or implicitly), whether or not it alleviates any or all of the problems addressed herein. Therefore, during the examination of this application (or an application claiming priority thereto), any such combination of features may be expressly expressed as a new claim. In particular, with reference to the appended claims, features from dependent claims may be combined with features from independent claims, and features from the respective independent claims may be combined in any suitable manner and not merely in the specific combinations listed in the appended claims.
[0048] The following examples are alternative embodiments. Various features of different embodiments, including some features and excluding others, can be combined in different ways to suit a wide variety of applications.
[0049] Example embodiment 1 includes an integrated circuit structure comprising: a substrate layer; an epitaxial layer coupled to the substrate layer; a fin trimmed isolation (FTI) plug including a compressed thin film; and a gate spacer layer between the FTI plug and the epitaxial layer.
[0050] Example 2 includes an integrated circuit structure of Example 1 or other examples herein, wherein the compression film of the FTI plug is subjected to compressive strain outward from the FTI plug.
[0051] Example embodiment 3 includes an integrated circuit structure of example embodiment 1 or other examples herein, wherein the compressed thin film includes: SiGe, SiO, SiN or AlN.
[0052] Example 4 includes an integrated circuit structure of Example 1 or other examples herein, wherein the integrated circuit structure includes non-planar transistors.
[0053] Example 5 includes an integrated circuit structure of Example 4 or other examples herein, wherein the non-planar transistor is a fin field-effect transistor (FinFET), a fork-type transistor, or a gate-all-around (GAA) transistor.
[0054] Example embodiment 6 includes an integrated circuit structure of example embodiment 5 or other examples herein, wherein the integrated circuit structure further includes a silicon channel coupled to an epitaxial layer.
[0055] Example embodiment 7 includes an integrated circuit structure of example embodiment 6 or other examples herein, wherein the nonplanar transistor is a fork-type transistor or a GAA transistor, and wherein the integrated circuit structure further includes a work function metal coupled to a silicon channel.
[0056] Example 8 includes an integrated circuit structure of Example 7 or other examples herein, further including a high-k dielectric material coupled to a work function metal.
[0057] Example 9 includes an integrated circuit structure of Example 8 or other examples herein, wherein the high-k dielectric material includes HfO2, ZrO2 or TiO2.
[0058] Example embodiment 10 includes an integrated circuit structure comprising: a substrate layer; a first epitaxial layer coupled to the substrate layer; a second epitaxial layer coupled to the substrate layer; a first fin trimmed isolation (FTI) plug including a compressed thin film; a second FTI plug including a compressed thin film; and a silicon channel between the first epitaxial layer and the second epitaxial layer, wherein the first epitaxial layer is between the first FTI plug and the silicon channel, and wherein the second epitaxial layer is between the second FTI plug and the silicon channel.
[0059] Example embodiment 11 includes an integrated circuit structure of example embodiment 10 or other examples herein, wherein the compression films of the first FTI plug and the second FTI plug are subjected to corresponding compressive strains outward from the respective FTI plugs.
[0060] Example embodiment 12 includes an integrated circuit structure of example embodiment 10 or other examples herein, wherein the compressed thin film includes: SiGe, SiO, SiN or AlN.
[0061] Example embodiment 13 includes an integrated circuit structure of example embodiment 10 or other examples herein, wherein the integrated circuit structure includes a non-planar transistor, which is a fin field-effect transistor (FinFET), a fork-type transistor, or a gate-all-around (GAA) transistor.
[0062] Example embodiment 14 includes an integrated circuit structure of example embodiment 13 or other examples herein, wherein the nonplanar transistor is a GAA or fork-type transistor, and wherein the integrated circuit structure further includes a work function metal coupled to a silicon channel.
[0063] Example embodiment 15 includes an integrated circuit structure of example embodiment 14 or other examples herein, further including a high-k dielectric material coupled to a work function metal.
[0064] Example 16 includes an integrated circuit structure of Example 15 or other examples herein, wherein the high-k dielectric material includes HfO2, ZrO2 or TiO2.
[0065] Example embodiment 17 includes a computing device comprising: a board; and components coupled to the board, the components including an integrated circuit structure, the integrated circuit structure including: a substrate layer; an epitaxial layer coupled to the substrate layer; a fin trimmed isolation (FTI) plug including a compressed thin film; and a gate spacer layer between the FTI plug and the epitaxial layer.
[0066] Example embodiment 18 includes a computing device of example embodiment 17 or other examples herein, and further includes: a processor coupled to the board, a communication chip coupled to the board, or a camera coupled to the board.
[0067] Example embodiment 19 includes a computing device comprising: a board; and components coupled to the board, the components including an integrated circuit structure, the integrated circuit structure including: a substrate layer; a first epitaxial layer coupled to the substrate layer; a second epitaxial layer coupled to the substrate layer; a first fin trimmed isolation (FTI) plug including a compressed thin film; a second FTI plug including a compressed thin film; and a silicon channel between the first epitaxial layer and the second epitaxial layer, wherein the first epitaxial layer is between the first FTI plug and the silicon channel, and wherein the second epitaxial layer is between the second FTI plug and the silicon channel.
[0068] Example embodiment 20 includes a computing device of example embodiment 19 or other examples herein, further including: a processor coupled to the board, a communication chip coupled to the board, or a camera coupled to the board.
Claims
1. An integrated circuit structure (100) including a gate-all-around structure, comprising: First epitaxial layer (109); A second epitaxial layer (109) that is laterally separated from the first epitaxial layer; A silicon channel (112) is laterally located between the first epitaxial layer and the second epitaxial layer. Gate stacking surrounding the silicon channel; First gate spacer (104) adjacent to the first side of the gate stack. A second gate spacer (104) is located adjacent to a second side of the gate stack, the second side being opposite to the first side; A first fin trimming isolation plug (114) is located on one side of the first epitaxial layer, the first fin trimming isolation plug comprising silicon and nitrogen; The first contact metal region (108) on the first epitaxial layer has a top surface that is at the same level as the top surface of the first fin trimming isolation structure. A second fin trimming isolation plug (114) is located on one side of the second epitaxial layer, the second fin trimming isolation plug comprising silicon and nitrogen; as well as The second contact metal region (108) on the second epitaxial layer has a top surface that is at the same level as the top surface of the second fin trimming isolation structure.
2. The integrated circuit structure according to claim 1, further comprising: The third gate spacer (104) is laterally located between the first fin trimming isolation plug (114) and the first contact metal region (108); as well as The fourth gate spacer (104) is laterally located between the second fin trimming isolation plug (114) and the second contact metal region (108).
3. The integrated circuit structure according to claim 2, further comprising: A fifth gate spacer (104) adjacent to the first fin trimmed isolation plug (114), wherein the first fin trimmed isolation plug is laterally located between the fifth gate spacer and the third gate spacer (104); and A sixth gate spacer (104) adjacent to the second fin trimmed isolation plug (114), wherein the second fin trimmed isolation plug is laterally located between the sixth gate spacer and the fourth gate spacer (104).
4. The integrated circuit structure according to claim 2 or 3, wherein, The third gate spacer (104) has a top surface that is at the same level as the top surface of the first fin trimming isolation plug (114), and the fourth gate spacer (104) has a top surface that is at the same level as the top surface of the second fin trimming isolation plug (114).
5. The integrated circuit structure according to any one of the preceding claims, wherein, The first fin trimming isolation plug (114) has a top surface that is at the same level as the top surface of the second fin trimming isolation plug (114).
6. The integrated circuit structure according to any one of the preceding claims, wherein, The first gate spacer (104) has a top surface that is at the same level as the top surface of the gate stack, and the second gate spacer (104) has a top surface that is at the same level as the top surface of the gate stack.
7. The integrated circuit structure according to any one of the preceding claims, wherein, The first gate spacer (104) has a top surface that is at the same level as the top surface of the second gate spacer (104).
8. The integrated circuit structure according to any one of the preceding claims, wherein, The first fin trimming isolation plug (114) and the second fin trimming isolation plug (114) provide stress to the silicon channel.
9. A method for manufacturing an integrated circuit structure including a gate-all-around structure, the method comprising: The first epitaxial layer (109) is formed. A second epitaxial layer (109) is formed that is laterally separated from the first epitaxial layer. A silicon channel (112) is formed laterally between the first epitaxial layer and the second epitaxial layer. A gate stack is formed around the silicon channel; A first gate spacer (104) is formed adjacent to the first side of the gate stack. A second gate spacer (104) is formed adjacent to a second side of the gate stack, the second side being opposite to the first side; A first fin trimming isolation plug (114) is formed on one side of the first epitaxial layer, the first fin trimming isolation plug comprising silicon and nitrogen; A first contact region (108) comprising metal is formed on the first epitaxial layer. The first contact region comprises metal having a top surface at the same level as the top surface of the first fin trimming isolation structure. A second fin trimming isolation plug (114) is formed on one side of the second epitaxial layer, the second fin trimming isolation plug comprising silicon and nitrogen; as well as A second contact region (108) comprising metal is formed on the second epitaxial layer. The second contact region comprises metal having a top surface at the same level as the top surface of the second fin trimming isolation structure.