A metal XPS structure based on an organic-layer-free design and its preparation method

Abstract

This invention relates to a metal XPS structure based on an organic-layer-free design and its fabrication method, belonging to the field of thin-film transistor liquid crystal display technology. Based on ORG skip and metal-3 design, the main and secondary gap materials in the back-channel etched TFT and top-gate TFT structures are both XPS structures. The top-gate structure can add intermediate gap materials to form three height differences. The height difference of the gap materials is directly and precisely controlled by the thickness of the array-side metal layer, which gets rid of the precision limitations of half-masking and etching in traditional PS processes. At the same time, it optimizes the pixel arrangement to reduce aperture ratio loss. The fabrication process of this invention is compatible with existing panel manufacturing processes, can significantly improve screen pressing stability, adapt to different support requirements of the display area and surrounding areas, and effectively improve the reliability and production yield of the liquid crystal panel structure.

Description

Technical Field

[0001] This invention belongs to the field of thin-film transistor liquid crystal display technology, and relates to a metal XPS structure based on an organic-layer-free design and its preparation method. Background Technology

[0002] A liquid crystal display (LCD) consists of an array and a color filter (CF). Liquid crystal fills the space between the array and the CF, and photo spacer (PS) supports the array and CF, ensuring the thickness of the liquid crystal layer. The photo spacer is divided into a main PS and a sub PS, with the main PS being taller and the sub PS shorter. Conventional PSs are columnar in shape and made of photoresist (PR). The height difference between the main PS and sub PS is achieved through different exposure levels of a half-tone mask. However, the overall consistency is limited by the CF exposure machine and etching effects, resulting in significant height errors in the PS. The XPS design splits the PS into two segments, one on the array side and one on the CF side, and changes the columnar shape to a strip shape, with the PS strips on the array and CF sides perpendicular to each other. This gives the main PS a cross-shaped top view, known as the XPS. In the XPS design, the main PS can be replaced with an XPS structure, or the sub PS can be replaced with an XPS structure.

[0003] The array includes designs for ORG skip and metal-3. ORG skip means no organic layer, while metal-3 means an additional metal layer is deposited on top of the common electrode layer. Since bottom-gate TFTs (thin-film transistors) generally only have two metal layers, this design is called metal-3.

[0004] Traditional XPS designs have significant technical drawbacks: typically only one of the main PS and sub PS materials uses an XPS design, and the main PS and sub PS can only achieve a single height difference, failing to accommodate multiple height differences. Furthermore, the PS height difference relies on half-mask exposure and etching processes for control, resulting in poor precision and difficulty in ensuring uniform liquid crystal layer thickness. In this application, the PS height difference no longer depends on the half-mask exposure on the CF side, but is controlled by the metal deposition thickness on the Array side. Both the main PS and sub PS employ XPS structures, and different PS height differences can be achieved simultaneously. Summary of the Invention

[0005] The purpose of this invention is to provide a metal XPS structure based on an organic layer-free design and its preparation method. Based on the ORG skip and metal-3 structures, the main and secondary gap materials are all XPS structures. The metal layer thickness is precisely controlled to adapt to multiple height requirements, thereby improving the screen's pressing stability, height control accuracy, and panel adaptability. At the same time, the use of a semi-mask is eliminated during PS manufacturing, reducing production costs.

[0006] The objective of this invention can be achieved through the following technical solutions: A method for fabricating a metal XPS structure based on an organic-layer-free design includes the following steps: Using an organic layer-free (ORG skip) design, a metal XPS structure is fabricated on a TFT array substrate by depositing a metal layer, an insulating layer, an active layer, and an electrode layer. The metal XPS structure includes a main gap material (main PS) and a sub gap material (sub PS), and both the main PS and sub PS are cross-shaped XPS structures. The height difference between the main PS and sub PS is directly controlled by the retention or removal state of the metal layer on the array side. The TFT array substrate is any one of the following: back channel etched TFT substrate, self-aligned top gate TFT substrate, or bottom contact top gate TFT substrate.

[0007] Furthermore, the TFT array substrate is a back-channel etched TFT (BCE TFT) substrate, and during fabrication, the main PS area retains the gate metal layer, gate insulating layer, source and drain metal layers, passivation layer one, common electrode layer, metal-3 layer and passivation layer two.

[0008] At the sub PS, the gate insulating layer, source / drain metal layer, passivation layer one, common electrode layer, metal-3 layer, and passivation layer two are retained, while the pixel electrode layer and active layer are removed at both the main PS and sub PS.

[0009] Furthermore, the gate metal layer is Ti / Cu (titanium / copper, indicating that the layer is a double-layer structure, with Ti deposited first and Cu deposited later, the same meaning is used in the following text), the source and drain metal layers are MoNb / Cu (molybdenum / niobium), and the metal-3 layer is Cu.

[0010] Furthermore, the TFT array substrate is a self-aligned top-gate TFT substrate, and during fabrication, the main PS area retains a light-blocking layer, a buffer layer, a gate insulating layer, a gate metal layer, an intermediate layer, a source / drain metal layer, a passivation layer one, a common electrode layer, a metal-3 layer, and a passivation layer two.

[0011] The sub PS layer retains a light-blocking layer, a buffer layer, a gate insulating layer, a gate metal layer, an intermediate layer, a passivation layer 1, a common electrode layer, a metal-3 layer, and a passivation layer 2.

[0012] At the mid PS, the buffer layer, gate insulating layer, gate metal layer, intermediate layer, passivation layer one, common electrode layer, metal-3 layer, and passivation layer two are retained. The pixel electrode layer and active layer are removed at the main PS, sub PS, and mid PS, forming a three-gradient metal XPS structure of main PS, sub PS, and mid PS.

[0013] The light-blocking layer is Ti / Cu, the gate metal layer is MoNb / Cu, the source and drain metal layers are MoNb / Cu, and the metal-3 layer is Cu.

[0014] Furthermore, the TFT array substrate is a bottom-contact top-gate TFT substrate, and during fabrication, a light-blocking layer, a buffer layer, a gate insulating layer, a gate metal layer, an intermediate layer, a common electrode layer, a metal-3 layer, and a passivation layer are retained at the main PS.

[0015] The sub PS layer retains a buffer layer, a gate insulating layer, a gate metal layer, an intermediate layer, a common electrode layer, a metal-3 layer, and a passivation layer 2.

[0016] The buffer layer, active layer, gate insulating layer, gate metal layer, intermediate layer, common electrode layer, metal-3 layer and passivation layer 2 are retained at the mid PS; the active layer is retained at the mid PS; the active layer is removed at the main PS and sub PS; the common electrode layer and metal-3 layer are retained at the main PS, sub PS and mid PS, forming a three-gradient metal XPS structure.

[0017] Furthermore, no metal-3 layer is placed above the common electrode layer, and a simplified metal layer structure without metal-3 is used to prepare three-gradient metal XPS.

[0018] Furthermore, the active layer is IGZO.

[0019] Furthermore, the electrode layer is ITO.

[0020] Furthermore, the metal layer and electrode layer are both prepared by PVD (physical vapor deposition), and the insulating layer is prepared by PECVD (plasma-enhanced chemical vapor deposition). The film patterning is achieved by coating, exposure, development, wet etching, dry etching, and photoresist stripping.

[0021] Furthermore, the active layer is subjected to a mixed plasma conductive treatment of argon and helium, so that the active layer below the gate metal layer retains its semiconductor properties, while the remaining area becomes a conductor.

[0022] Furthermore, overlap holes are opened above the metal layer or active layer to achieve electrode layer overlap. After the electrode layer is patterned, it is annealed. The passivation layer 2 uses SiNx as the pixel capacitor dielectric.

[0023] A metal XPS structure based on an organic-free design is used in the array substrate of a thin-film transistor liquid crystal display panel, including a main gap material (main PS), a sub gap material (sub PS), and an optional intermediate gap material (mid PS). Both the main PS and sub PS are cross-shaped metal XPS structures, formed by stacking metal layers, insulating layers, and electrode layers on the array side. The XPS on the array side does not contain organic materials. The metal XPS structure is compatible with three substrate structures: back-channel etched TFT, self-aligned top-gate TFT, and bottom-contact top-gate TFT. It can have or not have a third metal layer (metal-3) above the common electrode layer and can form a dual-gradient or triple-gradient height difference.

[0024] The beneficial effects of this invention are: 1. This invention is based on ORG skip and metal-3 structure design, so that both the main PS and sub PS adopt XPS structure. The PS strips on the Array side and CF side intersect each other perpendicularly to form a cross support. Compared with the traditional XPS solution, it greatly improves the support stability and force uniformity of the display screen when pressed, effectively improves the screen pressure resistance and touch reliability. The layout of 4 adjacent TFTs sharing one PS reduces the impact of PS on aperture ratio.

[0025] 2. This invention directly controls the height difference between the main PS, sub PS (and mid PS) by controlling the thickness of the metal layer on the array side. It abandons the traditional method of adjusting the height difference through PS half-mask exposure and etching, and is not limited by the precision of CF exposure machine and etching process. The PS height difference control is more precise, ensuring the consistency of liquid crystal layer thickness, improving the yield of display panels, and reducing production costs.

[0026] 3. In the top and bottom gate TFT structures, regardless of whether the metal-3 process is used, the present invention can realize the differentiated design of three PS heights: mainPS, midPS, and subPS. It can flexibly adapt to the different requirements of the effective display area and the surrounding area of ​​the screen for the height of the gap material, take into account the support performance of the display area and the surrounding area, and improve the overall structural adaptability and practicality of the panel. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the BCE TFT structure of ORG skip and metal-3 in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the main PS structure under the BCE structure in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the first design of the sub PS under the BCE structure in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the second design of the sub PS under the BCE structure in Embodiment 1 of the present invention; Figure 5 This is a schematic diagram of the TFT arrangement and PS layout on the Array side of the BCE structure in Embodiment 1 of the present invention; Figure 6 This is a schematic diagram showing the alignment of the PS on the Array side and the PS on the CF side of the BCE structure in Embodiment 1 of the present invention. Figure 7 This is a schematic diagram of the structure of the ORG skip and metal-3 self-aligned top gate TFT in Embodiment 2 of the present invention; Figure 8 This is a schematic diagram of the pixel arrangement of the self-aligned top gate structure and the position of the PS in Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of the self-aligned top grid structure main PS in Embodiment 2 of the present invention; Figure 10 This is a schematic diagram of the self-aligned top grid structure sub PS in Embodiment 2 of the present invention; Figure 11 This is a schematic diagram of the self-aligned top grid structure mid PS in Embodiment 2 of the present invention; Figure 12 This is a schematic diagram of the bottom contact top gate TFT of ORG skip and metal-3 in Embodiment 3 of the present invention; Figure 13 This is a schematic diagram of the pixel arrangement and PS position of the bottom contact top gate structure in Embodiment 3 of the present invention; Figure 14 This is a schematic diagram of the main PS structure in the bottom contact top grid of Embodiment 3 of the present invention; Figure 15 This is a schematic diagram of the bottom contact top grid structure mid PS in Embodiment 3 of the present invention; Figure 16 This is a schematic diagram of the bottom contact top grid structure sub PS in Embodiment 3 of the present invention; Figure 17 This is a schematic diagram of the main PS, a bottom contact top grid structure without metal-3, according to the present invention. Figure 18 This is a schematic diagram of the metal-3-free bottom contact top grid structure mid PS of the present invention; Figure 19 This is a schematic diagram of the metal-3-free bottom contact top grid structure (sub PS) of the present invention. Figure 20 This is a schematic diagram of the main PS structure of the metal-3-free BCE structure of the present invention; Figure 21 This is a schematic diagram of the mid PS of the metal-3-free BCE structure of the present invention; Figure 22 This is a schematic diagram of the subPS of the metal-3-free BCE structure of the present invention. Detailed Implementation

[0028] To further illustrate the technical means and effects of the present invention in achieving the intended purpose, the following detailed description of the specific implementation methods, features and effects of the present invention, in conjunction with preferred embodiments, is provided below.

[0029] Example 1: This example provides a metal XPS structure (BCE structure) based on an organic-layer-free design, which is prepared through the following steps: S1: The first metal layer -1 is deposited on the glass substrate using PVD (Physical Vapor Deposition), i.e. Figure 1 The gate metal layer shown has a thickness of 400nm. It is patterned through coating, exposure, development, wet etching, and photoresist stripping steps. The first metal layer-1 can be Ti / Cu. The first metal layer-1 is retained at the main PS and not retained at the sub PS.

[0030] S2: Based on the gate metal layer, the first insulating layer-2 is deposited using PECVD (plasma-enhanced chemical vapor deposition), i.e. Figure 1 The gate insulator (GI) shown in the figure has a first insulating layer -2 which can be SiNx / SiO2 (silicon nitride / silicon dioxide, which means that this layer is a double-layer structure, with SiNx deposited first and then SiO2 deposited, and the same meaning is used in the following text).

[0031] S3: Deposition using PVD method Figure 1 The active layer -3 shown is made of IGZO (indium gallium zinc oxide) with a thickness of 100nm and is patterned. The active layer -3 is not retained at the main PS and sub PS.

[0032] S4: Deposit the second metal layer -4 using PVD, i.e. Figure 1The source-drain metal layer (SD) shown is 400nm thick and patterned. The second metal layer -4 can be MoNb / Cu. The second metal layer -4 is retained at both the mainPS and subPS.

[0033] S5: Deposit the second insulating layer -5 using PECVD, i.e. Figure 1 The passivation layer shown is SiO2 / SiNx (silicon dioxide / silicon nitride).

[0034] S6: The first electrode layer -6 is deposited using PVD, i.e. Figure 1 The common electrode layer shown is made of ITO (indium tin oxide) with a thickness of 100 nm, followed by PVD deposition of the third metal layer -7 (located in...). Figure 1 The first electrode layer -6 and the third metal layer -7 are patterned using Cu directly above the common electrode layer shown in the diagram (i.e., the metal-3 layer). The thickness can be set to 400 nm. The first electrode layer -6 and the third metal layer -7 are patterned using a half-mask and then annealed. The first electrode layer -6 and the third metal layer -7 are retained at both the main PS and the sub PS.

[0035] S7: Deposit the third insulating layer -8 using PECVD, i.e. Figure 1 The second passivation layer shown is made of SiNx.

[0036] S8: Through the steps of coating, exposure, development, dry etching, and photoresist stripping, holes are drilled above the second metal layer-4 so that the second electrode layer-9 can overlap with the second metal layer-4 during subsequent deposition.

[0037] S9: The second electrode layer -9 is deposited using PVD, i.e. Figure 1 The pixel electrode layer shown is made of ITO (indium tin oxide) with a thickness of 100 nm. It is patterned and then annealed. The second electrode layer is not retained at either the main PS or the sub PS. At this point, the structure of the BCE TFT device, the main PS, and the sub PS is complete.

[0038] The specific structure of the BCE TFT device in this embodiment is as follows: Figure 1 As shown.

[0039] The specific structure of main PS in this embodiment is as follows: Figure 2 As shown.

[0040] The specific structure of sub PS in this embodiment is as follows: Figure 3 or Figure 4 As shown.

[0041] In this embodiment, the height difference between the main PS and the sub PS is the thickness of the gate metal layer or the source / drain metal layer, both of which are approximately 400 nm.

[0042] The TFT arrangement on the array side adopts the following... Figure 5 As shown, the main PS and sub PS are alternately placed between the pixels of four adjacent TFTs, and the area occupied by the PS is evenly divided among the four pixels, reducing the impact of the PS on the aperture ratio.

[0043] The diagram shows the alignment of the PS on the Array side and the PS on the CF side. Figure 6 As shown, both the main PS and sub PS are XPS designs, and the height difference is the thickness of the gate metal layer.

[0044] Example 2: This example provides a metal XPS structure based on an organic-layer-free design (XPS with a self-aligned top gate structure), which is prepared through the following steps: S1: The first metal layer -1 is deposited on the glass substrate using PVD (Physical Vapor Deposition), i.e. Figure 7 The light-blocking layer shown can be set to a thickness of 200nm. It is patterned through coating, exposure, development, wet etching, and photoresist stripping steps. The first metal layer-1 can be Ti / Cu. The first metal layer-1 is retained at the main PS and sub PS, but not at the mid PS.

[0045] S2: The first insulating layer -2 is deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition), i.e. Figure 7 The buffer layer shown, the first insulating layer -2 can be SiNx / SiO2.

[0046] S3: Deposition using PVD method Figure 7 The active layer -3 shown is made of IGZO (indium gallium zinc oxide), and the thickness can be set to 200nm. It is patterned, and the active layer -3 is not retained at the main PS, sub PS and mid PS.

[0047] S4: The second insulating layer -4 is deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition), i.e. Figure 7 The gate insulating layer shown is a second insulating layer -4 made of SiO2.

[0048] S5: Deposit the second metal layer -5 using PVD, i.e. Figure 7The gate metal layer shown can be made of MoNb / Cu with a thickness of 400nm. It is patterned, and then the second insulating layer-4 (gate insulating layer) is dry etched using the second metal layer-5 as a mask. In the end, only the second insulating layer-4 below the second metal layer-5 is retained. The second metal layer-5 (gate metal layer) and the second insulating layer-4 (gate insulating layer) below it are retained at the main PS, sub PS, and mid PS.

[0049] S6: Conductorization process is performed by treating the substrate with a mixed plasma of argon and helium (mixed in any ratio), so that the active layer-3 below the second metal layer-5 retains its semiconductor properties, while the active layer-3 outside the second metal layer-5 becomes a conductor.

[0050] S7: Deposit the second insulating layer -6 using PECVD, i.e. Figure 7 The intermediate layer shown is made of SiO2 / SiNx / SiO2 (silicon dioxide / silicon nitride / silicon dioxide) and is dry etched to form an overlap hole connecting the third metal layer -7 and the active layer -3.

[0051] S8: The third metal layer -7 - is deposited using PVD. Figure 7 The source and drain metal layers shown can be selected from MoNb / Cu, and the thickness can be set to 400nm. They are patterned, and the third metal layer -7 is retained at the main PS and mid PS, but not at the sub PS.

[0052] S9: The fourth insulating layer -8 - is deposited using PECVD. Figure 7 The first passivation layer shown is made of SiO2 / SiNx.

[0053] S10: The first electrode layer -9 is deposited using PVD, i.e. Figure 7 The common electrode layer shown is made of ITO (indium tin oxide) with a thickness of 100 nm, followed by PVD deposition of the fourth metal layer -10 (located in...). Figure 7 The first electrode layer -9 and the third metal layer -10 are patterned using Cu with a thickness of 400 nm directly above the common electrode layer shown in the diagram. After annealing, the first electrode layer -9 and the third metal layer -10 are retained at the main PS, sub PS and mid PS.

[0054] S11: The fifth insulating layer -11 is deposited using PECVD, i.e. Figure 7The second passivation layer shown uses SiNx as the dielectric of the pixel capacitor.

[0055] S12: Through the steps of coating, exposure, development, dry etching, and photoresist stripping, a hole is drilled above the third metal layer-7 so that the second electrode layer-12 can overlap with the third metal layer-7 during subsequent deposition.

[0056] S13: Deposit the second electrode layer -12 using PVD, i.e. Figure 7 The pixel electrode layer shown is made of ITO (indium tin oxide) with a thickness of 100 nm. It is patterned and then annealed. The second electrode layer -12 is not retained at the main PS, sub PS, and mid PS. At this point, the structure of the TFT device, main PS, sub PS, and mid PS is completed.

[0057] In this embodiment, the specific structure of the self-aligned top-gate TFT devices of ORG skip and metal-3 is as follows: Figure 7 As shown.

[0058] The specific structure of main PS in this embodiment is as follows: Figure 9 As shown.

[0059] The specific structure of sub PS in this embodiment is as follows: Figure 10 As shown.

[0060] The specific structure of mid PS in this embodiment is as follows: Figure 11 As shown.

[0061] In this embodiment, the pixel arrangement and PS position diagram are shown below. Figure 8 As shown.

[0062] In this embodiment, the height difference of the PS is the thickness of the source-drain metal layer, which is approximately 400nm. The sub PS can also retain the source-drain metal layer but remove the gate metal layer along with the gate insulating layer. In this case, the height difference of the PS is approximately 600nm. Compared to the main PS, the mid PS removes the light shield (LS). The thickness of the light shield can be adjusted, and here it can be set to 200nm. Therefore, the height difference between the main PS and the mid PS is 200nm, and the height difference between the mid PS and the sub PS is also 200nm. This three-PS design (main PS, mid PS, sub PS) is beneficial for taking into account the different requirements of the active display area (AA) and the surrounding area for the PS height. The AA area uses the main PS and sub PS, and the surrounding area uses the main PS and mid PS.

[0063] Example 3: This example provides a metal XPS structure based on an organic-layer-free design (XPS with a bottom-contact top-gate structure), which is prepared through the following steps: S1: The first metal layer -1 is deposited on the glass substrate using PVD, i.e. Figure 12 The light-blocking layer shown has a thickness of 400nm. It is patterned through coating, exposure, development, wet etching, and photoresist stripping steps. The first metal layer-1 can be Ti / Cu. The first metal layer-1 is retained at the main PS, but not at the sub PS and mid PS.

[0064] S2: The first insulating layer -2 is deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition), i.e. Figure 12 The buffer layer shown can be SiNx / SiO2. Dry etching is performed on the first insulating layer-2 to form an overlap hole that connects to the first metal layer-1 during the subsequent deposition of the active layer-3.

[0065] S3: Deposition using PVD method Figure 12 The active layer-3 shown is made of IGZO (indium gallium zinc oxide), and the thickness can be set to 200nm. It is patterned. The active layer-3 is not retained at the main PS and sub PS, but is retained at the mid PS.

[0066] S4: The second insulating layer -4 is deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition), i.e. Figure 12 The gate insulating layer shown is a second insulating layer -4 made of SiO2.

[0067] S5: Deposit the second metal layer -5 using PVD, i.e. Figure 12 The gate metal layer shown can be made of MoNb / Cu, and the thickness can be set to 400nm. It is patterned and then the second metal layer-5 is used as a mask to dry etch the second insulating layer-4 (gate insulating layer). In the end, only the second insulating layer-4 below the second metal layer-5 is retained. The second metal layer-5 (gate metal layer) and the second insulating layer-4 (gate insulating layer) below it are retained at the main PS, sub PS and mid PS.

[0068] S6: Perform a conductor treatment by using a mixed plasma of argon and helium to treat the substrate, so that the active layer-3 below the second metal layer-5 retains its semiconductor properties, while the active layer-3 outside the second metal layer-5 becomes a conductor.

[0069] S7: Deposit the second insulating layer -6 using PECVD, i.e. Figure 12The intermediate layer shown is made of SiO2 / SiNx.

[0070] S8: The first electrode layer -7 is deposited using PVD, i.e. Figure 12 The common electrode layer shown is made of ITO (indium tin oxide) with a thickness of 100 nm, followed by the deposition of a third metal layer -8 (located in...) using PVD. Figure 12 The first electrode layer -7 and the third metal layer -8 are patterned using Cu with a thickness of 400 nm directly above the common electrode layer shown. After annealing, the first electrode layer -7 and the third metal layer -8 are retained at the main PS, sub PS and mid PS.

[0071] S9: The fifth insulating layer -9 is deposited using PECVD. Figure 12 The second passivation layer shown uses SiNx as the dielectric of the pixel capacitor.

[0072] S10: Through coating, exposure, development, dry etching, and photoresist stripping steps, holes are drilled above the active layer-3 so that the second electrode layer-10 can overlap with the active layer-3 during deposition.

[0073] S11: Deposit the second electrode layer -10 using PVD, i.e. Figure 12 The pixel electrode layer shown is made of ITO (indium tin oxide) with a thickness of 100nm. It is patterned and then annealed. The second electrode layer -10 is not retained at the main PS, sub PS and mid PS. At this time, the structure of the TFT device, main PS, sub PS and mid PS is completed.

[0074] In this embodiment, the specific structure of the bottom-contact top-gate TFT devices of ORG skip and metal-3 is as follows: Figure 12 As shown.

[0075] The specific structure of main PS in this embodiment is as follows: Figure 14 As shown.

[0076] The specific structure of sub PS in this embodiment is as follows: Figure 16 As shown.

[0077] The specific structure of mid PS in this embodiment is as follows: Figure 15 As shown.

[0078] In this embodiment, the pixel arrangement and PS position diagram are shown below. Figure 13 As shown.

[0079] In this embodiment, the thickness of the light-blocking layer can be set to 400nm, and the active layer can be set to 200nm. Therefore, the height difference between the main PS and the mid PS is 200nm, and the height difference between the mid PS and the sub PS is also 200nm.

[0080] Example 4: This example provides a metal XPS structure based on an organic layer-free design (metal XPS structure without metal-3), which removes the third metal layer based on Example 3.

[0081] The specific structure of main PS in this embodiment is as follows: Figure 17 As shown.

[0082] The specific structure of sub PS in this embodiment is as follows: Figure 19 As shown.

[0083] The specific structure of mid PS in this embodiment is as follows: Figure 18 As shown.

[0084] In this embodiment, the height difference between the main PS and the mid PS is the thickness of the active layer, which is 200nm, and the height difference between the main PS and the sub PS is the thickness of the light-blocking layer, which is 400nm.

[0085] Example 5: This example provides a metal XPS structure based on an organic layer-free design (metal XPS structure without metal-3), which removes the third metal layer based on Example 1.

[0086] The specific structure of main PS in this embodiment is as follows: Figure 20 As shown.

[0087] The specific structure of sub PS in this embodiment is as follows: Figure 22 As shown.

[0088] The specific structure of mid PS in this embodiment is as follows: Figure 21 As shown.

[0089] The active layer thickness in the BCE structure is generally 100nm, so different PS height differences cannot be achieved by the active layer alone. However, they can be achieved by using a common electrode layer. The thickness of the common electrode layer can be set to 100nm. In this embodiment, the height difference between the main PS and the mid PS is the thickness of the active layer plus the common electrode layer, which is 200nm. The height difference between the main PS and the sub PS is the thickness of the gate metal layer, which is 400nm.

[0090] In the technical solution of this invention, a half-mask is not used when preparing PS. On the G8.5 generation production line, the cost of the half-mask and related processes can be reduced by about 50%.

[0091] In this invention, both the main PS and sub PS adopt a cross-shaped metal XPS structure. The PS strips on the Array side and the CF side are perpendicular to each other, forming a stable support structure. Those skilled in the art will know that, compared to traditional point (column) supports, the strip-shaped cross-support structure has superior stress dispersion and deformation resistance when subjected to pressure. Therefore, this technical solution can improve structural reliability.

[0092] In this invention, the height difference of the photoresist (PS) is controlled by the thickness of the metal layer on the array side, achieving a higher precision than traditional semi-mask photolithography. In traditional processes, the final height of the photoresist PS material, formed through semi-mask exposure, development, and curing, is cumulatively affected by multiple complex processes, including coating uniformity, exposure precision, development uniformity, and thermal shrinkage. For example, for a target height of approximately 4 micrometers, the total height error is typically higher than ±500nm. In contrast, the PVD process is more stable, controlling the height error within ±120nm for the same 4-micrometer target height. For a target height of 400nm, the advantages of PVD are even more pronounced, with the height error controlled within ±30nm (or even lower than ±20nm), while the height error of photoresist PS can reach as high as ±200nm. This patent enables high uniformity in the cell thickness of LCD displays.

[0093] This invention does not alter the original TFT structure or introduce new materials. Instead, it migrates the height difference control mechanism of the PS from the traditional, low-precision CF-side photolithography process to the high-precision, low-cost Array-side thin-film deposition process. This solution can be used for bottom-gate and top-gate TFT structures.

[0094] It should be noted that, in this document, terms such as “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.

[0095] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention.

Claims

1. A method for fabricating a metal XPS structure based on an organic-layer-free design, characterized in that, Includes the following steps: Using an ORG skip design, a metal XPS structure is fabricated on a TFT array substrate by depositing a metal layer, an insulating layer, an active layer, and an electrode layer. The metal XPS structure includes a main PS and a sub PS, and both the main PS and the sub PS are cross-shaped XPS structures. The height difference between the main PS and the sub PS is directly controlled by the retention or removal state of the array-side metal layer. The TFT array substrate is any one of a back-channel etched TFT substrate, a self-aligned top-gate TFT substrate, or a bottom-contact top-gate TFT substrate.

2. The method for fabricating a metal XPS structure based on an organic-layer-free design according to claim 1, characterized in that, The TFT array substrate is a BCE TFT substrate, and during fabrication, the main PS area retains a gate metal layer, a gate insulating layer, a source / drain metal layer, a passivation layer one, a common electrode layer, a metal-3 layer, and a passivation layer two. At the sub PS, the gate insulating layer, source and drain metal layers, passivation layer one, common electrode layer, metal-3 layer, and passivation layer two are retained, while the pixel electrode layer and active layer are removed at both the main PS and sub PS. The gate metal layer is Ti / Cu; the source and drain metal layers are MoNb / Cu; and the metal-3 layer is Cu.

3. The method for fabricating a metal XPS structure based on an organic-layer-free design according to claim 1, characterized in that, The TFT array substrate is a self-aligned top-gate TFT substrate. During fabrication, a light-blocking layer, a buffer layer, a gate insulating layer, a gate metal layer, an intermediate layer, a source-drain metal layer, a passivation layer one, a common electrode layer, a metal-3 layer, and a passivation layer two are retained at the main PS. The sub PS retains a light-blocking layer, a buffer layer, a gate insulating layer, a gate metal layer, an intermediate layer, a passivation layer one, a common electrode layer, a metal-3 layer, and a passivation layer two; At the mid PS, the buffer layer, gate insulating layer, gate metal layer, intermediate layer, passivation layer one, common electrode layer, metal-3 layer and passivation layer two are retained. The pixel electrode layer and active layer are removed at the main PS, sub PS and mid PS, forming a three-gradient metal XPS structure of main PS, sub PS and mid PS. The light-blocking layer is Ti / Cu; the gate metal layer is MoNb / Cu; the source and drain metal layers are MoNb / Cu; and the metal-3 layer is Cu.

4. The method for fabricating a metal XPS structure based on an organic-layer-free design according to claim 1, characterized in that, The TFT array substrate is a bottom-contact top-gate TFT substrate. During fabrication, a light-blocking layer, a buffer layer, a gate insulating layer, a gate metal layer, an intermediate layer, a common electrode layer, a metal-3 layer, and a passivation layer are retained at the main PS. The sub PS layer retains a buffer layer, a gate insulating layer, a gate metal layer, an intermediate layer, a common electrode layer, a metal-3 layer, and a passivation layer 2; The buffer layer, active layer, gate insulating layer, gate metal layer, intermediate layer, common electrode layer, metal-3 layer and passivation layer 2 are retained at the mid PS; the active layer is retained at the mid PS; the active layer is removed at the main PS and sub PS; the common electrode layer and metal-3 layer are retained at the main PS, sub PS and mid PS, forming a three-gradient metal XPS structure.

5. A method for preparing a metal XPS structure based on an organic-layer-free design according to claim 2 or 4, characterized in that, The common electrode layer does not have a metal-3 layer, and a simplified metal layer structure without metal-3 is used to prepare the three-gradient metal XPS.

6. The method for fabricating a metal XPS structure based on an organic-layer-free design according to claim 1, characterized in that, The active layer is IGZO; The electrode layer is ITO.

7. The method for fabricating a metal XPS structure based on an organic-layer-free design according to claim 1, characterized in that, The metal layer and electrode layer are both prepared by PVD, the insulating layer is prepared by PECVD, and the film patterning is achieved by coating, exposure, development, wet etching, dry etching, and photoresist stripping.

8. A method for preparing a metal XPS structure based on an organic-layer-free design according to claim 3 or 4, characterized in that, The active layer is subjected to a mixed plasma conductive treatment of argon and helium, so that the active layer below the gate metal layer retains its semiconductor properties, while the remaining area becomes a conductor.

9. The method for fabricating a metal XPS structure based on an organic-layer-free design according to claim 1, characterized in that, Overlap holes are formed above the metal layer or active layer to achieve electrode layer overlap. After the electrode layer is patterned, it is annealed. The passivation layer 2 uses SiNx as the pixel capacitor dielectric.

10. A metal XPS structure based on an organic-layer-free design, characterized in that, An array substrate used in thin-film transistor liquid crystal display panels, including main PS, sub PS, and optional mid PS; Both the main PS and the sub PS are cross-shaped metal XPS structures, formed by stacking metal layers, insulating layers, and electrode layers on the array side. The XPS on the array side does not contain organic materials. The metal XPS structure is compatible with three substrate structures: back-channel etched TFT, self-aligned top-gate TFT, and bottom-contact top-gate TFT. It can have or not have a metal-3 layer above the common electrode layer and can form a dual-gradient or triple-gradient height difference. The metal XPS structure based on the design without organic layers is prepared by the preparation method of the metal XPS structure based on the design without organic layers as described in any one of claims 1-4.

Images