Driving circuit board and manufacturing method of driving circuit board

Abstract

The precision of the unit driving circuit included in the driving circuit substrate is improved. The driving circuit substrate (1) includes a first transistor (T1), which has: an island-shaped first semiconductor layer (3); a first insulating layer (4) disposed on the first semiconductor layer (3); a first gate (G) which also serves as a second opposite electrode (CE1) disposed on the first insulating layer (4) in a manner that overlaps with a portion of the first channel region (3D1) and the first opposite electrode (CE2), i.e., the first source region (3ND2), when viewed from above; a first drain (D) electrically connected to the first drain region (3ND1); a first source (S) electrically connected to the first source region (3ND2); and a holding capacitor (Cs) including the first opposite electrode (CE2) and the second opposite electrode (CE1), and has a plurality of unit driving circuits, each unit driving circuit including the first transistor (T1).

Description

Technical Field

[0001] This disclosure relates to a drive circuit board and a method for manufacturing the drive circuit board. Background Technology

[0002] In recent years, unit driving circuits with multiple transistors on the driving circuit board have been used in the field of display devices as pixel circuits for display in the display area of ​​the display device, or as driving drivers for the pixel circuits located in the non-display area of ​​the display device. In fields other than display devices, they can also be applied to various fields such as 3D printers and fingerprint sensors. Therefore, their research and development are actively underway.

[0003] Existing technical documents Patent documents Patent Document 1: US Patent Publication US2015 / 0055051 Patent Document 2: US Patent Publication US2015 / 0053935 Summary of the Invention The technical problem to be solved by the present invention Patent documents 1 and 2 describe a case where a drive circuit board having multiple unit drive circuits including drive transistors and selection transistors is used as a pixel circuit for display in the display area of ​​a display device.

[0004] In the field of display devices, in order to improve image quality, the driving circuit board requires high precision in each driving circuit.

[0005] However, neither Patent Documents 1 nor 2 describe the structure or method for achieving high precision in the unit drive circuit contained in the drive circuit board.

[0006] One aspect of this disclosure is to provide a drive circuit board and a method for manufacturing the drive circuit board that enable high precision in unit drive circuits.

[0007] Technical solutions for solving technical problems To address the aforementioned issues, the driving circuit substrate of this disclosure includes a first transistor, the first transistor comprising: an island-shaped first semiconductor layer including a first channel region, a first source region containing impurities, and a first drain region; a first insulating layer disposed on the first semiconductor layer; a first gate and second opposite electrode disposed on the first insulating layer such that it overlaps with a portion of the first channel region and the first opposite electrode, i.e., the first source region, when viewed from above; a first drain electrically connected to the first drain region; a first source electrically connected to the first source region; and a holding capacitor including the first opposite electrode and the second opposite electrode, and having a plurality of unit driving circuits, the unit driving circuits including the first transistor.

[0008] To address the aforementioned issues, the present disclosure discloses a method for manufacturing a driving circuit substrate comprising: a first step of forming an island-shaped first semiconductor layer included in a first transistor, the first transistor including a holding capacitor, the holding capacitor including a first counter electrode and a second counter electrode; a second step of forming a first insulating layer on the first semiconductor layer; a third step of forming a resist film of a predetermined shape on the first insulating layer, using the resist film as a mask to implant impurities into a portion of the first semiconductor layer, thereby forming a first channel region and a first source region and a first drain region with a higher impurity concentration than the first channel region; a fourth step of, after removing the resist film, forming a first gate and a second counter electrode on the first insulating layer in a manner that overlaps with a portion of the first channel region and the first source region serving as the first counter electrode when viewed from above; and a fifth step of forming a first drain and a first source, the first drain being electrically connected to the first drain region and the first source being electrically connected to the first source region, forming a plurality of unit driving circuits, the unit driving circuits including the first transistor.

[0009] Beneficial effects According to one aspect of this disclosure, a drive circuit board capable of highly precise unit drive circuitry and a method for manufacturing the drive circuit board can be provided. Attached Figure Description

[0010] Figure 1 This is a circuit diagram of the unit drive circuit of the drive circuit board of the first embodiment.

[0011] Figure 2 This is a top view showing a schematic configuration of the drive circuit board according to the first embodiment.

[0012] Figure 3 This is a cross-sectional view showing the schematic configuration of the drive circuit board according to the first embodiment.

[0013] Figure 4This diagram illustrates a portion of the manufacturing process of the drive circuit board according to the first embodiment.

[0014] Figure 5 This diagram illustrates another part of the manufacturing process of the drive circuit board according to the first embodiment.

[0015] Figure 6 This diagram illustrates another part of the manufacturing process of the drive circuit board according to the first embodiment.

[0016] Figure 7 This is a top view showing the general configuration of the drive circuit board of Comparative Example 1.

[0017] Figure 8 This is a cross-sectional view showing the general structure of the drive circuit board of Comparative Example 1.

[0018] Figure 9 This is a diagram showing the difference between the sequence of some steps in the manufacturing method of the drive circuit board of the first embodiment and the sequence of some steps in the manufacturing method of the drive circuit board of Comparative Example 1.

[0019] Figure 10 This is a top view showing the schematic configuration of the drive circuit board according to the second embodiment.

[0020] Figure 11 This is a cross-sectional view showing the schematic configuration of the drive circuit board according to the second embodiment.

[0021] Figure 12 This diagram illustrates a portion of the manufacturing process of the drive circuit board according to the second embodiment.

[0022] Figure 13 This diagram illustrates another part of the manufacturing process of the drive circuit board according to the second embodiment.

[0023] Figure 14 This is a diagram showing another part of the manufacturing process of the drive circuit board according to the second embodiment.

[0024] Figure 15 This is a top view showing the schematic configuration of the drive circuit board according to the third embodiment.

[0025] Figure 16 This is a cross-sectional view showing the schematic configuration of the drive circuit board according to the third embodiment.

[0026] Figure 17 This is a top view showing the schematic configuration of the drive circuit board according to the fourth embodiment.

[0027] Figure 18This is a cross-sectional view showing the schematic configuration of the drive circuit board according to the fourth embodiment.

[0028] Figure 19 This is a diagram illustrating a schematic manufacturing method of the drive circuit board according to the fourth embodiment. Detailed Implementation

[0029] based on Figures 1 to 19 Embodiments of this disclosure will be described below. For ease of explanation, configurations having the same function as those described in specific embodiments will sometimes be marked with the same reference numerals and their descriptions will be omitted.

[0030] [First Implementation Method] Figure 1 This is a circuit diagram of the unit drive circuit DRU provided in the drive circuit board 1 of the first embodiment. Figure 2 This is a top view of the drive circuit board 1 according to the first embodiment, and it is a diagram showing the general structure of the drive circuit board 1. Furthermore, in Figure 2 The barrier layer 2, the first insulating layer 4, the second insulating layer 5, and the passivation film 6 are not shown in the figure. Figure 3 This is a cross-sectional view showing the schematic configuration of the drive circuit board 1 according to the first embodiment. Additionally, Figure 3 They are respectively along Figure 2 The cross-sectional view of the drive circuit substrate 1 with the X1-X1' and X2-X2' lines cut off is shown.

[0031] like Figure 1 , Figure 2 and Figure 3 As shown, the drive circuit board 1 includes multiple unit drive circuits DRU, each including a first transistor T1. Each first transistor T1 has a holding capacitor Cs containing a first opposing electrode CE2 and a second opposing electrode CE1. For example... Figure 3 As shown, a first transistor T1 having a holding capacitor Cs includes: an island-shaped first semiconductor layer 3; a first opposing electrode CE2 as part of the first semiconductor layer 3; a first insulating layer 4 disposed on the first semiconductor layer 3; a first gate G and second opposing electrode CE1 disposed on the first insulating layer 4; a first drain D; and a first source S. The island-shaped first semiconductor layer 3 includes a first channel region 3JD1, a first source region 3ND2 containing impurities, and a first drain region 3ND1. The first gate G and second opposing electrode CE1 are disposed on the first insulating layer 4 such that they overlap with the first channel region 3JD1 and part of the first source region 3ND2 as part of the first opposing electrode CE2 when viewed from above. The first drain D is electrically connected to the first drain region 3ND1, and the first source S is electrically connected to the first source region 3ND2.

[0032] like Figure 2 and Figure 3 As shown, the first transistor T1, which includes a holding capacitor Cs in each of the plurality of unit drive circuits DRUs provided on the drive circuit substrate 1, has a first gate G that also serves as a second counter electrode CE1. Therefore, it is not necessary to form a contact hole for electrically connecting the first gate G and the second counter electrode CE1. Since no contact hole is formed, the area of ​​the first transistor T1 can be reduced. Therefore, in the drive circuit substrate 1, the unit drive circuit DRU can be made highly refined. On the other hand, in the case of the drive circuit substrate 50, which includes a first transistor T1' that includes a holding capacitor Cs in Comparative Example 1 where the first gate G and the second counter electrode CE1 are different layers (see...), Figure 7 and Figure 8 It is necessary to form additional contact holes CON8 and CON9 in the second insulating layer 5 for electrically connecting the first gate G and the second opposite electrode CE1. Due to the formation of contact holes CON8 and CON9, the area of ​​the first transistor T1' becomes larger.

[0033] In this embodiment, the first channel region 3JD1 is, for example, made of polysilicon, a semiconductor free of impurities. The first source region 3ND2 and the first drain region 3ND1 containing impurities are formed by implanting impurities into the polysilicon, which is a semiconductor free of impurities. In this embodiment, the first source region 3ND2 and the first drain region 3ND1 containing impurities are formed by implanting P (phosphine ions), which are N-type impurities, but this is not a limitation. For example, they can be formed by implanting As (arsenic ions), which are N-type impurities, or by implanting B (boron ions), which are P-type impurities.

[0034] In this embodiment, such as Figure 1 As shown, an example is given of a unit drive circuit DRU consisting of a transistor T1 as a drive transistor, a transistor T2 as a selection transistor, and a holding capacitor Cs. However, the unit drive circuit DRU is not limited to this as long as it includes a first transistor T1 with a holding capacitor Cs.

[0035] In this embodiment, the plurality of unit drive circuits DRUs provided on the drive circuit board 1 each include a second transistor T2. For example... Figure 3As shown, the second transistor T2 includes: an island-shaped second semiconductor layer 3'; a first insulating layer 4 disposed on the second semiconductor layer 3'; a second gate G' disposed on the first insulating layer 4; a second drain D'; and a second source S'. The island-shaped second semiconductor layer 3' includes second channel regions 3JD1' and 3JD2' and a second source region 3ND1' and a second drain region 3ND3' containing impurities. The second gate G' is disposed on the first insulating layer 4 in a manner that overlaps with the second channel regions 3JD1' and 3JD2' when viewed from above. Figure 2 and Figure 3 As shown, the second drain D' is electrically connected to the second drain region 3ND3' and the first gate G, which is also the second opposite electrode CE1, and the second source S' is electrically connected to the second source region 3ND1'.

[0036] In this embodiment, similar to the first channel region 3JD1, the second channel regions 3JD1' and 3JD2' are each made of polysilicon, which is a semiconductor free of impurities. The second source region 3ND1' and the second drain region 3ND3' containing impurities are formed by implanting impurities into the polysilicon, which is a semiconductor free of impurities, in the same manner as the first source region 3ND2 and the first drain region 3ND1 containing impurities. In this embodiment, the second source region 3ND1' containing impurities, the high-concentration region 3ND2', and the second drain region 3ND3' are formed by implanting P (phosphine ions), which are N-type impurities, as impurities. However, this is not a limitation. For example, it can be formed by implanting As (arsenic ions), which are N-type impurities, or by implanting B (boron ions), which are P-type impurities.

[0037] like Figure 3 As shown, an island-shaped first semiconductor layer 3 and an island-shaped second semiconductor layer 3' are disposed on the barrier layer 2. The barrier layer 2 is a layer that prevents foreign matter such as water and oxygen from entering the first transistor T1 and the second transistor T2. For example, it can be composed of a silicon oxide film, a silicon nitride film, or a silicon oxide-nitride film, or a laminate of the above, formed by CVD. Furthermore, the thickness of the barrier layer 2 is not particularly limited as long as it can prevent foreign matter such as water and oxygen from entering the first transistor T1 and the second transistor T2.

[0038] In this embodiment, the island-shaped first semiconductor layer 3 and the island-shaped second semiconductor layer 3' are described as examples of being composed of polycrystalline silicon formed at low temperature with a film thickness of 40 nm, but they are not limited to this. For example, they can be composed of oxide semiconductors (e.g., In-Ga-Zn-O based semiconductors) or polycrystalline silicon formed at high temperature. In addition, the first source region 3ND2 and the first drain region 3ND1 containing impurities in the first semiconductor layer 3, and the second source region 3ND1' and the second drain region 3ND3' containing impurities in the second semiconductor layer 3', are each regions formed by implanting impurities into a semiconductor without impurities.

[0039] The first insulating layer 4 can be composed, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminate thereof formed by CVD. In this embodiment, a silicon nitride film formed with a thickness of 85 nm is used as the first insulating layer 4.

[0040] Figure 3 The first gate G, which also serves as the second opposite electrode CE1 of the first transistor T1, and the second gate G' of the second transistor T2 are formed from the same layer and can be made of the same material. For example, they can be composed of a single-layer film or a multilayer film of a metal containing at least one of aluminum, tungsten, molybdenum, tantalum, chromium, titanium, and copper. In this embodiment, an alloy film of molybdenum and tungsten, namely a MoW film, is used as the first gate G, which also serves as the second opposite electrode CE1, and the second gate G', respectively. The film thickness is 300 nm.

[0041] In this embodiment, such as Figure 3 As shown, the second drain D' of the second transistor T2 and the first gate G and second opposite electrode CE1 of the first transistor T1, which includes a holding capacitor Cs, are formed on different layers. Therefore, the drive circuit substrate 1 includes a second insulating layer 5. This second insulating layer 5 is provided to cover the first gate G and second opposite electrode CE1 and the second gate G' in order to ensure the insulation between the layer forming the second drain D' of the second transistor T2 and the layer forming the first gate G and second opposite electrode CE1 of the first transistor T1. The second insulating layer 5 can be, for example, composed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminate of the above formed by CVD. In this embodiment, a laminate of a silicon oxide film formed with a thickness of 680 nm and a silicon nitride film formed with a thickness of 160 nm is used as the second insulating layer 5. In addition, as Figure 2 As shown, the second drain D' of the second transistor T2 is electrically connected to the first gate G and second opposite electrode CE1 of the first transistor T1, which has a holding capacitor Cs, via a contact hole CON1 formed in the second insulating layer 5.

[0042] Figure 3The first drain D and first source S of the first transistor T1 and the second drain D' and second source S' of the second transistor T2 are formed in the same layer and can be made of the same material, such as a single-layer film or a multilayer film of a metal including at least one of aluminum, tungsten, molybdenum, tantalum, chromium, titanium, and copper. In this embodiment, the first drain D, first source S, second drain D', and second source S' are each formed using a multilayer film of titanium with a film thickness of 30 nm, aluminum with a film thickness of 300 nm, and titanium with a film thickness of 20 nm.

[0043] like Figure 3 As shown, the drive circuit substrate 1 includes a passivation film 6 to cover each of the first drain D, the first source S, the second drain D', and the second source S', and the second insulating layer 5. The passivation film 6 can be composed, for example, of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminate thereof formed by CVD, and can be made of a coatingable organic material such as polyimide or acrylic acid. In this embodiment, a silicon nitride film with a thickness of 300 nm is used as the passivation film 6.

[0044] In this embodiment, such as Figure 2 as well as Figure 3 The example shown illustrates the case where the second transistor T2 is a dual-gate transistor, but it is not limited to this; the second transistor T2 can also be a single-gate transistor. Since the second transistor T2 is a dual-gate transistor, therefore, as... Figure 3 As shown, it includes: a second semiconductor layer 3' having two second channel regions 3JD1' and 3JD2', and two second gates G' that overlap with the two second channel regions 3JD1' and 3JD2' respectively when viewed from above.

[0045] In this embodiment, such as Figure 3 As shown, the second drain D' of the second transistor T2 and the first gate G and second opposite electrode CE1 of the first transistor T1, which has a holding capacitor Cs, are formed as different layers. Therefore, as Figure 2 As shown, the second drain D' of the second transistor T2 is electrically connected to the first gate G and second opposite electrode CE1 of the first transistor T1, which has a holding capacitor Cs, via a contact hole CON1 formed in the second insulating layer 5. This is not a limitation; as in the second embodiment described later, the second drain D' of the second transistor T2 and the first gate G and second opposite electrode CE1 of the first transistor T1, which has a holding capacitor Cs, can also be in the same layer and formed of the same material. Furthermore, as in the third embodiment described later, the second drain D' can be configured to contact the second drain region 3ND3' via a contact hole CON3, and the first gate G and second opposite electrode CE1 can be configured to contact the second drain region 3ND3' via a contact hole.

[0046] In this embodiment, such as Figure 1 As shown, this example illustrates a case where a light-emitting element is provided as a functional unit FEL electrically connected to each unit drive circuit DRU, but it is not limited to this. For example, the functional unit FEL electrically connected to the unit drive circuit DRU may also include an anode electrode. Furthermore, in this embodiment, the light-emitting element is described as an OLED (Organic Light-Emitting Diode), but it is not limited to this; the light-emitting element may also be a QLED (Quantum Dot Light-Emitting Diode). The functional unit FEL may, for example, be provided with... Figure 3 On the passivation film 6 shown, the functional part FEL can be electrically connected to the first source S of the first transistor T1 through a contact hole formed on the passivation film 6 (not shown).

[0047] Figure 2 and Figure 3 The contact hole CON1 shown is a contact hole formed in the second insulating layer 5. Figure 2 and Figure 3 The contact holes CON2~CON7 shown are contact holes formed in the first insulating layer 4 and the second insulating layer 5.

[0048] like Figure 1 As shown, in the unit drive circuit DRU and the functional unit FEL, the first source S of the first transistor T1, which serves as the drive transistor, is electrically connected to the electrode on one side of the light-emitting element of the functional unit FEL, such as the anode electrode (not shown), and the first opposite electrode CE2 of the holding capacitor Cs. The first gate G of the first transistor T1 is electrically connected to the second opposite electrode CE1 of the holding capacitor Cs and the second drain D' of the second transistor T2, which serves as the selection transistor. The first drain D of the first transistor T1 is connected to the high-potential side power supply voltage line V, which is supplied with the high-potential side power supply voltage. DD Electrical connection. Additionally, the electrode on the other side of the light-emitting element, which is the functional unit FEL, such as the cathode electrode (not shown), is electrically connected to the low-potential side power supply voltage line that supplies the low-potential side power supply voltage, such as the grounded low-potential side power supply voltage line. Furthermore, the second source S' of the second transistor T2, which is the selection transistor, is connected to the data signal line V that supplies the data signal. DATA Electrically connected, the second gate G' of the second transistor T2 is connected to the scan signal line V that supplies the scan signal. SEL Electrically connected, the second drain D' of the second transistor T2 is electrically connected to the first gate G of the first transistor T1 and the second opposite electrode CE1 of the holding capacitor Cs. In this embodiment, as... Figure 1As shown, each unit drive circuit DRU has a current-driven light-emitting element and a functional part FEL electrically connected to the unit drive circuit DRU. Therefore, it is preferable that the first transistor T1 of each of the multiple unit drive circuits DRU on the drive circuit substrate 1 has a high current driving capability, and preferably the current driving capability of the first transistor T1 is stable. On the other hand, the second transistor T2 supplies a voltage corresponding to the data signal to the first transistor T1 according to the timing of the scan signal, thereby changing the voltage of the first transistor T1. Therefore, the second transistor T2 preferably has transistor characteristics with low leakage current.

[0049] In NMOS transistors such as the first transistor T1 and the second transistor T2, electrons, acting as charge carriers, gain high kinetic energy and are accelerated in the channel region by a high electric field, reaching their fastest speed near the drain region. A portion of these electrons then enter the first insulating layer 4, and subsequently the first gate G (which also serves as the second opposing electrode CE1) and the second gate G'. Under these conditions, the electrical characteristics of the first transistor T1 and the second transistor T2 change, resulting in a decrease in their driving capability.

[0050] Therefore, in this embodiment, a lightly doped drain (LDD) is provided in the first semiconductor layer 3 of the first transistor T1 and the second semiconductor layer 3' of the second transistor T2. The LDD is formed by injecting ions with a lower impurity concentration than the source and drain regions into the space between the channel region and the source region, and between the channel region and the drain region, at a shallower depth than the source and drain regions. When high-energy, accelerated charge carriers, i.e., electrons, reach the low-concentration portion of the impurity region, i.e., the LDD, near the drain, they are decelerated. Through momentum decay, entry into the first gate G (which also serves as the second opposite electrode) CE1 and the second gate G' is suppressed. Here, since an NMOS transistor is used, the case of electrons is illustrated. However, in a PMOS transistor, it is necessary to configure it to suppress the entry of holes, which are charge carriers, into the first gate G (which also serves as the second opposite electrode) CE1 and the second gate G'.

[0051] When a low-concentration region LDD is set up to mitigate the electric field, the same function can be maintained even if it is only set on the drain region side. Therefore, in this embodiment, as Figure 2 as well as Figure 3As shown, the first semiconductor layer 3 of the first transistor T1 is composed of a first channel region 3JD1, a first source region 3ND2, a first drain region 3ND1, and a first low-concentration region 3LD1 disposed between the first drain region 3ND1 and the first channel region 3JD1, but is not limited thereto. The first low-concentration region 3LD1 contains impurities, and the impurity concentration is lower than that of the first source region 3ND2 and the first drain region 3ND1, respectively. Furthermore, the first gate G and the second counter electrode CE1 do not overlap with the first low-concentration region 3LD1 when viewed from above.

[0052] In this embodiment, such as Figure 2 as well as Figure 3 As shown, the second transistor T2 is a dual-gate transistor. Therefore, the example given is the case where the second semiconductor layer 3' of the second transistor T2 is composed of the second channel regions 3JD1' and 3JD2', the second source region 3ND1' containing impurities at a high concentration, the high-concentration region 3ND2' containing impurities at a high concentration, the second drain region 3ND3' containing impurities at a high concentration, and the second low-concentration regions 3LD1', 3LD2', 3LD3', and 3LD4' containing impurities at a low concentration. However, the example is not limited to this. The second low-concentration region 3LD1' is the region formed between the second channel region 3JD1' and the second source region 3ND1', the second low-concentration region 3LD2' is the region formed between the second channel region 3JD1' and the high-concentration region 3ND2', the second low-concentration region 3LD3' is the region formed between the high-concentration region 3ND2' and the second channel region 3JD2', and the second low-concentration region 3LD4' is the region formed between the second channel region 3JD2' and the second drain region 3ND3'.

[0053] Figure 4 This diagram illustrates a portion of the manufacturing process of the drive circuit board 1 according to the first embodiment. Figure 5 This is a diagram illustrating another part of the manufacturing process of the drive circuit board 1 according to the first embodiment. Figure 6 This diagram illustrates another part of the manufacturing process of the drive circuit board 1 according to the first embodiment.

[0054] The first step in forming the island-shaped first semiconductor layer 3 comprising the first transistor T1 is Figure 4The S1 and S2 processes shown illustrate a first transistor T1 with a holding capacitor Cs comprising a first opposing electrode CE2 and a second opposing electrode CE1. In process S1, after forming an amorphous silicon layer on the barrier layer 2, an annealing (heat treatment) for hydrogen removal is performed, for example, at 450°C, followed by excimer laser processing at a relatively low temperature to obtain a polycrystalline silicon film PS formed at a low temperature. In process S2, the polycrystalline silicon film PS is etched using a photoresist film to obtain an island-shaped first semiconductor layer 3 consisting of an impurity-free first channel region 3JD1.

[0055] The second step in forming the first insulating layer 4 on the first semiconductor layer 3 is Figure 4 The S3 process is shown. In the S3 process, the first insulating layer 4 can be obtained by annealing (heat treatment) after film formation.

[0056] A resist film RM of a predetermined shape is formed on the first insulating layer 4. Using the resist film RM as a mask, impurities are implanted into a portion of the first semiconductor layer 3, thereby forming a first channel region 3JD1, a first source region 3ND2 with a higher impurity concentration than the first channel region 3JD1, and a first drain region 3ND1. The third step is... Figure 4 The S4 process is shown. In the S4 process, the resist film RM is used as a mask to implant HDP with a high concentration of impurities, thereby forming a first channel region 3JD1 that is free of impurities by being protected by the resist film RM, and a first source region 3ND2 and a first drain region 3ND1 that have a higher impurity concentration than the first channel region 3JD1 and contain a high concentration of impurities.

[0057] The process of removing the resist film RM is Figure 4 The S5 process shown is in Figure 4 In the S5 process shown, the resist film RM can be removed using a stripping solution.

[0058] The fourth step, after removing the resist film RM, is to form the first gate G and second opposite electrode CE1 on the first insulating layer 4, overlapping, in a top view, the first channel region 3JD1 and the first source region 3ND2, which is the first opposite electrode CE2. Figure 5 The S6 process is shown. In this embodiment, an example is given in which the first gate G, which is also the second opposite electrode CE1, is configured in the S6 process such that it does not overlap with a portion of the first drain region 3ND1 side of the first channel region 3JD1 when viewed from above. However, it is not limited to this, and the first gate G, which is also the second opposite electrode CE1, can also be formed to completely overlap with the first channel region 3JD1 when viewed from above.

[0059] The fifth step, which forms the first drain D electrically connected to the first drain region 3ND1 and the first source S electrically connected to the first source region 3ND2, is... Figure 5 The S9 process shown and Figure 6 The S10 process is shown. In the S9 process, a contact hole CON4 is formed to expose the first drain region 3ND1 and a contact hole CON5 to expose the first source region 3ND2. In the S10 process, the first drain D is electrically connected to the first drain region 3ND1 via the contact hole CON4, which exposes the first drain region 3ND1, and the first source S is electrically connected to the first source region 3ND2 via the contact hole CON5, which exposes the first source region 3ND2.

[0060] According to the manufacturing method of the drive circuit board 1 including the first to fifth processes described above, it is possible to manufacture a drive circuit board 1 in which multiple unit drive circuits DRU each have a first transistor T1 that serves as both a first gate G and a second counter electrode CE1. Since the first gate G serves as both the first gate G and the second counter electrode CE1, it is not necessary to form additional contact holes for electrically connecting the first gate G and the second counter electrode CE1. Because no contact holes are formed, the area of ​​the first transistor T1 can be reduced. Therefore, in the drive circuit board 1, the unit drive circuit DRU can be made highly refined.

[0061] In this embodiment, in the fourth step described above, i.e. Figure 5 In the S6 process shown, as described above, when viewed from above, the first gate G and the second opposing electrode CE1 are formed so that they do not overlap with a portion of the first drain region 3ND1 side of the first channel region 3JD1. Then, in the fourth process (… Figure 5 The S6 process shown) and the fifth process ( Figure 5 The S9 process shown and Figure 6 The process of forming the first low-concentration region 3LD1 between the steps shown in step S10. The process of forming the first low-concentration region 3LD1 is... Figure 5The S7 process is shown. In the S7 process, using the first gate G, which is also the second opposing electrode CE1, as a mask, impurities are implanted into a portion of the first semiconductor layer 3 to form a first low-concentration region 3LD1. The impurity concentration of the first low-concentration region 3LD1 is lower than that of the first source region 3ND2 and the first drain region 3ND1, and higher than that of the first channel region 3JD1. That is, in the S7 process, using the first gate G, which is also the second opposing electrode CE1, as a mask, a low-concentration impurity implantation LDP is performed, thereby forming the first low-concentration region 3LD1 in a portion of the first channel region 3JD1 that is not protected by the first gate G, which is also the second opposing electrode CE1. In addition, since the first source region 3ND2 and the first drain region 3ND1 already contain high concentrations of impurities, even with the low-concentration impurity implantation LDP, it is still a region containing high concentrations of impurities. When the charge carriers, i.e. electrons, which have obtained high kinetic energy and are accelerated, reach the first low-concentration region 3LD1, which is a low-concentration part of the impurity, they decelerate and, through momentum decay, can suppress their entry into the first gate G and the second opposite electrode CE1.

[0062] In this embodiment, in the first step described above, i.e. Figure 4 In the S1 and S2 processes shown, together with the first semiconductor layer formed by the first channel region 3JD1, an island-shaped second semiconductor layer formed by the second channel regions 3JD1' and 3JD2' included in the second transistor T2 is formed. Furthermore, in the aforementioned second process, i.e. Figure 4 In the S3 process shown, a first insulating layer 4 is formed on the first semiconductor layer composed of the first channel region 3JD1 and the second semiconductor layer composed of the second channel regions 3JD1' and 3JD2'. Next, in the aforementioned third process, i.e. Figure 4 In the S4 process shown, a resist film RM is also formed on the first insulating layer 4 disposed on the second semiconductor layer 3'. Using the resist film RM as a mask, impurities are implanted into a portion of the second semiconductor layer 3', thereby forming second channel regions 3JD1' and 3JD2', as well as a second source region 3ND1' and a second drain region 3ND3' with a higher impurity concentration than the second channel regions 3JD1' and 3JD2'. Furthermore, in the aforementioned fourth process, i.e. Figure 5 In the S6 process shown, the second gate G' is formed on the first insulating layer 4 in a manner that overlaps with the second channel regions 3JD1' and 3JD2' when viewed from above. Furthermore, in the aforementioned fifth process, namely... Figure 5 The S9 process shown and Figure 6In the S10 process shown, the second drain D', which is electrically connected to the second drain region 3ND3' and the first gate G and second opposite electrode CE1, the second source S', which is electrically connected to the second source region 3ND1', the first drain D, and the first source S are formed on the same layer from the same material. This allows for the realization of a drive circuit substrate 1 having multiple unit drive circuits DRUs containing first transistor T1 and second transistor T2.

[0063] Figure 5 The S8 step shown is the step of forming the second insulating layer 5. The second insulating layer 5 can be obtained by activation annealing (heat treatment) after film formation. In the aforementioned fifth step, that is, in... Figure 5 The S9 process shown and Figure 6 In the S10 process shown, contact holes CON2~CON5 are formed in the first insulating layer 4 and the second insulating layer 5 to expose the first source region 3ND2, the first drain region 3ND1, the second source region 3ND1', and the second drain region 3ND3'. Then, through the contact holes CON2~CON5, a first source S, a first drain D, a second source S', and a second drain D' are formed, which are electrically connected to the first source region 3ND2, the first drain region 3ND1, the second source region 3ND1', and the second drain region 3ND3', respectively. Furthermore, in the process of forming the first source S, the first drain D, the second source S', and the second drain D', etching using a resist film allows the first source S, the first drain D, the second source S', and the second drain D' to be formed into predetermined shapes. Figure 6 The S11 process shown is the process of forming the passivation film 6.

[0064] Figure 7 This is a top view of the drive circuit board 50 of Comparative Example 1, showing a schematic configuration of the drive circuit board 50. Additionally, in Figure 7 The barrier layer 2, the first insulating layer 4, the second insulating layer 5, and the passivation film 6 are not shown in the figure. Figure 8 This is a cross-sectional view showing the schematic configuration of the drive circuit board 50 in Comparative Example 1. Additionally, Figure 8 They are respectively along Figure 7 The cross-sectional view of the drive circuit board 50 with the X3-X3' and X4-X4' lines cut off is shown. Figure 9 This is a diagram showing the difference between the sequence of some steps in the manufacturing method of the drive circuit board 1 of the first embodiment and the sequence of some steps in the manufacturing method of the drive circuit board 50 of Comparative Example 1.

[0065] like Figure 7 and Figure 8As shown, in the case of the first transistor T1' in the drive circuit substrate 50 of Comparative Example 1, the gate G and the second opposite electrode CE1 are provided as different layers. Therefore, in the drive circuit substrate 50, contact holes CON8 and CON9 for electrically connecting the gate G and the second opposite electrode CE1 need to be provided in the second insulating layer 5. As described above, in the case of the drive circuit substrate 1 of the first embodiment, the formation area of ​​the first transistor T1' in the drive circuit substrate 50 of Comparative Example 1, which has unnecessary contact holes CON8 and CON9, is larger than the formation area of ​​the first transistor T1 in the drive circuit substrate 1 of the first embodiment. Therefore, in the drive circuit substrate 50 of Comparative Example 1, it is difficult to achieve high precision in the unit drive circuit DRU compared to the drive circuit substrate 1 of the first embodiment. In addition, in the case of the first transistor T1' in the drive circuit substrate 50 of Comparative Example 1, a first low-concentration region 3LD1 is provided on the drain side, and a first low-concentration region 3LD2 is also provided on the source side.

[0066] like Figure 9 As shown, in the manufacturing method of the drive circuit substrate 50 in Comparative Example 1, the following steps are performed sequentially: forming a first gate G (step S54); implanting a low-concentration impurity LDP into the semiconductor layer 3” using the first gate G as a mask to form a low-concentration region 3LD (step S55); and implanting a high-concentration impurity HDP into the semiconductor layer 3” using a resist film RM' as a mask to form a first source region 3ND2 and a first drain region 3ND1 (step S56). On the other hand, in the manufacturing method of the drive circuit substrate 1 in the first embodiment, the step corresponding to S56 is performed first. Figure 4 After the S4 process shown, proceed according to the steps corresponding to the S54 process. Figure 5 The S6 process shown and the corresponding S55 process are shown. Figure 5 The sequence of steps S7 shown is followed.

[0067] As described above, according to the manufacturing method of the drive circuit board 1 of the first embodiment, by only changing a part of the process sequence in the manufacturing method of the drive circuit board 50 of Comparative Example 1, the manufacturing method of the drive circuit board 1 with high precision of unit drive circuit DRU can be realized.

[0068] [Second Implementation] Figure 10 This is a top view of the drive circuit board 10 according to the second embodiment, and it is a top view showing the general structure of the drive circuit board 10. Furthermore, in Figure 10 The barrier layer 2, the first insulating layer 4, the second insulating layer 5, and the passivation film 6 are not shown in the figure. Figure 11 This is a cross-sectional view showing the schematic configuration of the drive circuit board 10 according to the second embodiment. Additionally, Figure 11 It is along Figure 10 The cross-sectional view of the drive circuit board 10 cut off from the X5-X5' line and the X6-X6' line is shown.

[0069] like Figure 10 and Figure 11 As shown, the driving circuit board 10 of the second embodiment includes multiple unit driving circuits DRU, each including a first transistor T1 and a second transistor T2' as a single-gate transistor. The configuration of the second transistor T2' differs from that of the second transistor T2 in the first embodiment described above. The second drain D' of the second transistor T2' is electrically connected to the second drain region 3ND2' via a contact hole CON10 provided in the first insulating layer 4. The second drain D' is formed of the same material as the first gate G and the second opposite electrode CE1, serving as the same layer as the first gate G and the second opposite electrode CE1.

[0070] The first embodiment described above Figure 2 The driving circuit board 1 shown is Figure 7 In the case of the drive circuit substrate 50 of Comparative Example 1, the second drain D' and the first gate G, which also serves as the second opposing electrode CE1, are formed as different layers. Therefore, a contact hole CON1 for electrically connecting the second drain D' and the first gate G, which also serves as the second opposing electrode CE1, needs to be provided in the second insulating layer 5. On the other hand, in the drive circuit substrate 10 according to the second embodiment, since the second drain D' and the first gate G, which also serves as the second opposing electrode CE1, are formed as the same layer and are made of the same material as the first gate G, which also serves as the second opposing electrode CE1, it is not necessary to separately provide a contact hole for electrically connecting the second drain D' and the first gate G, which also serves as the second opposing electrode CE1. In the unit drive circuit DRU of the drive circuit substrate 10, the formation area of ​​the first transistor T1 and the second transistor T2' can be reduced. Therefore, a drive circuit substrate 10 that enables high precision in the unit drive circuit DRU can be realized.

[0071] like Figure 10 as well as Figure 11As shown, the second semiconductor layer 3”’ of the second transistor T2’ includes a second low-concentration region 3LD1’ disposed between the second drain region 3ND2’ and the second channel region 3JD1’. The second low-concentration region 3LD1’ contains impurities and has a lower impurity concentration than the second source region 3ND1’ and the second drain region 3ND2’ respectively. The second gate G’ and the second drain D’ do not overlap with the second low-concentration region 3LD1’ when viewed from above. When the low-concentration region LDD is provided for the purpose of reducing the leakage current when the second transistor T2’ is turned off, the same function can be maintained even if the low-concentration region LDD is provided only on the drain side. Therefore, in this embodiment, the second low-concentration region 3LD1’ is provided only on the drain side in the second semiconductor layer 3”’ of the second transistor T2’. Therefore, without increasing the formation area of ​​the second transistor T2', the carriers, i.e. electrons, which have high kinetic energy and are accelerated, decelerate when they reach the low concentration region of impurities, i.e. the second low concentration region 3LD1', in front of the drain. Through momentum decay, it is possible to suppress entry into the second gate G'.

[0072] Figure 12 This is a diagram illustrating a portion of the manufacturing process of the drive circuit board 10 according to the second embodiment. Figure 13 This is a diagram illustrating another part of the manufacturing process of the drive circuit board 10 according to the second embodiment. Figure 14 This is a diagram showing another part of the manufacturing process of the drive circuit board 10 according to the second embodiment.

[0073] Figure 12 The S21, S22, S23, and S24 processes shown are each related to those in the first embodiment described above. Figure 4 The S1, S2, S3 and S4 processes shown are the same, so their descriptions are omitted here.

[0074] In this embodiment, in the first step described above, i.e. Figure 12 In processes S21 and S22 shown, together with the first semiconductor layer formed by the first channel region 3JD1, an island-shaped second semiconductor layer formed by the second channel region 3JD1' included in the second transistor T2 is formed. Furthermore, in the aforementioned second process, i.e. Figure 12 In the S23 process shown, a first insulating layer 4 is formed on a first semiconductor layer composed of a first channel region 3JD1 and a second semiconductor layer composed of a second channel region 3JD1'. Next, in the aforementioned third process, i.e. Figure 12In the S24 process shown, a resist film RM is also formed on the first insulating layer 4 disposed on the second semiconductor layer 3'. Using the resist film RM as a mask, impurities are implanted into a portion of the second semiconductor layer 3', thereby forming a second channel region 3JD1' and a second source region 3ND1' and a second drain region 3ND2' with a higher impurity concentration than the second channel region 3JD1'. Furthermore, in the process of forming the contact hole CON10 between the aforementioned third and fourth processes, i.e. Figure 12 In step S25 shown, a contact hole CON10 is formed in the first insulating layer 4 such that it overlaps with the second drain region 3ND2' when viewed from above. Next, in the aforementioned fourth step, i.e. Figure 12 In the S26 process shown, as the same layer as the first gate G and the second opposing electrode CE1, the second gate G' is formed on the first insulating layer 4 using the same material as the first gate G and the second opposing electrode CE1, overlapping with the second channel region 3JD1' when viewed from above. A second drain D' is also formed, electrically connected to the second drain region 3ND2' via contact hole CON10. Furthermore, in the aforementioned fifth process, namely... Figure 12 In the S29 and S30 processes shown, the second source S' electrically connected to the second source region 3ND1', the first drain D electrically connected to the first drain region 3ND1, and the first source S electrically connected to the first source region 3ND2 are treated as the same layer and formed of the same material.

[0075] In this embodiment, the process of forming the first low-concentration region 3LD1 is performed between the fourth and fifth processes, i.e. Figure 13 In process S27, using the second gate G' and the second drain D' as masks, impurities are implanted into a portion of the second semiconductor layer 3"', thereby forming a second low-concentration region 3LD1' with a lower impurity concentration than the second source region 3ND1' and the second drain region 3ND2', and a higher impurity concentration than the second channel region 3JD1'. That is, in process S27, using the second gate G' and the second drain D' as masks, low-concentration impurity implantation LDP is performed, thereby forming a second low-concentration region 3LD1' in a portion of the second channel region 3JD1' not protected by the second gate G' and the second drain D'. Furthermore, since the second source region 3ND1' and the second drain region 3ND2' already contain high concentrations of impurities, even with low-concentration impurity implantation LDP, the region remains a region containing high concentrations of impurities. Figure 13 The S28 process shown is the process for forming the second insulating layer 5. The second insulating layer 5 can be obtained by performing activation annealing (heat treatment) after film formation. Furthermore, Figure 14 The S31 process shown is the process of forming the passivation film 6.

[0076] [Third Implementation Method] Figure 15 This is a top view showing the schematic configuration of the drive circuit board 20 according to the third embodiment. Additionally, in Figure 15 The barrier layer 2, the first insulating layer 4, the second insulating layer 5, and the passivation film 6 are not shown in the figure. Figure 16 This is a cross-sectional view showing the schematic configuration of the drive circuit board 20 according to the third embodiment. Additionally, Figure 16 It is along Figure 15 The cross-sectional view of the drive circuit board 20 cut off from the X6-X6' line and the X7-X7' line is shown.

[0077] In this embodiment, Figure 15 and Figure 16 The driving circuit board 20 shown has a dual-gate transistor (i.e., the first transistor T1) and a dual-gate transistor (i.e., the second transistor T2), which is different from the board having a single-gate transistor (i.e., the first transistor T1) and a dual-gate transistor (i.e., the second transistor T2). Figure 2 and Figure 3 The first embodiment shown includes a drive circuit board 1 and a circuit having a single-gate transistor (i.e., a first transistor T1) and a single-gate transistor (i.e., a second transistor T2'). Figure 10 and Figure 11 The driving circuit 10 shown in the second embodiment is different. Furthermore, in each embodiment of this disclosure, the case of using a dual-gate transistor as a multi-gate transistor is described as an example, but it is not limited to this.

[0078] like Figure 15 and Figure 16 As shown, the first semiconductor layer 3 of the driving circuit substrate 20 includes a first source region 3ND2, a first drain region 3ND1, two first channel regions 3JD1 and 3JD2 disposed separately between the first source region 3ND2 and the first drain region 3ND1, a first low-concentration region 3LD1 disposed between the first channel region 3JD1 and the first drain region 3ND1 near the first drain region 3JD1 in the two first channel regions 3JD1 and 3JD2, and a first low-concentration region 3LD2 disposed between the first channel region 3JD1 and the first channel region 3JD2. The impurity concentration of the first low-concentration regions 3LD1 and 3LD2 is lower than that of the first drain region 3ND1. The first gate G, which also serves as the second opposing electrode CE1, does not overlap with the first low-concentration regions 3LD1 and 3LD2 when viewed from above. Furthermore, as Figure 15As shown, the second drain D' only needs to be electrically connected to the second drain region 3ND3' and the first gate G which is also the second opposite electrode CE1. In this embodiment, the second drain D' is configured to contact the second drain region 3ND3' via the contact hole CON3, and the first gate G which is also the second opposite electrode CE1 is configured to contact the second drain region 3ND3' via the contact holes CON1, CON4, and CON5.

[0079] Based on having a dual-gate transistor, i.e., the first transistor T1”, and a dual-gate transistor, i.e., the second transistor T2”. Figure 15 and Figure 16 The drive circuit board 20 shown can further improve current stability. The second transistor T2 included in the drive circuit board 20 has been described above in the first embodiment. The manufacturing method of the drive circuit board 20 can use the manufacturing method of the drive circuit board 1 described in the first embodiment, therefore detailed description is omitted here.

[0080] [Fourth Implementation Method] Figure 17 This is a top view showing the schematic configuration of the drive circuit board 30 according to the fourth embodiment. Additionally, Figure 17 The barrier layer 2, the first insulating layer 4, the second insulating layer 5, and the passivation film 6 are not shown in the figure. Figure 18 This is a cross-sectional view showing the schematic configuration of the drive circuit board 30 according to the fourth embodiment. Additionally, Figure 18 They are respectively along Figure 17 The cross-sectional view of the drive circuit board 30 with the X8-X8' and X9-X9' lines cut off is shown. Figure 19 This is a diagram illustrating a schematic manufacturing method of the drive circuit board 30 according to the fourth embodiment.

[0081] Figure 17 and Figure 18 The driving circuit substrate 30 shown in this embodiment differs from the first transistors T1 and T1” in the first embodiment 1 to the third embodiment in that it has a first transistor T1”’ having a first low concentration region 3LD1. The first low concentration region 3LD1 includes a first low concentration region 3LD1b and a second region 3LD1a. The second region 3LD1a is closer to the first drain region 3ND1 than the first low concentration region 3LD1b, and the impurity concentration is higher than that of the first region 3LD1b.

[0082] like Figure 17 and Figure 18As shown, the first semiconductor layer 3 of the driving circuit substrate 30 includes a first channel region 3JD, a first source region 3ND2, a first drain region 3ND1, and a first low-concentration region 3LD1 disposed between the first drain region 3ND1 and the first channel region 3JD. The impurity concentration of the first low-concentration region 3LD1 is lower than that of the first drain region 3ND1. The first low-concentration region 3LD1 includes a first region 3LD1b and a second region 3LD1a disposed closer to the first drain region 3ND1 than the first region 3LD1b. The impurity concentration of the second region 3LD1a is higher than that of the first region 3LD1b. The first gate G, which also serves as the second opposing electrode CE1, overlaps with the first region 3LD1b when viewed from above, but does not overlap with the second region 3LD1a.

[0083] like Figure 19 As shown, the manufacturing method of the drive circuit board 30 includes... Figure 19 The S41 process shown and Figure 19 The S42 process shown is a process in which a resist film RM of a predetermined shape is formed on the first insulating layer 4, and impurities are injected into a portion of the first semiconductor layer 3 using the resist film RM as a mask, thereby forming a first channel region 3JD, a first source region 3ND2 with a higher impurity concentration than the first channel region 3JD, and a first drain region 3ND1.

[0084] exist Figure 19 In the S41 process shown, a resist film (first resist film) RM is used as a mask to implant a low concentration of impurities LDP into a part of the first semiconductor layer 3, thereby forming a first channel region 3JD and a first low concentration region 3LD1b with a higher impurity concentration than the first channel region 3JD.

[0085] exist Figure 19 In the S42 process shown, after removing the resist film (first resist film) RM, a resist film (second resist film) RM, which is set in a way that overlaps with a portion of the first region 3LD1b of the first low-concentration region 3LD1 that is connected to the first channel region 3JD when viewed from above, is used as a mask to implant high-concentration impurities (HDP) into a portion of the first semiconductor layer 3, thereby forming a first source region 3ND2 and a first drain region 3ND1 with a higher impurity concentration than the first channel region 3JD and the first region 3LD1b of the first low-concentration region 3LD1.

[0086] In the process of forming the first gate G and the second counter electrode CE1, namely Figure 19In the S43 process shown, after the resist film (second resist film) RM is removed, a first gate G and second relative electrode CE1 is formed on the first insulating layer 4 in such a way that a part of the first region 3LD1b of the first low concentration region 3LD1 that is connected to the first channel region 3JD, the first channel region 3JD, and a part of the first source region 3ND2 that is the first relative electrode CE2 overlap.

[0087] Figure 19 The S44 process shown is the process for forming the second region 3LD1a of the first low-concentration region 3LD1. Figure 19 The S44 process shown is the process of forming the first gate G and the second opposite electrode CE1 in the second region 3LD1a of the first low concentration region 3LD1. Figure 19 The S43 process shown is related to the formation Figure 19 The process S45 shown is performed between the processes of the first drain electrode D, which is electrically connected to the first drain region 3ND1, and the first source electrode S, which is electrically connected to the first source region 3ND2. This is done during the formation of... Figure 19 In the S44 process shown, which is the process of the second region 3LD1a of the first low concentration region 3LD1, the first gate G, which is also the second opposite electrode CE1, is used as a mask to implant a portion of the first semiconductor layer 3 with low concentration impurities (LDP), thereby forming the second region 3LD1a of the first low concentration region 3LD1, which has a lower impurity concentration than the first source region 3ND2 and the first drain region 3ND1, and a higher impurity concentration than the first region 3LD1b of the first low concentration region 3LD1.

[0088] As described above, the drive circuit substrate 30 of this embodiment includes a first transistor T1”' having a first low-concentration region 3LD1. The first low-concentration region 3LD1 includes a first region 3LD1b and a second region 3LD1a. The second region 3LD1a is positioned closer to the first drain region 3ND1 than the first region 3LD1b, and has a higher impurity concentration than the first region 3LD1b. Furthermore, the first gate G and second opposite electrode CE1 of the first transistor T1”' overlaps with the first region 3LD1b when viewed from above, and the first transistor T1”' has a GOLD (Gate-Overlapped LDD) structure. In the case of such a GOLD (Gate-Overlapped LDD) structured first transistor T1”', compared with the LDD (Lightly Doped Drain) structured first transistors T1, T1”, reliability can be further improved, and the decrease in current (Ion) when the transistor is turned on can be suppressed. Therefore, according to the drive circuit substrate 30 having the first transistor T1”', a large current can be supplied without increasing the size of the substrate, and high reliability can be achieved.

[0089] [Cross-references to related applications] This application claims priority to Japanese Patent Application No. 2025-022666, filed on February 14, 2025, the entire contents of which are incorporated herein by reference.

[0090] Industrial availability This disclosure can be used for driving circuit boards and methods for manufacturing driving circuit boards.

[0091] Explanation of reference numerals in the attached figures 1, 10, 20, 30: Drive circuit board; 3, 3”: First semiconductor layer; 3', 3”': Second semiconductor layer; 4: First insulating layer; 5: Second insulating layer; 6: Passivation film; 3JD1, 3JD2: First trench area; 3JD1', 3JD2': Second channel area; 3ND2: First source region; 3ND1: First drain region; 3LD1, 3LD2: First low concentration region; 3LD1a: The second region of the first low-concentration region; 3LD1b: The first region of the first low concentration region; 3ND1': Second source region; 3ND3': Second drain region; 3ND2': High concentration region; 3LD1”~3LD4”: Second low concentration region; T1, T1', T1'”: First transistor; T2, T2': Second transistor; Cs: Holding capacitor; S: First source pole; D: First drain electrode; G: First gate; S': Second source pole; D': Second drain electrode; G': Second gate; CE2: First relative electrode; CEl: Second relative electrode; DRU: Unit drive circuit; CON1~CON12: Contact holes.

Claims

1. A driving circuit board, characterized in that, It includes a first transistor, the first transistor having: An island-shaped first semiconductor layer includes a first channel region, a first source region containing impurities, and a first drain region; A first insulating layer is disposed on the first semiconductor layer; The first gate electrode also serves as the second opposite electrode, and is disposed on the first insulating layer in such a way that it overlaps with a portion of the first channel region and the first opposite electrode, i.e., the first source region, when viewed from above. The first drain is electrically connected to the first drain region; The first source electrode is electrically connected to the first source electrode region; as well as A holding capacitor, comprising a first opposing electrode and a second opposing electrode, It has multiple unit drive circuits, each of which includes the first transistor.

2. The driving circuit board according to claim 1, characterized in that, The first semiconductor layer is composed of a first channel region, a first source region, a first drain region, and a first low-concentration region disposed between the first drain region and the first channel region. The impurity concentration in the first low-concentration region is lower than the impurity concentration in the first drain region. The first gate, which also serves as the second opposite electrode, does not overlap with the first low-concentration region when viewed from above.

3. The driving circuit board according to claim 1, characterized in that, The first semiconductor layer includes: The first source region; The first drain region; Two first channel regions, separated from each other, are provided between the first source region and the first drain region; and A first low-concentration region is located between the two first channel regions and between the first channel region and the first drain region in the two first channel regions. The impurity concentration in the first low-concentration region is lower than the impurity concentration in the first drain region. The first gate electrode, which also serves as the second opposite electrode, does not overlap with the first low-concentration region when viewed from above.

4. The driving circuit board according to claim 1, characterized in that, The first semiconductor layer includes a first channel region, a first source region, a first drain region, and a first low-concentration region disposed between the first drain region and the first channel region. The impurity concentration in the first low-concentration region is lower than the impurity concentration in the first drain region. The first low-concentration region includes a first region and a second region located closer to the first drain region than the first region. The impurity concentration in the second region is higher than that in the first region. The first gate electrode, which also serves as the second opposite electrode, overlaps with the first region when viewed from above, but does not overlap with the second region.

5. The driving circuit board according to any one of claims 1 to 4, characterized in that, Each of the plurality of unit drive circuits includes a second transistor. The second transistor has: The island-shaped second semiconductor layer includes a second channel region and a second source region and a second drain region containing the impurities; The first insulating layer is disposed on the second semiconductor layer; A second gate is disposed on the first insulating layer in such a way that it overlaps with the second channel region when viewed from above; The second drain is electrically connected to the second drain region and the first gate, which is also the second opposing electrode; and The second source is electrically connected to the second source region.

6. The driving circuit board according to claim 5, characterized in that, The second drain electrode is electrically connected to the second drain electrode region via a contact hole disposed in the first insulating layer. The second drain is in the same layer as the first gate and second opposite electrode, and is formed of the same material as the first gate and second opposite electrode.

7. The driving circuit board according to claim 6, characterized in that, The second semiconductor layer includes a second low-concentration region, which is disposed between the second drain region and the second channel region. The impurity concentration in the second low-concentration region is lower than the impurity concentration in the second drain region. The second gate and the second drain do not overlap with the second low-concentration region when viewed from above.

8. A method for manufacturing a driving circuit board, characterized in that, It includes: In the first step, an island-shaped first semiconductor layer is formed in a first transistor, the first transistor including a holding capacitor, the holding capacitor including a first opposite electrode and a second opposite electrode; The second step involves forming a first insulating layer on the first semiconductor layer; In the third step, a resist film of a specified shape is formed on the first insulating layer. Using the resist film as a mask, impurities are injected into a portion of the first semiconductor layer, thereby forming a first channel region and a first source region and a first drain region with a higher impurity concentration than the first channel region. In the fourth step, after removing the resist film, a first gate and second opposite electrode are formed on the first insulating layer in a manner that overlaps with the first channel region and a portion of the first source region which serves as the first opposite electrode when viewed from above. The fifth step involves forming a first drain and a first source. The first drain is electrically connected to the first drain region, and the first source is electrically connected to the first source region. Multiple unit drive circuits are formed, each unit drive circuit including the first transistor.

9. The method for manufacturing a driving circuit board according to claim 8, characterized in that, In the fourth step, when viewed from above, the first gate, which also serves as the second opposing electrode, is formed in a manner that does not overlap with a portion of the first drain region side of the first channel region. In the process of forming the first low-concentration region between the fourth and fifth processes, the first gate and second opposite electrode are used as a mask to implant the impurities into a portion of the first semiconductor layer, thereby forming the first low-concentration region. The impurity concentration in the first low-concentration region is lower than the impurity concentration in the first source region and the first drain region, and higher than the impurity concentration in the first channel region.

10. The method for manufacturing a driving circuit board according to claim 8 or 9, characterized in that, In the first step, an island-shaped second semiconductor layer comprising the second transistor is formed together with the first semiconductor layer. In the second process, the first insulating layer is formed on the first semiconductor layer and the second semiconductor layer. In the third step, the resist film is formed on the first insulating layer disposed on the second semiconductor layer. Using the resist film as a mask, the impurities are implanted into a portion of the second semiconductor layer, thereby forming a second channel region, a second source region with a higher impurity concentration than the second channel region, and a second drain region. In the fourth step, a second gate is formed on the first insulating layer in a manner that overlaps with the second channel region when viewed from above. In the fifth step, the second drain, the second source, the first drain, and the first source are treated as a single layer and formed of the same material. The second drain is electrically connected to the second drain region and the first gate / second opposing electrode, and the second source is electrically connected to the second source region. Multiple unit drive circuits are formed, each unit drive circuit comprising the first transistor and the second transistor.

11. The method for manufacturing a driving circuit board according to claim 9, characterized in that, In the first step, an island-shaped second semiconductor layer comprising the second transistor is formed together with the first semiconductor layer. In the second process, the first insulating layer is formed on the first semiconductor layer and the second semiconductor layer. In the third step, the resist film is formed on the first insulating layer disposed on the second semiconductor layer. Using the resist film as a mask, the impurities are implanted into a portion of the second semiconductor layer, thereby forming a second channel region, a second source region with a higher impurity concentration than the second channel region, and a second drain region. In the process of forming a contact hole between the third and fourth processes, the contact hole is formed in the first insulating layer in a manner that overlaps with the second drain region when viewed from above. In the fourth step, a second gate is formed on the first insulating layer, using the same material as the first gate and second opposing electrode, and overlapping with the second channel region when viewed from above. A second drain is also formed, electrically connected to the second drain region via the contact hole. In the fifth step, the second source, the first drain, and the first source, which are electrically connected to the second source region, are treated as the same layer and formed of the same material. Multiple unit drive circuits are formed, each unit drive circuit comprising the first transistor and the second transistor.

12. The method for manufacturing a driving circuit board according to claim 11, characterized in that, In the process of forming the first low-concentration region between the fourth and fifth processes, the impurities are implanted into a portion of the second semiconductor layer using the second gate and the second drain as masks, thereby forming a second low-concentration region. The impurity concentration of the second low-concentration region is lower than that of the second source region and the second drain region and higher than that of the second channel region.

13. The method for manufacturing a driving circuit board according to claim 8, characterized in that, The third process has the following characteristics: The process of forming a first region by implanting the impurities into a portion of the first semiconductor layer using a first resist film as a mask, thereby forming a first channel region and a first low-concentration region with a higher impurity concentration than the first channel region; After removing the first resist film, a second resist film is set up in such a way that it overlaps with a portion of the first region of the first low-concentration region connected to the first channel region when viewed from above. The impurities are then injected into a portion of the first semiconductor layer to form a first source region and a first drain region with an impurity concentration higher than that of the first channel region and the first region of the first low-concentration region. In the fourth step, after the second resist film is removed, a first gate and second opposite electrode are formed on the first insulating layer in such a way that a portion of the first region of the first low-concentration region that is connected to the first channel region when viewed from above, the first channel region and a portion of the first source region that serves as the first opposite electrode overlap. as well as In the process of forming the second region of the first low-concentration region between the fourth and fifth processes, the impurities are implanted into a portion of the first semiconductor layer by using the first gate and second opposite electrode as a mask, thereby forming the second region of the first low-concentration region, which has a lower impurity concentration than the impurity concentrations of the first source region and the first drain region, and a higher impurity concentration than the first region of the first low-concentration region.

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