Electrostatic discharge protection device with embedded PNP SCR structure and its preparation method

Abstract

This application discloses an electrostatic discharge (ESD) protection device with an embedded PNP SCR structure and its fabrication method, belonging to the field of semiconductor technology. The device includes: a P-type substrate; an N-type buried layer formed on the surface of the P-type substrate; multiple high-voltage N-wells formed on the surface of the N-type buried layer; wherein each high-voltage N-well has an N-well forming an N-type contact on its surface; several active regions, with an active region formed between each pair of adjacent high-voltage N-wells; each active region has at least two P-wells forming P-type contacts on its surface, and one P-type contact surface forms a sequentially arranged heavily doped N-type region, a heavily doped P-type region, and a heavily doped N-type region, while other P-type contact surfaces each form a heavily doped P-type region, thus forming multiple current discharge paths between the P-type contacts of adjacent active regions; the heavily doped regions of each active region are electrically connected as an electrode. The structure of this application has multiple parasitic current discharge paths, which can reduce the trigger voltage, improve the sustaining voltage, and enhance the discharge capability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an electrostatic discharge protection device with an embedded PNP SCR structure and its fabrication method. Background Technology

[0002] Conventional SCR (Silicon Controlled Rectifier) ​​structures for electrostatic discharge (ESD) devices are characterized by high failure current and low sustaining voltage. In traditional applications, excessively low sustaining voltage can easily cause severe snap-back phenomena, which can easily lead to ESD discharge devices turning on or discharging unevenly. Moreover, once triggered, they cannot actively exit and require power-off and power-on. If power-off is not timely, it can easily cause latch-up effects, and in severe cases, it can lead to direct chip burnout, which is not conducive to the design and application of high-voltage products. Summary of the Invention

[0003] The purpose of this invention is to overcome the problems of high failure current, low sustaining voltage and few discharge paths in the prior art, and to provide an electrostatic discharge protection device with an SCR structure embedded with a PNP structure and a method for its fabrication. By designing multiple parasitic current discharge paths, the trigger voltage is reduced and the sustaining voltage and discharge capability are improved.

[0004] The first aspect of this application provides an electrostatic discharge protection device with an SCR structure having an embedded PNP, comprising: P-type substrate; An N-type buried layer is formed on the surface of the P-type substrate; A P-type epitaxial layer is formed on the surface of the N-type buried layer; Multiple high-voltage N-wells are formed in the P-type epitaxial layer; wherein, each high-voltage N-well has an N-well as an N-type contact on its surface, an active region is formed between two adjacent high-voltage N-wells, and at least two P-wells are formed on the surface of each active region as P-type contacts, and an N-type heavily doped region, a P-type heavily doped region, and an N-type heavily doped region are formed on one of the P-type contact surfaces in sequence, and a P-type heavily doped region is formed on the other P-type contact surfaces to form multiple current discharge paths between the P-type contacts of two adjacent active regions; In this configuration, the heavily doped regions of two adjacent active regions are electrically connected and each serves as an electrode.

[0005] The device structure of this application forms two P+ / PW regions in each active region. Based on path 1, three discharge paths (2 / 3 / 4) are introduced, providing an initial startup current for path 1 and reducing the overall trigger voltage. Simultaneously, the introduction of new discharge paths extracts excess carriers from path 1, preventing carriers from concentrating in a single path (such as the traditional path 1) and instead dispersing them to other parasitic paths. This reduces the conductance modulation effect in the base region, improves the sustaining voltage, and effectively suppresses latch-up. Furthermore, under the same area conditions, its discharge capability is significantly greater than that of an LPNP device, and its failure current is also significantly greater, resulting in superior performance. This also improves the current discharge capability of the ESD device, increases the failure current level, and enhances product reliability.

[0006] As described above, the electrostatic discharge protection device with an embedded PNP SCR structure may optionally include three high-voltage N-wells and two active regions.

[0007] The symmetrical three-well, two-region structure is compact and easy to manufacture, ensuring uniform current distribution between the two active regions. This avoids local overheating and current congestion, and effectively constructs multiple current paths as required. This allows the device to trigger multiple paths simultaneously during ESD events, improving the uniformity of conduction. Furthermore, the three N-type deep wells provide sufficient isolation and carrier transport channels, ensuring the high-voltage performance of the device.

[0008] In the electrostatic discharge protection device with an embedded PNP SCR structure as described above, the active region may optionally include a P-type active region.

[0009] The P-type active region, as the main transport channel for holes, works in conjunction with the N-type layer to form parasitic PNP and NPN transistors, thus realizing the self-locking conduction characteristic of SCR.

[0010] As described above, in the electrostatic discharge protection device with an embedded PNP SCR structure, optionally, a shallow trench for insulating isolation is formed between two adjacent heavily doped regions.

[0011] Shallow trench isolation (STI) structures are used to insulate and isolate different heavily doped regions and devices, preventing leakage and parasitic conduction, thereby effectively suppressing parasitic effects between devices and ensuring that current flows mainly through the designed discharge path, thus improving device reliability.

[0012] As described above, the electrostatic discharge protection device with an embedded PNP SCR structure may optionally include multiple current discharge paths, including PNP discharge paths and PNPN discharge paths.

[0013] The PNP path can be triggered earlier, reducing the trigger voltage; the PNPN path provides high current discharge capability. The two work together to improve the overall ESD protection performance of the device, giving the device high holding voltage and high discharge capability.

[0014] In the electrostatic discharge protection device with an embedded PNP SCR structure as described above, optionally, each of the N-type contact surfaces has an N-type heavily doped region formed.

[0015] The N+ heavily doped region reduces the resistance of the N-type contact, making it easier for electrons to be injected and collected, thus improving the device's conduction efficiency.

[0016] A second aspect of this application provides a method for fabricating an electrostatic discharge (ESD) protection device with an embedded PNP SCR structure, comprising: Provide a P-type substrate; An N-type buried layer is formed on the surface of the P-type substrate; A P-type epitaxial layer is formed on the surface of the N-type buried layer; Multiple high-voltage N-wells are formed in the P-type epitaxial layer; wherein, each high-voltage N-well has an N-well forming on its surface as an N-type contact; An active region is formed between each of the two adjacent high-voltage N-wells; wherein, an N-well is formed on the surface of each high-voltage N-well as an N-type contact, an active region is formed between each of the two adjacent high-voltage N-wells, and at least two P-wells are formed on the surface of each active region as P-type contacts, and an N-type heavily doped region, a P-type heavily doped region, and an N-type heavily doped region are formed on the surface of one P-type contact, and a P-type heavily doped region is formed on the other P-type contact surfaces, so as to form multiple current discharge paths between the P-type contacts of the two adjacent active regions; Two adjacent heavily doped regions of the active region are electrically connected to each other as an electrode.

[0017] This fabrication method allows for precise control of the doping concentration and thickness of each layer, ensuring that the device's structure and performance meet design requirements. It also forms two P+ / PW regions in each active region and introduces three discharge paths (2 / 3 / 4) on top of path 1, creating multiple current discharge paths. This reduces the device's trigger voltage and increases its sustaining voltage, effectively suppressing latch-up. Furthermore, the parallel existence of multiple discharge paths significantly increases the total current the device can withstand, thereby improving the failure current It2 and overall ESD discharge capability, raising the failure current level, and further enhancing product reliability.

[0018] The method for fabricating an electrostatic discharge (ESD) protection device with an embedded PNP SCR structure as described above may optionally further include: An N-type heavily doped region is formed on the N-type contact surface.

[0019] By selectively forming heavily doped N-type regions 111 (i.e., N+ regions) on the surface of the N-well, the resistance of the N-type contact region is reduced, thereby improving the conduction efficiency and reliability of the device.

[0020] The method for fabricating an electrostatic discharge (ESD) protection device with an embedded PNP SCR structure as described above may optionally further include: Shallow trenches are formed between two adjacent heavily doped regions for insulation.

[0021] Shallow trench isolation (STI) structures are used to insulate and isolate different heavily doped regions and devices, preventing leakage and parasitic conduction. This effectively suppresses parasitic effects between devices, ensuring that current flows primarily through the designed discharge path and improving device reliability. Attached Figure Description

[0022] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, and the same or corresponding reference numerals denote the same or corresponding parts, wherein: Appendix Figure 1 A schematic diagram of an electrostatic discharge protection device with an embedded PNP SCR structure provided in an embodiment of this application; Appendix Figure 2 This is a schematic flowchart illustrating a method for fabricating an electrostatic discharge protection device with an embedded PNP SCR structure, as provided in an embodiment of this application. Attached image description: 101 - P-type substrate; 102 - N-type buried layer; 103 - High-voltage N-well; 104 - N-well; 105 - P-well; 106 / 108 / 111 - N-type heavily doped region; 107 / 109 - P-type heavily doped region; 110 - Shallow trench; 112 - P-type epitaxial layer; 1121 - Active region; A / B - Electrode. Detailed Implementation

[0024] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0025] In the existing technology, there are two methods to solve the shortcomings of conventional SCR structures in electrostatic discharge protection devices. The first is to use high-voltage LPNP devices. However, this solution has the characteristics of low failure current and poor discharge capability. Therefore, a larger area is required to achieve the same failure current requirement, which has high area cost requirements. It is rarely used in products with high voltage and high HBM level. This undoubtedly greatly increases the chip cost. The cost is not proportional to the return and it is not the mainstream solution in the industry.

[0026] The second type is the conventional SCR structure. Although there are slight differences in its structure and working principle under different processes or by different designers, the general structure and working principle are very similar. Both introduce avalanche current under high voltage triggering, which further promotes the conduction of the PNPN positive feedback path, thereby establishing a low-resistance discharge path. However, due to its large failure current and relatively simple discharge path, and in order to have a relatively large breakdown voltage, its PEPI doping concentration is usually low. When an avalanche breakdown current flows through the trigger HBM, the SCR discharge path PNPN opens, and the ESD device begins to discharge current. When the current continues to increase, a large number of charge carriers flow into the base region, and the base region conductance modulation effect of PNP and NPN is aggravated, resulting in an excessively low SCR holding voltage, which easily triggers the board-level latch-up effect, leading to chip failure. This is not conducive to the use of the chip in the application and causes some trouble for customers.

[0027] Based on this, such as Figure 1 As shown, this embodiment provides an electrostatic discharge (ESD) protection device with an embedded PNP SCR structure; it includes: a P-type substrate 101, which serves as the substrate of the device and provides the basis for the growth and fabrication of the entire structure; an N-type buried layer 102, formed on the surface of the P-type substrate, which provides a low-resistance lateral current channel and helps to isolate the bottom P-type substrate, reducing noise coupling and latch-up risk; and a P-type epitaxial layer 112, formed on the surface of the N-type buried layer, which is a single-crystal silicon layer grown on the N-type buried layer with a low doping concentration, providing a basis for the subsequent formation of active region devices. The material provides high-quality bulk material and forms an important part of the P-type region in both the longitudinal and lateral structures of the device. Multiple high-voltage N-wells 103 are formed in the N-type buried layer 102. Specifically, these high-voltage N-wells extend vertically downward from the surface of the P-type epitaxial layer, penetrate the P-type epitaxial layer, and connect to the bottom N-type buried layer. The through-through design ensures a low-resistance longitudinal connection from the device surface to the N-type buried layer. Each high-voltage N-well has an N-well (i.e., N-well 104) formed on its top surface region. This N-well serves as the N-type contact region for forming a good ohmic contact with the subsequent metal electrode.

[0028] Between two adjacent high-voltage N-wells 103, a region (i.e., an active region 1121) is naturally formed in the P-type epitaxial layer 112. This active region 1121 is used to construct an embedded PNP structure and multiple discharge paths. Within each active region 1121, at least two P-wells 105 are formed on its surface through an implantation process, serving as P-type contact regions. One of the P-type contact surfaces is selectively implanted to form three heavily doped regions arranged in sequence: an N-type heavily doped region 106, a P-type heavily doped region 107, and an N-type heavily doped region 108. This "NPN" implantation structure constitutes the emitter, base, and collector of an embedded N-type lateral transistor (NPN) within the P-well.

[0029] In addition, only one heavily doped P-type region 109 is formed on other P-type contact surfaces within the active region; and the heavily doped regions of each active region (including 106, 107, 108, and 109) are electrically connected through metal silicide processes or direct metal contacts, and are jointly led out as an electrode (electrode A or electrode B) for connecting the high-voltage terminal in ESD events.

[0030] Among them, such as Figure 1 As shown, multiple high-voltage N-wells 103 can be used to form multiple active regions 1121, and the structure within each active region 1121 is the same. The electrodes formed by electrically connecting the heavily doped regions of two adjacent active regions 1121 constitute the two electrodes (cathode and anode) of the device.

[0031] The number of P-wells 105 formed within an active region 1121 may include multiple ones. In this embodiment, two are preferred, which are used to form the "NPN" implantation structure (106, 107, 108) and a separate P-type heavily doped region 109, respectively. This ensures that multiple current discharge paths can be formed between two adjacent active regions 1121 while reducing chip size and area.

[0032] By setting multiple P-type contacts in each active region and employing differentiated injection techniques for different P-type contacts (one being an NPN structure and the rest being P+ structures), combined with the underlying P-type epitaxial layer 112, high-voltage N-well 103, and N-type buried layer 102, multiple parallel current discharge paths with different triggering characteristics are formed between the P-type contacts of adjacent active regions (e.g., Figure 1 The diagram illustrates paths 1 (red line), 2 (light green line), 3 (yellow line), and 4 (brown line). These paths include, but are not limited to, pure PNP paths (paths 2 and 3) and PNPN thyristor paths (paths 1 and 4).

[0033] By constructing multiple parallel current discharge paths within the device using the above structure, when an ESD event occurs (e.g., a positive voltage is applied to the positive terminal A), these paths do not activate simultaneously, but rather exhibit a graded, step-by-step triggering process. Specifically, path 3 triggers first, flowing a portion of the current, causing the inflection point of the IV curve to appear earlier, thus triggering the device earlier and effectively reducing the trigger voltage. As the current gradually increases, paths 1, 2, and 4 are successively activated.

[0034] This multi-parasitic-path design prevents charge carriers from concentrating in a single path (such as the traditional path 1), instead dispersing and drifting to other parasitic paths. This dispersion effect significantly reduces the conductance modulation effect in localized areas, thereby increasing the device's sustaining voltage and effectively suppressing latch-up. Simultaneously, the parallel existence of multiple discharge paths substantially increases the total current the device can withstand, thus improving the failure current It2 and overall ESD discharge capability, raising the failure current level, and further enhancing product reliability.

[0035] The device structure of this application forms two P+ / PW regions in each active region. Based on path 1, three discharge paths (2 / 3 / 4) are introduced, providing an initial startup current for path 1 and reducing the overall trigger voltage. Simultaneously, the introduction of new discharge paths extracts excess carriers from path 1, preventing carriers from concentrating in a single path (such as the traditional path 1) and instead dispersing them to other parasitic paths. This reduces the conductance modulation effect in the base region, improves the sustaining voltage, and effectively suppresses latch-up. Furthermore, under the same area conditions, its discharge capability is significantly greater than that of an LPNP device, and its failure current is also significantly greater, resulting in superior performance. This also improves the current discharge capability of the ESD device, increases the failure current level, and enhances product reliability.

[0036] As one implementation method, such as Figure 1 As shown, the preferred number of high-voltage N-wells 103 is three, and correspondingly, the number of active regions located between adjacent high-voltage N-wells is two. This symmetrical three-well, two-region structure is compact and simple to implement, ensuring uniform current distribution between the two active regions, avoiding local overheating and current congestion, and effectively constructing the required multiple current paths. This allows the device to trigger multiple paths simultaneously during ESD events, improving the uniformity of conduction. Furthermore, the three N-type deep wells provide sufficient isolation and carrier transport channels, ensuring the high-voltage performance of the device.

[0037] In this embodiment, the active region is specifically a P-type active region (PEPI / PW), which serves as the P-type layer of the SCR. It alternates with the N-type deep well and the N-type buried layer to form a PN junction, constituting the four-layer structure of the SCR. The P-type active region serves as the main transport channel for holes and, together with the N-type layer, forms parasitic PNP and NPN transistors, realizing the self-locking conduction characteristic of the SCR.

[0038] To further isolate the heavily doped regions, prevent surface leakage, and precisely control the current flow, shallow trench isolation structures (STI) 110 are formed between two adjacent heavily doped regions (e.g., between an N-type heavily doped region and a P-type heavily doped region) for insulating isolation. This is used to isolate different heavily doped regions and devices, prevent leakage and parasitic conduction, and thus effectively suppress parasitic effects between devices. It ensures that the current mainly flows through the designed discharge path, thereby improving the reliability of the devices.

[0039] for Figure 1 The structure forms multiple current discharge paths, including but not limited to PNP discharge paths and PNPN discharge paths. For example, a path starting from electrode A (anode), passing through the P+ heavily doped region / P-well, N-well / high-voltage N-well, P-well, and then to the N+ heavily doped region of electrode B (cathode), constitutes a PNPN thyristor path; while some paths may only involve punch-through or breakdown between P-wells and N-wells, constituting a PNP path.

[0040] Specifically, the PNP discharge path consists of a P-type active region (P+), an N-type deep well (HVNW / NBL), and a P-type active region (P+), with holes as the primary charge carrier. The PNPN discharge path consists of a P-type active region (P+), an N-type deep well (HVNW / NBL), a P-type active region (P+), and an N-type heavily doped region (N+), forming a four-layer structure for the SCR, achieving self-locking conduction.

[0041] The PNP path can be triggered earlier, reducing the trigger voltage; the PNPN path provides high current discharge capability. The two work together to improve the overall ESD protection performance of the device, giving the device high holding voltage and high discharge capability.

[0042] To form a good ohmic contact and reduce contact resistance, a heavily doped N-type region 111 (i.e., N+ region) is formed on the surface of each N-type contact region (i.e., N-well 104). The N+ heavily doped region reduces the resistance of the N-type contact, making it easier for electrons to be injected and collected, thereby improving the conduction efficiency of the device.

[0043] Based on the same application concept, such as Figure 2As shown, this embodiment provides a method for preparing an electrostatic discharge protection device with an embedded PNP SCR structure, comprising the following steps.

[0044] Step S10: Provide a P-type substrate; Step S20: Form an N-type buried layer on the surface of a P-type substrate; Step S30: Form a P-type epitaxial layer on the surface of the N-type buried layer; Step S40: Multiple high-voltage N-wells are formed in the P-type epitaxial layer; wherein, an N-well is formed on the surface of each high-voltage N-well as an N-type contact; Step S50: An active region is formed between two adjacent high-voltage N-wells; wherein, at least two P-wells are formed on the surface of each active region as P-type contacts, and an N-type heavily doped region, a P-type heavily doped region and an N-type heavily doped region are formed on the surface of a P-type contact, and a P-type heavily doped region is formed on the other P-type contact surfaces, so as to form multiple current discharge paths between the P-type contacts of two adjacent active regions. Step S60: Electrically connect the heavily doped regions of two adjacent active regions as one electrode.

[0045] Specifically, a high-purity P-type single-crystal silicon wafer is first selected as the substrate. Then, an N-type buried layer (NBL) is formed on the surface of the P-type substrate through ion implantation and annealing processes. After the formation of the N-type buried layer, an epitaxial growth technology such as chemical vapor deposition (CVD) is used to grow a P-type single-crystal silicon layer with a certain thickness and specific doping concentration on the surface of the N-type buried layer, namely the P-type epitaxial layer. In order to define the pattern of the high-voltage N-well through photolithography, a high-energy deep-well ion implantation process is used to implant N-type impurities (such as phosphorus) through the P-type epitaxial layer to the bottom and connect with the N-type buried layer. After a high-temperature push-well process, a high-voltage N-well is formed that extends vertically downward from the surface of the P-type epitaxial layer until it touches the N-type buried layer. Subsequently, N-wells are formed on the top surface area of ​​each high-voltage N-well through a conventional well implantation process.

[0046] After forming the N-wells, an active region is formed between two adjacent high-voltage N-wells, and differentiated P-type contacts and heavily doped regions are formed within the active region. Specifically, an active region is first defined in the P-type epitaxial layer region between two adjacent high-voltage N-wells; within each active region, at least two P-wells are formed as P-type contact regions through photolithography and implantation processes; for one specific P-type contact (e.g., the first P-well), three ion implantations are performed sequentially using a first set of implantation masks: first, N-type implantation is performed to form a heavily doped N-type region; then, P-type implantation is performed to form a heavily doped P-type region; finally, N-type implantation is performed again to form a heavily doped N-type region, so that three heavily doped regions are arranged sequentially on the inner surface of the same P-well, forming an embedded NPN transistor structure; for other P-type contacts within the active region (e.g., the second P-well), a second set of implantation masks is used to perform only one heavily doped P-type implantation, forming a single heavily doped P-type region on its surface.

[0047] Finally, a metallization process is performed to deposit a metal layer (such as aluminum or titanium / titanium nitride / aluminum stack) on the device surface, and interconnect patterns are formed through photolithography and etching. All heavily doped regions of each active region (including the N+, P+, and N+ regions on the first P-well, and the P+ region on the second P-well) are electrically connected together and brought out as a single electrode (e.g., anode A). Simultaneously, the N-type contact region (the heavily doped N+ region on the N-well) is also connected and serves as another electrode (e.g., cathode B), thus completing the fabrication of the entire electrostatic discharge (ESD) device.

[0048] This fabrication method allows for precise control of the doping concentration and thickness of each layer, ensuring that the device's structure and performance meet design requirements. It also forms two P+ / PW regions in each active region and introduces three discharge paths (2 / 3 / 4) on top of path 1, creating multiple current discharge paths. This reduces the device's trigger voltage and increases its sustaining voltage, effectively suppressing latch-up. Furthermore, the parallel existence of multiple discharge paths significantly increases the total current the device can withstand, thereby improving the failure current It2 and overall ESD discharge capability, raising the failure current level, and further enhancing product reliability.

[0049] Furthermore, after forming the N-well in step S30 or after step S40, a heavily doped N-type region is selectively formed on the surface of the N-well by implanting a mask to reduce the resistance of the N-type contact region and improve the conduction efficiency and reliability of the device.

[0050] Before or after each of the implantation steps described above, a shallow trench isolation structure (STI) is formed in the region between two adjacent heavily doped regions through etching and dielectric filling processes for insulating isolation. The shallow trench isolation structure (STI) is used to isolate different heavily doped regions and devices, prevent leakage and parasitic conduction, thereby effectively suppressing parasitic effects between devices, ensuring that current flows mainly through the designed discharge path, and improving device reliability.

[0051] In summary, this application provides an SCR structure with embedded PNPs and its fabrication method. Through a unique layout of the well region and heavily doped region, a multi-stage, multi-path current discharge channel is constructed inside the SCR. This structure not only reduces the trigger voltage by early triggering but also significantly improves the sustaining voltage by utilizing the carrier dispersion effect, and greatly enhances the overall ESD discharge capability of the device. It effectively avoids the problems of latch-up and insufficient robustness of traditional SCR structures in ESD protection applications.

[0052] In the foregoing description of this application, unless otherwise expressly specified and limited, the terms "fixed," "installed," "connected," or "linked" should be interpreted broadly. For example, the term "linked" can refer to a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; or it can refer to the internal communication of two components or the interaction between two components. Therefore, unless otherwise expressly limited in this application, those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0053] Based on the above description of this application, those skilled in the art will also understand that terms used, such as "upper," "lower," "length," "width," "top," "bottom," "inner," "outer," "axial," "longitudinal," "transverse," "clockwise," or "counterclockwise," indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings of this application. These terms are used only for the purpose of facilitating the explanation of the application and simplifying the description, and are not intended to explicitly or implicitly suggest that the device or element involved must have the stated specific orientation, or be constructed and operated in a specific orientation. Therefore, the aforementioned orientation or positional relationship terms should not be understood or interpreted as limitations on the application.

[0054] Furthermore, the terms "first" or "second," etc., used in this application to refer to numbers or ordinal numbers are for convenience of description only and should not be construed as explicitly or implicitly indicating relative importance or specifying the number of indicated technical features. Also, a feature specified as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, or more, unless otherwise explicitly specified.

[0055] While numerous embodiments of this application have been shown and described herein, it will be appreciated by those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will arise in the mind and spirit of this application without departing from its intent. It should be understood that various alternatives to the embodiments of this application described herein may be employed in the practice of this application. The appended claims are intended to define the scope of protection of this application and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. An electrostatic discharge protection device with an embedded PNP SCR structure, characterized in that, include: P-type substrate; An N-type buried layer is formed on the surface of the P-type substrate; A P-type epitaxial layer is formed on the surface of the N-type buried layer; Multiple high-voltage N-wells are formed in the P-type epitaxial layer; wherein, each high-voltage N-well has an N-well as an N-type contact on its surface, an active region is formed between two adjacent high-voltage N-wells, and at least two P-wells are formed on the surface of each active region as P-type contacts, and an N-type heavily doped region, a P-type heavily doped region, and an N-type heavily doped region are formed on one of the P-type contact surfaces, and a P-type heavily doped region is formed on the other P-type contact surfaces, so as to form multiple current discharge paths between the P-type contacts of two adjacent active regions; In this configuration, the heavily doped regions of two adjacent active regions are electrically connected and each serves as an electrode.

2. The electrostatic discharge protection device with an embedded PNP SCR structure as described in claim 1, characterized in that, The number of high-voltage N-wells includes 3, and the number of active regions includes 2.

3. The electrostatic discharge protection device with an embedded PNP SCR structure as described in claim 2, characterized in that, The active region includes a P-type active region.

4. The electrostatic discharge protection device with an embedded PNP SCR structure as described in claim 1, characterized in that, Shallow trenches are formed between two adjacent heavily doped regions for insulation.

5. The electrostatic discharge protection device with an embedded PNP SCR structure as described in claim 1, characterized in that, Multiple current discharge paths include PNP discharge paths and PNPN discharge paths.

6. The electrostatic discharge protection device with an embedded PNP SCR structure as described in claim 1, characterized in that, Each of the N-type contact surfaces has an N-type heavily doped region.

7. A method for fabricating an electrostatic discharge (ESD) protection device with an embedded PNP SCR structure, characterized in that, include: Provide a P-type substrate; An N-type buried layer is formed on the surface of the P-type substrate; A P-type epitaxial layer is formed on the surface of the N-type buried layer; Multiple high-voltage N-wells are formed in the P-type epitaxial layer; wherein, each high-voltage N-well has an N-well forming on its surface as an N-type contact; An active region is formed between each of the two adjacent high-voltage N-wells; wherein, an N-well is formed on the surface of each high-voltage N-well as an N-type contact, an active region is formed between each of the two adjacent high-voltage N-wells, and at least two P-wells are formed on the surface of each active region as P-type contacts, and an N-type heavily doped region, a P-type heavily doped region, and an N-type heavily doped region are formed on the surface of one P-type contact, and a P-type heavily doped region is formed on the other P-type contact surfaces, so as to form multiple current discharge paths between the P-type contacts of the two adjacent active regions; Two adjacent heavily doped regions of the active region are electrically connected to each other as an electrode.

8. The method for preparing an electrostatic discharge protection device with an embedded PNP SCR structure as described in claim 7, characterized in that, Also includes: An N-type heavily doped region is formed on the N-type contact surface.

9. The method for preparing an electrostatic discharge protection device with an embedded PNP SCR structure as described in claim 7, characterized in that, Also includes: Shallow trenches are formed between two adjacent heavily doped regions for insulation.

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