Semiconductor device structure and fabrication method

Abstract

This invention provides a semiconductor device structure and its fabrication method, relating to the field of semiconductor technology. The semiconductor device structure includes a substrate, a deep trench isolation structure, a multi-finger gate transistor, and a dummy transistor. The deep trench isolation structure is disposed on the substrate and encloses a device region. The multi-finger gate transistor is disposed within the device region. The dummy transistor is disposed on opposite sides of the multi-finger gate transistor, and is located at the two edges of the device region along a first direction. The dummy transistor is configured to form a reverse-biased isolation diode structure, so that the electrostatic discharge current is uniformly distributed between the dummy transistor and the multi-finger gate transistor. Compared to existing technologies, this invention, by designing a reverse-biased isolation diode structure on both sides of the multi-finger gate transistor, can improve the device's ESD resistance and trigger voltage (Vt1), and can avoid edge damage reliability issues during local conduction, thus improving the overall robustness of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device structure and its fabrication method. Background Technology

[0002] Electrostatic discharge (ESD) is one of the main causes affecting the stability of integrated circuit systems and causing performance degradation of semiconductor products. In power IC chips, power output transistors such as laterally diffused metal-oxide semiconductors (LDMOS) and laterally insulated gate bipolar transistors (LIGBTs) usually directly face the external interface of the chip, requiring the device to have a certain degree of self-protection capability to resist the large current and strong electric field caused by ESD. The trigger voltage (Vt1) of the device under transmission line pulse (TLP) testing is an important parameter for measuring the device's resistance to ESD stress.

[0003] as follows Figure 1 As shown, the multi-finger HV LDMOS device (high voltage lateral diffusion MOS device) under the DTI SOIBCD process (SOI-based BCD process using deep trench isolation technology) is a repeating unit. In the design process, each finger is often defined to maintain the same width, that is, let L1=L2 in the figure.

[0004] However, in actual DTI etching processes, due to the influence of the dry process window, the well width of the pads adjacent to the DTI trench (deep trench isolation) will fluctuate, causing L2 to be less than L1. This results in the ESD current flowing through the pads on both sides first under TLP pulse testing. Since LDMOS is a hysteresis device, its terminal voltage is clamped at a low level and cannot continue to rise, causing a large number of main pads in the middle part to fail to be triggered and turned on normally.

[0005] In this scenario, only the fingers at both ends discharge ESD current, making it highly susceptible to localized edge damage and causing the trigger voltage (Vt1) to fall below the design target. The trigger voltage (Vt1) in this state is insufficient to characterize the overall ESD resistance of the device. Furthermore, the fluctuation range of the trigger voltage (Vt1) varies with the number of fingers (typically 3-5V below the design specification), significantly increasing the complexity of device design. Simultaneously, the local reliability of the fingers adjacent to the DTI Trench under ESD stress also faces severe challenges. Summary of the Invention

[0006] The purpose of this invention is to provide a semiconductor device structure and a method for fabricating the semiconductor device structure, which can improve the device's ESD resistance and trigger voltage (Vt1), and avoid edge damage reliability issues during local conduction, thereby improving the overall robustness of the device.

[0007] In a first aspect, the present invention provides a semiconductor device structure, comprising: Substrate; A deep trench isolation structure is disposed on the substrate, the deep trench isolation structure enclosing a device region; A multi-finger gate transistor disposed within the device region, the multi-finger gate transistor comprising a plurality of gates arranged along a first direction, each gate extending along a second direction, wherein the first direction and the second direction are perpendicular to each other; The dummy transistors are disposed on opposite sides of the multi-finger gate transistor, and the dummy transistors are located at the two sides of the device region along the first direction. The dummy transistor is configured to form a reverse-biased isolated diode structure so that the electrostatic discharge current is evenly distributed between the dummy transistor and the multi-finger gate transistor.

[0008] In an optional embodiment, the pseudo transistor includes at least one first body region and a first drift region, the first drift region being in contact with the multi-finger gate transistor, the first body region being in contact with the first drift region and the deep trench isolation structure on both sides along the first direction, and the first drift region and the first body region having opposite conductivity types.

[0009] In an optional embodiment, a first electrode region is disposed on the surface of the first body region, and a second electrode region is disposed on the surface of the first drift region. The conductivity type of the first electrode region is the same as that of the first body region, and the doping concentration of the first electrode region is greater than that of the first body region. The conductivity type of the second electrode region is the same as that of the first drift region, and the doping concentration of the second electrode region is greater than that of the first drift region.

[0010] In an optional embodiment, a dummy gate is further provided at the interface between the first body region and the first drift region. The dummy gate is arranged parallel to the gate and contacts the first body region and the first drift region, and the dummy gate is configured to be grounded.

[0011] In an optional embodiment, the multi-finger gate transistor further includes a plurality of second body regions and second drift regions alternately distributed along the first direction, wherein the first drift region contacts the edge of the second body region or the second drift region, and the plurality of gates are respectively disposed on the interface between the second body region and the second drift region and contact the second body region and the second drift region, wherein the second body region and the second drift region have opposite conductivity types; A source region is disposed on the surface of the second body region. The conductivity type of the source region is opposite to that of the second body region, and the doping concentration of the source region is greater than that of the second body region. The surface of the second drift region is provided with a drain region, the conductivity type of the drain region is the same as that of the second drift region, and the doping concentration of the drain region is greater than that of the second drift region.

[0012] In an optional embodiment, the surface of the second body region is further provided with a body contact region, the source region is located on both sides of the body contact region along the first direction, the conductivity type of the body contact region is the same as that of the second body region, and the doping concentration of the body contact region is greater than that of the second body region.

[0013] In an optional embodiment, shallow trench isolation structures are further provided on both sides of the leak area along the first direction.

[0014] In an optional embodiment, the substrate includes a bottom silicon layer, a buried oxide layer, and a top silicon layer, wherein the buried oxide layer is located on the bottom silicon layer, the top silicon layer is located on the buried oxide layer, the deep trench isolation structure is located on the top silicon layer and connected to the buried oxide layer, and the device region is located on the top silicon layer.

[0015] In a second aspect, the present invention provides a method for fabricating a semiconductor device structure, used to fabricate the semiconductor device structure as described in the foregoing embodiments, the method comprising: Provide a substrate; A deep trench isolation structure is formed on the substrate so that the deep trench isolation structure encloses the device region; Multi-finger gate transistors and pseudo-transistors are formed within the device region; The multi-finger gate transistor includes a plurality of gates arranged along a first direction. The dummy transistor is disposed on opposite sides of the finger gate transistor and located at the two sides of the device region along the first direction. The dummy transistor is configured to form a reverse-biased isolated diode structure so that the electrostatic discharge current is uniformly distributed between the dummy transistor and the multi-finger gate transistor.

[0016] In an optional implementation, the step of forming a multi-finger gate transistor and a dummy transistor within the device region includes: Ion implantation is performed on both sides of the device region along the first direction to form a first body region and a first drift region, and ion implantation is performed in the middle region of the device region to form a second body region and a second drift region that are alternately distributed along the first direction. A dummy gate is formed at the interface between the first body region and the first drift region, and a gate is formed at the interface between the second body region and the second drift region; Ion implantation is performed on the surface of the first body region to form the first electrode region; Ion implantation is performed on the surfaces of the first drift region, the second drift region, and the second body region to form a second electrode region, a drain region, and a source region, wherein the second electrode region, the drain region, and the source region have the same conductivity type.

[0017] The beneficial effects of the embodiments of the present invention include: The semiconductor device structure provided in this embodiment of the invention includes a deep trench isolation structure on a substrate, which serves as a device boundary to enclose a device region. Multiple multi-finger gate transistors are disposed within the device region. Each multi-finger gate transistor includes multiple gates arranged along a first direction, and each gate extends along a second direction, with the first and second directions perpendicular to each other. Furthermore, dummy transistors are disposed along the two side edges of the device region along the first direction. These dummy transistors are located on opposite sides of the multi-finger gate transistors, and are configured as reverse-biased isolated diode structures to ensure uniform distribution of electrostatic discharge current between the dummy transistors and the multi-finger gate transistors.

[0018] Compared to existing technologies, the semiconductor device structure provided in this invention utilizes a reverse-biased isolation diode structure designed on both sides of the multi-finger gate transistor. When an ESD event occurs, the PN junctions within the pseudo-transistors at the edges will still break down and conduct first. However, since the reverse-biased diodes are non-hysteresis devices, the device terminal voltage continues to rise after the edge diodes break down due to reverse bias. This causes the internal multi-finger gate transistors to be triggered and turned on simultaneously before the device terminal voltage enters a hysteresis state. Therefore, the terminal voltage at the trigger moment characterizes the overall ESD resistance of the device. The fingers adjacent to the deep trench isolation structure no longer discharge ESD current independently, and the device's trigger voltage (Vt1) also increases accordingly, thus improving the device's ESD resistance and trigger voltage (Vt1). The uniform distribution of ESD current within the device also effectively avoids the local damage problem caused by the current accumulation at the edge fingers, thus avoiding edge damage reliability issues during local conduction and improving the overall robustness of the device. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of the structure of an existing multi-finger LDMOS device; Figure 2 A cross-sectional schematic diagram of the semiconductor device structure provided for an embodiment of the invention; Figure 3 A top view of a semiconductor device structure provided for an embodiment of the invention.

[0021] Icons: 100 - Semiconductor device structure; 110 - Substrate; 111 - Deep trench isolation structure; 112 - Bottom silicon layer; 113 - Buried oxide layer; 114 - Top silicon layer; 120 - Multi-finger gate transistor; 121 - Gate; 122 - Second body region; 123 - Second drift region; 124 - Source region; 125 - Drain region; 126 - Body contact region; 127 - Shallow trench isolation structure; 130 - Pseudo transistor; 131 - First body region; 132 - First drift region; 133 - Pseudo gate; 134 - First electrode region; 135 - Second electrode region. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0025] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0026] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0027] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0028] See Figure 2 and Figure 3 The present invention provides a semiconductor device structure 100 that can improve the device's ESD resistance and trigger voltage (Vt1), and can avoid edge damage reliability issues during local conduction, thereby improving the overall robustness of the device.

[0029] The semiconductor device structure 100 provided in this embodiment of the invention may include a substrate 110, a deep trench isolation structure 111, a multi-finger gate transistor 120, and a dummy transistor 130. The deep trench isolation structure 111 is disposed on the substrate 110 and can define the device boundary and enclose a device region. The multi-finger gate transistor 120 is disposed within the device region and includes a plurality of gates 121 arranged along a first direction, each gate 121 extending along a second direction, wherein the first direction and the second direction are perpendicular to each other. The dummy transistor 130 is disposed on opposite sides of the multi-finger gate transistor 120 and is located at the two side edges of the device region along the first direction. The dummy transistor 130 is configured to form a reverse-biased isolated diode structure so that the electrostatic discharge current is uniformly distributed between the dummy transistor 130 and the multi-finger gate transistor 120.

[0030] It should be noted that a reverse-biased isolation diode structure is designed on both sides of the multi-finger gate transistor 120. When an ESD event occurs, the PN junctions in the pseudo-transistors 130 at the two edges will still break down and conduct first. However, since the reverse-biased diodes are non-hysteresis devices, the device terminal voltage will continue to rise after the edge diodes break down due to reverse bias. This causes the internal multi-finger gate transistor 120 to be triggered and turned on simultaneously, and only then will the device terminal voltage enter a hysteresis state. Therefore, the terminal voltage at the trigger moment of this structure characterizes the overall ESD resistance of the device. The fingers adjacent to the deep trench isolation structure 111 no longer discharge ESD current separately, and the trigger voltage (Vt1) of the device will also increase accordingly, thus improving the device's ESD resistance and trigger voltage (Vt1). The uniform distribution of ESD current inside the device also effectively avoids the local damage problem caused by the current accumulation at the edge fingers, thus avoiding the edge damage reliability problem during local conduction and improving the overall robustness of the device.

[0031] It is worth noting that the multi-finger gate transistor 120 here can be an HV LDMOS device, the size of the device region has not been changed, and the fabrication process of the pseudo transistor 130 is compatible with the multi-finger gate transistor 120. That is, the pseudo transistor 130 can be fabricated at the same time as the multi-finger gate transistor 120, which simplifies the process steps. For details, please refer to the fabrication method in the following text.

[0032] In some embodiments, the dummy transistor 130 may include at least one first body region 131 and a first drift region 132, the first drift region 132 being in contact with the multi-finger gate transistor 120, the first body region 131 being in contact with the first drift region 132 and the deep trench isolation structure 111 on both sides along a first direction, and the first drift region 132 and the first body region 131 having opposite conductivity types.

[0033] Specifically, there can be two pseudo transistors 130, which are respectively disposed on both sides of the multi-finger gate transistor 120 along the first direction. Each pseudo transistor 130 may include a first body region 131 and a first drift region 132. The first body region 131 may be a P-doped well region, and the first drift region 132 may be an N-doped drift region. The first body region 131 and the first drift region 132 can form a PN structure, thereby enabling the pseudo transistor 130 to be configured as a diode structure.

[0034] Furthermore, a first electrode region 134 is disposed on the surface of the first body region 131, and a second electrode region 135 is disposed on the surface of the first drift region 132. The conductivity type of the first electrode region 134 is the same as that of the first body region 131, and the doping concentration of the first electrode region 134 is greater than that of the first body region 131. The conductivity type of the second electrode region 135 is the same as that of the first drift region 132, and the doping concentration of the second electrode region 135 is greater than that of the first drift region 132.

[0035] Specifically, the first electrode region 134 can be a P+ doped region, and the second electrode region 135 can be an N+ doped region, wherein the first electrode region 134 and the second electrode region 135 can serve as the cathode and the anode, respectively.

[0036] In some embodiments, a dummy gate 133 is further provided on the interface between the first body region 131 and the first drift region 132. The dummy gate 133 is arranged parallel to the gate 121 and contacts the first body region 131 and the first drift region 132. The dummy gate 133 is configured to be grounded.

[0037] Specifically, the dummy gate 133 and the gate 121 have the same shape and size, and the dummy gate 133 is located on both sides of the multiple gates 121. Grounding the dummy gate 133 at the edge can avoid false triggering under ESD stress.

[0038] In some embodiments, the multi-finger gate transistor 120 may further include a plurality of second body regions 122 and second drift regions 123 that are alternately distributed along a first direction.

[0039] In this embodiment, the first drift region 132 is in contact with the edge of the second body region 122 or the second drift region 123, and a plurality of gates 121 are respectively disposed on the interface of the second body region 122 and the second drift region 123 and in contact with the second body region 122 and the second drift region 123, wherein the conductivity types of the second body region 122 and the second drift region 123 are opposite.

[0040] In this embodiment, a source region 124 is disposed on the surface of the second body region 122. The conductivity type of the source region 124 is opposite to that of the second body region 122, and the doping concentration of the source region 124 is greater than that of the second body region 122. A drain region 125 is disposed on the surface of the second drift region 123. The conductivity type of the drain region 125 is the same as that of the second drift region 123, and the doping concentration of the drain region 125 is greater than that of the second drift region 123.

[0041] Specifically, the second body region 122 can be a P-doped well region, the second drift region 123 can be an N-doped drift region, and the source region 124 and the drain region 125 can both be N+ doped regions. Furthermore, a body contact region 126 is also provided on the surface of the second body region 122, and the source region 124 is located on both sides of the body contact region 126 along the first direction. The conductivity type of the body contact region 126 is the same as that of the second body region 122, and the doping concentration of the body contact region 126 is greater than that of the second body region 122.

[0042] Specifically, the body contact region 126 is a P+ doped region, and the source region 124 is located on both sides of the body contact region 126, thus making the source a P+ / N+ alternating structure, consistent with the internal structure of a conventional HV LDMOS device.

[0043] It should be noted that the device region here can be alternately provided with body regions and drift regions along the first direction. The body regions and drift regions located on both sides and adjacent to the deep trench isolation structure 111 are set as the first body region 131 and the first drift region 132. The remaining body regions and drift regions are set as the second body region 122 and the second drift region 123. The first drift region 132 can also be reused with the edge second drift region 123, so that the drain region 125 of the second drift region 123 can also serve as the second electrode region 135. Therefore, compared with the conventional structure, in this embodiment of the invention, the P+ / N+ alternating structure in the first body region 131 adjacent to the deep trench isolation structure 111 is transformed into a single P+ structure, and the edge pseudo gate 133 is grounded together with the source electrode. This design allows the edge pseudo-gate 133 to always be in the off state, while the edge pseudo-transistor 130 is transformed from the original MOS structure into a reverse-biased isolated diode structure, no longer participating in the normal conduction of the multi-finger gate transistor 120.

[0044] It should also be noted that the first drift region 132, the first body region 131, the first electrode region 134, the second electrode region 135, the second drift region 123, the second body region 122, the source region 124, the drain region 125, and the body contact region 126 in this embodiment can all be formed by ion implantation.

[0045] In some embodiments, shallow groove isolation structures 127 are further provided on both sides of the leak area 125 along the first direction. Specifically, the shallow groove isolation structures 127 are disposed within the first drift area 132 and do not penetrate the first drift area 132, thereby defining the range of the leak area 125.

[0046] In some embodiments, the substrate 110 may include a bottom silicon layer 112, a buried oxide layer 113, and a top silicon layer 114. The buried oxide layer 113 is located on the bottom silicon layer 112, the top silicon layer 114 is located on the buried oxide layer 113, a deep trench isolation structure 111 is located on the top silicon layer 114 and connected to the buried oxide layer 113, and the device region is located on the top silicon layer 114. Specifically, the substrate 110 may be an SOI substrate 110, or other types of substrate materials, which are not specifically limited here.

[0047] This invention also provides a method for fabricating a semiconductor device structure 100, used to fabricate the semiconductor device structure 100 as described in the foregoing embodiments. The method may include the following steps: S1: Provide a substrate 110.

[0048] Specifically, the substrate 110 may be an SOI substrate 110. The substrate 110 may include a bottom silicon layer 112, a buried oxide layer 113, and a top silicon layer 114, with the buried oxide layer 113 located on the bottom silicon layer 112 and the top silicon layer 114 located on the buried oxide layer 113.

[0049] S2: A deep trench isolation structure 111 is formed on the substrate 110 so that the deep trench isolation structure 111 encloses the device forming region.

[0050] Specifically, a deep trench isolation structure 111 (DTI) is formed on the top silicon layer 114 through photolithography, deep reactive ion etching (DRIE), dielectric filling and planarization processes to define the device boundary.

[0051] S3: Form a multi-finger gate transistor 120 and a pseudo transistor 130 within the device region.

[0052] The multi-finger gate transistor 120 may include a plurality of gates 121 arranged along a first direction. The dummy transistor 130 is disposed on opposite sides of the finger gate transistor and located at the two sides of the device region along the first direction. The dummy transistor 130 is configured to form a reverse-biased isolation diode structure so that the electrostatic discharge current is uniformly distributed between the dummy transistor 130 and the multi-finger gate transistor 120.

[0053] In actual fabrication, a first body region 131 and a first drift region 132 can be formed by ion implantation at both edges along the first direction within the device region, and a second body region 122 and a second drift region 123 can be alternately distributed along the first direction by ion implantation in the middle region of the device region. Specifically, there can be multiple second body regions 122 and second drift regions 123.

[0054] In this embodiment, alternating P-type well regions and N-type drift regions can be formed in the device region by ion implantation process to form a first body region 131, a first drift region 132, a second body region 122, and a second drift region 123.

[0055] In this embodiment, the first body region 131 and the second body region 122 are P-type well regions, and the first drift region 132 and the second drift region 123 are N-type drift regions. The first body region 131 and the second body region 122 can be formed by the same ion implantation process, and the first drift region 132 and the second drift region 123 can be formed by the same ion implantation process.

[0056] Then, a dummy gate 133 is formed at the interface between the first body region 131 and the first drift region 132, and a gate 121 is formed at the interface between the second body region 122 and the second drift region 123.

[0057] Specifically, the gate structure can be formed simultaneously, the gate dielectric and electrode material can be deposited, and the gate 121 and the pseudo gate 133 can be formed through photolithography and etching processes.

[0058] Finally, ion implantation is performed on the first body region 131, the first drift region 132, the second body region 122, and the second drift region 123 to form a first electrode region 134 located in the first body region 131, a second electrode region 135 located in the first drift region 132, a source region 124 and a body contact region 126 located in the second body region 122, and a drain region 125 located in the second drift region 123, respectively.

[0059] Specifically, P-type ion implantation can be performed on the surfaces of the first body region 131 and the second body region 122 to form a first electrode region 134 located in the first body region 131 and a body contact region 126 located in the second body region 122. Then, N-type ion implantation is performed on the surfaces of the first drift region 132, the second drift region 123, and the second body region 122 to form a second electrode region 135 located in the first drift region 132, a drain region 125 located in the second drift region 123, and a source region 124 located in the second body region 122. The source region 124 is located on both sides of the body contact region 126.

[0060] In one embodiment, before forming alternating P-type well regions and N-type drift regions within the device region, a shallow trench isolation (STI) process can be used to partition the device region enclosed by the DTI, forming a shallow trench isolation structure. The shallow trench isolation structure is used to define the source region 124 to be formed subsequently.

[0061] In summary, the semiconductor device structure 100 and its fabrication method provided in this embodiment of the invention have a deep trench isolation structure 111 on a substrate 110. This deep trench isolation structure 111 can serve as a device boundary to enclose a device region. A plurality of multi-finger gate transistors 120 are disposed within the device region. Each multi-finger gate transistor 120 includes a plurality of gates 121 arranged along a first direction, and each gate 121 extends along a second direction, with the first and second directions perpendicular to each other. Furthermore, dummy transistors 130 are disposed on both sides of the device region along the first direction. The dummy transistors 130 are disposed on opposite sides of the multi-finger gate transistors 120, and are configured as reverse-biased isolated diode structures to ensure uniform distribution of electrostatic discharge current between the dummy transistors 130 and the multi-finger gate transistors 120. Compared to the prior art, the semiconductor device structure 100 provided in this embodiment of the invention achieves this by designing reverse-biased isolated diode structures on both sides of the multi-finger gate transistors 120. When an ESD event occurs, the PN junctions within the pseudo-transistors 130 at both edges will still break down and conduct first. However, since the reverse-biased diodes are non-hysteresis devices, the device terminal voltage will continue to rise after the edge diodes break down due to reverse bias. This causes the internal multi-finger gate transistors 120 to be triggered and turned on simultaneously, and only then will the device terminal voltage enter a hysteresis state. Therefore, the terminal voltage at the trigger moment characterizes the overall ESD resistance of the device. The fingers adjacent to the deep trench isolation structure 111 no longer discharge ESD current independently, and the device's trigger voltage (Vt1) will also increase accordingly, thus improving the device's ESD resistance and trigger voltage (Vt1). The uniform distribution of ESD current inside the device also effectively avoids the local damage problem caused by the current accumulation at the edge fingers, thus avoiding the edge damage reliability problem during local conduction and improving the overall robustness of the device.

[0062] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device structure, characterized in that, include: Substrate; A deep trench isolation structure is disposed on the substrate, the deep trench isolation structure enclosing a device region; A multi-finger gate transistor disposed within the device region, the multi-finger gate transistor comprising a plurality of gates arranged along a first direction, each gate extending along a second direction, wherein the first direction and the second direction are perpendicular to each other; The dummy transistors are disposed on opposite sides of the multi-finger gate transistor, and the dummy transistors are located at the two sides of the device region along the first direction. The dummy transistor is configured as a reverse-biased isolated diode structure to ensure that the electrostatic discharge current is evenly distributed between the dummy transistor and the multi-finger gate transistor.

2. The semiconductor device structure according to claim 1, characterized in that, The pseudo transistor includes at least one first body region and a first drift region, the first drift region being in contact with the multi-finger gate transistor, and the first body region being in contact with the first drift region and the deep trench isolation structure on both sides along the first direction, respectively, the first drift region and the first body region having opposite conductivity types.

3. The semiconductor device structure according to claim 2, characterized in that, A first electrode region is disposed on the surface of the first body region, and a second electrode region is disposed on the surface of the first drift region. The conductivity type of the first electrode region is the same as that of the first body region, and the doping concentration of the first electrode region is greater than that of the first body region. The conductivity type of the second electrode region is the same as that of the first drift region, and the doping concentration of the second electrode region is greater than that of the first drift region.

4. The semiconductor device structure according to claim 2, characterized in that, A dummy gate is also provided at the interface between the first body region and the first drift region. The dummy gate is arranged parallel to the gate and is in contact with the first body region and the first drift region. The dummy gate is configured to be grounded.

5. The semiconductor device structure according to claim 2, characterized in that, The multi-finger gate transistor further includes a plurality of second body regions and second drift regions alternately distributed along the first direction. The first drift region is in contact with the edge of the second body region or the second drift region. The plurality of gates are respectively disposed on the interface between the second body region and the second drift region and in contact with the second body region and the second drift region. The second body region and the second drift region have opposite conductivity types. A source region is disposed on the surface of the second body region. The conductivity type of the source region is opposite to that of the second body region, and the doping concentration of the source region is greater than that of the second body region. The surface of the second drift region is provided with a drain region, the conductivity type of the drain region is the same as that of the second drift region, and the doping concentration of the drain region is greater than that of the second drift region.

6. The semiconductor device structure according to claim 5, characterized in that, The surface of the second body region is further provided with a body contact region, and the source region is located on both sides of the body contact region along the first direction. The conductivity type of the body contact region is the same as that of the second body region, and the doping concentration of the body contact region is greater than that of the second body region.

7. The semiconductor device structure according to claim 5, characterized in that, Shallow trench isolation structures are also provided on both sides of the leak area along the first direction.

8. The semiconductor device structure according to claim 1, characterized in that, The substrate includes a bottom silicon layer, a buried oxide layer, and a top silicon layer. The buried oxide layer is located on the bottom silicon layer, the top silicon layer is located on the buried oxide layer, the deep trench isolation structure is located on the top silicon layer and connected to the buried oxide layer, and the device region is located on the top silicon layer.

9. A method for fabricating a semiconductor device structure, used to fabricate the semiconductor device structure as described in claim 1, characterized in that, The method includes: Provide a substrate; A deep trench isolation structure is formed on the substrate so that the deep trench isolation structure encloses the device region; Multi-finger gate transistors and pseudo-transistors are formed within the device region; The multi-finger gate transistor includes a plurality of gates arranged along a first direction. The dummy transistor is disposed on opposite sides of the finger gate transistor and located at the two sides of the device region along the first direction. The dummy transistor is configured to form a reverse-biased isolated diode structure so that the electrostatic discharge current is uniformly distributed between the dummy transistor and the multi-finger gate transistor.

10. The method for fabricating a semiconductor device structure according to claim 9, characterized in that, The steps of forming multi-finger gate transistors and dummy transistors within the device region include: Ion implantation is performed on both sides of the device region along the first direction to form a first body region and a first drift region, and ion implantation is performed in the middle region of the device region to form a second body region and a second drift region that are alternately distributed along the first direction. A dummy gate is formed at the interface between the first body region and the first drift region, and a gate is formed at the interface between the second body region and the second drift region; Ion implantation is performed on the surface of the first body region to form the first electrode region; Ion implantation is performed on the surfaces of the first drift region, the second drift region, and the second body region to form a second electrode region, a drain region, and a source region, wherein the second electrode region, the drain region, and the source region have the same conductivity type.

Images