Low-voltage unidirectional silicon controlled rectifier electrostatic discharge (SCR) device and its fabrication method

Abstract

This invention provides a low-voltage unidirectional thyristor electrostatic discharge (ESD) device and its fabrication method, aiming to solve the problems of high trigger voltage and low sustaining voltage, which easily leads to latch-up, in existing thyristor designs under the 5V ESD window. This invention involves forming a localized P-type epitaxial layer and an underlying N-type buried layer on a P-type substrate, creating multiple well regions. A first gate is located above the second N-type well, forming a GDPMOS structure, reducing the trigger voltage to 9V-10V. A floating fourth P+ injection region is located within the first P-type well, which reduces the parasitic transistor amplification factor, increases the sustaining voltage, and significantly reduces the risk of latch-up. The fourth N+ injection region, the first N-type shallow well, the P-type epitaxial layer, the first P-type well, and the fifth P+ injection region constitute a reverse diode, enhancing the negative ESD discharge capability. This invention balances low trigger voltage and high sustaining voltage, making it suitable for 5V ESD design windows.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection, and in particular to a low-voltage unidirectional thyristor ESD protection device and its preparation method. Background Technology

[0002] With the advancement of semiconductor manufacturing processes, electrostatic discharge (ESD) has become increasingly serious, causing integrated circuit chips and electronic products to fail. Therefore, ESD protection for integrated circuit chips and electronic products has become one of the main challenges faced by product engineers.

[0003] like Figure 1 and Figure 2 As shown, traditional silicon controlled rectifiers (SCRs) have advantages over other ESD devices, such as high discharge efficiency per unit area, small parasitic capacitance per unit area, and good robustness. However, in low-voltage applications, traditional SCRs suffer from drawbacks such as excessively high trigger voltage and excessively low sustaining voltage. Excessively high trigger voltage can lead to the device failing to protect the core circuit in time and poses a risk of damaging the gate oxide layer of the 5V device in the core circuit. Insufficient sustaining voltage can cause latch-up, compromising the integrity of I / O port signal transmission. Therefore, in low-voltage 5V applications, MOS-type devices with suitable trigger voltages, such as GGNMOS (gate-grounded N-channel MOSFET) or GDPMOS (drain-grounded P-channel MOSFET), are primarily used as the main ESD discharge devices.

[0004] Therefore, how to provide a unidirectional thyristor electrostatic discharge protection device and its fabrication method to solve the problem that existing thyristor devices applied to the 5V ESD design window have high trigger voltage and low sustaining voltage has become one of the problems that urgently need to be solved by those skilled in the art.

[0005] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a low-voltage unidirectional thyristor electrostatic discharge (ESD) device and its preparation method, which solves the problem that existing thyristor devices applied to the 5V ESD design window have high trigger voltage and low sustaining voltage.

[0007] To achieve the above and other related objectives, the present invention provides a low-voltage unidirectional thyristor electrostatic discharge (ESD) protection device, wherein the low-voltage unidirectional thyristor ESD protection device comprises at least:

[0008] A low-voltage unidirectional thyristor electrostatic discharge (ESD) protection device, characterized in that the low-voltage unidirectional thyristor ESD protection device comprises at least:

[0009] P-type substrate;

[0010] An N-type buried layer is disposed in the P-type substrate and located in the upper region of the P-type substrate;

[0011] A P-type epitaxial layer is disposed on the P-type substrate and located in a region perpendicular to the N-type buried layer; wherein the upper surface of the P-type epitaxial layer is flush with the upper surface of the P-type substrate, and the sides of both the P-type epitaxial layer and the N-type buried layer are the P-type substrate.

[0012] The P-type epitaxial layer is provided with a first high-pressure N-well and a second high-pressure N-well, and the first high-pressure N-well and the second high-pressure N-well are respectively located on both sides of the transverse direction of the N-type buried layer.

[0013] The upper region of the first high-voltage N-well is provided with a first N-type well; the upper region of the second high-voltage N-well is provided with a third N-type well.

[0014] The P-type epitaxial layer is provided with a first P-type shallow well, a second N-type well, a first P-type well, and a first N-type shallow well from left to right; wherein the first P-type shallow well, the second N-type well, and the first P-type well are adjacent to each other, and there is a gap between the first P-type well and the first N-type shallow well.

[0015] The first N-type well is provided with a first N+ injection region;

[0016] The first P-type shallow well is provided with a first P+ injection region;

[0017] The second N-type well is provided with a second N+ injection region, a second P+ injection region and a third P+ injection region from left to right; a first gate is provided above the second N-type well, and the first gate covers the surface of the second N-type well between the second P+ injection region and the third P+ injection region;

[0018] The first P-type well is provided with a fourth P+ injection region, a third N+ injection region and a fifth P+ injection region from left to right;

[0019] The first N-type shallow well is provided with a fourth N+ injection region;

[0020] The third N-type well is provided with a fifth N+ injection region;

[0021] The first P+ injection region, the second N+ injection region, the second P+ injection region, the first gate, and the fourth N+ injection region are connected together and serve as the anode of the device; the third P+ injection region, the third N+ injection region, the fifth P+ injection region, the first N+ injection region, and the fifth N+ injection region are connected together and serve as the cathode of the device; the fourth P+ injection region is not connected to any potential.

[0022] The second P+ injection region, the second N-type well, and the third P+ injection region constitute a first PNP transistor PNP1; the second P+ injection region, the second N-type well, and the first P-type well constitute a second PNP transistor PNP2; the first P+ injection region, the first P-type shallow well, the second N-type well, and the first P-type well constitute a third PNP transistor PNP3; the second N-type well, the first P-type well, and the third N+ injection region constitute a first NPN transistor NPN1; in the reverse path, the fourth N+ injection region, the first N-type shallow well, the P-type epitaxial layer, the first P-type well, and the fifth P+ injection region constitute a reverse diode Diode1.

[0023] Optionally, the low-voltage unidirectional thyristor electrostatic discharge (ESD) device further includes: a first field oxygen isolation region disposed outside the first N+ injection region in the first N-type well; a second field oxygen isolation region disposed between the first N+ injection region and the first P+ injection region; a third field oxygen isolation region disposed between the first P+ injection region and the second N+ injection region; a fourth field oxygen isolation region disposed between the second N+ injection region and the second P+ injection region; a fifth field oxygen isolation region between the third P+ injection region and the fourth P+ injection region; a sixth field oxygen isolation region between the fourth P+ injection region and the third N+ injection region; a seventh field oxygen isolation region between the third N+ injection region and the fifth P+ injection region; an eighth field oxygen isolation region between the fifth P+ injection region and the fourth N+ injection region; a ninth field oxygen isolation region between the fourth N+ injection region and the fifth N+ injection region; and a tenth field oxygen isolation region disposed outside the fifth N+ injection region in the third N-type well.

[0024] Optionally, the first field oxygen isolation region extends downward from the surface of the P-type substrate and the surface of the first N-type well; the second field oxygen isolation region extends downward from left to right sequentially from the surface of the first N-type well, the surface of the P-type epitaxial layer, and the surface of the first P-type shallow well; the third field oxygen isolation region extends downward from the surface of the first P-type shallow well and the surface of the second N-type well; the fourth field oxygen isolation region extends downward from the surface of the second N-type well; the fifth field oxygen isolation region extends downward from the surface of the second N-type well and the surface of the first P-type well; the sixth field oxygen isolation region extends downward from the surface of the first P-type well; the seventh field oxygen isolation region extends downward from the surface of the first P-type well; the eighth field oxygen isolation region extends downward from left to right sequentially from the surface of the first P-type well, the surface of the P-type epitaxial layer, and the surface of the first N-type shallow well; the ninth field oxygen isolation region extends downward from left to right sequentially from the surface of the first N-type shallow well, the surface of the P-type epitaxial layer, and the surface of the third N-type well; and the tenth field oxygen isolation region extends downward from the surface of the third N-type well and the surface of the P-type substrate.

[0025] Optionally, the first N+ injection region, the first N-type well, the first high-pressure N-well, the N-type buried layer, the fifth N+ injection region, the third N-type well, and the second high-pressure N-well constitute an ISO isolation ring.

[0026] Optionally, the width of the first gate is configured to be adjustable to change the effective size of the avalanche breakdown surface formed between the second N-type well and the third P+ injection region, thereby adjusting the avalanche breakdown voltage and trigger voltage of the device.

[0027] This invention also provides a method for fabricating a low-voltage unidirectional silicon-controlled rectifier (SCR) electrostatic discharge (ESD) device, the method comprising:

[0028] Step 1) Provide a P-type substrate;

[0029] Step 2) An N-type buried layer is formed in the P-type substrate, wherein the N-type buried layer is located on the upper surface of the P-type substrate;

[0030] Step 3) A groove is etched on the upper surface of the P-type substrate, the groove is located in the vertical projection area of ​​the N-type buried layer, and the bottom of the groove exposes the N-type buried layer; a P-type epitaxial layer is formed in the groove, such that the upper surface of the P-type epitaxial layer is flush with the upper surface of the P-type substrate.

[0031] Step 4) Form a first high-voltage N-well and a second high-voltage N-well in the P-type epitaxial layer, and position the first high-voltage N-well and the second high-voltage N-well on opposite sides of the N-type buried layer in the transverse direction;

[0032] Step 5) A first N-type well is formed in the upper region of the first high-pressure N-well, and a third N-type well is formed in the upper region of the second high-pressure N-well; in the P-type epitaxial layer, a well region is formed from left to right, including a first P-type shallow well, a second N-type well, a first P-type well, and a first N-type shallow well; wherein, the first P-type shallow well, the second N-type well, and the first P-type well are adjacent, and there is a gap between the first P-type well and the first N-type shallow well;

[0033] Step 6) A first gate is formed above the second N-type well, the first gate covers the surface of the second N-type well, and reserves the area for the subsequent formation of the second P+ injection region and the third P+ injection region;

[0034] Step 7) Using the first gate as a mask, a second P+ injection region and a third P+ injection region are self-aligned and formed in the second N-type well, such that the first gate is located between the second P+ injection region and the third P+ injection region; then, a first N+ injection region is formed on the first N-type well, a first P+ injection region is formed on the first P-type shallow well, a second N+ injection region is formed on the second N-type well (to the left of the second P+ injection region), a fourth P+ injection region, a third N+ injection region and a fifth P+ injection region are formed on the first P-type well, a fourth N+ injection region is formed on the first N-type shallow well, and a fifth N+ injection region is formed on the third N-type well.

[0035] Step 8) Anneal each implanted region to activate the implanted impurities and repair lattice damage;

[0036] Step 9) Connect the first P+ injection region, the second N+ injection region, the second P+ injection region, the first gate, and the fourth N+ injection region together as the anode, and connect the third P+ injection region, the third N+ injection region, the fifth P+ injection region, the first N+ injection region, and the fifth N+ injection region together as the cathode.

[0037] Optionally, after step 5) and before step 6), the method further includes the steps of forming a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region, a fifth field oxygen isolation region, a sixth field oxygen isolation region, a seventh field oxygen isolation region, an eighth field oxygen isolation region, a ninth field oxygen isolation region, and a tenth field oxygen isolation region; the first field oxygen isolation region extends downward from the surface of the P-type substrate and the surface of the first N-type well; the second field oxygen isolation region extends downward from left to right sequentially from the surface of the first N-type well, the surface of the P-type epitaxial layer, and the surface of the first P-type shallow well; the third field oxygen isolation region extends downward from the surface of the first P-type shallow well and the surface of the second N-type well; the fourth field oxygen isolation region extends downward from the surface of the first P-type shallow well and the surface of the second N-type well; the fourth field oxygen isolation region extends downward from the surface of the first P-type shallow well and the surface of the second N-type well; the fifth field oxygen isolation region extends downward from the surface of the first N-type well and the surface of the second N-type well; the sixth field oxygen isolation region extends downward from the surface of the first N-type well and the surface of the second N-type well; the seventh field oxygen isolation region extends downward from the surface of the first N-type shallow well and the surface of the second N-type well; the eighth field oxygen isolation region extends downward from the surface of the first N-type shallow well and the surface of the second N-type well; the ninth field oxygen isolation region extends downward from the surface of the first N-type shallow well and the surface of the second N-type well; the tenth ... shallow well; the tenth field oxygen isolation region extends The surface of the second N-type well extends downward; the fifth field oxygen isolation region extends downward from the surface of the second N-type well and the surface of the first P-type well; the sixth field oxygen isolation region extends downward from the surface of the first P-type well; the seventh field oxygen isolation region extends downward from the surface of the first P-type well; the eighth field oxygen isolation region extends downward from left to right from the surface of the first P-type well, the surface of the P-type epitaxial layer, and the surface of the first N-type shallow well; the ninth field oxygen isolation region extends downward from left to right from the surface of the first N-type shallow well, the surface of the P-type epitaxial layer, and the surface of the third N-type well; the tenth field oxygen isolation region extends downward from the surface of the third N-type well and the surface of the P-type substrate.

[0038] Optionally, the first oxygen isolation region is located outside the first N+ injection region in the first N-type well; the second oxygen isolation region is between the first N+ injection region and the first P+ injection region; the third oxygen isolation region is between the first P+ injection region and the second N+ injection region; the fourth oxygen isolation region is between the second N+ injection region and the second P+ injection region; the fifth oxygen isolation region is between the third P+ injection region and the fourth P+ injection region; the sixth oxygen isolation region is between the fourth P+ injection region and the third N+ injection region; the seventh oxygen isolation region is between the third N+ injection region and the fifth P+ injection region; the eighth oxygen isolation region is between the fifth P+ injection region and the fourth N+ injection region; the ninth oxygen isolation region is between the fourth N+ injection region and the fifth N+ injection region; and the tenth oxygen isolation region is outside the fifth N+ injection region in the third N-type well.

[0039] Optionally, the first to the tenth oxygen isolation zones are all formed using the shallow trench isolation (STI) process.

[0040] Optionally, the step of forming the first gate includes: growing a gate oxide layer on the surface of the second N-type well, depositing a polysilicon layer on the gate oxide layer, doping the polysilicon layer, and then photolithography and etching to form the first gate.

[0041] As described above, this invention provides a low-voltage unidirectional thyristor electrostatic discharge (ESD) device and its fabrication method, aiming to solve the technical problems of high trigger voltage and low sustaining voltage, and easy latch-up, of existing thyristor devices under the 5V ESD design window. The device of this invention includes a P-type substrate, an N-type buried layer disposed in the P-type substrate, a P-type epitaxial layer selectively disposed on the P-type substrate and located in a region perpendicular to the N-type buried layer, a first high-voltage N-well and a second high-voltage N-well respectively located on both sides of the N-type buried layer, a first N-type well and a third N-type well respectively disposed in the upper regions of the first high-voltage N-well and the second high-voltage N-well, and a first P-type shallow well, a second N-type well, a first P-type well, and a first N-type shallow well sequentially disposed from left to right in the P-type epitaxial layer. The second N-type well contains a second N+ injection region, a second P+ injection region, and a third P+ injection region. A first gate is disposed above the second N-type well, and the first gate covers the surface of the second N-type well between the second P+ injection region and the third P+ injection region, forming a GDPMOS structure. This structure reduces the avalanche breakdown voltage of the device to 9V~10V, the same as GDPMOS or GGNMOS, effectively lowering the trigger voltage of the SCR device. A floating fourth P+ injection region is located within the first P-type well, reducing the amplification factor of the parasitic transistor, allowing for a deeper and longer ESD current discharge path, significantly improving the holding voltage, and greatly reducing the risk of latch-up in the SCR device. Furthermore, the fourth N+ injection region, the first N-type shallow well, the P-type epitaxial layer, the first P-type well, and the fifth P+ injection region constitute a reverse diode, providing a shorter and more robust reverse discharge path, greatly reducing the negative on-resistance and enhancing the negative ESD discharge capability. This invention significantly improves the holding voltage while reducing the trigger voltage, making it particularly suitable for 5V ESD design windows. Attached Figure Description

[0042] Figure 1 This is a cross-sectional view of a currently known unidirectional silicon controlled rectifier (SCR) electrostatic discharge (ESD) device.

[0043] Figure 2 This is the equivalent circuit diagram of the currently known unidirectional silicon controlled rectifier (SCR) electrostatic discharge (ESD) device.

[0044] Figure 3 This is a cross-sectional view of a low-voltage unidirectional thyristor electrostatic discharge (ESD) protection device provided in an embodiment of the present invention.

[0045] Figure 4 The equivalent circuit diagram of the low-voltage unidirectional thyristor electrostatic discharge protection device provided in the embodiments of the present invention.

[0046] Figure 5 This is a schematic diagram of the structure after an N-type buried layer is formed in a P-type substrate according to an embodiment of the present invention.

[0047] Figure 6This is a schematic diagram of the structure after a P-type epitaxial layer is formed above an N-type buried layer according to an embodiment of the present invention.

[0048] Figure 7 This is a schematic diagram of the structure after forming the first high-voltage N-well and the second high-voltage N-well according to an embodiment of the present invention.

[0049] Figure 8 This is a schematic diagram of the structure after forming the first N-type well, the second N-type well, the third N-type well, the first P-type well, the first P-type shallow well, and the first N-type shallow well according to an embodiment of the present invention.

[0050] Figure 9 This is a schematic diagram of the structure after forming the oxygen isolation zones in each field according to an embodiment of the present invention.

[0051] Figure 10 This is a schematic diagram of the structure after the first gate is formed according to an embodiment of the present invention.

[0052] Figure 11 This is a schematic diagram of the structure after each injection region is formed according to an embodiment of the present invention.

[0053] Figure 12 This is a schematic diagram of the structure after the anode and cathode are formed according to an embodiment of the present invention.

[0054] Component designation explanation

[0055] 100 P-type substrate 200 N-type buried layer 300 P-type epitaxial layer 401~402 First and second high-pressure N-wells 501~502 First and second N-type traps 503 First P-type well 504 Third N-type well 601 First type P shallow well 602 Type N shallow well 701~710 Oxygen isolation zones 1-10 801~805 First, second, third, fourth, fifth, and N+ injection zones 901~905 First, second, third, fourth, and fifth P+ injection zones 900 First gate Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Please see Figures 3-12 As shown. It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0058] Example 1

[0059] like Figures 3-4 As shown, this invention provides a low-voltage unidirectional thyristor electrostatic discharge (ESD) protection device to address the problem of high trigger voltage and low sustaining voltage in existing thyristor devices used in 5V ESD design windows. The low-voltage unidirectional thyristor ESD protection device includes:

[0060] P-type substrate 100;

[0061] An N-type buried layer 200 is disposed in a P-type substrate 100 and is located in the upper region of the P-type substrate 100;

[0062] Specifically, the upper surface of the N-type buried layer 200 is flush with the upper surface of the P-type substrate 100, serving as the bottom boundary of the subsequently formed P-type epitaxial layer 300.

[0063] A P-type epitaxial layer 300 is disposed on a P-type substrate 100 and located in a region perpendicular to the N-type buried layer 200; wherein, the upper surface of the P-type epitaxial layer 300 is flush with the upper surface of the P-type substrate 100, and the sides of both the P-type epitaxial layer 300 and the N-type buried layer 200 are the P-type substrate 100.

[0064] The P-type epitaxial layer 300 is provided with a first high-voltage N-well 401 and a second high-voltage N-well 402, and the first high-voltage N-well 401 and the second high-voltage N-well 402 are respectively located on both sides of the N-type buried layer 200 in the lateral direction and are in contact with the N-type buried layer 200.

[0065] The upper region of the first high-pressure N-well 401 is provided with a first N-type well 501; the upper region of the second high-pressure N-well 402 is provided with a third N-type well 504.

[0066] From left to right, the P-type epitaxial layer 300 is provided with a first P-type shallow well 601, a second N-type well 502, a first P-type well 503, and a first N-type shallow well 602; wherein, the first P-type shallow well 601, the second N-type well 502, and the first P-type well 503 are adjacent to each other, and there is a gap between the first P-type well 503 and the first N-type shallow well 602.

[0067] The first N-type well 501 is provided with a first N+ injection region 801;

[0068] The first P-type shallow well 601 is provided with a first P+ injection region 901;

[0069] The second N-type well 502 is provided with a second N+ injection region 802, a second P+ injection region 902 and a third P+ injection region 903 from left to right; a first gate 900 is provided above the second N-type well 502, and the first gate 900 covers the surface of the second N-type well 502 between the second P+ injection region 902 and the third P+ injection region 903.

[0070] The first P-type well 503 is provided with a fourth P+ injection region 904, a third N+ injection region 803 and a fifth P+ injection region 905 from left to right;

[0071] The first N-type shallow well 602 is provided with a fourth N+ injection region 804;

[0072] The third N-type well 504 is provided with a fifth N+ injection region 805;

[0073] The first P+ injection region 901, the second N+ injection region 802, the second P+ injection region 902, the first gate 900, and the fourth N+ injection region 804 are connected together and serve as the anode of the device; the third P+ injection region 903, the third N+ injection region 803, the fifth P+ injection region 905, the first N+ injection region 801, and the fifth N+ injection region 805 are connected together and serve as the cathode of the device; the fourth P+ injection region 904 is not connected to any potential.

[0074] Specifically, in this embodiment, an embedded GDPMOS structure is provided within the second N-type well 502. The GDPMOS structure is jointly formed by the first gate 900 and the second P+ injection regions 902 and 903 on both sides, and both the first gate 900 and the second P+ injection regions 902 are connected to the anode. Taking a forward ESD pulse as an example, the PN junction between the second N-type well 502 and the third P+ injection region 903 directly below the first gate 900 is the avalanche breakdown surface of the device. Compared with the avalanche junction directly formed by deep wells in traditional thyristor devices, this embodiment utilizes the inherent shallow junction breakdown characteristics of the GDPMOS structure to reduce the avalanche breakdown voltage of the device to the same 9V~10V as conventional GDPMOS or GGNMOS.

[0075] See Figure 3 and Figure 4 The low-voltage unidirectional thyristor electrostatic discharge (ESD) device also includes multiple field oxygen isolation regions: a first field oxygen isolation region 701 disposed outside the first N+ injection region 801 in the first N-type well 501; a second field oxygen isolation region 702 disposed between the first N+ injection region 801 and the first P+ injection region 901; a third field oxygen isolation region 703 disposed between the first P+ injection region 901 and the second N+ injection region 802; a fourth field oxygen isolation region 704 disposed between the second N+ injection region 802 and the second P+ injection region 902; and the third P+ injection region 903 and the fourth P+ injection region 704. The fifth oxygen isolation region 705 between the fourth P+ injection region 904 and the third N+ injection region 803, the sixth oxygen isolation region 706 between the fourth P+ injection region 904 and the third N+ injection region 803, the seventh oxygen isolation region 707 between the third N+ injection region 803 and the fifth P+ injection region 905, the eighth oxygen isolation region 708 between the fifth P+ injection region 905 and the fourth N+ injection region 804, the ninth oxygen isolation region 709 between the fourth N+ injection region 804 and the fifth N+ injection region 805, and the tenth oxygen isolation region 710 disposed outside the fifth N+ injection region 805 in the third N-type trap 504. As an example, the first oxygen isolation region 701 to the tenth oxygen isolation region 710 are all shallow trench isolation (STI) structures.

[0076] Furthermore, the first field oxygen isolation region 701 extends downward from the surface of the P-type substrate 100 and the surface of the first N-type well 501; the second field oxygen isolation region 702 extends downward from left to right from the surface of the first N-type well 501, the surface of the P-type epitaxial layer 300, and the surface of the first P-type shallow well 601; the third field oxygen isolation region 703 extends downward from the surface of the first P-type shallow well 601 and the surface of the second N-type well 502; the fourth field oxygen isolation region 704 extends downward from the surface of the second N-type well 502 and is located between the second N+ implantation region 802 and the second P+ implantation region 902; the fifth field oxygen isolation region 705 extends downward from the surface of the second N-type well 502 and the surface of the first P-type well 503; the sixth field oxygen isolation region 706 extends downward from the surface of the first P-type substrate 100 and the surface of the first P-type well 503; The surface of the first P-type well 503 extends downward and is located between the fourth P+ implantation region 904 and the third N+ implantation region 803; the seventh field oxygen isolation region 707 extends downward from the surface of the first P-type well 503 and is located between the third N+ implantation region 803 and the fifth P+ implantation region 905; the eighth field oxygen isolation region 708 extends downward from left to right from the surface of the first P-type well 503, the surface of the P-type epitaxial layer 300 and the surface of the first N-type shallow well 602; the ninth field oxygen isolation region 709 extends downward from left to right from the surface of the first N-type shallow well 602, the surface of the P-type epitaxial layer 300 and the surface of the third N-type well 504; the tenth field oxygen isolation region 710 extends downward from the surface of the third N-type well 504 and the surface of the P-type substrate 100.

[0077] In another embodiment, the width S1 of the first gate 900 is configured to be adjustable to change the effective size of the avalanche breakdown surface formed between the second N-type well 502 and the third P+ injection region 903, thereby adjusting the avalanche breakdown voltage and trigger voltage of the device. Specifically, since the third P+ injection region 903 is affected by the lateral diffusion of impurities from the adjacent second P+ injection region 902 during fabrication, its actual junction depth and lateral boundary are closely related to the opening width S1 of the first gate 900. When S1 increases, the avalanche breakdown surface is wider, and the total charge required to reach the critical electric field strength increases, resulting in a higher avalanche breakdown voltage; conversely, when S1 decreases, the avalanche breakdown voltage decreases. By reasonably adjusting S1, the trigger voltage of the device can be precisely matched to the requirements of a low-voltage ESD design window of 5V and below.

[0078] In addition, the first N+ injection region 801, the first N-type well 501, the first high-voltage N-well 401, the N-type buried layer 200, the fifth N+ injection region 805, the third N-type well 504, and the second high-voltage N-well 402 constitute an ISO isolation ring, which is used to isolate the low-voltage unidirectional thyristor structure from the outside world.

[0079] Figure 4 for Figure 3The equivalent circuit diagram of the device shown illustrates the interconnection relationship between the parasitic PNP transistor, the parasitic NPN transistor, and the reverse diode Diode1. The working principle of the low-voltage unidirectional thyristor electrostatic discharge (ESD) device in this embodiment is as follows:

[0080] In the forward path, the second P+ injection region 902, the second N-type well 502, and the third P+ injection region 903 constitute the first PNP transistor PNP1; the second P+ injection region 902, the second N-type well 502, and the first P-type well 503 constitute the second PNP transistor PNP2; the first P+ injection region 901, the first P-type shallow well 601, the second N-type well 502, and the first P-type well 503 constitute the third PNP transistor PNP3; and the second N-type well 502, the first P-type well 503, and the third N+ injection region 803 constitute the first NPN transistor NPN1. In the reverse path, the fourth N+ injection region 804, the first N-type shallow well 602, the P-type epitaxial layer 300, the first P-type well 503, and the fifth P+ injection region 905 constitute the reverse diode Diode1.

[0081] When an ESD pulse is applied to the anode and the cathode is connected to a low potential, the first P+ injection region 901, the second N+ injection region 802, the first gate 900, and the fourth N+ injection region 804 are at high potentials, while the third P+ injection region 903, the third N+ injection region 803, and the fifth P+ injection region 905 are at low potentials. The second N-type well 502 and the third P+ injection region 903 are reverse biased. When the voltage of the forward ESD pulse is higher than the avalanche breakdown voltage of the reverse-biased PN junction formed by the second N-type well 502 and the third P+ injection region 903, the reverse-biased PN junction undergoes avalanche breakdown, generating a large avalanche current. The avalanche current flows through the third P+ injection region 903, the first P-type well 503, the third N+ injection region 803, and the fifth P+ injection region 905, and finally flows into the cathode. As can be seen from the structural cross-sectional diagram, when the avalanche current is generated, the parasitic resistance R of the second N-type well 502... NW When the voltage drop generated is large enough, the parasitic PNP transistor PNP1 of the GDPMOS in the low-voltage unidirectional thyristor structure is triggered to turn on, discharging the initial ESD pulse current. Simultaneously, the conduction of the first PNP transistor PNP1 provides current to the base of the second PNP transistor PNP2, triggering PNP2 to turn on; the turning on of the second PNP transistor PNP2 is achieved through the parasitic resistance R of the first P-type well 503. PW A sufficiently large voltage drop is generated, which triggers the first NPN transistor NPN1 to turn on, forming a positive feedback loop. The forward SCR path is successfully turned on to discharge the ESD current. When the ESD pulse voltage reaches a certain value, the third PNP transistor PNP3 is also triggered to turn on, participating in the discharge of ESD current.

[0082] When there is an ESD pulse at the cathode and the anode is connected to a low potential, the third P+ injection region 903, the third N+ injection region 803, and the fifth P+ injection region 905 are at a high potential, while the first P+ injection region 901, the second N+ injection region 802, the second P+ injection region 902, the first gate 900, and the fourth N+ injection region 804 are at a low potential. The diode Diode1, which is composed of the fourth N+ injection region 804, the first N-type shallow well 602, the P-type epitaxial layer 300, the first P-type well 503, and the fifth P+ injection region 905, is forward biased and begins to discharge reverse ESD current when the voltage drop reaches 0.6V~0.7V.

[0083] This embodiment optimizes the traditional unidirectional silicon controlled rectifier structure as follows:

[0084] First, a GDPMOS structure with its gate connected to the anode is embedded within the second N-type well 502. Taking a forward ESD pulse as an example, the avalanche breakdown surface of the device (composed of the second N-type well 502 and the third P+ injection region 903) is located below the first gate 900. Therefore, this embodiment reduces the avalanche breakdown voltage of conventional silicon controlled rectifier devices to the same 9V~10V as GDPMOS or GGNMOS. Furthermore, the size of the avalanche breakdown surface (i.e., the width S1 of the first gate 900) is adjustable due to the diffusion effect of the concentration of the second P+ injection region 902 on the third P+ injection region 903. By adjusting the size of S1, the avalanche breakdown voltage and trigger voltage of the device can be directly adjusted, thereby adapting to a lower ESD window.

[0085] Second, the reverse discharge path has been optimized by adding a shorter and more robust reverse diode discharge path. A first N-type shallow well 602 and a fourth N+ injection region 804 are embedded on the right side of the P-type epitaxial layer 300 and connected to the anode. This, along with the first P-type well 503 and the fifth P+ injection region 905, forms a reverse diode path. When the device is subjected to a reverse ESD pulse, the ESD current flows sequentially through the fifth P+ injection region 905, the first P-type well 503, the P-type epitaxial layer 300, the first N-type shallow well 602, and the fourth N+ injection region 804. This shorter path significantly reduces the negative on-resistance of the thyristor structure, and the fourth N+ injection region 804 can be widened, further enhancing the negative ESD discharge capability.

[0086] Third, a floating fourth P+ injection region 904 is embedded to the left of the first P-type well 503. The floating fourth P+ injection region 904 can reduce the amplification factor β of the parasitic transistor NPN1, and at the same time reduce the carrier mobility in the region below it, so that the ESD current path is away from the device surface and the discharge path is deeper and longer, thereby effectively improving the thyristor sustaining voltage.

[0087] Fourth, by embedding a first P-type shallow well 601 and a first P+ injection region 901 on the left side of the embedded GDPMOS structure (a parasitic transistor PNP1 composed of a second P+ injection region 902, a second N-type well 502, and a third P+ injection region 903), an additional parasitic transistor PNP3 is formed, which is triggered to conduct and participate in the discharge during the later stages of ESD discharge. Thus, in the thyristor circuit composed of parasitic PNP and parasitic NPN, the proportion of parasitic PNP is increased, thereby significantly improving the sustaining voltage of the thyristor device and greatly reducing the risk of latch-up.

[0088] In summary, this embodiment embeds a GDPMOS structure at the avalanche breakdown surface, giving it the same low breakdown voltage and trigger voltage as traditional GDPMOS and GGNMOS, effectively reducing the trigger voltage of the SCR device. At the same time, by embedding multiple parasitic PNP transistors (including the PNP1 inherent in the GDPMOS structure and the additional PNP2 and PNP3), the proportion of parasitic PNPs is increased, thereby significantly improving the sustaining voltage and enabling the device to meet the requirements of the 5V ESD design window.

[0089] Example 2

[0090] This invention also provides a method for fabricating the above-mentioned low-voltage unidirectional silicon-controlled electrostatic discharge (SCD) device, so as to... Figure 3 The cross-sectional view structure is used as an example, and includes the following steps:

[0091] See Figure 5 (Execute step 1), providing a P-type substrate 100.

[0092] See Figure 5 (Execute step 2) to form an N-type buried layer 200 in the P-type substrate 100, with the N-type buried layer 200 adjacent to the upper surface of the P-type substrate 100.

[0093] Specifically, as an example, before forming the N-type buried layer 200, step 1) further includes a pretreatment step of the P-type substrate 100; including: forming a hard mask layer (e.g., a stacked silicon dioxide layer and silicon nitride layer) on the P-type substrate 100; spin-coating a photoresist layer on the hard mask layer, and exposing and developing based on the mask to form an implantation window pattern to define the area where the N-type buried layer 200 needs to be formed; etching away the hard mask layer below the implantation window pattern to expose the upper surface of the P-type substrate 100; and removing the remaining photoresist. Then, an ion implantation process is used to implant N-type impurities (such as phosphorus or arsenic) into the exposed P-type substrate 100 area, followed by high-temperature annealing to activate the impurities and form the N-type buried layer 200.

[0094] See Figure 6(Execute step 3) to etch a groove on the upper surface of the P-type substrate 100. The groove is located in the vertical projection area of ​​the N-type buried layer, and the bottom of the groove exposes the N-type buried layer 200. A P-type epitaxial layer 300 is formed in the groove, and the upper surface of the P-type epitaxial layer 300 is flush with the upper surface of the P-type substrate 100.

[0095] See Figure 7 (Execute step 4) to form a first high-pressure N-well 401 and a second high-pressure N-well 402 in the P-type epitaxial layer 300, and to place the first high-pressure N-well 401 and the second high-pressure N-well 402 on both sides of the transverse direction of the N-type buried layer 200.

[0096] See Figure 8 (Execute step 5) A first N-type well 501 is formed in the upper region of the first high-pressure N-well 401, and a third N-type well 504 is formed in the upper region of the second high-pressure N-well 402; in the P-type epitaxial layer 300, a well region is formed from left to right, including a first P-type shallow well 601, a second N-type well 502, a first P-type well 503 and a first N-type shallow well 602; wherein the first P-type shallow well 601, the second N-type well 502 and the first P-type well 503 are adjacent, and there is a gap between the first P-type well 503 and the first N-type shallow well 602.

[0097] In one embodiment, see Figure 9After step 5), the process further includes forming a first oxygen isolation zone 701, a second oxygen isolation zone 702, a third oxygen isolation zone 703, a fourth oxygen isolation zone 704, a fifth oxygen isolation zone 705, a sixth oxygen isolation zone 706, a seventh oxygen isolation zone 707, an eighth oxygen isolation zone 708, a ninth oxygen isolation zone 709, and a tenth oxygen isolation zone 710. The first field oxygen isolation region 701 extends downward from the surface of the P-type substrate 100 and the surface of the first N-type well 501; the second field oxygen isolation region 702 extends downward from left to right from the surface of the first N-type well 501, the surface of the P-type epitaxial layer 300, and the surface of the first P-type shallow well 601; the third field oxygen isolation region 703 extends downward from the surface of the first P-type shallow well 601 and the surface of the second N-type well 502; the fourth field oxygen isolation region 704 extends downward from the surface of the second N-type well 502; the fifth field oxygen isolation region 705 extends downward from the surface of the second N-type well 502 and the surface of the first P-type well 503; the sixth field oxygen isolation region 704 extends downward from the surface of the second N-type well 502; the sixth field oxygen isolation region 705 extends downward from the surface of the second N-type well 502 and the surface of the first P-type well 503; the sixth field oxygen isolation region 705 extends downward from the surface of the second N-type well 502 and the surface of the first P-type well 503; the sixth field oxygen isolation region 702 extends downward from the surface of the first N-type well 502 and the surface of the first P-type well 503; the sixth field oxygen isolation region 702 extends downward from the surface of the first N-type well 501 ...1; the sixth field oxygen isolation region 702 extends downward from the surface of the first N-type well 50 Oxygen isolation region 706 extends downward from the surface of the first P-type well 503; seventh field oxygen isolation region 707 extends downward from the surface of the first P-type well 503; eighth field oxygen isolation region 708 extends downward from left to right from the surface of the first P-type well 503, the surface of the P-type epitaxial layer 300, and the surface of the first N-type shallow well 602; ninth field oxygen isolation region 709 extends downward from left to right from the surface of the first N-type shallow well 602, the surface of the P-type epitaxial layer 300, and the surface of the third N-type well 504; tenth field oxygen isolation region 710 extends downward from the surface of the third N-type well 504 and the surface of the P-type substrate 100.

[0098] See Figure 10 (Execute step 6) to form a first gate 900 above the second N-type well 502. The first gate 900 covers the surface of the second N-type well 502 and reserves the area for the subsequent formation of the second P+ injection region 902 and the third P+ injection region 903.

[0099] Specifically, the steps for forming the first gate 900 include: First, a high-quality gate oxide layer is grown on the surface of the second N-type well 502 using thermal oxidation. The gate oxide layer is used to isolate the first gate 900 from the channel region and determines the gate control capability of the device. Then, a polysilicon layer is deposited on the gate oxide layer and doped to reduce resistance and improve conductivity. Finally, the first gate 900 is obtained through photolithography and etching processes. The first gate 900 is located between the second P+ injection region 902 and the third P+ injection region 903, and the region below it serves as the channel region and avalanche breakdown surface of the GDPMOS. By adjusting the width S1 of the first gate 900, the effective size of the avalanche breakdown surface can be changed, thereby controlling the trigger voltage of the device.

[0100] See Figure 11(Execute step 7) Using the first gate 900 as a mask, a second P+ injection region 902 and a third P+ injection region 903 are self-aligned and formed in the second N-type well 502, such that the first gate 900 is located between the second P+ injection region 902 and the third P+ injection region 903; then, a first N+ injection region 801 is formed on the first N-type well 501, a first P+ injection region 901 is formed on the first P-type shallow well 601, and a second P+ injection region 903 is formed in the second N-type well 502. A second N+ injection region 802 is formed on the left side of the second P+ injection region 902. A fourth P+ injection region 904, a third N+ injection region 803, and a fifth P+ injection region 905 are formed on the first P-type well 503 (where the fourth P+ and the fifth P+ are P-type injections and the third N+ is an N-type injection, which is carried out in steps). A fourth N+ injection region 804 is formed on the first N-type shallow well 602, and a fifth N+ injection region 805 is formed on the third N-type well 504.

[0101] In one embodiment, the first N+ implantation region 801 is located between the first field oxygen isolation region 701 and the second field oxygen isolation region 702; the first P+ implantation region 901 is located between the second field oxygen isolation region 702 and the third field oxygen isolation region 703; the second N+ implantation region 802 is located between the third field oxygen isolation region 703 and the fourth field oxygen isolation region 704; and the second P+ implantation region 902 is located between the fourth field oxygen isolation region 704 and the channel region directly below the first gate 900. The third P+ implantation region 903 is located between the channel region directly below the first gate 900 and the fifth field oxygen isolation region 705; the fourth P+ implantation region 904 is located between the fifth field oxygen isolation region 705 and the sixth field oxygen isolation region 706; the third N+ implantation region 803 is located between the sixth field oxygen isolation region 706 and the seventh field oxygen isolation region 707; the fifth P+ implantation region 905 is located between the seventh field oxygen isolation region 707 and the eighth field oxygen isolation region 708; the fourth N+ implantation region 804 is located between the eighth field oxygen isolation region 708 and the ninth field oxygen isolation region 709; and the fifth N+ implantation region 805 is located between the ninth field oxygen isolation region 709 and the tenth field oxygen isolation region 710.

[0102] Step 8) involves annealing each implanted region to activate the implanted impurities and repair lattice damage.

[0103] See Figure 12 (Execute step 9) Connect the first P+ injection region 901, the second N+ injection region 802, the first gate 900 and the fourth N+ injection region 804 together as the anode, and connect the third P+ injection region 903, the third N+ injection region 803, the fifth P+ injection region 905, the first N+ injection region 801 and the fifth N+ injection region 805 together as the cathode.

[0104] As an example, in the step of connecting the injection regions together as an anode or cathode, a multilayer metal interconnect structure is used, including a deposited interlayer dielectric layer, etched contact holes, and filler metal.

[0105] Specifically, firstly, an interlayer dielectric layer is deposited on the surface of the completed device structure to isolate the underlying semiconductor device from the upper metal interconnect layer, preventing unnecessary leakage and short circuits. Then, through photolithography and etching processes, contact holes are formed in the interlayer dielectric layer at positions corresponding to the implantation regions that need to be connected (such as the first P+ implantation region 901, the second N+ implantation region 802, the second P+ implantation region 902, the first gate 900, and the fourth N+ implantation region 804, etc.). These contact holes penetrate the dielectric layer and reach the surface of the implantation region or the gate surface. Next, metal (such as tungsten, titanium / titanium nitride composite layer, etc.) is filled into the contact holes to form vertical conductive plugs, achieving low-resistance ohmic contact between the metal layer and the underlying silicon region. Finally, a first metal layer (such as an aluminum-copper alloy) is deposited on the dielectric layer after the contact holes are filled, and the metal layer is patterned into the required interconnect lines through photolithography and etching to short-circuit and connect the implantation regions belonging to the same electrode, forming a complete anode or cathode lead-out. Optionally, for more complex wiring requirements, a multi-layer metal interconnect structure can be used. This involves depositing an interlayer dielectric layer, creating vias, and then a second metal layer on top of the first metal layer to achieve cross-region connections or reduce interconnect resistance. This multi-layer metal interconnect structure allows for the flexible and reliable connection of multiple injection regions distributed in different well regions to a single electrode, ensuring uniform conduction and current discharge capability of the device under high-current ESD events.

[0106] It should be noted that this article is based on Figure 3 The structure shown is illustrated as an example, but the preparation method of the present invention is not limited to this example. Those skilled in the art will understand that this method is equally applicable to other structural variations covered by the present invention.

[0107] In summary, this invention provides a low-voltage unidirectional thyristor electrostatic discharge (ESD) device and its fabrication method, aiming to solve the technical problems of high trigger voltage and low sustaining voltage, and easy latch-up, of existing thyristor devices under the 5V ESD design window. The device of this invention includes a P-type substrate, an N-type buried layer disposed in the P-type substrate, a P-type epitaxial layer selectively disposed on the P-type substrate and located in a region perpendicular to the N-type buried layer, a first high-voltage N-well and a second high-voltage N-well located on both sides of the N-type buried layer, a first N-type well and a third N-type well disposed in the upper regions of the first and second high-voltage N-wells, and a first P-type shallow well, a second N-type well, a first P-type well, and a first N-type shallow well disposed sequentially from left to right in the P-type epitaxial layer. The second N-type well contains a second N+ injection region, a second P+ injection region, and a third P+ injection region. A first gate is disposed above the second N-type well, and the first gate covers the surface of the second N-type well between the second P+ injection region and the third P+ injection region, forming a GDPMOS structure. This structure reduces the avalanche breakdown voltage of the device to 9V~10V, the same as GDPMOS or GGNMOS, effectively lowering the trigger voltage of the SCR device. A floating fourth P+ injection region is provided within the first P-type well, which reduces the amplification factor of the parasitic transistor, making the ESD current discharge path deeper and longer, significantly improving the holding voltage, and greatly reducing the risk of latch-up in the SCR device. Furthermore, the fourth N+ injection region, the first N-type shallow well, the P-type epitaxial layer, the first P-type well, and the fifth P+ injection region constitute a reverse diode, providing a shorter and more robust reverse discharge path, greatly reducing the negative conduction resistance and enhancing the negative ESD discharge capability. This invention significantly improves the holding voltage while reducing the trigger voltage, making it particularly suitable for 5V ESD design windows. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0108] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A low-voltage unidirectional thyristor electrostatic discharge (ESD) protection device, characterized in that, The low-voltage unidirectional thyristor electrostatic discharge protection device includes at least: P-type substrate; An N-type buried layer is disposed in the P-type substrate and located in the upper region of the P-type substrate; A P-type epitaxial layer is disposed on the P-type substrate and located in a region perpendicular to the N-type buried layer; wherein the upper surface of the P-type epitaxial layer is flush with the upper surface of the P-type substrate, and the sides of both the P-type epitaxial layer and the N-type buried layer are the P-type substrate. The P-type epitaxial layer is provided with a first high-pressure N-well and a second high-pressure N-well, and the first high-pressure N-well and the second high-pressure N-well are respectively located on both sides of the transverse direction of the N-type buried layer. The upper region of the first high-voltage N-well is provided with a first N-type well; the upper region of the second high-voltage N-well is provided with a third N-type well. The P-type epitaxial layer is provided with a first P-type shallow well, a second N-type well, a first P-type well, and a first N-type shallow well from left to right; wherein the first P-type shallow well, the second N-type well, and the first P-type well are adjacent to each other, and there is a gap between the first P-type well and the first N-type shallow well. The first N-type well is provided with a first N+ injection region; The first P-type shallow well is provided with a first P+ injection region; The second N-type well is provided with a second N+ injection region, a second P+ injection region and a third P+ injection region from left to right; a first gate is provided above the second N-type well, and the first gate covers the surface of the second N-type well between the second P+ injection region and the third P+ injection region; The first P-type well is provided with a fourth P+ injection region, a third N+ injection region and a fifth P+ injection region from left to right; The first N-type shallow well is provided with a fourth N+ injection region; The third N-type well is provided with a fifth N+ injection region; The first P+ injection region, the second N+ injection region, the second P+ injection region, the first gate, and the fourth N+ injection region are connected together and serve as the anode of the device; the third P+ injection region, the third N+ injection region, the fifth P+ injection region, the first N+ injection region, and the fifth N+ injection region are connected together and serve as the cathode of the device; the fourth P+ injection region is not connected to any potential. The second P+ injection region, the second N-type well, and the third P+ injection region constitute a first PNP transistor PNP1; the second P+ injection region, the second N-type well, and the first P-type well constitute a second PNP transistor PNP2; the first P+ injection region, the first P-type shallow well, the second N-type well, and the first P-type well constitute a third PNP transistor PNP3; the second N-type well, the first P-type well, and the third N+ injection region constitute a first NPN transistor NPN1; in the reverse path, the fourth N+ injection region, the first N-type shallow well, the P-type epitaxial layer, the first P-type well, and the fifth P+ injection region constitute a reverse diode Diode1.

2. The low-voltage unidirectional thyristor electrostatic discharge protection device according to claim 1, characterized in that, The low-voltage unidirectional thyristor electrostatic discharge (ESD) device further includes: a first field oxygen isolation region disposed outside the first N+ injection region in the first N-type well; a second field oxygen isolation region disposed between the first N+ injection region and the first P+ injection region; a third field oxygen isolation region disposed between the first P+ injection region and the second N+ injection region; a fourth field oxygen isolation region disposed between the second N+ injection region and the second P+ injection region; a fifth field oxygen isolation region between the third P+ injection region and the fourth P+ injection region; a sixth field oxygen isolation region between the fourth P+ injection region and the third N+ injection region; a seventh field oxygen isolation region between the third N+ injection region and the fifth P+ injection region; an eighth field oxygen isolation region between the fifth P+ injection region and the fourth N+ injection region; a ninth field oxygen isolation region between the fourth N+ injection region and the fifth N+ injection region; and a tenth field oxygen isolation region disposed outside the fifth N+ injection region in the third N-type well.

3. The low-voltage unidirectional thyristor electrostatic discharge protection device according to claim 2, characterized in that: The first field oxygen isolation region extends downward from the surface of the P-type substrate and the surface of the first N-type well; the second field oxygen isolation region extends downward from left to right from the surface of the first N-type well, the surface of the P-type epitaxial layer, and the surface of the first P-type shallow well; the third field oxygen isolation region extends downward from the surface of the first P-type shallow well and the surface of the second N-type well; the fourth field oxygen isolation region extends downward from the surface of the second N-type well; the fifth field oxygen isolation region extends downward from the surface of the second N-type well and the surface of the first P-type well; the sixth field oxygen isolation region extends downward from the surface of the first P-type well; the seventh field oxygen isolation region extends downward from the surface of the first P-type well; the eighth field oxygen isolation region extends downward from left to right from the surface of the first P-type well, the surface of the P-type epitaxial layer, and the surface of the first N-type shallow well; the ninth field oxygen isolation region extends downward from left to right from the surface of the first N-type shallow well, the surface of the P-type epitaxial layer, and the surface of the third N-type well; and the tenth field oxygen isolation region extends downward from the surface of the third N-type well and the surface of the P-type substrate.

4. The low-voltage unidirectional thyristor electrostatic discharge protection device according to claim 1, characterized in that: The first N+ injection region, the first N-type well, the first high-pressure N-well, the N-type buried layer, the fifth N+ injection region, the third N-type well, and the second high-pressure N-well constitute an ISO isolation ring.

5. The low-voltage unidirectional thyristor electrostatic discharge protection device according to claim 1, characterized in that: The width of the first gate is configured to be adjustable to change the effective size of the avalanche breakdown surface formed between the second N-type well and the third P+ injection region, thereby adjusting the avalanche breakdown voltage and trigger voltage of the device.

6. A method for fabricating a low-voltage unidirectional thyristor electrostatic discharge (ESD) device, characterized in that, The method for fabricating the low-voltage unidirectional thyristor electrostatic discharge (ESD) device includes: Step 1) Provide a P-type substrate; Step 2) An N-type buried layer is formed in the P-type substrate, wherein the N-type buried layer is located on the upper surface of the P-type substrate; Step 3) A groove is etched on the upper surface of the P-type substrate, the groove is located in the vertical projection area of ​​the N-type buried layer, and the bottom of the groove exposes the N-type buried layer; a P-type epitaxial layer is formed in the groove, such that the upper surface of the P-type epitaxial layer is flush with the upper surface of the P-type substrate. Step 4) Form a first high-voltage N-well and a second high-voltage N-well in the P-type epitaxial layer, and position the first high-voltage N-well and the second high-voltage N-well on opposite sides of the N-type buried layer in the transverse direction; Step 5) A first N-type well is formed in the upper region of the first high-pressure N-well, and a third N-type well is formed in the upper region of the second high-pressure N-well; in the P-type epitaxial layer, a well region is formed from left to right, including a first P-type shallow well, a second N-type well, a first P-type well, and a first N-type shallow well; wherein, the first P-type shallow well, the second N-type well, and the first P-type well are adjacent, and there is a gap between the first P-type well and the first N-type shallow well; Step 6) A first gate is formed above the second N-type well, the first gate covers the surface of the second N-type well, and reserves the area for the subsequent formation of the second P+ injection region and the third P+ injection region; Step 7) Using the first gate as a mask, a second P+ injection region and a third P+ injection region are self-aligned and formed in the second N-type well, such that the first gate is located between the second P+ injection region and the third P+ injection region; then, a first N+ injection region is formed on the first N-type well, a first P+ injection region is formed on the first P-type shallow well, a second N+ injection region is formed on the second N-type well, a fourth P+ injection region, a third N+ injection region and a fifth P+ injection region are formed on the first P-type well, a fourth N+ injection region is formed on the first N-type shallow well, and a fifth N+ injection region is formed on the third N-type well; Step 8) Anneal each implanted region to activate the implanted impurities and repair lattice damage; Step 9) Connect the first P+ injection region, the second N+ injection region, the second P+ injection region, the first gate, and the fourth N+ injection region together as the anode, and connect the third P+ injection region, the third N+ injection region, the fifth P+ injection region, the first N+ injection region, and the fifth N+ injection region together as the cathode.

7. The method for preparing a low-voltage unidirectional thyristor electrostatic discharge (ESD) device according to claim 6, characterized in that: After step 5) and before step 6), the process further includes the steps of forming a first field oxygen isolation region, a second field oxygen isolation region, a third field oxygen isolation region, a fourth field oxygen isolation region, a fifth field oxygen isolation region, a sixth field oxygen isolation region, a seventh field oxygen isolation region, an eighth field oxygen isolation region, a ninth field oxygen isolation region, and a tenth field oxygen isolation region; the first field oxygen isolation region extends downward from the surface of the P-type substrate and the surface of the first N-type well; the second field oxygen isolation region extends downward from left to right sequentially from the surface of the first N-type well, the surface of the P-type epitaxial layer, and the surface of the first P-type shallow well; the third field oxygen isolation region extends downward from the surface of the first P-type... The surface of the shallow well and the surface of the second N-type well extend downwards; the fourth field oxygen isolation region extends downwards from the surface of the second N-type well and is located between the second N+ injection region and the second P+ injection region; the fifth field oxygen isolation region extends downwards from the surface of the second N-type well and the surface of the first P-type well; the sixth field oxygen isolation region extends downwards from the surface of the first P-type well and is located between the fourth P+ injection region and the third N+ injection region; the seventh field oxygen isolation region extends downwards from the surface of the first P-type well and is located between the third N+ injection region and the fifth P+ injection region; The eighth field oxygen isolation region extends downward from left to right from the surface of the first P-type well, the surface of the P-type epitaxial layer, and the surface of the first N-type shallow well; the ninth field oxygen isolation region extends downward from left to right from the surface of the first N-type shallow well, the surface of the P-type epitaxial layer, and the surface of the third N-type well; the tenth field oxygen isolation region extends downward from the surface of the third N-type well and the surface of the P-type substrate.

8. The method for preparing a low-voltage unidirectional thyristor electrostatic discharge (ESD) device according to claim 7, characterized in that: The first field oxygen isolation region is located outside the first N+ injection region in the first N-type trap; the second field oxygen isolation region is between the first N+ injection region and the first P+ injection region; the third field oxygen isolation region is between the first P+ injection region and the second N+ injection region. The fourth oxygen isolation zone is located between the second N+ injection zone and the second P+ injection zone; The fifth oxygen isolation zone is located between the third P+ injection zone and the fourth P+ injection zone; The sixth oxygen isolation zone is located between the fourth P+ injection zone and the third N+ injection zone; The seventh oxygen isolation zone is located between the third N+ injection zone and the fifth P+ injection zone; The eighth oxygen isolation zone is located between the fifth P+ injection zone and the fourth N+ injection zone; The ninth oxygen isolation zone is located between the fourth N+ injection zone and the fifth N+ injection zone; The tenth oxygen isolation zone is located outside the fifth N+ injection zone in the third N-type trap.

9. The method for preparing a low-voltage unidirectional thyristor electrostatic discharge (ESD) device according to claim 6, characterized in that: The first to the tenth oxygen isolation zones are all formed using the shallow trench isolation (STI) process.

10. The method for preparing a low-voltage unidirectional thyristor electrostatic discharge (ESD) device according to claim 6, characterized in that, The steps for forming the first gate include: growing a gate oxide layer on the surface of the second N-type well, depositing a polysilicon layer on the gate oxide layer, doping the polysilicon layer, and then photolithography and etching to form the first gate.

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