A synergistic enhancement gate-controlled transistor with multi-stage current discharge modes and its fabrication method

Abstract

This invention discloses a synergistic enhancement gate-controlled transistor with multi-level current discharge modes and its fabrication method, comprising a substrate P-Sub; first and second DN-Well regions are provided in the substrate P-Sub; a first N-Well region is provided in the first DN-Well region; a first P-Well region is provided between the first DN-Well and second DN-Well regions; a second P-Well region is provided to the right of the second DN-Well region; a first N-Well region and a first P+ injection region with segmented topology are provided in the first N-Well region; the first P-Well region is provided with a first polysilicon gate, a second N+ injection region, a second P+ injection region, a third N+ injection region, a second polysilicon gate, and a fourth N+ injection region from left to right; the second P-Well region is provided with a fifth N+ injection region, a third polysilicon gate, and a sixth N+ injection region from left to right. This invention constructs a synergistic enhancement gate-controlled transistor with multi-level current discharge modes through internally formed NMOS1, NMOS2, parasitic PNP transistors, and parasitic NPN transistors. By controlling the gate potential to coordinate the conduction states of each transistor, a multi-stage, multi-path current discharge mode is formed. This invention can effectively improve the continuous overvoltage and overcurrent capability of chip I / O ports, has a simple structure, is compatible with standard CMOS processes, and is suitable for high-reliability applications such as automotive electronics and industrial control.

Description

Technical Field

[0001] This invention relates to the field of electrical overstress (EOS) protection for semiconductor devices, and particularly to a synergistic enhancement gate transistor with multi-level current discharge modes and its fabrication method. Background Technology

[0002] As semiconductor processes enter the era of deep submicron and advanced packaging, the threat of EOS (Effective Overvoltage / Overcurrent) events to the long-term reliability of chips is becoming increasingly prominent. Industry statistics show that in chip lifecycle failure cases in automotive electronics, industrial control, and other fields, performance degradation and structural damage caused by continuous overvoltage and overcurrent account for over 35%, far exceeding other failure modes. Especially in high-voltage power supply scenarios such as automotive power supplies and motor drives, transient surges, load drops, and wiring harness coupling can trigger overvoltage and overcurrent impacts lasting from microseconds to milliseconds, with energy densities far exceeding those of conventional EOS events, posing severe challenges to the response speed and current-discharging capabilities of protection devices.

[0003] Currently, traditional over-current protection (EOS) structures mostly employ gate-grounded NMOS (GGNMOS), but this approach presents numerous problems in practical applications. When EOS stress is applied to the drain of the GGNMOS, the device forms a parasitic NPN transistor to release the EOS current due to the avalanche effect. However, this type of structure relies solely on a single parasitic bipolar transistor for discharge, resulting in low discharge efficiency and failing to meet the electrical over-stress protection requirements of chips operating in complex environments such as automotive electronics and industrial control.

[0004] The structure and equivalent circuit of a traditional gate-grounded NMOS are as follows: Figure 1 As shown, when the anode of the device is subjected to EOS stress, an avalanche breakdown effect occurs between its N+ injection and P-Well, generating a large number of avalanche carriers. Under the action of the electric field, the electrons generated by avalanche multiplication enter the P-Well of the device and are generated at the parasitic resistance R. P-Well A voltage drop is generated, thus turning on the parasitic NPN transistor composed of an anode N+ injection, a cathode N+ injection, and a P-Well. The anode N+ injection acts as the collector, the cathode N+ injection as the emitter, and the P-Well as the base, connected through resistor R. P-Well The P+ injection is led to the cathode and connected to the cathode through the P+ injection ohmic contact. GGNMOS only releases overvoltage stress through the internal parasitic NPN transistor. Under high current conditions, it is difficult to respond quickly and discharge energy to ground in time, which leads to permanent burn-out of the device and cannot effectively guarantee the normal operation of the internal core circuit.

[0005] To address the aforementioned technical problems, this invention, based on research into gate-controlled bipolar devices, provides a simple, monolithically integrated, CMOS-compatible, synergistically enhanced gate-controlled transistor with multi-level current discharge modes, and also provides its fabrication method.

[0006] The technical solution of this invention to solve the above problems is: a cooperative enhancement gate-controlled transistor structure with multi-level current discharge modes, characterized in that: a substrate P-Sub; the substrate P-Sub region is provided with, from bottom to top and from left to right, a first DN-Well region, a second DN-Well region, a first N-Well region, a first P-Well region, a second P-Well region, a first field oxygen isolation region, a first segmented topology N+ injection region, a first segmented topology P+ injection region, a second field oxygen isolation region, a first polysilicon gate, a second N+ injection region, a second P+ injection region, a third field oxygen isolation region, a third N+ injection region, a second polysilicon gate, a fourth N+ injection region, a fourth field oxygen isolation region, a fifth N+ injection region, a third polysilicon gate, a sixth N+ injection region, and a fifth field oxygen isolation region. An isolation region; the first segmented topology N+ implantation region and the first segmented topology P+ implantation region are located in the first N-Well region; the first polysilicon gate is located between the second field oxygen isolation region and the second N+ implantation region; the second N+ implantation region, the second P+ implantation region, the third N+ implantation region, the second polysilicon gate, and the fourth N+ implantation region are located in the first P-Well region; the fifth N+ implantation region, the third polysilicon gate, and the sixth N+ implantation region are located in the second P-Well region; the second N+ implantation region, the second P+ implantation region, the third N+ implantation region, the second polysilicon gate, and the fifth N+ implantation region are connected to serve as the cathode of the device; the first segmented topology N+ implantation region, the first segmented topology P+ implantation region, the fourth N+ implantation region, and the sixth N+ implantation region are connected to serve as the anode of the device; The aforementioned synergistic enhancement gate-controlled transistor structure with multi-stage current discharge modes, when EOS stress is applied to the anode of the device, the cathode is grounded, and the potential of the third polysilicon gate is higher than the threshold voltage, turns on the NMOS2 formed by the fifth N+ injection region, the second P-Well region, the third polysilicon gate, and the sixth N+ injection region. The fifth N+ injection region acts as the source of NMOS2, and the sixth N+ injection region acts as the drain of NMOS2. Under the action of the gate voltage, a vertically downward electric field is formed below the third polysilicon gate, forming an electron channel below the gate, constituting a discharge path in low-current mode. As the EOS stress applied to the anode increases, the fourth N+ injection region and the first P-Well region undergo avalanche breakdown, turning on the NPN transistor formed by the third N+ injection region, the fourth N+ injection region, and the first P-Well region. The base region of the NPN transistor is connected through the parasitic resistance R. P-WellThe first polysilicon gate is connected to the second P+ injection region and leads out the cathode from the second P+ injection region. The second polysilicon gate is used to shorten the base region width of the parasitic NPN transistor, thereby improving the transistor's amplification factor and discharge efficiency. Since the discharge efficiency of the NPN transistor is higher than that of NMOS2, the parasitic NPN transistor forms the discharge path in the medium current mode. In the high current mode, when the potential of the first polysilicon gate is higher than the threshold voltage, minority carriers in the substrate P-Sub region and the first P-Well region are attracted to move upward, forming an electron communication connection between the first DN-Well region and the second N+ injection region below the gate. Under the action of the anode voltage, electrons drift from the second N+ injection region to the first DN-Well region through the electron channel, turning on NMOS1, which is composed of the first N+ injection region, the first N-Well region, the first DN-Well region, the substrate P-Sub, the first P-Well region, the second N+ injection region, and the first polysilicon gate. The electronic current from NMOS1 further constitutes the base current of the parasitic PNP transistor, which consists of the first P+ injection region, the first N-Well region, the first DN-Well region, the substrate P-Sub region, the first P-Well region, and the second P+ injection region. Under the current gain of the parasitic PNP transistor, the channel current of NMOS1 is further amplified. The composite bipolar transistor composed of NMOS1 and PNP forms a current discharge path in high-current mode. This forms a synergistic enhancement gate transistor structure with multi-stage current discharge modes. By coordinating the conduction states of the internal transistors through the gate potential, efficient discharge of EOS stress is achieved, thereby effectively protecting the core circuit from the influence of complex external electromagnetic environments.

[0007] A method for fabricating a synergistic enhancement gate-controlled transistor with multi-stage current discharge modes includes the following steps: Step 1: Form the first and second DN-Well regions in the P-Sub substrate; Step 2: Form the first to fifth field oxygen isolation regions on the P-Sub substrate using photolithography; Step 3: Form the first P-Well region and the second P-Well region in the P-Sub substrate by photolithography; Step 4: Form the first N-Well region in the first DN-Well region using photolithography; Step 5: By photolithography, a first polysilicon gate is formed above the second field oxygen isolation region, the first DN-Well region, the substrate P-Sub, and the first P-Well region; a second polysilicon gate is formed in the first P-Well region; and a third polysilicon gate is formed in the second P-Well region.

[0008] Step 6: Using photolithography, a first segmented topology P+ injection region is formed in the first N-Well region, and a second P+ injection region is formed in the first P-Well region.

[0009] Step 7: Through photolithography, a first segmented N+ implantation region is formed in the first N-Well region, a second N+ implantation region, a third N+ implantation region and a fourth N+ implantation region are formed in the first P-Well region, and a fifth N+ implantation region and a sixth N+ implantation region are formed in the second P-Well region.

[0010] The technical solution of the present invention to solve the above problems is: 1. The present invention constitutes a synergistic enhancement gate-controlled transistor structure with multi-level current discharge mode. Through the regulation of the gate electric field, the conduction state of each parasitic bipolar transistor and MOSFET inside the device is coordinated, thereby realizing a multi-level discharge mode of EOS stress.

[0011] 2. This invention discharges through the electronic channel of NMOS2 in low-current mode; through the parasitic NPN transistor in medium-current mode; and through the composite structure of NMOS1 and the parasitic PNP transistor in high-current mode, where the channel current of NMOS1 constitutes the base current of the parasitic PNP transistor. This multi-stage current discharge mode achieves monolithic integration of each current path without occupying additional chip area.

[0012] 3. The segmented topology N+ and P+ injection design of this invention does not require additional anode area, effectively improving the area utilization efficiency of the device. Furthermore, the P+ injection region of the segmented topology provides a carrier path for the conductance modulation effect caused by current injection in low-doped DN-Wells, effectively reducing the device turn-off speed and avoiding the risk of forming latch-up paths and burning out the circuit. Attached Figure Description

[0013] Figure 1 The diagram shows a cross-sectional view and an equivalent circuit diagram of a traditional GGNMOS structure.

[0014] Figure 2 This is a cross-sectional view and circuit connection diagram of a cooperative enhancement gate-controlled transistor structure with multi-stage current discharge modes in an embodiment of the present invention.

[0015] Figure 3 This is a three-dimensional structural diagram of a cooperative enhancement gate-controlled transistor structure with multi-stage current discharge modes in an embodiment of the present invention.

[0016] Figure 4 This is the equivalent circuit of the EOS release path of the cooperative enhancement gate transistor structure with multi-stage current discharge modes in the embodiments of the present invention.

[0017] Figure 5 This is a top view of a cooperative enhancement gate-controlled transistor structure with multi-stage current discharge modes in an embodiment of the present invention.

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0019] like Figures 1-5 As shown, a synergistic enhancement gate-controlled transistor structure with multi-level current discharge modes is characterized by: including a substrate P-Sub101; wherein the substrate P-Sub101 is provided with, from bottom to top and from left to right, a first DN-Well region 201, a second DN-Well region 202, a first N-Well region 301, a first P-Well region 401, a second P-Well region 402, a first field-oxygen isolation region 701, a first segmented topology N+ injection region 501, a first segmented topology P+ injection region 601, a second field-oxygen isolation region 702, a first polysilicon gate 801, a second N+ injection region 502, a second P+ injection region 602, a third field-oxygen isolation region 703, a third N+ injection region 503, and a second polysilicon gate. The system comprises a gate 802, a fourth N+ implantation region 504, a fourth field oxygen isolation region 704, a fifth N+ implantation region 505, a third polysilicon gate 803, a sixth N+ implantation region 506, and a fifth field oxygen isolation region 705; the first segmented topology N+ implantation region 501 and the first segmented topology P+ implantation region 601 are located in the first N-Well region 301; the first polysilicon gate 801 is located between the second field oxygen isolation region 702 and the second N+ implantation region 502; the third N+ implantation region 503, the second polysilicon gate 802, and the fourth N+ implantation region 504 are located in the first P-Well region 401; the fifth N+ implantation region 505, the third polysilicon gate 803, and the sixth N+ implantation region 506 are located in the second P-Well region 402; The second N+ injection region 502 is connected to the third metal layer 903 of metal layer 1 through a contact hole. The second P+ injection region 602 is connected to the fourth metal layer 904 of metal layer 1 through a contact hole. The third N+ injection region 503 is connected to the fifth metal layer 905 of metal layer 1 through a contact hole. The second polysilicon gate is connected to the sixth metal layer 906 of metal layer 1 through a contact hole. The fifth N+ injection region 505 is connected to the eighth metal layer 908 of metal layer 1 through a contact hole. A metal via 1103 is provided on the third metal layer 1003 of metal layer 2. The third metal layer 903, fourth metal layer 904, fifth metal layer 905, sixth metal layer 906 and eighth metal layer 908 of metal layer 1 are connected to the third metal layer 1003 of metal layer 2 through the metal via 1103, serving as the cathode of the device.

[0020] The first segmented topology N+ injection region 501 and the first segmented topology P+ injection region 601 are connected to the first metal layer 901 of metal layer 1 through contact holes. The fourth N+ injection region 504 is connected to the seventh metal layer 907 of metal layer 1 through contact holes. The sixth N+ injection region 506 is connected to the tenth metal layer 910 of metal layer 1 through contact holes. A metal through-hole 1101 is provided on the first metal layer 1001 of metal layer 2. The first metal layer 901, the seventh metal layer 907, and the tenth metal layer 910 of metal layer 1 are connected to the first metal layer 1001 of metal layer 2 through the metal through-hole 1101, and are used as the anode of the device.

[0021] The first polysilicon gate 801 is connected to the second metal layer 902 of metal layer 1 through a contact hole. A metal through-hole 1102 is provided on the second metal layer 1002 of metal layer 2. The second metal layer 902 of metal layer 1 is connected to the second metal layer 1002 of metal layer 2 and serves as the gate of the device.

[0022] The third polysilicon gate 803 is connected to the ninth metal layer 909 of metal layer 1 through a contact hole. A metal through-hole 1104 is provided on the fourth metal layer 1004 of metal layer 2. The ninth metal layer 909 of metal layer 1 is connected to the fourth metal layer 1004 of metal layer 2 and serves as the gate of the device.

[0023] A method for fabricating a synergistic enhancement gate-controlled transistor with multi-stage current discharge modes includes the following steps: Step 1: Form a first DN-Well region 201 and a second DN-Well region 202 in the substrate P-Sub101; specifically: The first DN-Well region 201 and the second DN-Well region 202 are fabricated on the surface of the substrate P-Sub101. Then, a silicon dioxide thin film is formed by thermal oxidation to alleviate stress damage caused by silicon nitride formed in subsequent process steps. A silicon nitride layer is deposited using chemical vapor deposition (LPCVD) as a stop layer for CMP in subsequent process steps.

[0024] Photoresist is uniformly applied to the wafer, and then exposed and developed. This step is used to define shallow trench isolation (STI). Silicon nitride, silicon dioxide, and the isolation trenches are then etched to remove the photoresist layer. A layer of silicon dioxide is deposited using LPCVD, followed by chemical mechanical polishing until the silicon nitride thin film layer is reached. Finally, the silicon nitride thin film layer is removed using hot phosphoric acid wet etching.

[0025] Step 2: Using photolithography, form the first field oxygen isolation region 701, the second field oxygen isolation region 702, the third field oxygen isolation region 703, the fourth field oxygen isolation region 704, and the fifth field oxygen isolation region 705 on the substrate P-Sub101. Specifically: Using field oxygen (LOCOS) isolation technology, a silicon dioxide thin film is grown using thermal oxidation as a buffer layer. Then, silicon nitride is deposited using LPCVD technology. Photoresist is applied to the wafer, and photolithography is used to define the first field oxygen isolation region 701, the second field oxygen isolation region 702, the third field oxygen isolation region 703, the fourth field oxygen isolation region 704, and the fifth field oxygen isolation region 705. Reactive ions then etch away the silicon nitride on the first field oxygen isolation region 701, the second field oxygen isolation region 702, the third field oxygen isolation region 703, the fourth field oxygen isolation region 704, and the fifth field oxygen isolation region 705. Field implantation is then performed to prevent field activation.

[0026] Step 3: Form the first N-Well region 301 in the first DN-Well region 201 by photolithography.

[0027] Step 4: Using photolithography, form the first P-Well region 401 and the second P-Well region 402 in the substrate P-Sub101. Specifically: Photoresist is applied to the wafer to define the first N-Well region 301, and then high-energy phosphorus ion implantation is performed to form a local N-type region, after which the photoresist layer is removed.

[0028] Photoresist is applied to the wafer to define the first P-Well region 401 and the second P-Well region 402. Then, high-energy boron ions are implanted to form local P-type regions, and the photoresist is removed.

[0029] Annealing is performed on the first N-Well region 301, the first P-Well region 401, and the second P-Well region 402 to repair the crystal damage on the silicon surface caused by ion implantation, activate the implanted impurities, and eliminate further diffusion of impurities using the RTP process.

[0030] Step 5: A first polysilicon gate 801 is formed above the second field oxygen isolation region, the first DN-Well region, the substrate P-Sub, and the first P-Well region. A second polysilicon gate 802 is formed in the first P-Well region, and a third polysilicon gate 803 is formed in the second P-Well region. Specifically: The growth of a sacrificial oxide layer is used to capture defects on the silicon surface. Gate oxide layer growth, serving as the gate insulating layer for the transistor, involves depositing the first polysilicon gate 801, the second polysilicon gate 802, and the third polysilicon gate 803 using LPCVD. Photoresist is then used for shaping, followed by polysilicon etching, requiring precise shaping of the polysilicon from the photoresist before removing the photoresist layer. Polysilicon oxidation serves as a buffer to isolate the polysilicon from the silicon nitride formed in subsequent steps. A layer of silicon nitride is deposited using LPCVD, followed by silicon nitride etching to leave isolation sidewalls, and precise ion implantation to locate the transistor source and drain regions.

[0031] Step Six: Using photolithography, a first segmented topology P+ injection region 601 is formed in the first N-Well region 301, and a second P+ injection region 602 is formed in the first P-Well region 401. Specifically: Photoresist formation is used to control ion implantation. Shallow-depth, heavily doped boron ion implantation removes the photoresist layer, forming the first segmented topology P+ implantation region 601 and the second P+ implantation region 602.

[0032] Step 7: Using photolithography, a first segmented topology N+ injection region 501 is formed in the first N-Well region 301; a second N+ injection region 502, a third N+ injection region 503, and a fourth N+ injection region 504 are formed in the first P-Well region 401; and a fifth N+ injection region 505 and a sixth N+ injection region 506 are formed in the second P-Well region 402. Specifically: Photoresist formation is used to control ion implantation. Shallow-depth, heavily doped arsenic ion implantation removes the photoresist layer, forming the first segmented topology N+ implantation region 501, the second N+ implantation region 502, the third N+ implantation region 503, the fourth N+ implantation region 504, the fifth N+ implantation region 505, and the sixth N+ implantation region 506.

[0033] This invention constructs a synergistic enhancement gate-controlled transistor with multi-stage current discharge modes. By controlling the potentials of the first and third polysilicon gates, the conduction states of the transistors within the device can be coordinated, thereby forming a multi-stage current discharge mode. EOS stress is discharged through the gate-controlled bipolar transistor, and multi-path parallel discharge effectively protects the chip from EOS stress damage under harsh operating environments. The anode of this invention adopts a segmented P+ and N+ injection structure with a topological structure, which effectively improves the turn-off speed while saving chip area. Its equivalent circuit is shown below. Figure 4 and Figure 5 As shown. Specifically: When EOS stress is applied to the anode of the device, the cathode is grounded, and the potential of the third polysilicon gate 803 is higher than the threshold voltage, the NMOS2, composed of the fifth N+ injection region 505, the second P-Well region 401, the third polysilicon gate 803, and the sixth N+ injection region 506, is turned on. The fifth N+ injection region 505 serves as the source of the NMOS2, and the sixth N+ injection region 506 serves as the drain of the NMOS2. Under the action of the gate voltage, a vertically downward electric field is formed below the third polysilicon gate 803, forming an electron channel below the gate, constituting a discharge path in low-current mode. As the EOS stress applied to the anode increases, the fourth N+ injection region 504 and the first P-Well region 401 undergo avalanche breakdown, turning on the NPN transistor composed of the third N+ injection region 503, the fourth N+ injection region 504, and the first P-Well region 401. The base region of the NPN transistor is connected through the parasitic resistance R. P-Well It is connected to the second P+ injection region and the cathode is led out from the second P+ injection region 602. The second polysilicon gate 802 is used to shorten the base width of the parasitic NPN transistor, thereby improving the transistor's amplification factor and discharge efficiency. Since the discharge efficiency of NPN transistor is higher than that of NMOS2, parasitic NPN transistor forms a discharge path in medium current mode. In high current mode, when the potential of the first polysilicon gate 801 is higher than the threshold voltage, minority carriers in the substrate P-Sub region 101 and the first P-Well region 401 are attracted to move upward, forming an electron communication connection between the first DN-Well region 201 and the second N+ injection region 502 below the gate. Under the action of the anode voltage, electrons drift from the second N+ injection region 502 to the first DN-Well region 201 through the electron channel, turning on NMOS1, which is composed of the first N+ injection region 501, the first N-Well region 301, the first DN-Well region 201, the substrate P-Sub 101, the first P-Well region 401, the second N+ injection region 502, and the first polysilicon gate 801. The electronic current from NMOS1 further constitutes the base current of the parasitic PNP transistor, which consists of the first P+ injection region 601, the first N-Well region 301, the first DN-Well region 201, the substrate P-Sub region 101, the first P-Well region 401, and the second P+ injection region 602. Under the current gain of the parasitic PNP transistor, the channel current of NMOS1 is further amplified. The composite bipolar transistor composed of NMOS1 and PNP forms a current discharge path in high-current mode. This forms a synergistic enhancement gate transistor structure with multi-stage current discharge modes. By coordinating the conduction states of the internal transistors through the gate potential, efficient discharge of EOS stress is achieved, thereby effectively protecting the core circuit from the influence of complex external electromagnetic environments.

[0034] In summary, this invention provides a synergistic enhancement gate-controlled transistor with multi-stage current discharge modes and its fabrication method. Its structure is simple, requires no additional mask layers, and is compatible with standard CMOS processes. Through multi-stage current discharge modes and discharge paths, it can effectively protect the chip in complex operating environments.

Claims

1. A synergistic enhancement gate-controlled transistor structure with multi-stage current discharge modes, characterized in that: include: Substrate P-Sub; The substrate P-Sub region is provided with the following regions in sequence from bottom to top and from left to right: a first DN-Well region, a second DN-Well region, a first N-Well region, a first P-Well region, a second P-Well region, a first field oxygen isolation region, a first segmented topology N+ implantation region, a first segmented topology P+ implantation region, a second field oxygen isolation region, a first polysilicon gate, a second N+ implantation region, a second P+ implantation region, a third field oxygen isolation region, a third N+ implantation region, a second polysilicon gate, a fourth N+ implantation region, a fourth field oxygen isolation region, a fifth N+ implantation region, a third polysilicon gate, a sixth N+ implantation region, and a fifth field oxygen isolation region; The first segmented topology N+ implantation region and the first segmented topology P+ implantation region are located in the first N-Well region; the first polysilicon gate is located between the second field oxygen isolation region and the second N+ implantation region; the second N+ implantation region, the second P+ implantation region, the third N+ implantation region, the second polysilicon gate, and the fourth N+ implantation region are located in the first P-Well region; The fifth N+ implantation region, the third polysilicon gate, and the sixth N+ implantation region are located in the second P-Well region; The second N+ implantation region, the second P+ implantation region, the third N+ implantation region, the second polysilicon gate, and the fifth N+ implantation region are connected to serve as the cathode of the device; The first segmented topology N+ injection region, the first segmented topology P+ injection region, the fourth N+ injection region, and the sixth N+ injection region are connected as the anode of the device; The first polysilicon gate and the third polysilicon gate serve as the gate of the device.

2. The synergistic enhancement gate-controlled transistor structure with multi-stage current discharge modes according to claim 1, characterized in that: When EOS stress is applied to the anode of the device, the cathode is grounded, and the potential of the third polysilicon gate is higher than the threshold voltage, NMOS2, which is composed of the fifth N+ injection region, the second P-Well region, the third polysilicon gate, and the sixth N+ injection region, is turned on. The fifth N+ injection region serves as the source of NMOS2, and the sixth N+ injection region serves as the drain of NMOS2. Under the action of the gate voltage, a vertically downward electric field is formed below the third polysilicon gate, forming an electron channel below the gate, thus constituting a discharge path in low-current mode. As the EOS stress applied to the anode increases, avalanche breakdown occurs in the fourth N+ injection region and the first P-Well region, turning on the NPN transistor composed of the third N+ injection region, the fourth N+ injection region, and the first P-Well region. The base region of the NPN transistor is connected through the parasitic resistance R. P-Well It is connected to the second P+ injection region, and the cathode is led out from the second P+ injection region. The second polysilicon gate is used to shorten the base width of the parasitic NPN transistor, thereby improving the transistor's amplification factor and discharge efficiency. Since the discharge efficiency of the NPN transistor is higher than that of the NMOS2, the parasitic NPN transistor forms the current-mode discharge path. In high-current mode, when the potential of the first polysilicon gate is higher than the threshold voltage, minority carriers in the substrate P-Sub region and the first P-Well region are attracted to move upward, forming an electron communication connection between the first DN-Well region and the second N+ injection region below the gate. Under the action of the anode voltage, electrons drift from the second N+ injection region to the first DN-Well region through the electron channel, turning on the NMOS1 composed of the first N+ injection region, the first N-Well region, the first DN-Well region, the substrate P-Sub region, the first P-Well region, the second N+ injection region, and the first polysilicon gate. The electron current of NMOS1 further constitutes the base current of the parasitic PNP transistor composed of the first P+ injection region, the first N-Well region, the first DN-Well region, the substrate P-Sub region, the first P-Well region, and the second P+ injection region. Under the action of the parasitic PNP transistor current gain, the channel current of NMOS1 is further amplified. The composite bipolar transistor composed of NMOS1 and PNP forms the current discharge path in high-current mode. This results in a synergistic enhancement gate-controlled transistor structure with multi-level current discharge modes. By coordinating the conduction states of each internal transistor through the gate potential, efficient discharge of EOS stress is achieved, thereby effectively protecting the core circuit from the influence of complex external electromagnetic environments.

3. A method for fabricating a synergistic enhancement gate-controlled transistor structure with multi-stage current discharge modes based on any one of claims 1-2, comprising the following steps: Step 1: Form the first and second DN-Well regions in the P-Sub substrate; Step 2: Form the first to fifth field oxygen isolation regions on the P-Sub substrate using photolithography; Step 3: Form the first P-Well region and the second P-Well region in the P-Sub substrate by photolithography; Step 4: Form the first N-Well region in the first DN-Well region using photolithography; Step 5: By photolithography, a first polysilicon gate is formed above the second field oxygen isolation region, the first DN-Well region, the substrate P-Sub, and the first P-Well region; a second polysilicon gate is formed in the first P-Well region; and a third polysilicon gate is formed in the second P-Well region.

4. Step Six: Form the first segmented topology P+ injection region in the first N-Well region by photolithography, and form the second P+ injection region in the first P-Well region.

5. Step 7: Through photolithography, a first segmented N+ implantation region is formed in the first N-Well region, a second N+ implantation region, a third N+ implantation region and a fourth N+ implantation region are formed in the first P-Well region, and a fifth N+ implantation region and a sixth N+ implantation region are formed in the second P-Well region.

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