A compact, symmetrical, bidirectional electrostatic discharge protection device with strong latch-up resistance.

Abstract

This invention provides a compact, symmetrical, bidirectional electrostatic discharge (ESD) protection device with strong latch-up resistance. It includes a high-voltage deep N-well, a first P-well, a second P-well, a heavily doped P-type region, and a heavily doped N-type region. A first I / O port is located above the first P-well, and a second I / O port is located above the second P-well. The high-voltage deep N-well, the first P-well, and the heavily doped N-type region above the first P-well constitute a parasitic NPN bipolar junction transistor (BJT). The high-voltage deep N-well, the second P-well, and the heavily doped N-type region above the second P-well also constitute a parasitic NPN BJT. The first P-well, the second P-well, and the high-voltage deep N-well together form a bidirectional PNP BJT. The two parasitic NPN BJTs and the bidirectional PNP BJT together constitute a bidirectional silicon controlled rectifier (SCR). The beneficial effect of this invention is that it enables simultaneous improvement of both the sustaining voltage and sustaining current parameters of the bidirectional ESD protection device.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection devices, and specifically to a compact, symmetrical, bidirectional ESD protection device with strong anti-latch-up capability. Background Technology

[0002] Electrostatic discharge (ESD) protection devices are protective devices designed to prevent the burning out of various electrical components due to static electricity. A silicon controlled rectifier (SCR) is a relatively new type of ESD protection device. The most significant characteristic of an SCR is its extremely strong discharge capability, which allows it to provide a lower holding voltage (Vh) for the circuit.

[0003] Electrostatic discharge (ESD) protection devices provide electrostatic protection for circuits or chips. When a voltage surge or spike in the protected circuit exceeds the device's turn-on voltage, the device hysteresis and provides a low-impedance path for ESD (Electro-Static Discharge) current, thus protecting the circuit from damage caused by the voltage spike. Holding voltage (Vh) is a critical performance indicator for ESD protection devices; only by clamping high ESD voltages within a safe range can the device protect the circuit from damage. If the Vc of the ESD protection device exceeds the safe value for the protected circuit, the device may lose its protective function, leading to the risk of electronic circuit malfunction, failure, and damage.

[0004] Electronic circuit systems are highly susceptible to damage from transient energies such as Electrical Over Stress (EOS) and Electrostatic Discharge (ESD). Therefore, appropriate ESD protection devices must be designed to protect the corresponding ports. Furthermore, due to the different functions of the ports, port signals may exhibit both positive and negative voltages. For example, CAN interfaces, commonly used in automotive and industrial control applications, require devices with bidirectional ESD protection capabilities.

[0005] Among various bidirectional ESD protection devices currently available, the bidirectional silicon controlled rectifier (SCR) has become an important ESD protection device due to its bidirectional protection capability, strong discharge current capability, and high area utilization. For example... Figure 1 The diagram shown is a typical electrostatic discharge (ESD) protection scheme for bidirectional SCRs in the prior art.

[0006] However, due to the low sustaining voltage of traditional bidirectional SCRs, latch-up is prone to occur at higher operating voltages, leading to damage to ESD protection devices. Currently, the mainstream approach is to increase the sustaining voltage or sustaining current of the bidirectional SCR. Increasing the sustaining voltage directly raises it above the operating voltage of the protected circuit, fundamentally solving the latch-up problem. Increasing the sustaining current raises the hysteresis sustaining current of the bidirectional SCR, ensuring that after the large current discharge is complete, the current during normal operation of the protected circuit cannot reach the sustaining current required to keep the bidirectional SCR on, thus eliminating the latch-up effect. However, both existing optimization schemes can only optimize one electrical parameter at a time, with little or negligible impact on the other parameter, making it impossible to simultaneously improve both parameters, thus limiting the upper limit of the device's anti-latch-up performance optimization. Furthermore, to simultaneously optimize voltage and current parameters in existing improved bidirectional SCRs, additional independent resistors and transistors need to be added to the chip layout. The placement of discrete components significantly occupies the active area of ​​the chip, hindering miniaturization and increasing chip manufacturing costs. Therefore, this approach still cannot meet the needs of users. Summary of the Invention

[0007] To address the problems in existing technologies, this invention provides a compact, symmetrical, bidirectional electrostatic discharge (ESD) protection device with strong anti-latch-up capability. By applying a parasitic PNP bipolar junction transistor (BJT) formed by active region resistance coupling to the bidirectional ESD protection device, the device's holding voltage and holding current parameters can be simultaneously improved. This significantly enhances the overall anti-latch-up performance of the bidirectional ESD protection device, effectively suppressing latch-up conduction and false triggering lock-up phenomena that are prone to occur during device operation. It also significantly improves the device's operational stability, robustness, and reliability under complex high-voltage and high-current conditions. This solves the problems of existing bidirectional ESD protection devices, such as the inability to simultaneously improve holding voltage and holding current, poor anti-latch-up performance, and large layout area required for the improved design.

[0008] The present invention provides a compact symmetrical bidirectional electrostatic discharge protection device with strong latch-up resistance, comprising a semiconductor substrate and an N-type buried layer disposed on the semiconductor substrate. A high-voltage deep N-well is disposed on the upper side of the N-type buried layer. A first P-well and a second P-well are symmetrically disposed on the left and right sides of the high-voltage deep N-well. A first I / O port is disposed above the first P-well, and a second I / O port is disposed above the second P-well. An N-type heavily doped region is disposed above the high-voltage deep N-well. Two heavily doped P-type regions are provided above the first P-well, and an N-type heavily doped region is provided between the two heavily doped P-type regions. The first I / O port is connected to one of the heavily doped P-type regions and the N-type heavily doped region. The first I / O port is connected to the other heavily doped P-type region through an external P-type active region resistor. The first I / O port is connected to the N-type heavily doped region above the high-voltage deep N-well through an external P-type active region resistor. An isolation N-well is provided between the external P-type active region resistor between the first I / O port and the other heavily doped P-type region and the external P-type active region resistor between the first I / O port and the N-type heavily doped region above the high-voltage deep N-well. The two external P-type active region resistors are arranged in parallel and coupled to form multiple parasitic PNP bipolar junction transistors. Two heavily doped P-type regions are symmetrically arranged above the second P-well, and an N-type heavily doped region is also arranged between the two heavily doped P-type regions. The second I / O port is connected to one of the heavily doped P-type regions and the other heavily doped N-type region. The second I / O port is connected to the other heavily doped P-type region through an external P-type active region resistor. The second I / O port is connected to the heavily doped N-type region above the high-voltage deep N-well through an external P-type active region resistor. An isolation N-well is provided between the external P-type active region resistor between the second I / O port and the other heavily doped P-type region, and between the external P-type active region resistor between the second I / O port and the heavily doped N-type region above the high-voltage deep N-well. The two external P-type active region resistors are arranged in parallel and coupled to form multiple parasitic PNP bipolar junction transistors. The high-voltage deep N-well, the first P-well, and the heavily doped N-type region above the first P-well constitute a parasitic NPN bipolar junction transistor. The high-voltage deep N-well, the second P-well, and the heavily doped N-type region above the second P-well constitute a parasitic NPN bipolar junction transistor. The first P-well, the second P-well, and the high-voltage deep N-well constitute a bidirectional PNP bipolar junction transistor. The two parasitic NPN bipolar junction transistors and the bidirectional PNP bipolar junction transistor constitute a bidirectional thyristor rectifier.

[0009] In a further improvement, the present invention further includes a first diode disposed between the first I / O port and the external P-type active region resistor above the high-voltage deep N-well, the anode of the first diode being connected to the first I / O port; and a second diode disposed between the second I / O port and the external P-type active region resistor above the high-voltage deep N-well, the anode of the second diode being connected to the second I / O port.

[0010] In a further improvement to the present invention, the potential of the isolated N-well is connected to the potential of the heavily doped N-type region above the high-voltage deep N-well, or to the potential of an external independent peripheral circuit.

[0011] In a further improvement, the external P-type active region resistor is replaced with an external N-type active region resistor. An external N-type active region resistor is provided between the first I / O port and the heavily doped P-type region, and between the second I / O port and the heavily doped N-type region above the high-voltage deep N-well. A first isolation P-well is provided between the two external N-type active region resistors. The potential of the first isolation P-well is connected to the potential of the heavily doped P-type region above the first P-well, near the heavily doped N-type region above the high-voltage deep N-well, or to the potential of an external independent peripheral circuit. A second isolation P-well is provided between the external N-type active region resistors between the second I / O port and the heavily doped P-type region, and between the first I / O port and the heavily doped N-type region above the high-voltage deep N-well. The potential of the second isolation P-well is connected to the potential of the heavily doped P-type region above the second P-well, near the heavily doped N-type region above the high-voltage deep N-well, or to the potential of an external independent peripheral circuit.

[0012] The present invention is further improved in that the P-type heavily doped region above the first P-well, the first P-well, the high-voltage deep N-well, the second P-well, and the N-type heavily doped region above the second P-well cooperate to form the main forward ESD discharge path; the P-type heavily doped region above the second P-well, the second P-well, the high-voltage deep N-well, the first P-well, and the N-type heavily doped region above the first P-well cooperate to form the symmetrical main reverse ESD discharge path.

[0013] In a further improvement to the present invention, a grounded P-type heavily doped region protection ring is also provided outside the semiconductor substrate.

[0014] The present invention is further improved in that the manufacturing process of the compact symmetrical bidirectional electrostatic protection device includes nanoscale complementary metal-oxide-semiconductor process, three-dimensional fin field-effect transistor, all-around gate transistor process or silicon on insulating substrate process.

[0015] This invention is further improved in that the compact symmetrical bidirectional electrostatic discharge (ESD) protection device operates in four stages from cutoff to full conduction. In the first stage, neither the parasitic PNP bipolar junction transistor (PJT) nor the bidirectional thyristor rectifier is conducting. In the second stage, the PJT is triggered to conduct alone. In the third stage, the bidirectional thyristor rectifier is gradually turned on, and the current is transferred from the PJT to the thyristor rectifier. In the fourth stage, the thyristor rectifier is fully on, and the PJT is turned off. The maintenance current of the compact symmetrical bidirectional ESD protection device is distributed from cutoff to full conduction.

[0016] Compared with the prior art, the beneficial effects of the present invention are: it provides a compact symmetrical bidirectional electrostatic discharge (ESD) protection device with strong anti-latch-up capability based on a novel structure. By applying a parasitic PNP bipolar junction transistor (BJT) coupled with an active region resistor to the bidirectional ESD protection device, compared with the traditional bidirectional ESD protection device structure used to improve the holding current, the multiplexing of the PNP BJT transistor and resistor, and the presence of the heavily doped P-type regions 208 and 214 to achieve current shunting, can simultaneously improve the holding voltage and holding current parameters of the bidirectional ESD protection device, thus enhancing its voltage withstand capability and... By synergistically optimizing the two core dimensions of current carrying capacity threshold, the overall anti-latch-up performance of bidirectional electrostatic discharge (ESD) protection devices is significantly enhanced in all aspects. This effectively suppresses adverse phenomena such as latch-up conduction and false triggering during device operation, significantly improving the device's working stability, robustness, and operational reliability under complex high-voltage and high-current conditions. It also broadens the range of practical application conditions for the device. At the same time, the reuse and integration of components results in a more compact circuit structure, reduced chip area, and lower production costs. This solves the problems of existing bidirectional ESD protection devices, such as the inability to simultaneously increase holding voltage and holding current, poor anti-latch-up performance, and large layout area required by the improved solution. Attached Figure Description

[0017] To more clearly illustrate the solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a structural diagram of a typical electrostatic discharge (ESD) protection scheme for bidirectional SCRs in the prior art; Figure 2 This is a structural diagram of the compact, symmetrical, bidirectional electrostatic discharge protection device with strong anti-latch-up capability of the present invention; Figure 3This is a schematic diagram of the TLP curve of the compact symmetrical bidirectional electrostatic protection device with strong anti-latch capability of the present invention. Figure 4(a) is a schematic diagram of the process principle of the positive discharge of ESD events by the compact symmetrical bidirectional electrostatic protection device with strong anti-latch capability of the present invention. Figure 4(b) is a schematic diagram of the process principle of the positive discharge of ESD events by the compact symmetrical bidirectional electrostatic protection device with strong anti-latch capability of the present invention. Figure 4(c) is a schematic diagram of the process principle of the positive discharge of ESD events by the compact symmetrical bidirectional electrostatic protection device with strong anti-latch capability of the present invention. Figure 5(a) is a schematic diagram of the reverse discharge ESD event process of the compact symmetrical bidirectional electrostatic protection device with strong anti-latch capability of the present invention. Figure 5(b) is a schematic diagram of the reverse discharge ESD event process of the compact symmetrical bidirectional electrostatic protection device with strong anti-latch capability of the present invention. Figure 5(c) is a schematic diagram of the reverse discharge ESD event process of the compact symmetrical bidirectional electrostatic protection device with strong anti-latch capability of the present invention. Figure 6 This is a simulation TLP diagram of the compact symmetrical bidirectional electrostatic protection device with strong anti-latch-up capability according to the present invention. Detailed Implementation

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects and not to describe a particular order.

[0020] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0021] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0022] like Figure 1 As shown in Figure 100, this is a structural diagram of a conventional bidirectional PNP bipolar junction transistor (BJT). In this diagram, 101 represents the first I / O port, 102 represents the second I / O port, 103 represents the semiconductor substrate, 104 and 110 represent heavily P-type doped regions, 106 and 108 represent heavily N-type doped regions, 110, 112, and 114 represent high-voltage deep N-wells, 116 and 118 represent P-wells, and 120 represents an N-type buried layer. The heavily N-type doped region 106, the P-well 116, and the high-voltage deep N-well 114 constitute the emitter, base, and collector regions of a parasitic NPN BJT, respectively. Similarly, the heavily N-type doped region 108, the P-well 118, and the high-voltage deep N-well 114 constitute the emitter, base, and collector regions of a parasitic NPN BJT, respectively. P-well 116, P-well 118, and high-voltage deep N-well 114 constitute the emitter / collector region, emitter / collector region, and base region of the parasitic bidirectional PNP bipolar junction transistor, respectively.

[0023] like Figures 2-6As shown, the present invention provides a compact, symmetrical, bidirectional electrostatic discharge (ESD) protection device with strong latch-up resistance, comprising a semiconductor substrate and an N-type buried layer disposed on the semiconductor substrate. A high-voltage deep N-well is disposed on the upper side of the N-type buried layer. A first P-well and a second P-well are symmetrically arranged in the high-voltage deep N-well. A first I / O port is disposed above the first P-well, and a second I / O port is disposed above the second P-well. An N-type heavily doped region is disposed above the high-voltage deep N-well. Two P-type heavily doped regions are disposed above the first P-well, and an N-type heavily doped region is disposed between the two P-type heavily doped regions. The first I / O port is located between one of the P-type heavily doped regions and the N-type heavily doped region. The first I / O port is connected to another heavily doped P-type region via an external P-type active region resistor. The first I / O port is also connected to the heavily doped N-type region above the high-voltage deep N-well via an external P-type active region resistor. An isolation N-well is provided between the external P-type active region resistors between the first I / O port and the other heavily doped P-type region, and between the first I / O port and the heavily doped N-type region above the high-voltage deep N-well. These two external P-type active region resistors are arranged in parallel and coupled together to form multiple parasitic PNP bipolar junction transistors. Above the second P-well, there is also... The system symmetrically features two heavily P-type doped regions, with an N-type heavily doped region situated between them. A second I / O port is connected to one of the heavily P-type and N-type doped regions. The second I / O port is also connected to the other heavily P-type doped region via an external P-type active region resistor. Furthermore, the second I / O port is connected to the heavily N-type doped region above the high-voltage deep N-well via an external P-type active region resistor. Both the external P-type active region resistor between the second I / O port and the other heavily P-type doped region, and the external P-type active region resistor between the second I / O port and the heavily N-type doped region above the high-voltage deep N-well, are considered valid connections. An isolation N-well is provided between the two external P-type active region resistors, which are arranged in parallel and coupled to form multiple parasitic PNP bipolar junction transistors. The high-voltage deep N-well, the first P-well, and the heavily doped N-type region above the first P-well constitute a parasitic NPN bipolar junction transistor. The high-voltage deep N-well, the second P-well, and the heavily doped N-type region above the second P-well constitute a parasitic NPN bipolar junction transistor. The first P-well, the second P-well, and the high-voltage deep N-well constitute a bidirectional PNP bipolar junction transistor. The two parasitic NPN bipolar junction transistors and the bidirectional PNP bipolar junction transistor constitute a bidirectional thyristor rectifier.

[0024] like Figures 1-6As shown, a first diode is also provided between the external P-type active region resistor between the first I / O port and the heavily doped N-type region above the high-voltage deep N-well, with the anode of the first diode connected to the first I / O port; a second diode is also provided between the external P-type active region resistor between the second I / O port and the heavily doped N-type region above the high-voltage deep N-well, with the anode of the second diode connected to the second I / O port. The potential of the isolation N-well is connected to the potential of the heavily doped N-type region above the high-voltage deep N-well, or to the potential of an independent peripheral circuit. The heavily doped P-type region above the first P-well, the first P-well, the high-voltage deep N-well, the second P-well, and the heavily doped N-type region above the second P-well cooperate to form the main forward ESD discharge path; the heavily doped P-type region above the second P-well, the second P-well, the high-voltage deep N-well, the first P-well, and the heavily doped N-type region above the first P-well cooperate to form the symmetrical main reverse ESD discharge path. A grounded heavily doped P-type region protection ring is also provided outside the semiconductor substrate. The manufacturing processes for compact symmetrical bidirectional electrostatic discharge (ESD) protection devices include nanoscale complementary metal-oxide-semiconductor (CMOS) processes, three-dimensional fin field-effect transistors (FETs), all-around gate transistor (AGB) processes, or silicon-on-insulator (SCI) processes. The external P-type active region resistor is replaced with an external N-type active region resistor. An external N-type active region resistor is connected between the first I / O port and the heavily doped P-type region, and between the second I / O port and the heavily doped N-type region above the high-voltage deep N-well. A first isolation P-well is provided between the two external N-type active region resistors. The potential of the first isolation P-well is connected to the potential of the heavily doped P-type region above the first P-well, near the heavily doped N-type region above the high-voltage deep N-well, or to the potential of an external independent peripheral circuit. Similarly, an external N-type active region resistor is connected between the second I / O port and the heavily doped P-type region, and between the first I / O port and the heavily doped N-type region above the high-voltage deep N-well. A second isolation P-well is provided between the two external N-type active region resistors. The potential of the second isolation P-well is connected to the potential of the heavily doped P-type region above the second P-well, near the heavily doped N-type region above the high-voltage deep N-well, or to the potential of an external independent peripheral circuit. The compact symmetrical bidirectional electrostatic discharge (ESD) protection device operates in four phases from cutoff to full conduction. In the first phase, neither the parasitic PNP bipolar junction transistor (PJT) nor the bidirectional thyristor rectifier is conducting. In the second phase, the PJT is triggered to conduct independently. In the third phase, the bidirectional thyristor rectifier gradually turns on, and the current transfers from the PJT to the thyristor. In the fourth phase, the thyristor rectifier is fully conducting, and the PJT is turned off. The maintenance current of the compact symmetrical bidirectional ESD protection device is distributed from cutoff to full conduction.

[0025] like Figure 2As shown in this embodiment, 200 is a structural diagram of this patent embodiment, 201 represents the first I / O port, 202 represents the second I / O port, 203 represents the semiconductor substrate, 204, 208, 210 and 214 represent P-type heavily doped regions, 206, 209 and 212 represent N-type heavily doped regions, 216, 217 and 218 represent high-voltage deep N-wells, 220 is the first P-well, 221 represents the second P-well, 222 represents the N-type buried layer, 224, 226, 228 and 230 represent external P-type active region resistors, 232 represents the first diode, 234 represents the second diode, 227 represents the junction between the two diodes 232 and the external P-type active region resistor 228, 231 represents the junction between the second diode 234 and the external P-type active region resistor 230, and 229 represents the junction between the external P-type active region resistors 228 and 230. In this configuration, the heavily doped N-type region 206, the first P-well 220, and the high-voltage deep N-well 218 constitute the emitter, base, and collector regions of the parasitic NPN bipolar junction transistor, respectively. The heavily doped N-type region 212, the second P-well 221, and the high-voltage deep N-well 218 also constitute the emitter, base, and collector regions of the parasitic NPN bipolar junction transistor. The first P-well 220, the second P-well 221, and the high-voltage deep N-well 218 constitute the emitter, collector, and base regions of the parasitic bidirectional PNP bipolar junction transistor, respectively. The strip-shaped active region formed by the external P-type active region resistors 226 and 228 can be considered as numerous small resistors connected in series, separated by an isolation N-well. Each segment of the parallel small resistor forms a parasitic PNP bipolar junction transistor at both ends. The strip-shaped active region formed by the external P-type active region resistors 224 and 230 can be considered as a series of numerous small resistors connected in series, separated by an isolation N-well. Each segment of the parallel small resistor forms a parasitic PNP bipolar junction transistor at its two ends. The high-voltage deep N-well can be configured with various connection potentials, including but not limited to the junction 229 between the external P-type active region resistors 228 and 230 and the external circuitry.

[0026] like Figure 3 As shown, the compact symmetrical bidirectional electrostatic protection device in this invention patent goes through four stages from turn-off to trigger.

[0027] During the first operating phase, the voltage across the compact symmetrical bidirectional electrostatic discharge (ESD) device is insufficient to trigger either the parasitic PNP bipolar junction transistor or the bidirectional thyristor rectifier, and the device remains off.

[0028] In the second operating phase, the voltage has reached the trigger voltage of the parasitic PNP bipolar junction transistor. At this time, the parasitic PNP bipolar junction transistor has been triggered, but the current injected from the P-type heavily doped region 214 cannot establish a sufficient forward conduction voltage on the PN junction formed by the second P-well 221 and the N-type heavily doped region 212, and can only flow out from the P-type heavily doped region 210.

[0029] In the third operating phase, the bidirectional thyristor rectifier gradually turns on. At the same time, since the holding voltage of the bidirectional thyristor rectifier is lower than the trigger voltage of the parasitic PNP bipolar junction transistor, the current that should have flowed through the parasitic PNP bipolar junction transistor gradually shifts to the current discharge path of the bidirectional thyristor rectifier until the parasitic PNP bipolar junction transistor turns off.

[0030] In the fourth operating phase, all current is discharged by the bidirectional thyristor rectifier, and the current rises rapidly with increasing voltage. At this time, the parasitic PNP bipolar junction transistor (PNT) turns off. Essentially, the presence of the parasitic PNP PNT delays the turn-on of the bidirectional thyristor rectifier. Once the bidirectional thyristor rectifier turns on, it can draw all the current from the parasitic PNP PNT, thus indirectly increasing the holding current of the bidirectional thyristor rectifier. Simultaneously, the presence of the heavily doped P-type regions 208 and 214 acts as a current shunt, further increasing the holding voltage.

[0031] Figures 4(a)-4(c) illustrate the process of a forward-discharge ESD event in this embodiment. Figure 4(a) shows the scenario where the parasitic PNP bipolar junction transistor is turned on but the bidirectional silicon controlled rectifier is not turned on, corresponding to... Figure 3The second working stage. As shown in Figure 4(b), in the early stage of an ESD event, the parasitic PNP bipolar junction transistor turns on, and part of the current flows from the heavily doped P-type region 214 into the bidirectional thyristor rectifier. At this time, the current is sufficient to form a sufficient forward conduction voltage between the PN junction formed by the second P-well 221 and the heavily doped N-type region 212, and the PN junction turns on. The current flowing in from the heavily doped P-type region 214 can quickly establish positive feedback inside the bidirectional thyristor rectifier, realizing the rapid triggering of the bidirectional thyristor rectifier. After the bidirectional thyristor rectifier is triggered, it quickly seizes the current from the parasitic PNP bipolar junction transistor, transitioning to Figure 4(c). Ultimately, the parasitic PNP bipolar junction transistor is turned off, and only the bidirectional thyristor rectifier discharges the large current. Simultaneously, the function of the heavily doped P-type region 214, originally used for injecting trigger current, changes from a trigger tap function to a second collector region function. This is achieved by the heavily doped P-type region 214, the high-voltage deep N-well 218, and the first P-well 220. The parasitic PNP bipolar junction transistor that forms turns on runs parallel to the current discharge path formed by the main parasitic PNP bipolar junction transistor formed by the second P-well 221, the high-voltage deep N-well 218, and the first P-well 220. This creates competition, diverting some current and making it more difficult for the voltage between the PN junction formed by the second P-well 221 and the heavily doped N-type region 212 to reach the forward conduction voltage. This results in a higher voltage being required across the bidirectional thyristor rectifier to maintain conduction, thus increasing the sustaining voltage. This corresponds to... Figure 3 The fourth phase of the work.

[0032] Figures 5(a)-5(c) illustrate the process of a reverse-discharge ESD event in this embodiment, which is similar in principle to a forward-discharge ESD event. Figure 5(a) shows the scenario where the parasitic PNP bipolar junction transistor is turned on but the bidirectional thyristor rectifier is not turned on, corresponding to... Figure 3The second working stage. As shown in Figure 5(b), in the early stage of an ESD event, the parasitic PNP bipolar junction transistor turns on, and part of the current flows from the heavily doped P-type region 208 into the bidirectional thyristor rectifier. At this time, the current is sufficient to form a sufficient forward conduction voltage between the PN junction formed by the first P-well 220 and the heavily doped N-type region 206, and the PN junction turns on. The current flowing in from the heavily doped P-type region 208 can quickly establish positive feedback inside the bidirectional thyristor rectifier, realizing the rapid triggering of the bidirectional thyristor rectifier. After the triac rectifier is triggered, it quickly takes over the current from the parasitic PNP bipolar junction transistor, transitioning to Figure 5(c). Ultimately, the parasitic PNP bipolar junction transistor is turned off, and only the triac rectifier discharges the large current. At the same time, the function of the P-type heavily doped region 208, which was originally used to inject the trigger current, changes from the original trigger tap function to the second collector region function. The parasitic PNP bipolar junction transistor formed by the P-type heavily doped region 208, the high-voltage deep N-well 218, and the second P-well 221 turns on, running parallel to the current discharge channel formed by the main parasitic PNP bipolar junction transistor formed by the first P-well 220, the high-voltage deep N-well 218, and the second P-well 221. This creates competition and diverts some current, making it more difficult for the voltage between the PN junction formed by the first P-well 220 and the N-type heavily doped region 206 to reach the forward conduction voltage. This requires a higher voltage across the triac rectifier to maintain conduction, thereby increasing the holding voltage. This corresponds to Figure 3 The fourth phase of the work.

[0033] like Figure 6 The image shown is the simulated TLP image. It can be seen that the forward and reverse directions are basically symmetrical. Furthermore, the sustaining voltage of the novel high sustaining voltage and current bidirectional electrostatic discharge (ESD) protection device of this invention is 28.7V, while the sustaining voltage of the conventional bidirectional ESD protection device under the same conditions is 21.2V. The sustaining voltage of the new structure is increased by 7.5V, a significant improvement. Simultaneously, the sustaining current of the novel high sustaining voltage and current bidirectional ESD protection device of this invention is 0.79A, while the sustaining current of the conventional bidirectional ESD protection device under the same conditions is 0.66A. The sustaining current of the new structure is increased by 0.13A, again a significant improvement.

[0034] As can be seen from the above, this invention provides a compact, symmetrical, bidirectional electrostatic discharge (ESD) protection device with strong anti-latch-up capability based on a novel structure. By applying a parasitic PNP bipolar junction transistor (BJT) coupled with an active region resistor to the bidirectional ESD protection device, compared to traditional bidirectional ESD protection device structures used to improve holding current, the reuse of the PNP BJT transistor and resistor, along with the presence of the heavily doped P-type regions 208 and 214 which act as current shunting points, enables the simultaneous improvement of both holding voltage and holding current parameters of the bidirectional ESD protection device, thus enhancing both voltage withstand capability and current carrying capacity. By optimizing two core dimensions in a coordinated manner, the overall anti-latch-up performance of bidirectional electrostatic discharge (ESD) protection devices is significantly enhanced in all aspects. This effectively suppresses adverse phenomena such as latch-up conduction and false triggering during device operation, significantly improving the device's working stability, robustness, and operational reliability under complex conditions of high voltage and high current. It also broadens the range of practical application conditions for the device. At the same time, the reuse and integration of components results in a more compact circuit structure, reduced chip area, and lower production costs. This solves the problems of existing bidirectional ESD protection devices, such as the inability to simultaneously increase the holding voltage and holding current, poor anti-latch-up performance, and large layout area required by the improved solution.

[0035] The specific embodiments described above are preferred embodiments of the present invention and are not intended to limit the specific scope of the present invention. The scope of the present invention includes, but is not limited to, these specific embodiments. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. A compact, symmetrical, bidirectional electrostatic discharge protection device with strong anti-latch-up capability, characterized in that: The device includes a semiconductor substrate and an N-type buried layer disposed on the semiconductor substrate. A high-voltage deep N-well is disposed on the upper side of the N-type buried layer. A first P-well and a second P-well are symmetrically disposed on the left and right sides of the high-voltage deep N-well. A first I / O port is disposed above the first P-well, and a second I / O port is disposed above the second P-well. An N-type heavily doped region is disposed above the high-voltage deep N-well. Two heavily doped P-type regions are provided above the first P-well, and an N-type heavily doped region is provided between the two heavily doped P-type regions. The first I / O port is connected to one of the heavily doped P-type regions and the N-type heavily doped region. The first I / O port is connected to the other heavily doped P-type region through an external P-type active region resistor. The first I / O port is connected to the N-type heavily doped region above the high-voltage deep N-well through an external P-type active region resistor. An isolation N-well is provided between the external P-type active region resistor between the first I / O port and the other heavily doped P-type region and the external P-type active region resistor between the first I / O port and the N-type heavily doped region above the high-voltage deep N-well. The two external P-type active region resistors are arranged in parallel and coupled to form multiple parasitic PNP bipolar junction transistors. Two heavily doped P-type regions are symmetrically arranged above the second P-well, and an N-type heavily doped region is also arranged between the two heavily doped P-type regions. The second I / O port is connected to one of the heavily doped P-type regions and the other heavily doped N-type region. The second I / O port is connected to the other heavily doped P-type region through an external P-type active region resistor. The second I / O port is connected to the heavily doped N-type region above the high-voltage deep N-well through an external P-type active region resistor. An isolation N-well is provided between the external P-type active region resistor between the second I / O port and the other heavily doped P-type region, and between the external P-type active region resistor between the second I / O port and the heavily doped N-type region above the high-voltage deep N-well. The two external P-type active region resistors are arranged in parallel and coupled to form multiple parasitic PNP bipolar junction transistors. The high-voltage deep N-well, the first P-well, and the heavily doped N-type region above the first P-well constitute a parasitic NPN bipolar junction transistor. The high-voltage deep N-well, the second P-well, and the heavily doped N-type region above the second P-well constitute a parasitic NPN bipolar junction transistor. The first P-well, the second P-well, and the high-voltage deep N-well constitute a bidirectional PNP bipolar junction transistor. The two parasitic NPN bipolar junction transistors and the bidirectional PNP bipolar junction transistor constitute a bidirectional thyristor rectifier.

2. The compact symmetrical bidirectional electrostatic discharge protection device with strong anti-latch-up capability according to claim 1, characterized in that: A first diode is provided between the first I / O port and the external P-type active region resistor above the high-voltage deep N-well, and the anode of the first diode is connected to the first I / O port; a second diode is provided between the second I / O port and the external P-type active region resistor above the high-voltage deep N-well, and the anode of the second diode is connected to the second I / O port.

3. The compact symmetrical bidirectional electrostatic discharge protection device with strong anti-latch-up capability according to claim 2, characterized in that: The potential of the isolated N-well is connected to the potential of the heavily doped N-type region above the high-voltage deep N-well, or to the potential of an external independent peripheral circuit.

4. The compact symmetrical bidirectional electrostatic discharge protection device with strong anti-latch-up capability according to claim 3, characterized in that: The external P-type active region resistor is replaced with an external N-type active region resistor. The external N-type active region resistor between the first I / O port and the heavily doped P-type region, and the external N-type active region resistor between the second I / O port and the heavily doped N-type region above the high-voltage deep N-well, are provided with a first isolation P-well between the two external N-type active region resistors. The potential of the first isolation P-well is connected to the potential of the heavily doped P-type region above the first P-well that is close to the heavily doped N-type region above the high-voltage deep N-well, or to the potential of an external independent peripheral circuit. An external N-type active region resistor is provided between the second I / O port and the P-type heavily doped region, and an external N-type active region resistor is provided between the first I / O port and the N-type heavily doped region above the high-voltage deep N-well. A second isolation P-well is provided between the two external N-type active region resistors. The potential of the second isolation P-well is connected to the potential of the P-type heavily doped region above the second P-well and close to the N-type heavily doped region above the high-voltage deep N-well, or to the potential of an external independent peripheral circuit.

5. The compact symmetrical bidirectional electrostatic discharge protection device with strong anti-latch-up capability according to claim 3, characterized in that: The P-type heavily doped region above the first P-well, the first P-well, the high-voltage deep N-well, the second P-well, and the N-type heavily doped region above the second P-well cooperate to form the main forward ESD discharge path. The heavily doped P-type region above the second P-well, the second P-well, the high-voltage deep N-well, the first P-well, and the heavily doped N-type region above the first P-well work together to form a symmetrical main reverse ESD discharge path.

6. The compact symmetrical bidirectional electrostatic discharge protection device with strong anti-latch-up capability according to claim 5, characterized in that: The semiconductor substrate is also provided with a grounded P-type heavily doped region protection ring.

7. The compact symmetrical bidirectional electrostatic discharge protection device with strong anti-latch-up capability according to claim 6, characterized in that: The manufacturing processes for compact symmetrical bidirectional electrostatic discharge (ESD) protection devices include nanoscale complementary metal-oxide-semiconductor (CMOS) processes, three-dimensional fin field-effect transistors (FETs), all-around gate transistor (AGB) processes, or silicon-on-insulator (SCI) processes.

8. The compact symmetrical bidirectional electrostatic discharge protection device with strong anti-latch-up capability according to claim 7, characterized in that: The compact symmetrical bidirectional electrostatic discharge (ESD) protection device operates in four phases from cutoff to full conduction. In the first phase, neither the parasitic PNP bipolar junction transistor (PJT) nor the bidirectional thyristor rectifier is conducting. In the second phase, the PJT is triggered to conduct independently. In the third phase, the bidirectional thyristor rectifier gradually turns on, and the current transfers from the PJT to the thyristor. In the fourth phase, the thyristor rectifier is fully conducting, and the PJT is turned off. The maintenance current of the compact symmetrical bidirectional ESD protection device is distributed from cutoff to full conduction.

Images