A back-contact heterojunction solar cell and its fabrication method

Abstract

This invention discloses a back-contact heterojunction solar cell and its fabrication method. The back-contact heterojunction solar cell may include: a crystalline silicon substrate, with alternating first and second conductive regions on its back side; a carrier collection layer comprising contact and non-contact regions disposed in the first conductive region; a first doped silicon-containing film layer disposed outside the contact region with a doping type opposite to that of the carrier collection layer; a second intrinsic silicon-containing film layer and a second doped silicon-containing film layer sequentially stacked from the inside to the outside in the second conductive region, the second doped silicon-containing film layer having the same doping type as the first doped silicon-containing film layer; a transparent conductive film layer disposed outside the first and second doped silicon-containing film layers and disconnected between the first and second conductive regions; and a first electrode electrically connected to the transparent conductive film layer located outside the first doped silicon-containing film layer. This back-contact heterojunction solar cell can effectively improve the fill factor and short-circuit current.

Description

Technical Field

[0001] This invention relates to a back-contact heterojunction solar cell and its fabrication method. Background Technology

[0002] A back-contact heterojunction solar cell (HBC) is a high-efficiency crystalline silicon solar cell that combines heterojunction technology with a back-contact structure. By eliminating light shading from the front electrode and improving passivation, it achieves higher photoelectric conversion efficiency. The back side of a HBC solar cell can have a tunneling passivation layer and a doped polycrystalline silicon layer; however, the doped polycrystalline silicon layer introduces parasitic absorption problems.

[0003] Currently, parasitic absorption can be reduced by thinning the doped polycrystalline silicon layer. However, thinning the doped polycrystalline silicon layer can easily increase the lateral transport resistance and contact resistance, which is not conducive to improving the fill factor and short-circuit current of back-contact heterojunction solar cells. Summary of the Invention

[0004] In view of this, the present invention provides a back-contact heterojunction solar cell and a method for fabricating the same. In this back-contact heterojunction solar cell, the thickness of the non-contact region of the current collection layer is smaller than the thickness of the contact region. In combination with the first doped silicon-containing film layer disposed in the contact region, parasitic absorption can be reduced. Compared with the reduction in carrier transport efficiency caused by directly placing a transparent conductive film layer on the thinned carrier collection layer, the composite junction conductive channel formed by the current collection layer and the first doped silicon-containing film layer disposed in the contact region can ensure the collection and transport of carriers in the first conductive region, thereby improving the fill factor and short-circuit current of the solar cell.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a back-contact heterojunction solar cell, comprising: A crystalline silicon substrate, the back side of which includes alternating first and second conductive regions; A carrier collection layer is disposed in the first conductive region; the carrier collection layer includes a contact region and a non-contact region, wherein the thickness of the non-contact region is less than the thickness of the contact region; A first doped silicon-containing film layer is disposed on the outside of the contact region, and the doping type of the first doped silicon-containing film layer is opposite to that of the carrier collection layer. The second intrinsic silicon-containing film layer and the second doped silicon-containing film layer are sequentially stacked from the inside to the outside in the second conductive region, and the second doped silicon-containing film layer has the same doping type as the first doped silicon-containing film layer. A transparent conductive film layer is disposed outside the first doped silicon-containing film layer and the second doped silicon-containing film layer, and is disconnected between the first conductive region and the second conductive region; The first electrode is electrically connected to a transparent conductive film layer located outside the first doped silicon-containing film layer.

[0006] Secondly, embodiments of the present invention provide a method for fabricating a back-contact heterojunction solar cell, comprising: Step S201: Provide a crystalline silicon substrate, the back side of which includes alternating first and second conductive regions; Step S202: A carrier collection layer is formed in the first conductive region, the carrier collection layer including a contact region and a non-contact region, the thickness of the non-contact region being less than the thickness of the contact region; a second intrinsic silicon-containing film layer and a second doped silicon-containing film layer are formed in the second conductive region; a first doped silicon-containing film layer is formed outside the contact region, the doping type of the first doped silicon-containing film layer being opposite to the doping type of the carrier collection layer and the same as the doping type of the second doped silicon-containing film layer. Step S203: A transparent conductive film layer is formed on the outside of the first doped silicon-containing film layer and the second doped silicon-containing film layer, and the transparent conductive film layer is disconnected between the first conductive region and the second conductive region. Step S204: Form a first electrode on a transparent conductive film layer located outside the first doped silicon-containing film layer.

[0007] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: by making the thickness of the non-contact region of the charge carrier collection layer smaller than the thickness of the contact region, and in conjunction with the first doped silicon-containing film layer disposed in the contact region, parasitic absorption can be reduced. Compared with the reduction in charge carrier transport efficiency caused by directly disposing a transparent conductive film layer on the thinned charge carrier collection layer, the composite junction conductive channel formed by the charge carrier collection layer and the first doped silicon-containing film layer disposed in the contact region can ensure the collection and transport of charge carriers in the first conductive region, thereby improving the fill factor and short-circuit current of the solar cell.

[0008] In addition, the second doped silicon-containing film layer disposed in the second conductive region has the same doping type as the first doped silicon-containing film layer disposed in the contact region of the first conductive region. This allows the work function of the transparent conductive film layer to match both the second doped silicon-containing film layer and the first doped silicon-containing film layer simultaneously, ensuring that the transparent conductive film layer can achieve better contact with both the first doped silicon-containing film layer and the second doped silicon-containing film layer, thereby further improving the short-circuit current of the solar cell. Attached Figure Description

[0009] Figure 1 This is a partial cross-sectional structural diagram of a back-contact heterojunction solar cell provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the main process of a method for fabricating a back-contact heterojunction solar cell according to an embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of the structural changes corresponding to each step in the preparation method according to an embodiment of the present invention; Figure 4 This is a schematic cross-sectional view of the partial structural changes corresponding to step S202 in the preparation method according to an embodiment of the present invention; Figure 5 This is a schematic cross-sectional view of the partial structural changes of the solar cell corresponding to steps S203 to S205 based on the structure obtained in step S2024 according to the preparation method of the present invention.

[0010] The attached figures are labeled as follows: 10-Crystal silicon substrate; 11-First conductive region; 12-Second conductive region; 13-Electrically isolated region; 131-First isolation region; 132-Second isolation region; 133-Third intrinsic silicon-containing film layer; 134-Third doped silicon-containing film layer; 20-Carrier collection layer; 21-Contact region; 22-Non-contact region; 23-Tunneling passivation layer; 24-Doped polycrystalline silicon layer; 20'-Mask layer; 30-First doped silicon-containing film layer; 41-Second intrinsic silicon-containing film layer; 41'-Initial intrinsic silicon-containing film layer; 42-Second doped silicon-containing film layer; 42'-Initial doped silicon-containing film layer; 40'-First protective layer; 40''-Second protective layer; 40'''-Third protective layer; 50-Transparent conductive film layer; 61-First electrode; 62-Second electrode; 70-Front-side passivation and anti-reflection layer; 71-Front-side passivation layer; 72-Front-side anti-reflection layer. Detailed Implementation

[0011] The back-contact heterojunction solar cell involved in the embodiments of the present invention refers to a crystalline silicon solar cell obtained by combining a passivated contact structure with heterojunction technology.

[0012] Existing back-contact heterojunction solar cells typically feature a passivation contact structure (comprising a stacked tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer) in the n-type conductive region of a crystalline silicon substrate. A film layer in the p-type conductive region forms a heterojunction with the crystalline silicon substrate. Specifically, this film layer typically includes an intrinsic amorphous silicon layer and a p-type doped amorphous silicon layer (typically an intrinsic boron-doped amorphous silicon layer) stacked from the inside out. Because the intrinsic amorphous silicon layer and the boron-doped amorphous silicon layer have relatively poor lateral conductivity, back-contact heterojunction solar cells generally feature a transparent conductive film layer on top of the boron-doped amorphous silicon layer and the phosphorus-doped polycrystalline silicon layer, and a metal electrode is placed on the transparent conductive film layer to transport charge carriers. Compared to using high-temperature sintered printed metal paste to set metal electrodes for solar cells, although the transparent conductive film layer, when combined with the metal electrode, can avoid sintering damage to the back-contact heterojunction solar cell, there are still some drawbacks. First, the phosphorus-doped polycrystalline silicon layer exhibits significant parasitic absorption, as described in the background section. Thinning the phosphorus-doped polycrystalline silicon layer can lead to severe lateral transport resistance, which is detrimental to carrier transport. Second, the contact resistance between the transparent conductive film layer and the phosphorus-doped polycrystalline silicon layer is relatively high. In particular, the contact resistance between the thinned phosphorus-doped polycrystalline silicon layer and the transparent conductive film layer will increase further. All of these factors are detrimental to improving the fill factor and short-circuit current of the back-contact heterojunction solar cell.

[0013] To address the aforementioned problems with existing back-contact heterojunction solar cells and their existing fabrication processes, this invention provides a novel back-contact heterojunction solar cell structure and a new fabrication method for the novel back-contact heterojunction solar cell structure.

[0014] It should be noted that the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0015] In the embodiments of the present invention, the back side of the crystalline silicon substrate 10 generally refers to the main surface of the crystalline silicon substrate 10 that faces away from sunlight during the operation of the solar cell. The front side of the crystalline silicon substrate 10 generally refers to the main surface of the crystalline silicon substrate 10 that faces sunlight during the operation of the solar cell.

[0016] In the embodiments of this invention, "from the inside out" generally refers to the crystalline silicon substrate 10 as a reference, and the direction from the position closest to the crystalline silicon substrate 10 to the position furthest away from the crystalline silicon substrate 10 is "from the inside out". Correspondingly, the inner and outer sides of a film layer are also based on the crystalline silicon substrate 10. The side of the film layer closest to the crystalline silicon substrate 10 is the inner side of the film layer, and the side of the film layer furthest from the crystalline silicon substrate 10 is the outer side of the film layer.

[0017] In the embodiments of the present invention, one film layer is located on another film layer. This film layer may be located on the side of the other film layer away from the crystalline silicon substrate 10. In the absence of other conflicting descriptions, the one film layer and the other film layer may be in direct contact, and other film layers may also be included between the one film layer and the other film layer.

[0018] The contact area 21 and non-contact area 22 of the first doped silicon-containing film layer 30 involved in the embodiments of the present invention are generally defined based on the first doped silicon-containing film layer 30 and the first electrode 61. That is, the area of ​​the first doped silicon-containing film layer 30 where the first doped silicon-containing film layer 30 and the first electrode 61 are provided is the contact area 21, while the area of ​​the first doped silicon-containing film layer 30 where the first doped silicon-containing film layer 30 and the first electrode 61 are not provided is the non-contact area 22.

[0019] In the embodiments of this invention, an n-type doped film generally means that the film is doped with n-type doped atoms such as phosphorus atoms or arsenic atoms, and a p-type doped film generally means that the film is doped with p-type doped atoms such as boron atoms or gallium atoms.

[0020] The doping concentration of a film layer in the embodiments of the present invention generally refers to the average number of activated doped atoms contained in a unit volume of the film layer.

[0021] The degree of crystallinity of a film layer in the embodiments of the present invention generally refers to the percentage of the volume of the crystalline phase contained in the film layer to the total volume of the film layer. Furthermore, in the film layer containing the crystalline phase in the embodiments of the present invention, the crystalline phase is generally uniformly distributed within the film layer.

[0022] Specifically, embodiments of the present invention provide a novel back-contact heterojunction solar cell structure. More specifically, as... Figure 1 As shown, the back-contact heterojunction solar cell may include: a crystalline silicon substrate 10, a carrier collection layer 20 including a contact region 21 and a non-contact region 22, a first doped silicon-containing film layer 30, a second intrinsic silicon-containing film layer 41, a second doped silicon-containing film layer 42, a transparent conductive film layer 50, and a first electrode 61, wherein, The back side of the crystalline silicon substrate 10 includes alternating first conductive regions 11 and second conductive regions 12; The carrier collection layer 20 is disposed in the first conductive region 11; the thickness of the non-contact region 22 included in the carrier collection layer is less than the thickness of the contact region 21 included in the carrier collection layer; The first doped silicon-containing film layer 30 is disposed on the outside of the contact region 21, and the doping type of the first doped silicon-containing film layer 30 is opposite to that of the carrier collection layer 20. The second intrinsic silicon-containing film layer 41 and the second doped silicon-containing film layer 42 are sequentially stacked from the inside to the outside in the second conductive region 12. The second doped silicon-containing film layer 42 has the same doping type as the first doped silicon-containing film layer 30. A transparent conductive film layer 50 is disposed outside the first doped silicon-containing film layer 30 and outside the second doped silicon-containing film layer 42, and is disconnected between the first conductive region 11 and the second conductive region 12. The first electrode 61 is electrically connected to the transparent conductive film layer 50 located outside the first doped silicon-containing film layer 30.

[0023] In this structure, the crystalline silicon substrate 10 and the carrier collection layer 20 generally have the same doping type. For example, both the crystalline silicon substrate 10 and the carrier collection layer 20 are either n-type or p-type doped. Correspondingly, when both the crystalline silicon substrate 10 and the carrier collection layer 20 are n-type doped, the first doped silicon-containing film layer 30 and the second doped silicon-containing film layer 42 are p-type doped; when both the crystalline silicon substrate 10 and the carrier collection layer 20 are p-type doped, the first doped silicon-containing film layer 30 and the second doped silicon-containing film layer 42 are n-type doped. This ensures that the crystalline silicon substrate 10, the carrier collection layer, and the second doped silicon-containing film layer 42 work together to form the basic structure of a back-contact heterojunction solar cell. The crystalline silicon substrate 10 and the second doped silicon-containing film layer 42 constitute a PN junction. In a preferred embodiment, the crystalline silicon substrate 10 and the carrier collection layer 20 are n-type doped, and the first doped silicon-containing film layer 30 and the second doped silicon-containing film layer 42 are p-type doped. Compared with the p-type doped crystalline silicon substrate 10, the n-type doped crystalline silicon substrate 10 can effectively extend the minority carrier lifetime and avoid boron-oxygen defects and light-induced degradation in the crystalline silicon substrate 10. In addition, the defects caused by doped atoms in the n-type crystalline silicon substrate 10 are lower, and the bulk lifetime is more stable. Therefore, choosing the n-type crystalline silicon substrate 10 can effectively improve the efficiency of the back contact heterojunction solar cell.

[0024] Compared to existing back-contact heterojunction solar cells, Figure 1The back-contact heterojunction solar cell provided in the embodiment of the present invention is a novel back-contact heterojunction solar cell. It achieves a back-contact heterojunction structure by cooperating with a crystalline silicon substrate 10, a carrier collection layer 20 disposed in the first conductive region 11, a first doped silicon-containing film layer 30, and a second doped silicon-containing film layer 42 disposed in the second conductive region 12. Furthermore, the thickness of the non-contact region 22 of the first conductive region 11 is less than the thickness of the contact region 21 by the carrier collection layer 20, which can effectively reduce the parasitic absorption of the non-contact region 22. In addition, compared with the reduction of carrier transport efficiency caused by directly disposing of a transparent conductive film layer 50 on the thinned carrier collection layer, the composite junction conductive channel formed by the carrier collection layer and the first doped silicon-containing film layer 30 disposed in the contact region can form a conductive channel between the first doped silicon-containing film layer 30 and the carrier collection layer 20, which can ensure the collection and transport of carriers in the first conductive region, thereby improving the fill factor and short-circuit current of the solar cell.

[0025] In addition, the second doped silicon-containing film layer disposed in the second conductive region has the same doping type as the first doped silicon-containing film layer disposed in the contact region of the first conductive region. This allows the work function of the transparent conductive film layer to match both the second doped silicon-containing film layer and the first doped silicon-containing film layer simultaneously, ensuring that the transparent conductive film layer can achieve better contact with both the first doped silicon-containing film layer and the second doped silicon-containing film layer, thereby further improving the short-circuit current of the solar cell.

[0026] In addition, compared with different transparent conductive film layers in different conductive regions, the solar cell provided in this embodiment of the invention can provide the same transparent conductive film layer 60 in the first conductive region 11 and the second conductive region 12, and can ensure that the first doped silicon-containing film layer 30 in the first conductive region 11 and the second doped silicon-containing film layer 42 in the second conductive region 12 simultaneously form a better contact with the transparent conductive film layer 60, so that the solar cell provided in this embodiment of the invention has a simple structure and is easy to industrialize.

[0027] The following sections will describe each film layer or structure included in a back-contact heterojunction solar cell.

[0028] In one embodiment of the present invention, the height difference between the back surface of the crystalline silicon substrate 10 corresponding to the first conductive region 11 and the back surface of the crystalline silicon substrate 10 corresponding to the second conductive region 12 is 0 μm to 5 μm. For example, the height difference can be 0 μm, 0.5 μm, 1 μm, 1.5 μm, 2 μm, 3 μm, 4 μm, or 5 μm, etc. By controlling the height difference within the range of 0 μm to 5 μm, reliable electrical isolation between the first conductive region 11 and the second conductive region 12 can be ensured, while effectively reducing the side defects and leakage risk of the first conductive region 11 and the second conductive region 12.

[0029] Furthermore, in the carrier collection layer 20 provided in this embodiment of the invention, the width of the contact region 21 is 20μm~200μm, and the width of the non-contact region 22 is 80μm~300μm. For example, the width of the contact region 21 can be 20μm, 30μm, 50μm, 80μm, 100μm, 120μm, 150μm, 180μm or 200μm, etc., and the width of the non-contact region 22 can be 80μm, 100μm, 150μm, 200μm, 250μm or 300μm, etc. By controlling the width of the contact region 21, it can be ensured that a good fit is formed between the contact region 21, the first doped silicon-containing film layer 30, the transparent conductive film layer 50 and the first electrode 61 of the carrier collection layer 20, so as to effectively improve the fill factor and short-circuit current of the back contact heterojunction solar cell.

[0030] In this embodiment of the invention, the carrier collection layer 20 generally includes a tunneling passivation layer 23 and a doped polysilicon layer 24 stacked from the inside out. The thickness of the doped polysilicon layer 24 corresponding to the contact region 21 is greater than the thickness of the doped polysilicon layer 24 corresponding to the non-contact region 22. When the silicon substrate is n-type doped, the doped polysilicon layer 24 is n-type doped, meaning it is doped with n-type dopant atoms such as phosphorus or arsenic atoms. When the silicon substrate is p-type doped, the doped polysilicon layer 24 is p-type doped, meaning it is doped with p-type dopant atoms such as boron or gallium atoms.

[0031] The tunneling passivation layer 23 can be a silicon oxide layer or a silicon nitride layer. The thickness of the tunneling passivation layer 23 is generally 0.5nm to 3nm. For example, the thickness of the tunneling passivation layer 23 can be 0.5nm, 1nm, 1.5nm, 2nm or 3nm, etc. By controlling the thickness of the tunneling passivation layer 23, the back side of the crystalline silicon substrate 10 can be passivated while ensuring carrier tunneling.

[0032] The thickness of the doped polysilicon layer 24 corresponding to the contact region 21 is 30nm~200nm, and the thickness of the doped polysilicon layer 24 corresponding to the non-contact region 22 is 20nm~80nm. For example, the thickness of the doped polycrystalline silicon layer 24 corresponding to the contact region 21 can be 30nm, 50nm, 60nm, 80nm, 100nm, 120nm, 150nm, 180nm or 200nm, etc., and the thickness of the doped polycrystalline silicon layer 24 corresponding to the non-contact region 22 can be 20nm, 30nm, 40nm, 50nm, 70nm or 80nm, etc. By controlling the thickness of the doped polycrystalline silicon layer 24 corresponding to the non-contact region 22, parasitic absorption can be effectively reduced. At the same time, in conjunction with the doped polycrystalline silicon layer 24 corresponding to the contact region 21, the first doped silicon-containing film layer 30 and the transparent conductive film layer 50, the negative impact of the increase in the lateral transport resistance of the doped polycrystalline silicon layer 24 corresponding to the non-contact region 22 can be effectively offset, and the performance of the back contact heterojunction solar cell, such as the fill factor, short-circuit current and open-circuit voltage, can be improved to a certain extent.

[0033] The doping concentration of the polysilicon layer 24 is 5 × 10⁻⁶. 18 atoms / cm 3 ~9×10 19 atoms / cm 3 For example, the doping concentration of the polycrystalline silicon layer 24 can be 5 × 10⁻⁶. 18 atoms / cm 3 7×10 18 atoms / cm 3 8×10 18 atoms / cm 3 9×10 18 atoms / cm 3 1×10 19 atoms / cm 3 3×10 19 atoms / cm 3 5×10 19 atoms / cm 3 8×10 19 atoms / cm 3 Or 9×10 19 atoms / cm 3 By controlling the doping concentration of the doped polysilicon layer 24, parasitic absorption can be effectively reduced, and a better fit can be formed between the contact region 21 of the doped polysilicon layer 24 and the first doped silicon-containing film layer 30, ensuring the reliability of the conductive channel of the composite junction.

[0034] In any embodiment of the present invention, the first doped silicon-containing film layer 30 generally includes microcrystalline silicon particles and / or nanocrystalline silicon particles to ensure that the first doped silicon-containing film layer 30 has a certain degree of crystallinity, improve the conductivity of the first doped silicon-containing film layer 30, and reduce the parasitic absorption of the first doped silicon-containing film layer 30, thereby helping to improve the fill factor, short-circuit current, and photoelectric conversion efficiency of the solar cell. Microcrystalline silicon particles refer to crystalline silicon particles with a particle size of 20 nm to 100 nm, and nanocrystalline silicon particles refer to crystalline silicon particles with a particle size of 1 nm to 20 nm.

[0035] Furthermore, in addition to the first doped silicon-containing film layer 30 comprising microcrystalline silicon particles and / or nanocrystalline silicon particles, the first doped silicon-containing film layer 30 may also include amorphous silicon, and / or, the first doped silicon-containing film layer 30 may also include silicon oxide and / or silicon carbide. That is, in addition to the first doped silicon-containing film layer 30 comprising microcrystalline silicon particles and / or nanocrystalline silicon particles, the first doped silicon-containing film layer 30 may also include one or more of amorphous silicon, silicon oxide, and silicon carbide to ensure good conductivity of the first doped silicon-containing film layer 30.

[0036] In this embodiment of the invention, the second intrinsic silicon-containing film layer 41 may include microcrystalline silicon particles and / or nanocrystalline silicon particles, and / or, the second intrinsic silicon-containing film layer 41 may include amorphous silicon, and / or, the second intrinsic silicon-containing film layer 41 may include silicon oxide and / or silicon carbide. That is, the silicon atoms contained in the second intrinsic silicon-containing film layer 41 may exist in the form of microcrystalline silicon particles and / or nanocrystalline silicon particles, or in the form of amorphous silicon, silicon oxide, or silicon carbide. The second intrinsic silicon-containing film layer 41 may contain one or more of the following forms: microcrystalline silicon particles, nanocrystalline silicon particles, amorphous silicon, silicon oxide, and silicon carbide. This second intrinsic silicon-containing film layer 41 can passivate the surface of the crystalline silicon substrate 10 of the second conductive region 12 while ensuring carrier transport.

[0037] The thickness of the second intrinsic silicon-containing film 41 is 1 nm to 30 nm. For example, the thickness of the second intrinsic silicon-containing film 41 can be 1 nm, 4 nm, 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 20 nm, 25 nm or 30 nm, etc. By controlling the thickness of the second intrinsic silicon-containing film 41, the passivation effect on the surface of the crystalline silicon substrate 10 can be guaranteed.

[0038] In this embodiment of the invention, the second doped silicon-containing film layer 42 generally includes microcrystalline silicon particles and / or nanocrystalline silicon particles to ensure that the second doped silicon-containing film layer 42 has a certain degree of crystallinity. This improves the conductivity of the first doped silicon-containing film layer 30, while the grain boundaries between the microcrystalline silicon particles and / or nanocrystalline silicon particles allow charge carriers to transport more along the thickness direction of the second doped silicon-containing film layer 42. Furthermore, in addition to including microcrystalline silicon particles and / or nanocrystalline silicon particles, the second doped silicon-containing film layer 42 may also include amorphous silicon, and / or silicon oxide and / or silicon carbide. That is, the silicon atoms included in the second doped silicon-containing film layer 42 can exist in one or more of the following forms: amorphous silicon, silicon oxide, and silicon carbide, besides being in the form of microcrystalline silicon particles and / or nanocrystalline silicon particles.

[0039] In this embodiment of the invention, the crystallinity of the second doped silicon-containing film layer 42 is lower than that of the first doped silicon-containing film layer 30, so that the interface energy level between the second doped silicon-containing film layer 42 and the second intrinsic silicon-containing film layer 41 is better matched, reducing interface recombination between the second doped silicon-containing film layer 42 and the second intrinsic silicon-containing film layer 41. Furthermore, the higher crystallinity of the first doped silicon-containing film layer 30 results in a better match between the interface energy level of the carrier collection layer 20 (especially with the doped polycrystalline silicon layer 24), and gives the first doped silicon-containing film layer 30 better conductivity, which is more conducive to constructing a composite junction conductive channel.

[0040] More specifically, the crystallinity of the first doped silicon-containing film layer 30 is 5%-90%. For example, the crystallinity of the first doped silicon-containing film layer 30 can be 5%, 10%, 20%, 30%, 40%, 50%, 70%, 80%, or 90%, etc. By controlling the crystallinity of the first doped silicon-containing film layer 30, the conductivity of the first doped silicon-containing film layer 30 can be guaranteed, while further improving the reliability of its cooperation with the carrier collection layer 20 and the transparent conductive film layer 50.

[0041] In a preferred embodiment, the thickness of the second doped silicon-containing film layer 42 is less than the thickness of the first doped silicon-containing film layer 30. In the second conductive region 12, the second doped silicon-containing film layer 42 cooperates with the second intrinsic silicon-containing film layer 41 to ensure that the second doped silicon-containing film layer 42 separates and collects more charge carriers, and that the charge carriers transported through the second doped silicon-containing film layer 42 maintain a high energy, allowing more charge carriers to be transported through the second electrode 62. The thicker first doped silicon-containing film layer 30 cooperates with the charge carrier collection layer 20 to ensure the formation of a composite junction conductive channel while also ensuring that the first doped silicon-containing film layer 30 transports charge carriers, thereby enabling the second doped silicon-containing film layer 42 and the second intrinsic silicon-containing film layer 41, and the first doped silicon-containing film layer 30 and the charge carrier collection layer 20 to simultaneously achieve optimal matching. In addition, the thickness of the second doped silicon-containing film layer 42 and the thickness of the first doped silicon-containing film layer 30 are matched with the preparation process provided in the embodiments of the present invention. The fact that the thickness of the second doped silicon-containing film layer 42 is smaller than the thickness of the first doped silicon-containing film layer 30 is also conducive to industrialization.

[0042] The thickness of the first doped silicon-containing film layer 30 is generally 3nm to 80nm. For example, the thickness of the first doped silicon-containing film layer 30 can be 3nm, 5nm, 10nm, 20nm, 50nm, 60nm, or 80nm. By controlling the thickness of the first doped silicon-containing film layer 30, on the one hand, the surface flatness of the first doped silicon-containing film layer 30 can be ensured, thereby ensuring the uniformity of the thickness of the formed transparent conductive film layer 50; on the other hand, it can ensure that the first doped silicon-containing film layer 30 and the carrier collection layer 20 form a matching composite junction conductive channel, thereby ensuring carrier transport. It is worth noting that this composite junction conductive channel can form a conductive channel between the first doped silicon-containing film layer 30 and the carrier collection layer 20 (which is essentially the doped polysilicon layer 24 included in the carrier collection layer 20), enabling carriers to be transported through this composite junction conductive channel, the first doped silicon-containing film layer 30, the transparent conductive film layer 50, and the first electrode 61.

[0043] The thickness of the second doped silicon-containing film layer 42 is typically 2 nm to 70 nm. For example, the thickness of the second doped silicon-containing film layer 42 can be 1 nm, 5 nm, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, or 70 nm. By controlling the thickness of the second doped silicon-containing film layer 42, a relatively uniform surface can be ensured, thereby forming a uniform transparent conductive film layer 50 on the surface of the second doped silicon-containing film layer 42. In addition, controlling the thickness of the second doped silicon-containing film layer 42 allows charge carriers to pass through the second doped silicon-containing film layer 42 quickly, resulting in less energy attenuation of the charge carriers passing through the second doped silicon-containing film layer 42, thus giving the second conductive region 12 a better charge carrier transport efficiency.

[0044] In an optional embodiment, the transparent conductive film layer 50 is also disposed outside the non-contact region 22 of the carrier collection layer to further improve the carrier collection efficiency of the first conductive region 11.

[0045] In this embodiment, the doping type of the transparent conductive film layer 50 is opposite to that of the first doped silicon-containing film layer 30. In a preferred embodiment, the first doped silicon-containing film layer 30 is p-type doped, and the transparent conductive film layer 50 is n-type doped, allowing the transparent conductive film layer 50 to be made from conventional materials, thus ensuring its quality. Furthermore, compared to the prior art where the n-type doped polycrystalline silicon layer in the n-type conductive region and the p-type doped silicon-containing film layer in the p-type conductive region need to be matched with transparent conductive film layers of different work functions, in the solar cell provided by this invention, since the first doped silicon-containing film layer 30 and the second doped silicon-containing film layer 42 have the same doping type, transparent conductive film layers with the same work function can simultaneously match the first doped silicon-containing film layer 30 and the second doped silicon-containing film layer 42, ensuring that both the first conductive region 11 and the second conductive region 12 achieve optimal contact, which is beneficial for improving carrier transport efficiency.

[0046] The transparent conductive film layer 50 may include metal oxides or nitrides and doping atoms. The doping atoms included in the transparent conductive film layer 50 may include one or more of indium, tin, calcium, aluminum, cadmium, zinc, cerium and fluorine. The metal oxides included in the transparent conductive film layer 50 may include one or more of indium oxide, tin oxide, zinc oxide and cadmium oxide. The metal nitrides included in the transparent conductive film layer 50 may be titanium nitride.

[0047] Furthermore, in existing back-contact heterojunction solar cells, the tunneling oxide layer and phosphorus-doped polycrystalline silicon layer in the n-type conductive region, and the intrinsic amorphous silicon layer and boron-doped amorphous silicon layer in the p-type conductive region, generally extend into the electrical isolation region between adjacent n-type and p-type conductive regions. The intrinsic amorphous silicon layer and boron-doped amorphous silicon layer are located outside the phosphorus-doped polycrystalline silicon layer. However, the intrinsic amorphous silicon layer and boron-doped amorphous silicon layer in the p-type conductive region are identical to those extending into the electrical isolation region. These intrinsic amorphous silicon layers and boron-doped amorphous silicon layers not only affect carrier transport in the p-type conductive region but also the electrical isolation effect of the electrical isolation region. Studies have found that increasing the crystallinity of the intrinsic amorphous silicon layer and the boron-doped amorphous silicon layer can improve carrier transport in the p-type conductive region. However, the increased crystallinity of the boron-doped amorphous silicon layer leads to a significant conduction risk between the phosphorus-doped polycrystalline silicon layer and the intrinsic and boron-doped amorphous silicon layers in the electrically isolated region, resulting in a significant short-circuit risk in the electrically isolated region. Although adding an insulating film layer between the phosphorus-doped polycrystalline silicon layer and the intrinsic amorphous silicon layer in the electrically isolated region can reduce the short-circuit risk, this increases the fabrication steps of the back-contact heterojunction solar cell. Furthermore, the existing process involves first forming the entire surface and then removing the insulating film layers in the n-type and p-type conductive regions. This process damages the phosphorus-doped polycrystalline silicon layer in the n-type conductive region of the back-contact solar cell, increasing defects in the phosphorus-doped polycrystalline silicon layer and increasing the carrier recombination risk in the back-contact heterojunction solar cell. Therefore, there is still room for improvement in the fill factor of the back-contact heterojunction solar cell. Thus, the back-contact solar cell provided by this invention further improves the electrically isolated region 13.

[0048] Specifically, based on the structure of the back-contact heterojunction solar cell provided in any of the above embodiments, such as Figure 1 As shown, the back-contact heterojunction solar cell may further include: an electrical isolation region 13 disposed between adjacent first conductive region 11 and second conductive region 12, the electrical isolation region 13 being used to electrically isolate the first conductive region 11 and the second conductive region 12. More specifically, the electrical isolation region 13 may include a first isolation region 131 near the first conductive region 11 and a second isolation region 132 near the second conductive region 12; a carrier collection layer 20 extends from the first conductive region 11 to the first isolation region 131; a third intrinsic silicon-containing film layer 133 and a third doped silicon-containing film layer 134 stacked on the outside of the carrier collection layer 20 in the first isolation region 131 and the second isolation region 132 are disposed, which can effectively improve the electrical isolation effect of the electrical isolation region 13, while avoiding side leakage of the first conductive region 11 and the second conductive region 12.

[0049] The width of the electrical isolation region 13 is 5μm to 150μm. For example, the width of the electrical isolation region 13 can be 5μm, 10μm, 20μm, 40μm, 50μm, 70μm, 80μm, 100μm or 150μm, etc., to ensure the electrical isolation effect of the electrical isolation region 13.

[0050] In one embodiment of the present invention, the thickness of the third intrinsic silicon-containing film layer 133 is greater than the thickness of the second intrinsic silicon-containing film layer 41, so as to effectively improve the electrical isolation effect of the electrical isolation region 13. Specifically, while the thickness of the third intrinsic silicon-containing film layer 133 is greater than the thickness of the second intrinsic silicon-containing film layer 41, the thickness of the third intrinsic silicon-containing film layer 133 is generally 2nm to 20nm. For example, the thickness of the third intrinsic silicon-containing film layer 133 can be 2nm, 4nm, 5nm, 8nm, 10nm, or 20nm, etc. By controlling the thickness of the third intrinsic silicon-containing film layer 133, the electrical isolation effect of the electrical isolation region 13 can be guaranteed, and the surface of the crystalline silicon substrate 10 corresponding to the second isolation region 132 can be passivated relatively well, reducing carrier recombination.

[0051] In an optional embodiment, the crystallinity of the third doped silicon-containing film layer 134 is less than that of the second doped silicon-containing film layer 42. Since the higher the crystallinity of the first doped silicon-containing film layer 30, the third doped silicon-containing film layer 134, and the second doped silicon-containing film layer 42, the stronger the conductivity, the conductivity of the third doped silicon-containing film layer 134 is lower than that of the second doped silicon-containing film layer 42. This can reduce or even prevent the migration of charge carriers transported by the second doped silicon-containing film layer 42 to the third doped silicon-containing film layer 134, thereby further improving the electrical isolation effect of the electrical isolation region 13.

[0052] In an optional embodiment, the thickness of the third doped silicon-containing film 134 is less than the thickness of the second doped silicon-containing film 42, so as to further improve the electrical isolation effect of the electrical isolation region 13.

[0053] Furthermore, by combining the carrier collection layer 20 of the electrically isolated region 13 with the third intrinsic silicon-containing film layer 133 and the third doped silicon-containing film layer 134, since the third intrinsic silicon-containing film layer 133 and the third doped silicon-containing film layer 134 are extensions of the second intrinsic silicon-containing film layer 41 and the second doped silicon-containing film layer 42 of the second conductive region 12, process defects on the side of the second conductive region 12 can be avoided, thereby reducing the risk of side leakage of the second conductive region 12. In addition, no additional insulating layer is required in the electrically isolated region 13. The lower crystallinity of the third intrinsic silicon-containing film layer 133 and the third doped silicon-containing film layer 134 can also reduce the risk of short circuit and leakage in the electrically isolated region 13, thereby improving the stability and reliability of the back contact heterojunction solar cell.

[0054] In a preferred embodiment, a portion of the thickness of the third intrinsic silicon-containing film layer 133 is integral with the second intrinsic silicon-containing film layer 41 and is on the same plane, and a portion of the thickness of the third doped silicon-containing film layer 134 is integral with the second doped silicon-containing film layer 42 and is on the same plane, so that the third intrinsic silicon-containing film layer 133 and the second intrinsic silicon-containing film layer 41 can be formed based on the same intrinsic silicon-containing film layer, and the third doped silicon-containing film layer 134 and the second doped silicon-containing film layer 42 can be based on the same doped silicon-containing film layer, effectively simplifying the preparation process of the third intrinsic silicon-containing film layer 133 and the second intrinsic silicon-containing film layer 41, as well as the third doped silicon-containing film layer 134 and the second doped silicon-containing film layer 42.

[0055] In a preferred embodiment, the doping concentration of the third doped silicon-containing film layer 134 is lower than that of the first doped silicon-containing film layer 30. In conjunction with the third intrinsic silicon-containing film layer 133, the electrical isolation effect of the electrical isolation region 13 can be further guaranteed, thereby improving the reliability of the back contact heterojunction solar cell.

[0056] Furthermore, such as Figure 1 As shown, the back-contact heterojunction solar cell also includes a second electrode 62, which is electrically connected to a transparent conductive film layer 50 located outside the second doped silicon-containing film layer 42.

[0057] The first electrode 61 and the second electrode 62 provided in the embodiments of the present invention can be made of the same material.

[0058] Furthermore, the back-contact heterojunction solar cell provided in any of the above embodiments may further include: a front passivation and antireflection layer 70 disposed on the front side of the crystalline silicon substrate 10. Specifically, the front passivation and antireflection layer 70 may include a front passivation layer 71 and a front antireflection layer 72 stacked from the inside to the outside. The front passivation layer 71 generally includes one or more of silicon oxide, aluminum oxide, potassium oxide, and titanium oxide. The front passivation layer 71 may be a single-layer film or a multilayer film. The front antireflection layer 72 generally includes one or more of silicon nitride, silicon oxynitride, silicon oxide, magnesium fluoride, and lithium fluoride. The front antireflection layer 72 may also be a single-layer film or a multilayer film. The thickness of the front passivation layer 71 is generally 1 nm to 15 nm. For example, the thickness of the front passivation layer 71 can be 1 nm, 5 nm, 8 nm, 10 nm, 13 nm, or 15 nm. By controlling the thickness of the front passivation layer 71, the morphology of the front side of the crystalline silicon substrate 10 can be maintained while passivating the front side. The thickness of the front antireflection layer 72 is generally 1 nm to 300 nm. For example, the thickness of the front antireflection layer 72 can be 1 nm, 10 nm, 50 nm, 100 nm, 150 nm, 200 nm, or 300 nm, to ensure improved light utilization of the front side of the back contact heterojunction solar cell.

[0059] Furthermore, embodiments of the present invention also provide a method for fabricating a back-contact heterojunction solar cell. This method is used to fabricate the back-contact heterojunction solar cell provided in any of the above embodiments. This fabrication method is completely different from the existing fabrication process of back-contact heterojunction solar cells. More specifically, as... Figure 2 As shown, the preparation method may include the following steps: Step S201: Provide a crystalline silicon substrate 10, the back side of which includes alternating first conductive regions 11 and second conductive regions 12.

[0060] The silicon substrate 10 provided in step S201 can be an n-type silicon substrate or a p-type silicon substrate. It is worth noting that the first conductive region 11 and the second conductive region 12 are defined for the convenience of subsequent positioning and setting of each film layer. After each film layer is formed on the back side of the silicon substrate 10, the first conductive region 11 and the second conductive region 12 are formed due to the differences in the functions of each film layer. The back side of the silicon substrate 10 itself does not have the first conductive region 11 and the second conductive region 12.

[0061] Step S202: A carrier collection layer 20 is formed in the first conductive region 11. The carrier collection layer 20 includes a contact region 21 and a non-contact region 22. The thickness of the non-contact region 22 is less than the thickness of the contact region 21. A second intrinsic silicon-containing film layer 41 and a second doped silicon-containing film layer 42 are formed in the second conductive region 12. A first doped silicon-containing film layer 30 is formed on the outside of the contact region 21. The doping type of the first doped silicon-containing film layer 30 is opposite to the doping type of the carrier collection layer 20 and the same as the doping type of the second doped silicon-containing film layer 42.

[0062] The formed carrier collection layer 20 generally includes a tunneling passivation layer 23 and a doped polysilicon layer 24 stacked from the inside to the outside. The tunneling passivation layer 23 can be a silicon oxide layer or a silicon nitride layer.

[0063] Step S203: A transparent conductive film layer 50 is formed on the outside of the first doped silicon-containing film layer 30 and the second doped silicon-containing film layer 42, and the transparent conductive film layer 50 is disconnected between the first conductive region 11 and the second conductive region 12.

[0064] Step S204: Form a first electrode 61 on a transparent conductive film layer 50 located outside the first doped silicon film layer 30.

[0065] Taking the carrier collection layer 20 as an example, which includes a tunneling passivation layer 23 and a doped polysilicon layer 24 stacked from the inside to the outside, the structural changes corresponding to the above steps S201 to S04 are as follows: Figure 3 As shown.

[0066] The preparation method provided in this invention can prepare a novel back-contact heterojunction solar cell. The back-contact heterojunction solar cell prepared by this method can achieve a back-contact heterojunction structure by combining a crystalline silicon substrate 10, a carrier collection layer 20 formed in the first conductive region 11 of the crystalline silicon substrate 10 and a first doped silicon-containing film layer 30 with a second doped silicon-containing film layer 41 formed in the second conductive region 12. Furthermore, the thickness of the non-contact region 22 formed in the carrier collection layer 20 of the first conductive region 11 is less than the thickness of the contact region 21, which can effectively reduce the parasitic absorption of the non-contact region 22. Furthermore, compared to the reduction in carrier transport efficiency caused by directly setting a transparent conductive film layer on the thinned carrier collection layer, the combination of the thicker contact region 21 of the formed carrier collection 20, the first doped silicon-containing film layer 30 with the opposite doping type to the carrier collection layer 20, and the formed transparent conductive film layer 50, forms a composite junction conductive channel between the thicker contact region 21 of the formed carrier collection layer 20 with the opposite doping type and the first doped silicon-containing film layer 30, which can ensure the collection and transport of carriers in the first conductive region, thereby improving the fill factor and short-circuit current of the solar cell.

[0067] Furthermore, in the back-contact heterojunction solar cell prepared by this method, the second doped silicon-containing film layer 42 disposed in the second conductive region 12 has the same doping type as the first doped silicon-containing film layer 30 disposed in the contact region 21 of the first conductive region 11. This allows the work function of the transparent conductive film layer 60 to match both the second doped silicon-containing film layer 42 and the first doped silicon-containing film layer 30 simultaneously, ensuring that the transparent conductive film layer 60 can achieve better contact with both the first doped silicon-containing film layer 30 and the second doped silicon-containing film layer 42, thereby further improving the short-circuit current of the solar cell.

[0068] In addition, the transparent conductive film 60 corresponding to the first doped silicon-containing film layer 30 and the transparent conductive film 60 corresponding to the second doped silicon-containing film layer 42 can be formed simultaneously, which effectively simplifies the fabrication process.

[0069] Furthermore, such as Figure 3 As shown, to improve the electrical isolation effect between the various film layers formed on the first conductive region 11 and the various film layers formed on the second conductive region 12, the back side of the crystalline silicon substrate 10 may further include an electrical isolation region 13 disposed between adjacent first conductive regions 11 and second conductive regions 12. More specifically, the electrical isolation region 13 may include a first isolation region 131 near the first conductive region 11 and a second isolation region 132 near the second conductive region 12. Figure 4 and Figure 5 As shown, the first isolation region 131 and the second isolation region 132 are determined by the respective film layers formed on the back side of the crystalline silicon substrate 10.

[0070] More specifically, the specific implementation scheme for step S202 above includes: Step S2021: A carrier collection layer 20 is formed in the first conductive region 11, and an initial intrinsic silicon-containing film layer 41' and an initial doped silicon-containing film layer 42' are formed on the outside of the carrier collection layer 20 and in the second conductive region 12.

[0071] Specifically, a specific implementation of step S2021 may include: first forming a carrier collection layer 20 on the entire back side of the crystalline silicon substrate 10, and then removing at least the carrier collection layer 20 corresponding to the second conductive region 12. More specifically, taking the carrier collection layer 20 formed in step S201 as an example, which includes a tunneling passivation layer 23 and a doped polycrystalline silicon layer 24 stacked from the inside to the outside, the tunneling passivation layer 23 and the doped polycrystalline silicon layer 24 can be sequentially stacked by a deposition method (such as low-temperature chemical vapor deposition or plasma-enhanced chemical vapor deposition, etc.), and then the final doped polycrystalline silicon layer 24 and the mask layer 20' can be formed by high-temperature diffusion or annealing. The mask layer 20' can be a doped silicon glass layer formed on the outside of the doped polycrystalline silicon layer 24 (e.g., if the doped polycrystalline silicon layer 24 is a phosphorus-doped polycrystalline silicon layer, the doped silicon glass layer is a phosphorus-doped silicon glass layer). 20' can also be a protective layer made of other materials (such as silicon nitride or silicon oxynitride, which have certain alkali resistance) (requiring a separate CVD process for preparation). First, the mask layer 20' corresponding to at least the second conductive region 12 is removed by laser etching. Then, the exposed doped polysilicon layer 24 and the tunneling passivation layer 23 located inside the exposed doped polysilicon layer 24 are removed by etching with an alkaline solution (e.g., a 2% NaOH solution). The back side of the exposed silicon substrate 10 is then polished. In a preferred embodiment, the back side of the exposed silicon substrate 10 can be further texturized after polishing. Furthermore, in step S2021, after polishing or texturizing the back side of the exposed silicon substrate 10, the remaining mask layer 20' is removed by cleaning with an HF solution. Therefore, after step S2021, the mask layer 20' is completely removed. That is, before the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' are formed in step S2021, the mask layer 20' is completely removed. After the mask layer 20' is removed, the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' are sequentially stacked on the back side of the exposed crystalline silicon substrate 10 and on the outside of the remaining carrier collection layer 20.

[0072] Additionally, in step S2021, after the tunneling passivation layer 23, the doped polysilicon layer 24, and the mask layer 20' are stacked and formed, and before the mask layer 20' corresponding to at least the second conductive region 12 is removed by laser etching, step S2021 may further include: forming a front passivation antireflection layer 70 on the front side of the silicon substrate 10. The front side of the silicon substrate 10 can be a polished surface or a textured surface.

[0073] More specifically, during the process of stacking and forming the tunneling passivation layer 23, the doped polysilicon layer 24, and the mask layer 20' in step S2021, a first wrap-around coating corresponding to the tunneling passivation layer 23, a second wrap-around coating corresponding to the doped polysilicon layer 24, and a third wrap-around coating corresponding to the mask layer 20' are also stacked from the inside to the outside on the front side of the crystalline silicon substrate 10. For the first wrap-around coating, the second wrap-around coating, and the third wrap-around coating, the third wrap-around coating can be removed by single-sided cleaning with HF solution or by single-sided laser etching. Then, the second wrap-around coating and the first wrap-around coating are removed by cleaning with alkaline solution. The front side of the crystalline silicon substrate 10 is then polished, and the polished surface of the front side of the crystalline silicon substrate 10 is further texturized.

[0074] Taking step S2021, which involves removing the mask layer 20' corresponding to the second conductive region 12 and the second isolation region 132, as an example, the structural change corresponding to step S2021 is as follows: Figure 4 As shown. That is, for the case where the electrical isolation region 13 on the back side of the crystalline silicon substrate 10 includes a first isolation region 131 and a second isolation region 132, step S2021 may also include simultaneously forming a carrier collection layer 20 in the first isolation region 131.

[0075] in, Figure 4 The diagram only shows, by way of example, a structure where the second conductive region 12 and the second conductive region 132 on the front and back sides of the crystalline silicon substrate 10 are polished surfaces. The second conductive region 12 and the second isolation region 132 on the front and back sides of the crystalline silicon substrate 10 can also be... Figure 1 The velvet structure shown.

[0076] It is worth noting that in step S2021, conventional materials can be used to form the carrier collection layer 20, the initial intrinsic silicon-containing film layer 41', and the initial doped silicon-containing film layer 42'. However, the thickness of the initial intrinsic silicon-containing film layer 41' and the doping concentration and thickness of the initial doped silicon-containing film layer 42' need to be controlled. The thickness of the initial intrinsic silicon-containing film layer 41' is generally 2nm to 20nm, and the thickness of the initial doped silicon-containing film layer 42' is generally 1nm to 60nm. For example, the thickness of the initial intrinsic silicon-containing film layer 41' can be 2nm, 5nm, 8nm, 10nm, 15nm, 18nm, or 20nm, and the thickness of the initial doped silicon-containing film layer 42' can be 1nm, 5nm, 8nm, 10nm, 15nm, 20nm, 25nm, 35nm, 40nm, 50nm, or 60nm, etc.

[0077] In addition, the initial doping concentration of the silicon-containing film layer 42' is 1×10⁻⁶. 17 atoms / cm 3 ~5×10 19 atoms / cm 3 For example, the doping concentration of the initial doped silicon film 42' can be 1×10⁻⁶. 17 atoms / cm 3 5×10 17 atoms / cm 3 8×10 17 atoms / cm 3 2×10 18 atoms / cm 3 5×10 18 atoms / cm 3 7×10 18 atoms / cm 3 9×10 18 atoms / cm 3 1×10 19 atoms / cm 3 3×10 19 atoms / cm 3 Or 5×10 19 atoms / cm 3The doping concentration of the initial doped silicon-containing film layer 42' can be coordinated with the first, second, and third laser processing steps S2022 to obtain the desired doping concentration and thickness of the first doped silicon-containing film layer 30, the second doped silicon-containing film layer 42, and the third doped silicon-containing film layer 134. Furthermore, by coordinating the doping concentration and thickness of the initial doped silicon-containing film layer 42' with the first, second, and third laser processing steps S2022, the crystallinity of the first doped silicon-containing film layer 30, the second doped silicon-containing film layer 42, and the third doped silicon-containing film layer 134 can be effectively controlled. Moreover, the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' cooperate in absorbing the laser, which can prevent laser damage to the carrier collection layer 20 of the first conductive region 11.

[0078] Step S2022: The initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' of the second conductive region 12 are treated with a first laser to form a second intrinsic silicon-containing film layer 41, a second doped silicon-containing film layer 42, and a first protective layer 40'; and the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' of the target area of ​​the first conductive region 11 are treated with a second laser to form a first doped silicon-containing film layer 30 and a second protective layer 40'', wherein the energy of the second laser is higher than that of the first laser.

[0079] Step S2022 employs a first laser to treat the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' of the second conductive region 12. This is to push the doped atoms in the initial doped silicon-containing film layer 42' towards the outer portion of the initial intrinsic silicon-containing film layer 41' and activate the doped atoms, making the initial doped silicon-containing film layer 42' part of the second doped silicon-containing film layer 42. Simultaneously, the outer portion of the initial intrinsic silicon-containing film layer 41' also becomes part of the second doped silicon-containing film layer 42. Furthermore, the first laser treatment in step S2022 can increase the crystallinity of the second doped silicon-containing film layer 42. Simultaneously, the first laser treatment can also form a first protective layer 40' on the outer side of the second doped silicon-containing film layer 42. That is, a single process simultaneously forms the second intrinsic silicon-containing film layer 41, the second doped silicon-containing film layer 42, and the first protective layer 40', eliminating the need for a separate mask setting step and effectively simplifying the processing steps.

[0080] In other words, after the processing in step S2022, the second doped silicon-containing film layer 42 is obtained by converting the outer portion of the initial doped silicon-containing film layer 42' and the initial intrinsic silicon-containing film layer 41'. The first laser processing not only pushes the doped atoms in the initial doped silicon-containing film layer 42' to the outer portion of the initial intrinsic silicon-containing film layer 41', but also activates the doped atoms in the initial doped silicon-containing film layer 42' and the doped atoms pushed to the outer portion of the initial intrinsic silicon-containing film layer 41'. Furthermore, it can transform some of the amorphous silicon included in the outer portion of the initial doped silicon-containing film layer 42' and the initial intrinsic silicon-containing film layer 41' into crystalline silicon (i.e., only some of the amorphous silicon in the outer portion of the initial doped silicon-containing film layer 42' and the initial intrinsic silicon-containing film layer 41' is transformed into crystalline silicon, and amorphous silicon still exists in the second doped silicon-containing film layer 42), thereby increasing the crystallinity of the second doped silicon-containing film layer 42 and thus improving the conductivity of the second doped silicon-containing film layer 42. For the second doped silicon-containing film layer 42, the increased crystallinity will increase the work function of the second doped silicon-containing film layer 42. Compared with the initially doped silicon-containing film layer 42', the work function of the second doped silicon-containing film layer 42 is further improved, which can effectively reduce the work function difference between the second doped silicon-containing film layer 42 and the transparent conductive film layer 50, and effectively improve the carrier collection efficiency of the second conductive region 12.

[0081] In addition, during the first laser treatment of the second conductive region 12, which is carried out in an oxygen-containing environment, a first protective layer 40' can also be formed on the outside of the second doped silicon-containing film layer 42. The first protective layer 40' is formed by oxygen atoms entering the surface of the second doped silicon-containing film layer 42. That is, the first protective layer 40' contains doped atoms, oxygen atoms and silicon atoms. The first protective layer 40' has a certain degree of alkali resistance but is not acid resistant.

[0082] In step S2022, the target area of ​​the first conductive region 11 in the second laser treatment ultimately serves as the contact area 21 of the first conductive region 11. During this second laser treatment, doped atoms in the initial doped silicon-containing film layer 42' corresponding to the target region are advanced to the initial intrinsic silicon-containing film layer 41' corresponding to the target region, and the doped atoms are activated, so that both the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' corresponding to the target region can be completely converted into the first doped silicon-containing film layer 30. In addition, this second laser treatment process is also completed in an oxygen environment to form a second protective layer 40'' on the outside of the first doped silicon-containing film layer 30. The second protective layer 40'' is formed by oxygen atoms entering the surface of the first doped silicon-containing film layer 30, that is, the second protective layer 40'' contains doped atoms, oxygen atoms, and silicon atoms. The second protective layer 40'' has a certain degree of alkali resistance but is not acid resistant. That is, after the second laser treatment, a second protective layer 40'' can also be formed simultaneously on the outside of the first doped silicon-containing film layer 30. In other words, the second laser treatment also realizes the simultaneous formation of the first doped silicon-containing film layer 30 and the second protective layer 40'' in one step, omitting the separate mask setting process and effectively simplifying the processing steps.

[0083] Understandably, for a structure in which an electrical isolation region 13 is included between adjacent first conductive regions 11 and second conductive regions 12, step S2022 may further include: simultaneously forming an initial intrinsic silicon-containing film layer 41' and an initial doped silicon-containing film layer 42' on the outside of the carrier collection layer 20 of the second isolation region 132 and the first isolation region 131; and using a third laser to treat the surface of the initial doped silicon-containing film layer 42' of the second isolation region 132 and the first isolation region 131 to form a stacked third intrinsic silicon-containing film layer 133, a third doped silicon-containing film layer 134 and a third protective layer 40''' from the inside out, wherein the energy of the third laser is lower than the energy of the first laser. It is worth noting that during the third laser treatment of the second isolation region 132 and the first isolation region 131, laser treatment is performed on the surface of the initially doped silicon-containing film layer 42'. This third laser treatment process also introduces oxygen atoms into the surface of the initially doped silicon-containing film layer 42' corresponding to the second isolation region 132 and the first isolation region 131 in an oxygen-containing environment, transforming the surface of the initially doped silicon-containing film layer 42' corresponding to the second isolation region 132 and the first isolation region 131 into the third protective layer 40'''. That is, the remaining portion of the initially doped silicon-containing film layer 42' corresponding to the second isolation region 132 and the first isolation region 131 constitutes the third doped silicon-containing film layer. 134. Understandably, compared to the initial intrinsic silicon-containing film layer 41', the structure of the third intrinsic silicon-containing film layer 133 obtained after the third laser treatment is basically unchanged. Compared to the initial doped silicon-containing film layer 42', the thickness of the third doped silicon-containing film layer 134 is thinner. Compared to the doping concentration of the initial doped silicon-containing film layer 42', the doping concentration of the third doped silicon-containing film layer 134 is basically unchanged. That is, the purpose of the third laser treatment in step S2022 is mainly to form a third protective layer 40''' on the surface of the first isolation region 131 and the second isolation region 132, so that the third intrinsic silicon-containing film layer 133 and the third doped silicon-containing film layer 134 of the first isolation region 131 and the second isolation region 132 can be retained during the alkaline solution cleaning process in the subsequent step S2023. That is, after the third laser treatment, a third protective layer 40''' can also be formed simultaneously on the outside of the third doped silicon-containing film layer 134. In other words, the third laser treatment also realizes the simultaneous formation of the third doped silicon-containing film layer 134 and the third protective layer 40''' in one step, omitting the separate mask setting process and effectively simplifying the processing steps.

[0084] The single-spot energy density of the first laser processing used in step S2022 is 50 mJ / cm²–150 mJ / cm². For example, the single-spot energy density of the first laser processing can be 50 mJ / cm², 80 mJ / cm², 100 mJ / cm², 120 mJ / cm², or 150 mJ / cm², etc.

[0085] The single-spot energy density of the second laser processing used in step S2022 is 80 mJ / cm² to 250 mJ / cm². For example, the single-spot energy density of the second laser processing can be 80 mJ / cm², 100 mJ / cm², 120 mJ / cm², or 150 mJ / cm², etc.

[0086] The single-spot energy density of the third laser processing used in step S2022 is 10mJ / cm² to 50mJ / cm². For example, the single-spot energy density of the third laser processing can be 10mJ / cm², 20mJ / cm², 30mJ / cm², 40mJ / cm², or 50mJ / cm², etc.

[0087] The laser source can be the laser source commonly used in existing solar cells, and it is only necessary to control the energy density of a single spot in the laser processing process.

[0088] As can be seen from the above, step S2022, through the first laser processing, the second laser processing, and the third laser processing, respectively transforms the outer portion of the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' corresponding to the second conductive region 12 into the second doped silicon-containing film layer 42, the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' corresponding to the first conductive region 11 into the first doped silicon-containing film layer 30, and the initial doped silicon-containing film layer 42' corresponding to the electrically isolated region 13 into the third doped silicon-containing film layer 134, instead of through laser film opening. The fabrication process provided by the embodiments of the present invention does not require special equipment to prepare masks or protective layers, requires less equipment, and is beneficial to reducing the production cost of back contact heterojunction solar cells. Furthermore, the technical solution provided by the embodiments of the present invention, by simultaneously forming a protective layer through laser processing, can avoid the complex processes of special mask deposition and patterning mask processing, greatly simplifying the fabrication process, ensuring process controllability and yield of back contact heterojunction solar cells, and is conducive to large-scale production and industrialization.

[0089] Furthermore, laser processing alters the crystallinity of the outer portion of the initial intrinsic silicon-containing film 41' and the initial doped silicon-containing film 42', preventing the laser from reaching the crystalline silicon substrate 10 and the carrier collection layer 20, thus avoiding laser damage to these components. Moreover, compared to preparing a film with a certain degree of crystallinity using microcrystalline equipment, the preparation method provided in this embodiment directly alters the crystallinity of the outer portion of the initial intrinsic silicon-containing film 41' and the initial doped silicon-containing film 42' through laser processing, requiring less equipment investment, further reducing production costs, and facilitating large-scale production.

[0090] The structural change corresponding to step S2022 can be described as follows: Figure 4 As shown.

[0091] Step S2023: Use an alkaline solution to clean and remove the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' corresponding to other regions of the first conductive region 11, and thin the carrier collection layer 20 corresponding to other regions of the first conductive region 11 to form a non-contact region 22. The carrier collection layer 20 corresponding to the target region is the contact region 21.

[0092] The other regions corresponding to the first conductive region 11 generally refer to the regions within the first conductive region 11 that are outside the target region used to form the contact region 21, and these other regions correspond to the non-contact region 22. The mass fraction of the alkaline solution used in step S2023 is 0.5% to 2.0%, and the cleaning time is 30s to 300s. For example, the mass fraction of the alkaline solution used in step S2023 can be 0.5%, 1.0%, 1.5%, or 2.0%, and the cleaning time can be 30s, 60s, 90s, 180s, 200s, 240s, or 300s. Since the first protective layer 40', the second protective layer 40'', and the third protective layer 40''' have certain alkali resistance, during the cleaning process using alkaline solution in step S2023, the first protective layer 40' can protect the second doped silicon-containing film layer 42 inside it, the second protective layer 40'' can protect the first doped silicon-containing film layer 30 inside it, and the third protective layer 40''' can protect the third doped silicon-containing film layer 134 inside it, so as to prevent the second doped silicon-containing film layer 42, the first doped silicon-containing film layer 30, and the third doped silicon-containing film layer 134 from being etched during the cleaning process in step S2023, and to ensure the integrity of the film layers 42, 30, and 134.

[0093] Meanwhile, regarding the carrier collection layer 20, which includes a tunneling passivation layer 23 and a doped polysilicon layer 24 stacked from the inside out, during step S2023 of cleaning and removing the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' corresponding to other regions of the first conductive region 11, the doped polysilicon layer 24 can also be thinned. The structural change corresponding to step S2023 can be as follows: Figure 4 As shown.

[0094] Compared to laser etching to remove the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' corresponding to other regions of the first conductive region 11, wet etching can be used in conjunction with steps S2022 and S2023 to remove the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' corresponding to other regions of the first conductive region 11, and to thin the carrier collection layer 20 corresponding to other regions of the first conductive region 11, thereby reducing parasitic absorption in the first conductive region 11, making it easier for industrial operation, and avoiding laser damage to the carrier collection layer 20, thus improving the performance of the back contact heterojunction solar cell.

[0095] Step S2024: Remove the first protective layer 40' and the second protective layer 40'' by cleaning with an acid solution.

[0096] Specifically, this step mainly involves using an HF solution with a mass fraction of 1% to 2% to clean and remove the first protective layer 40' and the second protective layer 40''. Additionally, for structures where an electrical isolation region 13 is provided between adjacent first conductive regions 11 and second conductive regions 12, step S2024 may further include cleaning and removing the third protective layer 40''' using an acid solution. For example, the mass fraction of the HF solution used in step S2024 may be 1%, 1.5%, or 2%, etc.

[0097] The structural change corresponding to step S2024 is as follows: Figure 4 As shown. Further, based on step S2024, in step S203, a continuous transparent conductive film layer 50 is formed on the outer side of the thinned non-contact region of the carrier collection layer 20 in the first conductive region 11, the outer side of the first doped silicon-containing film layer 30, the outer side of the second doped silicon-containing film layer 42 in the second conductive region 12, and the outer side of the third doped silicon-containing film layer 134 in the electrically isolated region 13. A portion of the transparent conductive film layer 50 in the electrically isolated region 13 can be removed by laser etching, thereby disconnecting the transparent conductive film layer 50 corresponding to the first conductive region 11 from the transparent conductive film layer 50 corresponding to the second conductive region 12 in the electrically isolated region 13. The structural change corresponding to step S203 is as follows: Figure 5 As shown.

[0098] The technical solution provided by this invention, through the above steps S2021 to S2024, allows the first doped silicon-containing film layer 30 of the first conductive region 11, the second doped silicon-containing film layer 42 of the second conductive region 12, and the third doped silicon-containing film layer 134 of the electrically isolated region 13 to have differentiated crystallinity, doping concentration, and thickness, so that the first conductive region 11, the second conductive region 12, and the electrically isolated region 13 can all obtain better structures. Since the crystallinity of the third doped silicon-containing film layer 134 is less than that of the second doped silicon-containing film layer 42, the solution can achieve different crystallinity, doping concentration, and thickness. The third doped silicon-containing layer 134 has a lower conductivity than the second doped silicon-containing layer 42 and the first doped silicon-containing layer 30 due to the layer 42 and the first doped silicon-containing layer 30. This can prevent the carriers transported by the second doped silicon-containing layer 42 and the first doped silicon-containing layer 30 from migrating to the third doped silicon-containing layer 134. Therefore, no additional insulating layer is needed in the isolation region 13, which can also reduce the leakage and short-circuit risks of the isolation region 13 and improve the fill factor and short-circuit current of the back contact heterojunction solar cell.

[0099] Furthermore, the first doped silicon-containing film layer 30 in the first conductive region 11, the second doped silicon-containing film layer 42 in the second conductive region 12, and the third doped silicon-containing film layer 134 in the electrically isolated region 13 are obtained through differentiated laser processing based on the initially formed intrinsic silicon-containing film layer 41' and initially doped silicon-containing film layer 42'. The entire processing is relatively simple, and differentiated processing can be achieved by adjusting the laser processing conditions, making it easy to industrialize and produce. In addition, the entire preparation process uses commonly used procedures and equipment in existing production processes, which helps to control production costs.

[0100] In addition, the above steps S2021 to S2024 modify the initial intrinsic silicon-containing film layer 41' and the initial doped silicon-containing film layer 42' corresponding to the first conductive region 11 and the second conductive region through laser processing, while also forming the first protective layer 40', the second protective layer 40'' and the third protective layer 40''' as masks, avoiding the complex process of additional mask deposition and local patterning, greatly simplifying the process and making it applicable to large-scale industrialization.

[0101] Furthermore, compared with the existing technology that sets different work functions for the n-type functional region and the p-type functional region respectively, the preparation method provided by the present invention can set transparent conductive film layers with the same work function for the first conductive region 11 and the second conductive region 12, ensuring that the first conductive region 11 and the second conductive region 12 form a better match with the transparent conductive film layer, while effectively simplifying the preparation process and facilitating industrialization.

[0102] Furthermore, in step S204 above, a second electrode 62 may also be formed simultaneously on the outside of the transparent conductive film layer 50 corresponding to the second doped silicon-containing film layer 42 in the second conductive region 12. The structural change corresponding to step S204 can be as follows: Figure 5 As shown.

[0103] The above steps are provided only to help understand the method, structure, and core ideas of this invention. Those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A back-contact heterojunction solar cell, characterized in that, include: The crystalline silicon substrate (10) has an alternating arrangement of a first conductive region (11) and a second conductive region (12) on its back side. A carrier collection layer (20) is disposed in the first conductive region (11); the carrier collection layer includes a contact region (21) and a non-contact region (22), the thickness of the non-contact region (22) being less than the thickness of the contact region (21); A first doped silicon-containing film layer (30) is disposed on the outside of the contact region (21), and the doping type of the first doped silicon-containing film layer (30) is opposite to that of the carrier collection layer (20); The second intrinsic silicon-containing film layer (41) and the second doped silicon-containing film layer (42) are sequentially stacked from the inside to the outside in the second conductive region (12). The second doped silicon-containing film layer (42) has the same doping type as the first doped silicon-containing film layer (30). A transparent conductive film layer (50) is disposed on the outside of the first doped silicon-containing film layer (30) and the outside of the second doped silicon-containing film layer (42), and is disconnected between the first conductive region (11) and the second conductive region (12); The first electrode (61) is electrically connected to the transparent conductive film (50) located outside the first doped silicon film layer (30).

2. The back-contact heterojunction solar cell according to claim 1, characterized in that, The crystalline silicon substrate (10) and the carrier collection layer (20) are n-type doped, and the first doped silicon film layer (30) and the second doped silicon film layer (42) are p-type doped; And / or, The doping type of the transparent conductive film layer (50) is opposite to that of the first doped silicon-containing film layer (30); Optionally, the transparent conductive film layer (50) is n-type doped; the first doped silicon-containing film layer (30) is p-type doped; Optionally, the transparent conductive film layer (50) includes doped atoms and includes metal oxides or nitrides, wherein the doped atoms in the transparent conductive film layer (50) include one or more of indium, tin, calcium, aluminum, cadmium, zinc, cerium and fluorine, and the metal oxides in the transparent conductive film layer (50) include one or more of indium oxide, tin oxide, zinc oxide and cadmium oxide; optionally, the nitride in the transparent conductive film layer (50) is titanium nitride.

3. The back-contact heterojunction solar cell according to claim 1, characterized in that, The carrier collection layer (20) includes a tunneling passivation layer (23) and a doped polysilicon layer (24) stacked from the inside to the outside. The thickness of the doped polysilicon layer (24) corresponding to the contact region (21) is greater than the thickness of the doped polysilicon layer (24) corresponding to the non-contact region (22). Optionally, the transparent conductive film layer (50) is also disposed outside the non-contact region (22) of the carrier collection layer; Optionally, the thickness of the doped polysilicon layer (24) corresponding to the contact area (21) is 30nm~200nm, and the thickness of the doped polysilicon layer (24) corresponding to the non-contact area (22) is 20nm~80nm. Optionally, the doping concentration of the doped polycrystalline silicon layer (24) is 5 × 10⁻⁶. 18 atoms / cm 3 ~9×10 19 atoms / cm 3 ; Optionally, the width of the contact area (21) is 20μm to 200μm, and the width of the non-contact area (22) is 80μm to 300μm.

4. The back-contact heterojunction solar cell according to claim 1, characterized in that, The crystallinity of the second doped silicon-containing film layer (42) is less than that of the first doped silicon-containing film layer (30); Optionally, the thickness of the second doped silicon-containing film layer (42) is less than the thickness of the first doped silicon-containing film layer (30); Optionally, the crystallinity of the first doped silicon-containing film layer (30) is 5%~90%; Optionally, the thickness of the second doped silicon-containing film layer (42) is 2 nm to 70 nm; Optionally, the thickness of the first doped silicon film layer (30) is 3 nm to 80 nm.

5. The back-contact heterojunction solar cell according to claim 1, characterized in that, The back side of the crystalline silicon substrate (10) further includes an electrical isolation region (13) disposed between adjacent first conductive region (11) and second conductive region (12), the electrical isolation region (13) including a first isolation region (131) near the first conductive region (11) and a second isolation region (132) near the second conductive region (12). The carrier collection layer (20) extends from the first conductive region (11) to the first isolation region (131); A third intrinsic silicon-containing film layer (133) and a third doped silicon-containing film layer (134) stacked on the outside of the carrier collection layer (20) in the first isolation region (131) and the second isolation region (132) are provided. Optionally, the thickness of the third intrinsic silicon-containing film layer (133) is greater than the thickness of the second intrinsic silicon-containing film layer (41). Optionally, the thickness of the third intrinsic silicon-containing film layer (133) is 2nm~20nm. The thickness of the second intrinsic silicon-containing film layer (41) is 1 nm to 30 nm; Optionally, the crystallinity of the third doped silicon-containing film layer (134) is less than that of the second doped silicon-containing film layer (42); Optionally, the thickness of the third doped silicon-containing film layer (134) is less than the thickness of the second doped silicon-containing film layer (42); Optionally, a portion of the thickness of the third intrinsic silicon-containing film layer (133) is integral with the second intrinsic silicon-containing film layer (41) and is on the same plane; a portion of the thickness of the third doped silicon-containing film layer (134) is integral with the second doped silicon-containing film layer (42) and is on the same plane. Optionally, the doping concentration of the third doped silicon film layer (134) is less than the doping concentration of the first doped silicon film layer (30); Optionally, the width of the electrical isolation region (13) is 5μm to 150μm.

6. The back-contact heterojunction solar cell according to claim 1, characterized in that, Also includes: The second electrode (62) is electrically connected to the transparent conductive film (50) located outside the second doped silicon film (42); Optionally, the height difference between the back side of the crystalline silicon substrate (10) corresponding to the first conductive region (11) and the back side of the crystalline silicon substrate (10) corresponding to the second conductive region (12) is 0 μm to 5 μm.

7. The back-contact heterojunction solar cell according to any one of claims 1 to 6, characterized in that, The first doped silicon-containing film layer (30) includes microcrystalline silicon particles and / or nanocrystalline silicon particles; The first doped silicon-containing film (30) further includes amorphous silicon, and / or the first doped silicon-containing film (30) further includes silicon oxide and / or silicon carbide.

8. A method for fabricating a back-contact heterojunction solar cell, characterized in that, Step S201: Provide a crystalline silicon substrate (10) with alternating first conductive regions (11) and second conductive regions (12) on the back side. Step S202: A carrier collection layer (20) is formed in the first conductive region (11), the carrier collection layer including a contact region (21) and a non-contact region (22), the thickness of the non-contact region (22) being less than the thickness of the contact region (21), and a second intrinsic silicon-containing film layer (41) and a second doped silicon-containing film layer (42) are formed in the second conductive region (12), and a first doped silicon-containing film layer (30) is formed on the outside of the contact region (21), the doping type of the first doped silicon-containing film layer (30) being opposite to the doping type of the carrier collection layer (20) and the same as the doping type of the second doped silicon-containing film layer (42); Step S203: A transparent conductive film layer (50) is formed on the outside of the first doped silicon-containing film layer (30) and the second doped silicon-containing film layer (42), and the transparent conductive film layer (50) is disconnected between the first conductive region (11) and the second conductive region (12); Step S204: Form a first electrode (61) on a transparent conductive film layer (50) located outside the first doped silicon film layer (30).

9. The preparation method according to claim 8, characterized in that, Step S202 specifically includes: Step S2021: A carrier collection layer (20) is formed in the first conductive region (11), and an initial intrinsic silicon-containing film layer (41') and an initial doped silicon-containing film layer (42') are formed on the outside of the carrier collection layer (20) and on the second conductive region (12). Step S2022: The initial intrinsic silicon-containing film layer (41') and the initial doped silicon-containing film layer (42') of the second conductive region (12) are treated with a first laser to form a second intrinsic silicon-containing film layer (41), a second doped silicon-containing film layer (42), and a first protective layer (40'); and the initial intrinsic silicon-containing film layer (41') and the initial doped silicon-containing film layer (42') of the target area of ​​the first conductive region (11) are treated with a second laser to form a first doped silicon-containing film layer (30) and a second protective layer (40''), wherein the energy of the second laser is higher than that of the first laser. Step S2023: Use an alkaline solution to clean and remove the initial intrinsic silicon-containing film layer (41') and the initial doped silicon-containing film layer (42') corresponding to other regions of the first conductive region (11), and thin the carrier collection layer (20) corresponding to other regions of the first conductive region (11) to form a non-contact region (22). The carrier collection layer (20) corresponding to the target region is the contact region (21). Step S2024: Use acid solution to clean and remove the first protective layer (40') and the second protective layer (40'').

10. The preparation method according to claim 9, characterized in that, The back side of the crystalline silicon substrate (10) further includes an electrical isolation region (13) disposed between adjacent first conductive region (11) and second conductive region (12), the electrical isolation region (13) including a first isolation region (131) near the first conductive region (11) and a second isolation region (132) near the second conductive region (12). Step S2021 further includes: synchronously forming the carrier collection layer (20) in the first isolation region (131); Step S2022 further includes: simultaneously forming an initial intrinsic silicon-containing film layer (41') and an initial doped silicon-containing film layer (42') on the outside of the carrier collection layer (20) of the second isolation region (132) and the first isolation region (131); The surfaces of the initial doped silicon-containing film (42') of the second isolation region (132) and the first isolation region (131) are treated with a third laser to form a third intrinsic silicon-containing film (133), a third doped silicon-containing film (134) and a third protective layer (40''') stacked from the inside to the outside in the second isolation region (132) and the first isolation region (131). The energy of the third laser is lower than that of the first laser. Step S2024 further includes: cleaning with an acid solution to remove the third protective layer (40'''); Optionally, the single-spot energy density of the first laser is 50 mJ / cm²–150 mJ / cm²; Optionally, the single-spot energy density of the second laser is 80 mJ / cm² to 250 mJ / cm²; Optionally, the single-spot energy density of the third laser is 10 mJ / cm² to 50 mJ / cm²; Optionally, the carrier collection layer (20) includes a tunneling passivation layer (21) and a doped polysilicon layer (22) stacked from the inside to the outside. Optionally, the thickness of the initial intrinsic silicon-containing film layer (41') is 2 nm to 20 nm; Optionally, the doping concentration of the initial doped silicon-containing film (42') is 1×10⁻⁶. 17 atoms / cm 3 ~5×10 19 atoms / cm 3 ; Optionally, the thickness of the initial doped silicon film (42') is 1 nm to 60 nm.

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