An adjustable PN-type SiC / graphene heterojunction device and its fabrication method

Abstract

This invention discloses an adjustable PN-type SiC / graphene heterojunction device and its fabrication method, belonging to the field of optical sensors. The invention includes: selective high-temperature Al ion implantation and activation of an N-type SiC substrate to form a P-type conversion layer in a predetermined region to construct a PN junction; thermal oxidation and NO atmosphere annealing of the substrate to eliminate amorphous regions and rough structures on the surface; and mechanical transfer of graphene to a predetermined region of the treated substrate to form a SiC / graphene heterojunction. This invention achieves flexible and adjustable PN-type configuration through ion implantation, improves interfacial bonding quality through surface optimization treatment, and simplifies the graphene fabrication process through mechanical transfer. It solves the problems of low fabrication efficiency, simple device structure, and poor interfacial compatibility in existing technologies, and can be widely applied to optoelectronic devices such as high-speed optical modulators and optical sensors.

Description

Technical Field

[0001] This invention relates to the field of optical sensors, and in particular to an adjustable PN-type SiC and graphene heterojunction device and its fabrication method. Background Technology

[0002] SiC (silicon carbide) and graphene heterojunction devices, as a novel type of optoelectronic device, combine the excellent optical properties of SiC with the unique electrical properties of graphene, demonstrating broad application potential. The patents in this technical background cover innovations in the fabrication, structural design, and applications of such heterojunction devices, which will be detailed below.

[0003] First, SiC is a wide-bandgap semiconductor material with excellent optical properties such as high refractive index, dispersion characteristics, and optical transparency. Due to its good optical performance over a wide wavelength range, SiC has become one of the important materials for fabricating optical devices. Meanwhile, graphene is a two-dimensional thin-film material with excellent electrical properties, such as high carrier mobility and wide optical transparency, making it suitable for the electro-tuning and modulation of optical devices. SiC-graphene heterojunction devices combine SiC and the two-dimensional material graphene, fully utilizing the advantages of both to achieve multifunctionality and high performance in optical devices. By introducing a graphene layer into the SiC photonic crystal structure, the optical properties of the SiC photonic crystal can be tuned to achieve light modulation and control. Simultaneously, utilizing the electrically tunable properties of graphene, electro-modulation and electro-optic modulation of light can also be achieved, improving the flexibility and tunability of optical devices. In the field of optical communication, SiC-graphene heterojunction devices have significant application value. By leveraging the fast carrier response of graphene and the high-quality factor resonant cavity of SiC photonic crystals, high-speed optical modulators and photodetectors can be realized, improving the transmission rate and bandwidth of optical communication systems. Furthermore, this technology can also be applied to optical sensing, optical imaging, quantum technology, and other fields, promoting the development and application of related technologies.

[0004] In summary, SiC / graphene heterojunction devices represent the latest advancements in optoelectronics and nanotechnology, with broad application prospects. The patents in this technological background cover innovations in the fabrication, structural design, and applications of these devices, providing crucial technical support for the research and development and application of optical devices.

[0005] The shortcomings of existing technologies: The closest existing technology is the Chinese invention patent CN119133302A, "A method for preparing a heterojunction device of SiC and graphene with adjustable PN type". This patent uses chemical vapor deposition to grow graphene and combine it with a SiC substrate to prepare a heterojunction device. Although it achieves basic optoelectronic functions, it has the following defects: First, the preparation of graphene requires a complex vapor phase growth process, which is inefficient and has poor quality controllability; second, the SiC substrate is not PN type controlled, resulting in a simple device structure and poor adaptability; third, the SiC substrate is not specifically optimized, resulting in low interface bonding quality and poor optoelectronic performance and stability of the device. Summary of the Invention

[0006] To address the complexity of the fabrication process, this invention employs mechanical transfer to bypass the material growth step, enabling rapid and large-scale fabrication of high-performance graphene materials, significantly improving both efficiency and quality. Given the relatively limited range of SiC and graphene devices currently being fabricated, this invention introduces high-temperature ion implantation to achieve PN-type modulation of the SiC surface, making subsequent fabrication of complex, large-scale devices possible. Regarding material compatibility, in addition to the excellent properties of mechanical transfer, this invention specifically subjects the SiC to thermal oxidation and NO annealing treatments to eliminate surface roughness caused by oxidation during wafer storage, thereby optimizing lattice fit conditions.

[0007] The objective of this invention is achieved by at least one of the following technical solutions.

[0008] A method for fabricating an tunable PN-type SiC / graphene heterojunction device includes the following steps: S1: Selective ion implantation and high-temperature activation treatment are performed on the N-type SiC substrate (1) to form a P-type conductive PN-type conversion layer (5) in a preset region of the N-type SiC substrate (1), thereby constructing a PN junction structure on the N-type SiC substrate (1); S2: The N-type SiC substrate (1) on which the PN-type conversion layer (5) is formed is subjected to thermal oxidation treatment, and then annealed in a nitrogen-containing atmosphere to eliminate the amorphous region and rough structure on its surface. S3: Using a mechanical transfer method, the pre-prepared graphene material is transferred to a predetermined area of ​​the N-type SiC substrate (1) after the surface optimization treatment step, so that the graphene material is closely bonded to the N-type SiC substrate (1) to form a SiC / graphene heterojunction structure.

[0009] Furthermore, the specific steps for fabricating the PN-type conversion layer include: S11: Mask layer formation step, forming a mask layer (2) on the surface of the N-type SiC substrate (1); S12: Photolithography window formation step, forming at least one photolithography window (4) on the mask layer (2) to define the ion implantation region; S13: Ion implantation step, implanting P-type doped ions into the N-type SiC substrate (1) through the photolithography window (4); S14: Activation step, the implanted N-type SiC substrate (1) is subjected to high-temperature annealing activation treatment to change the conductivity type of the implanted region from N-type to P-type, forming the PN-type conversion layer (5). S15: Mask layer removal step, removing the remaining mask layer (2).

[0010] Furthermore, the P-type doped ion is an Al ion; the conditions for the ion implantation step are: implantation temperature of 400-500℃ and implantation dose of 1×10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 The injected energy is 50-200 keV; the activation step is performed under an inert gas atmosphere at 900-1000℃ for 1-3 hours.

[0011] Furthermore, in the surface optimization treatment step, the thermal oxidation treatment is carried out in a dry oxygen environment at 1200-1400℃ for 1-3 hours; the annealing treatment is carried out in a NO atmosphere at 900-1100℃ for 0.5-2 hours.

[0012] Furthermore, the steps for forming the heterostructure specifically include: S31: Using a first transfer medium, the graphene single crystal is peeled off from the original growth substrate and transferred to a temporary support substrate to obtain the first graphene; S32: A polymethyl methacrylate layer is formed on a viscous polymer substrate to prepare a second transfer medium; S33: The second transfer medium is applied to the surface of the first graphene and pressed to bond the first graphene with the second transfer medium. Then the second transfer medium is peeled off to obtain the second graphene attached to the second transfer medium. S34: Transfer the second graphene attached to the second transfer medium to a predetermined area of ​​the N-type SiC substrate (1) so that the second graphene adheres to the N-type SiC substrate (1).

[0013] Furthermore, after the surface optimization treatment step and before the heterostructure formation step, an electrode deposition step is also included: depositing a metal electrode (6) in a predetermined area of ​​the N-type SiC substrate (1) to form electrical contacts of the device.

[0014] Furthermore, in the electrode deposition step, the metal electrode (6) is a Ti / Al multilayer metal, which is deposited by electron beam evaporation process, and the thickness of the Ti layer is 30-70 nm and the thickness of the Al layer is 150-250 nm.

[0015] The present invention also provides an adjustable PN-type SiC and graphene heterojunction device, comprising: The N-type SiC substrate (1) has a PN junction structure formed by ion implantation and high temperature activation. The PN junction structure includes an N-type body region and a P-type conversion layer (5). The P-type conversion layer (5) is located in a predetermined area on the surface of the N-type SiC substrate (1). The surface optimization layer, located on the upper surface of the N-type SiC substrate (1), is an atomically smooth surface formed by thermal oxidation and nitrogen atmosphere annealing. The graphene layer is mechanically transferred to the surface optimization layer of the N-type SiC substrate (1) and is in close contact with the surface optimization layer to form a heterojunction interface. A metal electrode (6) is disposed in a predetermined region of the N-type SiC substrate (1) and forms an electrical connection with the N-type SiC substrate (1) and / or the graphene layer.

[0016] Furthermore, the N-type SiC substrate (1) is an N-type 4H-SiC substrate; the internal doping element of the P-type conversion layer (5) is Al.

[0017] Furthermore, the metal electrode (6) includes a Ti / Al stacked electrode, wherein the Ti layer in the Ti / Al stacked electrode is in contact with the N-type SiC substrate (1), and the Al layer is located on top of the Ti layer; the surface optimization layer is a clean and flat N-type SiC crystal surface exposed after removing the sacrificial oxide layer formed by thermal oxidation.

[0018] Compared with the prior art, the present invention has the following significant advantages: Simplified preparation process for large-scale production: The mechanical transfer method is used to prepare graphene, which directly skips the complex graphene growth steps and peels and transfers the graphene from the prepared graphene single crystal. This method can quickly and massively prepare high-performance graphene materials, avoid the complexity and uncertainty of the growth process, greatly improve preparation efficiency, reduce equipment and technology costs, and meet the needs of large-scale production.

[0019] Achieving flexible PN-type adjustment and expanding device functionality: The introduction of high-temperature ion implantation technology to adjust the PN-type of N-type SiC substrates enables precise and controllable conversion from N-type to P-type, solving the problem of the single structure of existing SiC / graphene devices. This provides the possibility for the fabrication of subsequent complex large-scale optoelectronic devices and greatly expands the functionality and application range of the devices.

[0020] Optimize interface quality and improve material compatibility: Dry oxygen thermal oxidation at 1200-1400℃ + NO atmosphere annealing effectively eliminates amorphous regions and oxidation roughness on the SiC substrate surface, optimizing lattice adaptation conditions; combined with the excellent bonding characteristics of mechanical transfer method, it significantly improves the interfacial bonding strength between SiC and graphene, solves the material compatibility problems of lattice mismatch and poor interfacial bonding, and significantly improves the optoelectronic performance and stability of the device.

[0021] The process is highly controllable and the device performance is excellent: the parameters of each process step can be precisely controlled, the dose and depth of ion implantation can be finely adjusted to achieve PN-type conversion, the graphene transfer process can be optimized and screened, the deposition position and size of the Hall electrode can be precisely controlled by photolithography, and the fabricated device has sensitive photoelectric response and stable electrical characteristics, which can meet the application needs of various optoelectronic devices such as optical sensors and high-speed optical modulators. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the mask layer preparation, photolithography, and etching structure during the fabrication of the adjustable PN-type SiC and graphene heterojunction device of the present invention.

[0023] Figure 2 This is a simulation result of the PN-type conversion of the N-type SiC substrate after Al ion implantation in this invention.

[0024] Figure 3 An optical microscope image of the SiC / graphene heterojunction device prepared for this invention.

[0025] Figure 4 The image shows the IV characteristic curves of the SiC / graphene heterojunction device prepared according to this invention. Detailed Implementation

[0026] The specific implementation of the present invention will be further described below with reference to the accompanying drawings and embodiments. However, the implementation and protection of the present invention are not limited thereto. It should be noted that any processes or process parameters that are not described in particular below are those that can be implemented by those skilled in the art with reference to the prior art.

[0027] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and method steps have been omitted so as not to obscure the description of this application with unnecessary detail.

[0028] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. References such as "one embodiment" or "some embodiments" described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and their variations all mean "including but not limited to," unless otherwise specifically emphasized. The following related parameters are not intended to limit the implementation of the technical solutions of the present invention, but are used as examples.

[0029] This embodiment provides a specific fabrication process for an adjustable PN-type SiC / graphene heterojunction device. The method includes key steps such as PN-type conversion layer fabrication, surface optimization treatment, electrode deposition, graphene mechanical transfer, and performance testing. Each step is described in detail below.

[0030] S1: Substrate pretreatment and mask layer preparation A clean N-type SiC substrate 1 is selected as the substrate, and its surface is cleaned and dried. A 2 μm thick SiO2 mask layer 2 is grown on the surface of the N-type SiC substrate 1 by vertical low-pressure chemical vapor deposition (LPCVD) to complete the mask preparation before ion implantation. This step can be carried out by selecting either N-type to P-type or P-type to N-type process direction according to the requirements.

[0031] S2: Area to be etched, formed by photolithography process Positive photoresist 3 is spin-coated on the surface of SiO2 mask layer 2. Photolithography is used for exposure and development to remove the positive photoresist 3 in the preset area, forming an array of photolithography windows 4 to obtain the area to be etched for ion implantation. The photolithography windows 4 penetrate the positive photoresist 3 layer to the surface of SiO2 mask layer 2.

[0032] S3: Etching and Shaping Ion Implantation Window Using inductively coupled plasma (ICP) electron beam etching, the SiO2 mask layer 2 that is not covered by positive photoresist 3 is selectively etched. After etching, acid washing is used to remove the residual positive photoresist 3 on the surface, forming a SiO2 mask structure with an array of implantation windows on the surface of the N-type SiC substrate 1. The implantation windows provide a precise channel for Al ion implantation.

[0033] S4: High-temperature ion implantation and PN-type conversion An ion implanter was used to implant high-temperature Al ions into an N-type SiC substrate 1 through an implantation window. After implantation, the substrate was subjected to high-temperature activation treatment, which caused the N-type SiC in the implanted region to undergo inversion to form a P-type region, namely the PN-type conversion layer 5. The simulation verified that a clear PN-type conversion effect could be observed. Throughout the process, the implanted object was uniformly defined as the entire N-type SiC substrate 1.

[0034] S5: Mask layer removal A composite process combining dry etching and buffered oxide etching (BOE) wet immersion was used to completely remove the 2μm SiO2 mask layer 2 deposited on the surface of the N-type SiC substrate 1, while retaining the complete composite structure of the N-type SiC substrate 1 and the PN-type conversion layer 5.

[0035] S6: Surface optimization treatment of SiC substrate The N-type SiC substrate 1 after removing the mask layer was placed in a dry oxygen environment at 1350℃ for thermal oxidation treatment, and then annealed in a NO atmosphere to eliminate the amorphous regions and surface roughness on the SiC substrate surface caused by production or air storage, optimize the lattice adaptation conditions, and improve the interfacial bonding performance with graphene.

[0036] S7: Thermal oxidation sacrificial layer removal The SiO2 thermal oxidation sacrificial layer formed on the surface of the SiC substrate after the thermal oxidation treatment in step S6 is removed by using the BOE wet immersion process, resulting in a flat and clean N-type SiC substrate 1.

[0037] S8: Hall electrode deposition A predetermined photolithography pattern was prepared on the surface of an optimized N-type SiC substrate 1 using vertical exposure technology. Ti / Al metal was then deposited in the preset area corresponding to the photolithography pattern using electron beam evaporation to form a Ti / Al Hall electrode 6, thus completing the fabrication of the device's electrical structure.

[0038] S9: Graphene mechanical transfer and heterostructure formation (1) Use a tape of appropriate viscosity to peel off the graphene single crystal, and attach a portion of the graphene single crystal to the tape A; (2) Select a silicon wafer and pre-treat it by drying at 50°C for 5 min, and transfer the graphene on the tape A to the surface of the pre-treated silicon wafer to obtain graphene A; (3) Drop the prepared PMMA solution onto the cut PDMS, and dry it at 50°C for 8 min to prepare viscous transfer material A; (4) Cover the surface of graphene A with transfer material A and perform mechanical pressing treatment, peel off to obtain the preferred graphene B; (5) Accurately transfer graphene B to the predetermined area of ​​the N-type SiC substrate 1 on which the Ti / Al Hall electrode 6 has been prepared, so that the graphene and the SiC substrate are closely bonded to form a SiC / graphene heterojunction structure.

[0039] S10: Device Performance Testing The photoelectric performance of the fabricated SiC / graphene heterojunction device was tested, and the photoelectric response characteristics of the device were verified by characterization methods such as IV curves, thus completing the overall fabrication of the device.

[0040] Example 1 A method for fabricating an tunable PN-type SiC / graphene heterojunction device includes the following steps: Step 1: Substrate selection and pretreatment An N-type 4H-SiC substrate 1 was selected as the substrate. The substrate was ultrasonically cleaned sequentially with acetone, anhydrous ethanol, and deionized water for 10 minutes, 10 minutes, and 15 minutes, respectively, and then dried with nitrogen gas to obtain a clean substrate surface.

[0041] Step 2: Mask layer preparation A 2 μm thick SiO2 mask layer 2 was grown on the surface of an N-type SiC substrate 1 using vertical low-pressure chemical vapor deposition (LPCVD). The growth conditions were: temperature 700℃, pressure 100 Pa, and growth rate 5 nm / min. Figure 1 As shown in the first image, the grown SiO2 mask layer 2 completely covers the surface of the N-type SiC substrate 1, with the edges of the two layers completely overlapping.

[0042] Step 3: Photolithography process to form the photolithographic window Positive photoresist 3 is spin-coated onto the surface of the SiO2 mask layer 2. Spin-coating parameters: spin speed 3000 r / min, time 30 s, followed by pre-baking on a 90℃ hot plate for 90 s. Photolithography is then performed with an exposure dose of 100 mJ / cm² and a development time of 60 s to remove the positive photoresist 3 from the predetermined area, forming an array of photolithographic windows 4. The photolithographic windows 4 penetrate the positive photoresist 3 layer to the surface of the SiO2 mask layer 2. Figure 1 As shown in the second image, several rectangular cutout areas are uniformly opened in the photoresist layer, which are the photolithography windows 4. The windows are distributed in an array.

[0043] Step 4: Etching to shape the ion implantation window The SiO2 mask layer 2, which was not covered by the positive photoresist 3, was selectively etched using inductively coupled plasma (ICP) electron beam etching. The etching power was 500W, and the etching time was 300s. After etching, the surface was rinsed with a 1:1 sulfuric acid-hydrogen peroxide mixture for 10 minutes to remove any residual positive photoresist 3. Figure 1 As shown in the third figure, after etching and removing the resist, the surface of the N-type SiC substrate 1 retains the array of protrusions formed by the SiO2 mask layer. The hollow channels between the protrusions are the injection windows 4, forming a mesa pattern with a spacing of 1 cm.

[0044] Step 5: High-temperature ion implantation and PN-type conversion High-temperature Al ion implantation was performed on an N-type SiC substrate 1 using an ion implanter through an implantation window. Implantation conditions: implantation temperature 450℃, implantation dose 1×10⁻⁶. 20 cm -3 The injection energy was 200 keV. After injection, it was activated at 950℃ for 2 hours under an argon atmosphere, causing the N-type SiC in the injected region to invert and form a P-type region, i.e., the PN-type conversion layer 5. Figure 1 As shown in the fourth image, a P-type ion implantation layer was formed in the window area on the substrate surface after implantation. Figure 2 The graph shows the simulation results of ion implantation PN-type conversion. The horizontal axis represents the implantation depth (Microns), and the vertical axis represents the carrier concentration ( / cm²). -3 The figure shows the concentration ranges of n-type and p-type carriers marked with black lines, clearly displaying the concentration difference between the Al ion implantation region (P-type) and the original N-type SiC region. The PN-type conversion boundary is also marked, with the P-type region to the left of the boundary and the original N-type region to the right. The 4H-SiC material type is marked within the simulation area.

[0045] Step 6: Mask layer removal A composite process combining dry etching and buffered oxide etching (BOE) wet immersion was used to remove the SiO2 mask layer 2. First, dry etching was performed at an etching rate of 10 nm / min, followed by BOE wet immersion for 20 minutes to completely remove the 2 μm SiO2 mask layer 2 deposited on the surface of the N-type SiC substrate 1, while preserving the complete composite structure of the N-type SiC substrate 1 and the PN-type conversion layer 5.

[0046] Step 7: SiC substrate surface optimization treatment The N-type SiC substrate 1 after removing the mask layer was placed in a dry oxygen environment at 1350℃ for thermal oxidation treatment for 2 hours, and then annealed at 1000℃ for 1 hour in a NO atmosphere to eliminate the amorphous regions and surface roughness on the SiC substrate surface caused by production or air storage, optimize the lattice adaptation conditions, and improve the interfacial bonding performance with graphene.

[0047] Step 8: Removal of the sacrificial layer by thermal oxidation The SiC substrate after the thermal oxidation treatment in step 7 was immersed for 15 minutes using the BOE wet immersion process to remove the SiO2 thermal oxidation sacrificial layer formed on the surface of the SiC substrate after the thermal oxidation treatment. Then, it was dried with nitrogen to obtain a smooth and clean N-type SiC substrate 1.

[0048] Step 9: Hall electrode deposition A predetermined photolithographic pattern was prepared on the surface of an optimized N-type SiC substrate 1 using vertical exposure technology. Ti / Al metal was then deposited in the predetermined area corresponding to the photolithographic pattern using electron beam evaporation to form a Ti / Al Hall electrode 6. The Ti layer thickness was 50 nm, and the Al layer thickness was 200 nm. Figure 3 As shown in the image (optical microscope image of SiC / graphene heterojunction, black and white format), several regular rectangular structures on the substrate surface are Ti / Al Hall electrodes, which are uniformly distributed in the preset area.

[0049] Step 10: Graphene mechanical transfer and heterostructure formation (1) Use a tape of suitable viscosity to peel off the graphene single crystal, and attach a portion of the graphene single crystal to the tape A; (2) Select a silicon wafer and pre-treat it by drying at 50°C for 5 min, then transfer the graphene on the tape A to the surface of the pre-treated silicon wafer to obtain graphene A; (3) Drop the prepared PMMA solution onto the cut PDMS, and dry it at 50°C for 8 min to prepare viscous transfer material A; (4) Cover the surface of graphene A with transfer material A and perform mechanical pressing treatment, peeling off to obtain the preferred graphene B; (5) Accurately transfer graphene B to the predetermined area of ​​the N-type SiC substrate 1 on which the Ti / Al Hall electrode (6) has been prepared, so that the graphene and the SiC substrate are tightly bonded to form a SiC / graphene heterojunction structure. Figure 3 As shown, the continuous thin film area covering the electrode surface and the preset area of ​​the substrate is the graphene layer, which is closely attached to the SiC substrate and the Hall electrode without obvious gaps or wrinkles.

[0050] Step 11: Device Performance Testing The photoelectric performance of the fabricated SiC / graphene heterojunction device was tested. IV characteristic curves were measured under both dark and white light conditions to verify the device's photoelectric response characteristics. Figure 4As shown, the horizontal axis represents the bias voltage Vds (V), ranging from -1.0 to 1.0V, and the vertical axis represents the current (A). The font size of the axes is 12pt. The figure contains two black curves, labeled White (under white light) and Dark (under dark light), respectively, to show the IV response characteristics of the device under different illumination conditions. The curves are smooth and clearly reflect the photoelectric response sensitivity of the device.

[0051] Through the above steps, this embodiment successfully fabricated an adjustable PN-type SiC and graphene heterojunction device, which has an adjustable PN junction structure, a high-quality heterojunction interface, and excellent photoelectric response performance.

[0052] Example 2 A method for fabricating an tunable PN-type SiC / graphene heterojunction device includes the following steps: Step 1: Substrate selection and pretreatment An N-type 4H-SiC substrate 1 was selected as the substrate. The substrate was ultrasonically cleaned sequentially with acetone, anhydrous ethanol, and deionized water for 10 minutes, 10 minutes, and 15 minutes, respectively, and then dried with nitrogen gas to obtain a clean substrate surface.

[0053] Step 2: Mask layer preparation A 2 μm thick SiO2 mask layer 2 was grown on the surface of an N-type SiC substrate 1 using vertical low-pressure chemical vapor deposition (LPCVD). The growth conditions were: temperature 700℃, pressure 100 Pa, and growth rate 5 nm / min. Figure 1 As shown in the first image, the grown SiO2 mask layer 2 completely covers the surface of the N-type SiC substrate 1, with the edges of the two layers completely overlapping.

[0054] Step 3: Photolithography process to form the photolithographic window Positive photoresist 3 is spin-coated onto the surface of the SiO2 mask layer 2. Spin-coating parameters: spin speed 4000 r / min, time 30 s, followed by pre-baking on a 90℃ hot plate for 90 s. Photolithography is then performed with an exposure dose of 100 mJ / cm² and a development time of 50 s to remove the positive photoresist 3 from the predetermined area, forming an array of photolithographic windows 4. The photolithographic windows 4 penetrate the positive photoresist 3 layer to the surface of the SiO2 mask layer 2. Figure 1 As shown in the second image, several rectangular cutout areas are uniformly opened in the photoresist layer, which are the photolithography windows 4. The windows are distributed in an array.

[0055] Step 4: Etching to shape the ion implantation window Selective etching of the SiO2 mask layer 2, which was not covered by the positive photoresist 3, was performed using inductively coupled plasma (ICP) electron beam etching. The etching power was 600W, and the etching time was 250s. After etching, the surface was rinsed with a 1:1 sulfuric acid-hydrogen peroxide mixture for 10 minutes to remove any residual positive photoresist 3. Figure 1 As shown in the third figure, after etching and removing the resist, the surface of the N-type SiC substrate 1 retains the array of protrusions formed by the SiO2 mask layer. The hollow channels between the protrusions are the injection windows 4, forming a mesa pattern with a spacing of 1 cm.

[0056] Step 5: High-temperature ion implantation and PN-type conversion High-temperature Al ion implantation was performed on an N-type SiC substrate 1 using an ion implanter through an implantation window. Implantation conditions: implantation temperature 500℃, implantation dose 1×10¹ 9 cm -3 The injection energy was 100 keV. After injection, it was activated at 950℃ for 2 hours under an argon atmosphere, causing the N-type SiC in the injected region to invert and form a P-type region, i.e., the PN-type conversion layer 5. Figure 1 As shown in the fourth image, a P-type ion implantation layer was formed in the window area on the substrate surface after implantation. Figure 2 The figure shows the simulation results of PN-type conversion by ion implantation. The horizontal axis represents the implantation depth (Microns), and the vertical axis represents the carrier concentration ( / cm³). The n-type and p-type carrier concentration ranges are marked with black lines in the figure, clearly showing the concentration difference between the Al ion implantation region (P-type) and the original N-type SiC region. The PN-type conversion boundary is also marked. The P-type region is on the left side of the boundary, and the original N-type region is on the right side. The 4H-SiC material type is marked in the simulation area.

[0057] Step 6: Mask layer removal A composite process combining dry etching and buffered oxide etching (BOE) wet immersion was used to remove the SiO2 mask layer 2. First, dry etching was performed at an etching rate of 10 nm / min, followed by BOE wet immersion for 20 minutes to completely remove the 2 μm SiO2 mask layer 2 deposited on the surface of the N-type SiC substrate 1, while preserving the complete composite structure of the N-type SiC substrate 1 and the PN-type conversion layer 5.

[0058] Step 7: SiC substrate surface optimization treatment The N-type SiC substrate 1 after removing the mask layer was placed in a dry oxygen environment at 1300℃ for thermal oxidation treatment for 3 hours, and then annealed at 1000℃ for 1 hour in a NO atmosphere to eliminate the amorphous regions and surface roughness on the SiC substrate surface caused by production or air storage, optimize lattice adaptation conditions, and improve the interfacial bonding performance with graphene.

[0059] Step 8: Removal of the sacrificial layer by thermal oxidation The SiC substrate after the thermal oxidation treatment in step 7 was immersed for 15 minutes using the BOE wet immersion process to remove the SiO2 thermal oxidation sacrificial layer formed on the surface of the SiC substrate after the thermal oxidation treatment. Then, it was dried with nitrogen to obtain a smooth and clean N-type SiC substrate 1.

[0060] Step 9: Hall electrode deposition A predetermined photolithographic pattern was prepared on the surface of an optimized N-type SiC substrate 1 using vertical exposure technology. Ti / Al metal was then deposited in the predetermined area corresponding to the photolithographic pattern using electron beam evaporation to form a Ti / Al Hall electrode 6. The Ti layer thickness was 50 nm, and the Al layer thickness was 200 nm. Figure 3 As shown in the image (optical microscope image of SiC / graphene heterojunction, black and white format), several regular rectangular structures on the substrate surface are Ti / Al Hall electrodes, which are uniformly distributed in the preset area.

[0061] Step 10: Graphene mechanical transfer and heterostructure formation (61) Use a tape of suitable viscosity to peel off the graphene single crystal, and attach a portion of the graphene single crystal to the tape A; (2) Select a silicon wafer and pre-treat it by drying at 100°C for 3 min, then transfer the graphene on the tape A to the surface of the pre-treated silicon wafer to obtain graphene A; (3) Drop the prepared PMMA solution onto the cut PDMS, and dry it at 100°C for 5 min to prepare viscous transfer material A; (4) Cover the surface of graphene A with transfer material A and perform mechanical pressing treatment, peel off to obtain the preferred graphene B; (5) Accurately transfer graphene B to the predetermined area of ​​the N-type SiC substrate 1 on which the Ti / Al Hall electrode (6) is prepared, so that the graphene and the SiC substrate are tightly bonded to form a SiC / graphene heterojunction structure. Figure 3 As shown, the continuous thin film area covering the electrode surface and the preset area of ​​the substrate is the graphene layer, which is closely attached to the SiC substrate and the Hall electrode without obvious gaps or wrinkles.

[0062] Step 11: Device Performance Testing The photoelectric performance of the fabricated SiC / graphene heterojunction device was tested. IV characteristic curves were measured under both dark and white light conditions to verify the device's photoelectric response characteristics. Figure 4 As shown, the horizontal axis represents the bias voltage Vds (V), ranging from -1.0 to 1.0V, and the vertical axis represents the current (A). The font size of the axes is 12pt. The figure contains two black curves, labeled White (under white light) and Dark (under dark light), respectively, to show the IV response characteristics of the device under different illumination conditions. The curves are smooth and clearly reflect the photoelectric response sensitivity of the device.

[0063] Through the above steps, this embodiment successfully fabricated an adjustable PN-type SiC and graphene heterojunction device, which has an adjustable PN junction structure, a high-quality heterojunction interface, and excellent photoelectric response performance.

[0064] The above embodiments are merely preferred examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, can make various modifications and changes in form and detail according to the method of the present invention without departing from the principles and scope of the present invention. However, these modifications and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims

1. A method for fabricating an tunable PN-type SiC / graphene heterojunction device, characterized in that, Includes the following steps: S1: Selective ion implantation and high-temperature activation treatment are performed on the N-type SiC substrate (1) to form a P-type conductive PN-type conversion layer (5) in a preset region of the N-type SiC substrate (1), thereby constructing a PN junction structure on the N-type SiC substrate (1); S2: The N-type SiC substrate (1) on which the PN-type conversion layer (5) is formed is subjected to thermal oxidation treatment, and then annealed in a nitrogen-containing atmosphere to eliminate the amorphous region and rough structure on its surface. S3: Using a mechanical transfer method, the pre-prepared graphene material is transferred to a predetermined area of ​​the N-type SiC substrate (1) after the surface optimization treatment step, so that the graphene material is closely bonded to the N-type SiC substrate (1) to form a SiC / graphene heterojunction structure.

2. The preparation method according to claim 1, characterized in that, The specific steps for fabricating the PN-type conversion layer include: S11: Mask layer formation step, forming a mask layer (2) on the surface of the N-type SiC substrate (1); S12: Photolithography window formation step, firstly, photoresist is applied to the mask layer (2) to form a photoresist coating layer (3), and then at least one photolithography window (4) is formed to define the ion implantation region; S13: Ion implantation step, implanting P-type doped ions into the N-type SiC substrate (1) through the photolithography window (4); S14: Activation step, the implanted N-type SiC substrate (1) is subjected to high-temperature annealing activation treatment to change the conductivity type of the implanted region from N-type to P-type, forming the PN-type conversion layer (5). S15: Mask layer removal step, removing the remaining mask layer (2).

3. The preparation method according to claim 2, characterized in that, The P-type doped ion is an Al ion; the conditions for the ion implantation step are: implantation temperature of 400-500℃ and implantation dose of 1×10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 The injected energy is 50-200 keV; the activation conditions are: activation at 1000-1300℃ for 1-3 hours in an inert gas atmosphere.

4. The preparation method according to claim 1, characterized in that, In the surface optimization treatment steps, the thermal oxidation treatment is carried out in a dry oxygen environment at 1200-1400℃ for 1-3 hours; the annealing treatment is carried out in a NO atmosphere at 900-1100℃ for 0.5-2 hours.

5. The preparation method according to claim 1, characterized in that, The steps involved in forming the heterostructure specifically include: S31: Using a first transfer medium, the graphene single crystal is peeled off from the original growth substrate and transferred to a temporary support substrate to obtain the first graphene; S32: A polymethyl methacrylate layer is formed on a viscous polymer substrate to prepare a second transfer medium; S33: The second transfer medium is applied to the surface of the first graphene and pressed to bond the first graphene with the second transfer medium. Then the second transfer medium is peeled off to obtain the second graphene attached to the second transfer medium. S34: Transfer the second graphene attached to the second transfer medium to a predetermined area of ​​the N-type SiC substrate (1) so that the second graphene adheres to the N-type SiC substrate (1).

6. The preparation method according to claim 1, characterized in that, After the surface optimization treatment step and before the heterostructure formation step, an electrode deposition step is also included: depositing a metal electrode (6) in a predetermined region of the N-type SiC substrate (1) to form electrical contacts of the device.

7. The preparation method according to claim 6, characterized in that, In the electrode deposition step, the metal electrode (6) is a Ti / Al stacked metal, which is deposited by electron beam evaporation process, and the thickness of the Ti layer is 30-70 nm and the thickness of the Al layer is 150-250 nm.

8. An adjustable PN-type SiC / graphene heterojunction device prepared by the preparation method according to any one of claims 1-7, characterized in that, include: The N-type SiC substrate (1) has a PN junction structure formed by ion implantation and high temperature activation. The PN junction structure includes an N-type body region and a P-type conversion layer (5). The P-type conversion layer (5) is located in a predetermined area on the surface of the N-type SiC substrate (1). The surface optimization layer, located on the upper surface of the N-type SiC substrate (1), is an atomically smooth surface formed by thermal oxidation and nitrogen atmosphere annealing. The graphene layer is mechanically transferred to the surface optimization layer of the N-type SiC substrate (1) and is in close contact with the surface optimization layer to form a heterojunction interface. A metal electrode (6) is disposed in a predetermined region of the N-type SiC substrate (1) and forms an electrical connection with the N-type SiC substrate (1) and / or the graphene layer.

9. The heterojunction device according to claim 8, characterized in that, The N-type SiC substrate (1) is an N-type 4H-SiC substrate; the internal doping element of the P-type conversion layer (5) is Al.

10. The heterojunction device according to claim 9, characterized in that, The metal electrode (6) includes a Ti / Al stacked electrode, wherein the Ti layer in the Ti / Al stacked electrode is in contact with the N-type SiC substrate (1), and the Al layer is located on the Ti layer; the surface optimization layer is a clean and flat N-type SiC crystal surface exposed after removing the sacrificial oxide layer formed by thermal oxidation.

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