A method for fabricating optoelectronic devices based on the negative quantum capacitance effect and the optoelectronic device itself.

Abstract

This invention relates to the field of electronic component design and manufacturing technology, and discloses a method for fabricating an optoelectronic device based on the negative quantum capacitance effect and the optoelectronic device itself. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a floating gate layer on the dielectric layer, the floating gate layer being composed of a topological half-metal material; forming a tunneling layer on the floating gate layer; forming a channel layer on the tunneling layer, the channel layer being composed of a two-dimensional semiconductor material; forming source and drain electrodes, making the source and drain electrodes electrically contacting the channel layer; and performing annealing in an inert atmosphere to improve the interfacial contact between the layers. This invention provides a multifunctional integrated optoelectronic device that utilizes the negative quantum capacitance effect of topological half-metals to simultaneously realize both multi-state non-volatile storage and artificial synapse functions in the same device, providing a novel basic unit for the fusion of high-density storage and neuromorphic computing.

Description

Technical Field

[0001] This invention relates to the field of electronic component design and manufacturing technology, and in particular to a method for preparing an optoelectronic device based on the negative quantum capacitance effect and the optoelectronic device itself. Background Technology

[0002] With the advent of the era of big data and artificial intelligence, traditional single-function electronic devices can no longer meet the combined demands of intelligent systems for high-density information storage and efficient parallel computing. On the one hand, the storage density of traditional binary memory is approaching physical limits, and polymorphic memory technology has become a breakthrough direction because it can store multiple bits of information in a single memory cell; however, existing polymorphic memories often rely on complex spintronic structures or require high-voltage programming, making it difficult to balance low power consumption and high state stability. On the other hand, neuromorphic computing requires the underlying hardware to simulate the plasticity of biological synapses and achieve in-memory computing; however, existing artificial synapse devices have relatively simple functions, usually focusing only on synaptic behavior simulation and lacking the integration of polymorphic non-volatile storage capabilities.

[0003] Furthermore, traditional floating-gate devices often require thick tunneling dielectric layers to achieve sufficiently long data retention times, resulting in programming voltages as high as tens of volts and energy consumption on the order of picojoules per operation, making it difficult to reduce power consumption while maintaining state stability. Therefore, there is an urgent need to develop a low-power integrated device capable of simultaneously realizing multi-state storage and artificial synaptic functions. The negative quantum capacitance effect, as a novel physical mechanism that can generate voltage amplification within a device, holds promise for forming multiple distinguishable channel conductance states with a very small amount of stored charge, fundamentally resolving the energy consumption and performance contradiction in functional integration. However, this effect is difficult to achieve in conventional materials. How to design a low-power device that combines multi-state non-volatile storage and artificial synaptic functions using new materials and structures is currently a hot research topic and frontier.

[0004] For example, the existing technology CN120676664A uses a top-gate structure with the channel stacked first and the gate stacked in that order. The negative quantum capacitance effect is used to amplify the gate voltage, thereby increasing the total capacitance and reducing the subthreshold swing. This breaks through the Boltzmann limit of 60 mV / dec and improves the switching speed of the device. It does not involve charge storage or built-in electric field enhancement. Summary of the Invention

[0005] This invention addresses the problem that existing multistate memories often rely on complex spintronic structures or require high-voltage programming, making it difficult to balance low power consumption and high state stability. It provides a method for fabricating optoelectronic devices based on the negative quantum capacitance effect and the optoelectronic device itself.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: A method for fabricating an optoelectronic device based on the negative quantum capacitance effect, the method comprising: Provide substrate; A dielectric layer is formed on the substrate; A floating gate layer is formed on the dielectric layer, the floating gate layer being made of a topologically semi-metallic material; A tunneling layer is formed on the floating grid layer; A trench layer is formed on the tunneling layer, and the trench layer is made of a two-dimensional semiconductor material; A source electrode and a drain electrode are formed, and the source electrode and the drain electrode are electrically contacted with the channel layer; Annealing is performed in an inert atmosphere to improve the interfacial contact between layers; The floating gate layer is configured such that, after charge tunneling injection, its Fermi level is tuned to the vicinity of the topological node, thereby generating a negative quantum capacitance effect.

[0007] Preferably, the topological semimetal material includes Weyl semimetal or Dirac semimetal.

[0008] Preferably, the Weyl semimetal comprises WTe2 or MoTe2.

[0009] Preferably, the two-dimensional semiconductor material includes transition metal chalcogenides, black phosphorus, and indium selenide.

[0010] Preferably, the dielectric layer and the tunneling layer comprise a two-dimensional insulating material or a high dielectric constant dielectric material.

[0011] Preferably, the two-dimensional insulating material includes hexagonal boron nitride, and the high dielectric constant dielectric material includes aluminum oxide, hafnium oxide, and silicon oxide.

[0012] Preferably, the substrate is a conductive substrate and also serves as a bottom gate electrode; or the substrate is an insulating substrate or a semiconductor substrate, and an independent bottom gate electrode is disposed above or inside the substrate.

[0013] Preferably, the source electrode and drain electrode comprise at least one of a Cr / Au composite layer, a Ti / Au composite layer, a Pd / Au composite layer, a Cr / Pt layer, or a graphene conductive layer.

[0014] Preferably, the dielectric layer, floating gate layer, tunneling layer and channel layer are formed by at least one of mechanical stripping, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0015] To address the aforementioned technical problems, this application also provides an optoelectronic device based on the negative quantum capacitance effect, which is fabricated using the aforementioned method for fabricating an optoelectronic device based on the negative quantum capacitance effect; comprising: Substrate; A node layer, on which a dielectric layer is formed, is formed on the substrate; A floating gate layer is formed on the dielectric layer, and the floating gate layer is made of a topologically semi-metallic material; A tunneling layer is formed on the floating grid layer; A trench layer is formed on the tunneling layer, and the trench layer is made of a two-dimensional semiconductor material; Source and drain electrodes are formed to make the source and drain electrodes electrically contact the channel layer. Annealing is performed in an inert atmosphere to improve the interfacial contact between layers; The floating gate layer is configured such that, after charge tunneling injection, its Fermi level is tuned to the vicinity of the topological node, thereby generating a negative quantum capacitance effect. This invention, by adopting the above technical solutions, has significant technical effects: This invention provides a multifunctional integrated optoelectronic device that utilizes the negative quantum capacitance effect of topological half-metals to simultaneously realize both multi-state non-volatile storage and artificial synapse functions in the same device, providing a novel basic unit for the fusion of high-density storage and neuromorphic computing.

[0016] The optoelectronic device designed in this invention can establish 128 discrete and stable conductance states in terms of multi-state storage, and can maintain each state without decay for a long time under zero gate voltage. The programming and reading paths are naturally separated, avoiding read-write crosstalk. The device structure is simple, requiring no auxiliary magnetic field or special nucleation process, and is easy to integrate at high density.

[0017] In the field of artificial synapses, this invention allows multiple conductance states to be directly mapped to synaptic weights, successfully simulating synaptic behaviors such as double-pulse facilitation, short-term plasticity, and long-term enhancement / inhibition, with excellent cycle durability. It achieves ultra-low readout power consumption of less than 1 fJ, lower than that of biological synapses, providing a novel synaptic unit for constructing low-power neuromorphic chips integrating in-memory computing. Attached Figure Description

[0018] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the structure of the two-dimensional optoelectronic device of the present invention. Figure 1 .

[0019] Figure 2 This is a schematic diagram of the structure of the two-dimensional optoelectronic device of the present invention. Figure 2 .

[0020] Figure 3 This is a graph showing the output characteristics of the present invention.

[0021] Figure 4 This is a graph showing the transfer characteristics of the optoelectronic device of the present invention under different gate voltage scanning ranges.

[0022] Figure 5 This is a graph showing the change in synaptic plasticity of the optoelectronic device of the present invention under different optical power densities.

[0023] Figure 6 This is a graph showing the change in synaptic plasticity of the optoelectronic device of the present invention under different light pulse numbers.

[0024] Figure 7 This is a graph showing the synaptic plasticity variation of the functional optoelectronic device of the present invention with different light pulse widths.

[0025] Figure 8 This is a graph showing the change of the dual-pulse facilitation index of the optoelectronic device of the present invention with the pulse interval.

[0026] Figure 9 This is a graph showing the long-term performance characteristics of the optoelectronic device of the present invention.

[0027] Figure 10 This is a graph showing the low-energy consumption characteristics of the optoelectronic device of the present invention.

[0028] Figure 11 This is a graph showing the cyclic long-term enhancement / long-term suppression characteristics of the optoelectronic device of the present invention.

[0029] Figure 12 This invention aims to maintain 128 discrete stable conductance states within 180 seconds under zero gate voltage conditions.

[0030] Among them, 1—substrate, 2—source electrode, 3—drain electrode, 4—dielectric layer, 5—floating gate layer, 6—tunneling layer, and 7—channel layer. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0032] Example 1

[0033] This embodiment provides a two-dimensional photoelectric synapse device based on the negative quantum capacitance effect, the structure of which is as follows: Figure 1 The diagram shows a vertically stacked heterojunction structure. Specifically, it includes: Substrate 1 uses heavily doped p-type silicon with SiO2 on its surface as the back gate electrode; Both source 2 and drain 3 are located on the substrate and are composite metal layers composed of 5 nm Ti and 30 nm Au. Dielectric layer 4 is located between the source and drain electrodes and does not overlap with the source and drain electrodes. It is a mechanically peeled h-BN thin layer with a thickness of approximately 10.5 nm. The floating gate layer 5 is located on the dielectric layer 4 and is a mechanically peeled WTe2 thin layer with a thickness of approximately 2.2 nm. The tunneling layer 6 is located on the floating gate layer 5 and is a mechanically exfoliated two-dimensional h-BN material with a thickness of approximately 19.7 nm. The channel layer 7 is located on the tunneling layer 6 and is a mechanically exfoliated two-dimensional MoS2 material with a thickness of approximately 21.5 nm.

[0034] In this device, the source and drain electrodes are not in direct contact with the floating gate layer or the tunneling layer, but only with the channel layer. The channel layer is located at the top of the device and is capacitively coupled and modulated through the tunneling layer and the floating gate layer.

[0035] All two-dimensional sheets were obtained by mechanical exfoliation and then stacked sequentially in a glove box using a dry transfer technique to prevent material oxidation and ensure atomically clear interfaces.

[0036] Example 2

[0037] This embodiment provides a two-dimensional photoelectric synapse device based on the negative quantum capacitance effect, the structure of which is as follows: Figure 1 The diagram shows a vertically stacked heterojunction structure. Specifically, it includes: Substrate 1 uses heavily doped p-type silicon with SiO2 on its surface as the back gate electrode; Both source 2 and drain 3 are located on the substrate and are composite metal layers composed of 5 nm Cr and 30 nm Au; Dielectric layer 4 is located between the source and drain electrodes and does not overlap with the source and drain electrodes. It is a mechanically peeled h-BN thin layer with a thickness of about 8 nm. The floating gate layer 5 is located on the dielectric layer 4 and is a mechanically peeled WTe2 thin layer with a thickness of about 4nm. The tunneling layer 6 is located on the floating gate layer 5 and is a mechanically exfoliated two-dimensional h-BN material with a thickness of approximately 10.3 nm. The channel layer 7 is located on the tunneling layer 6 and is a mechanically exfoliated two-dimensional MoS2 material with a thickness of approximately 18.5 nm.

[0038] In this device, the source and drain electrodes are not in direct contact with the floating gate layer or the tunneling layer, but only with the channel layer. The channel layer is located at the top of the device and is capacitively coupled and modulated through the tunneling layer and the floating gate layer.

[0039] All two-dimensional sheets were obtained by mechanical exfoliation and then stacked sequentially in a glove box using a dry transfer technique to prevent material oxidation and ensure atomically clear interfaces.

[0040] Example 3

[0041] This embodiment provides a two-dimensional photoelectric synapse device based on the negative quantum capacitance effect, the structure of which is as follows: Figure 1The diagram shows a vertically stacked heterojunction structure. Specifically, it includes: Substrate 1 uses heavily doped p-type silicon with SiO2 on its surface as the back gate electrode; Both source 2 and drain 3 are located on the substrate, which is a composite metal layer composed of 3 nm Ti and 20 nm Au. Dielectric layer 4 is located between the source and drain electrodes and does not overlap with the source and drain electrodes. It is a mechanically peeled h-BN thin layer with a thickness of approximately 10.3 nm. The floating gate layer 5 is located on the dielectric layer 4 and is a mechanically peeled MoTe2 thin layer with a thickness of approximately 3.8 nm. The tunneling layer 6 is located on the floating gate layer 5 and is a mechanically exfoliated two-dimensional h-BN material with a thickness of approximately 13.3 nm. The channel layer 7 is located on the tunneling layer 6 and is a mechanically exfoliated two-dimensional MoS2 material with a thickness of approximately 23.5 nm.

[0042] In this device, the source and drain electrodes are not in direct contact with the floating gate layer or the tunneling layer, but only with the channel layer. The channel layer is located at the top of the device and is capacitively coupled and modulated through the tunneling layer and the floating gate layer.

[0043] All two-dimensional sheets were obtained by mechanical exfoliation and then stacked sequentially in a glove box using a dry transfer technique to prevent material oxidation and ensure atomically clear interfaces.

[0044] Example 4

[0045] This embodiment provides a two-dimensional photoelectric synapse device based on the negative quantum capacitance effect, the structure of which is as follows: Figure 1 The diagram shows a vertically stacked heterojunction structure. Specifically, it includes: Substrate 1 uses heavily doped p-type silicon with SiO2 on its surface as the back gate electrode; Both source 2 and drain 3 are located on the substrate and are composite metal layers composed of 5nm Cr and 30nm Pt; Dielectric layer 4 is located between the source and drain electrodes and does not overlap with the source and drain electrodes. It is a mechanically peeled h-BN thin layer with a thickness of about 11 nm. The floating gate layer 5 is located on the dielectric layer 4 and is a mechanically peeled MoTe2 thin layer with a thickness of approximately 4.3 nm. The tunneling layer 6 is located on the floating gate layer 5 and is a mechanically exfoliated two-dimensional h-BN material with a thickness of approximately 15.4 nm. The channel layer 7 is located on the tunneling layer 6 and is a mechanically exfoliated two-dimensional MoS2 material with a thickness of about 20 nm.

[0046] In this device, the source and drain electrodes are not in direct contact with the floating gate layer or the tunneling layer, but only with the channel layer. The channel layer is located at the top of the device and is capacitively coupled and modulated through the tunneling layer and the floating gate layer.

[0047] All two-dimensional sheets were obtained by mechanical exfoliation and then stacked sequentially in a glove box using a dry transfer technique to prevent material oxidation and ensure atomically clear interfaces.

[0048] Example 5

[0049] Based on the above embodiments, this embodiment is a method for fabricating a two-dimensional photoelectric synaptic device based on the negative quantum capacitance effect, and the specific steps are as follows: Source and drain electrodes were fabricated by spin-coating photoresist onto a clean substrate and defining the source and drain electrode patterns using laser direct-write lithography. After development, 5 nm Ti and 30 nm Au were deposited sequentially using magnetron sputtering. Finally, the electrodes were stripped in acetone and washed with isopropanol and deionized water to form the source and drain electrodes.

[0050] Dielectric layer transfer: Thin sheets are repeatedly peeled from the h-BN bulk material using adhesive tape and transferred onto the PDMS film. h-BN sheets of uniform thickness and suitable area are selected under an optical microscope. Inside a glove box, the h-BN sheets on the PDMS are aligned and released onto the substrate using a dry transfer method, positioning them between the source and drain electrodes.

[0051] Transferring the floating gate layer: A suitable sheet is mechanically peeled off from the WTe2 bulk material. Since WTe2 is easily oxidized in air, the entire peeling and screening process must be completed inside a glove box. It is then transferred to the h-BN dielectric layer using a dry transfer method, positioning it above the region between the source and drain electrodes to avoid overlap with the source and drain electrodes.

[0052] Transfer tunneling layer: A suitable sheet is peeled off from the h-BN bulk material and transferred to the WTe2 floating gate layer by dry transfer, ensuring complete coverage of the floating gate layer.

[0053] Transferring the channel layer: Thin sheets are peeled off from the MoS2 bulk material. Thin sheets with a length greater than 10µm and neat edges are selected and transferred to the h-BN tunneling layer by dry transfer. The position of the channel layer should be such that its two ends can directly contact the source and drain.

[0054] Annealing: Annealing was performed at 150 °C for 30 minutes in a nitrogen atmosphere to improve interfacial contact between layers and enhance device stability. After annealing, the device was allowed to cool naturally to room temperature, thus completing the device fabrication.

[0055] Example 6

[0056] This embodiment provides a photoelectric synapse device based on the negative quantum capacitance effect using Al2O3 as the gate dielectric, with the structure as follows: Figure 2 As shown, the specific steps are as follows: Dielectric layer deposition: An Al2O3 dielectric layer is deposited on a clean substrate using atomic layer deposition (ALD). Trimethylaluminum (TMA) and water are used as precursors, and the deposition temperature is controlled between 150 and 200 °C. The Al2O3 thickness is precisely controlled by adjusting the number of deposition cycles. Alternatively, an Al2O3 thin film can be deposited on the substrate as the dielectric layer using magnetron sputtering.

[0057] Transferring the floating gate layer: Suitable flakes are mechanically peeled off from the WTe2 bulk material. Because WTe2 is easily oxidized in air, the entire peeling and screening process must be completed inside a glove box. The WTe2 flakes are then transferred onto the Al2O3 dielectric layer using a dry transfer method.

[0058] Deposition of the tunneling layer: An Al2O3 tunneling layer was deposited on the WTe2 floating gate layer using atomic layer deposition (ALD). To protect the WTe2 floating gate layer from oxidation or damage during deposition, a low-temperature ALD process was employed, with the deposition temperature not exceeding 150°C. TMA and water were used as precursors, and the tunneling layer thickness was controlled by adjusting the number of deposition cycles. If process conditions permit, ozone can be used instead of water as the oxygen source to achieve high-quality Al2O3 film deposition at even lower temperatures. Alternatively, a low-temperature magnetron sputtering method can be used to deposit the Al2O3 tunneling layer.

[0059] Transfer tunnel layer: Thin sheets are peeled off from the MoS2 bulk material, and thin sheets of appropriate length and neat edges are selected and transferred to the Al2O3 tunneling layer by dry transfer.

[0060] Fabrication of source and drain electrodes: Source and drain electrode patterns are defined above the channel layer using photolithography, with the electrode patterns spanning both ends of the channel layer. After development, 5 nm Ti and 30 nm Au are deposited sequentially using magnetron sputtering or electron beam evaporation. Finally, the electrodes are stripped in acetone and cleaned with isopropanol and deionized water to form the source and drain electrodes, ensuring direct contact between the source and drain electrodes and both ends of the channel layer.

[0061] Annealing: Annealing was performed at 100 °C for 50 minutes in a nitrogen atmosphere to improve interfacial contact between layers and enhance device stability. After annealing, the device was allowed to cool naturally to room temperature, thus completing device fabrication.

[0062] Example 7

[0063] Based on the above embodiments, this embodiment uses a Keysight B1500 semiconductor parameter analyzer with a probe station to test the device performance in room temperature and dark room environments.

[0064] During testing, a back-gate voltage was applied to the substrate, and source-drain voltages were applied to the source and drain electrodes. The channel current was read through the source and drain electrodes. The test results for Example 1 are as follows: Figure 3 These are the output characteristic curves of the fabricated photoelectric synaptic device. The source-drain current variations were measured within the source-drain voltage range of -0.2 V to 0.2 V under different gate voltage conditions of -2 V, -1 V, 0 V, 1 V, and 2 V. The results show that the source-drain current exhibits a good linear relationship with the voltage under all gate voltage conditions, indicating the formation of a low Schottky barrier ohmic contact between the MoS2 channel and the metal electrode. This phenomenon can be attributed to the good matching between the work function of Au and the conduction band bottom of MoS2, and the effective improvement of interface quality by annealing.

[0065] Figure 4 These are the transfer characteristic curves of the fabricated photoelectric synaptic device tested under different bidirectional gate voltage scan ranges of -4 V to 4 V and -6 V to 6 V. At a source-drain voltage of 0.1 V, the device exhibits good n-type transistor characteristics and achieves over 10... 5 The current switching ratio is [not specified]. The hysteresis window increases slightly with the increase of the scan range, but the maximum is only 67mV, indicating that only a small number of carriers tunnel into and out of the floating gate layer at low gate voltage, which is consistent with the working mechanism of the negative quantum capacitance effect.

[0066] Figure 5 Synaptic plasticity variation curves of the prepared photoelectric synaptic device under different optical power densities stimulated by 254 nm wavelength light; Figure 6 Synaptic plasticity variation curves of the fabricated photoelectric synaptic device under 254 nm wavelength light stimulation with different light pulse widths; and Figure 7 These are the synaptic plasticity curves of the fabricated photoelectric synaptic device under different numbers of light pulses stimulated at a wavelength of 254 nm. The results show that with increasing light power density, pulse width, and number of pulses, both the peak current and the holding current after the pulse end significantly increase. This is because enhanced light stimulation generates more photogenerated electron-hole pairs. Under the influence of the built-in electric field generated by the stored charge in the floating gate layer, holes are effectively collected and tunneled into the floating gate layer or accumulated at the interface, increasing the channel electron concentration. This characteristic can be used to simulate the weight enhancement process of biological synapses, and the enhancement amplitude can be finely controlled by the pulse width.

[0067] Figure 8 This is a graph showing the change in the double-pulse facilitation index of the fabricated photoelectric synaptic device under 254 nm wavelength light stimulation. The double-pulse facilitation index is usually defined as the ratio of the current change amplitude generated by the second pulse to that generated by the first pulse in two consecutive pulses. As the pulse interval increases, the double-pulse facilitation index decreases. The fast and full relaxation time constants obtained from the fitting are highly consistent with the behavior of biological synapses, indicating that the device successfully simulates the short-term plasticity characteristics of biological synapses.

[0068] Figure 9This describes the long-term retention characteristics of the fabricated photoelectric synaptic device. An application of light for 5 seconds was performed, with a power density of 65 µW / cm². 2 Illumination was applied to the device, placing it in a high-conductivity state. After the illumination was removed, the decay of the source-drain current was monitored under conditions of 0 V gate voltage and 0.1 V source-drain voltage. The results showed that the current decayed to 70% after 2000 seconds. After more than 5000 seconds of measurement, the current was still greater than 50% of the maximum photoresponse current. Model fitting calculations showed that the device could still maintain 30% of the maximum photoresponse current after nearly a year, demonstrating excellent non-volatile storage capability.

[0069] Figure 10 The low-energy consumption characteristic of the fabricated photoelectric synaptic device was demonstrated by a measured optical power density of 25 µW / cm² with an applied duration of 0.1 seconds. 2 The device exhibits a low current response under illumination. At a source-drain voltage of 1 mV, the device achieves a minimum readout power consumption of 0.26 fJ, lower than the estimated power consumption of a biological synapse. This ultra-low power consumption is attributed to a strong built-in electric field generated by the negative quantum capacitance effect, which efficiently separates photogenerated electron-hole pairs and prevents their recombination, thus enabling detectable photocurrent at extremely low readout voltages.

[0070] Figure 11 This describes the cyclic long-term boost / suppression (LTP / LTD) characteristics of the fabricated photoelectric synaptic device. After 10 consecutive alternating applications of optical boost and electrical suppression pulse sequences, the device's conductance state was reversibly modulated in each cycle, exhibiting good repeatability between cycles, indicating excellent durability and stability. This LTP / LTD characteristic forms the basis for constructing weight update rules in artificial neural networks.

Claims

1. A method for fabricating an optoelectronic device based on the negative quantum capacitance effect, characterized in that, The methods include: Provide substrate; A dielectric layer is formed on the substrate; A floating gate layer is formed on the dielectric layer, the floating gate layer being made of a topologically semi-metallic material; A tunneling layer is formed on the floating grid layer; A trench layer is formed on the tunneling layer, and the trench layer is made of a two-dimensional semiconductor material; A source electrode and a drain electrode are formed, and the source electrode and the drain electrode are electrically contacted with the channel layer; Annealing is performed in an inert atmosphere to improve the interfacial contact between layers; The floating gate layer is configured such that, after charge tunneling injection, its Fermi level is tuned to the vicinity of the topological node, thereby generating a negative quantum capacitance effect.

2. The method for fabricating an optoelectronic device based on the negative quantum capacitance effect according to claim 1, characterized in that, The topological semimetal material includes Weyl semimetals or Dirac semimetals.

3. The method for fabricating an optoelectronic device based on the negative quantum capacitance effect according to claim 2, characterized in that, The Weyl semimetal includes WTe2 or MoTe2.

4. The method for fabricating an optoelectronic device based on the negative quantum capacitance effect according to claim 1, characterized in that, The two-dimensional semiconductor materials include transition metal chalcogenides, black phosphorus, and indium selenide.

5. The method for fabricating an optoelectronic device based on the negative quantum capacitance effect according to claim 1, characterized in that, The dielectric layer and the tunneling layer comprise two-dimensional insulating materials or high dielectric constant dielectric materials.

6. The method for fabricating an optoelectronic device based on the negative quantum capacitance effect according to claim 5, characterized in that, The two-dimensional insulating material includes hexagonal boron nitride, and the high dielectric constant dielectric material includes aluminum oxide, hafnium oxide, and silicon oxide.

7. The method for fabricating an optoelectronic device based on the negative quantum capacitance effect according to claim 1, characterized in that, The substrate is a conductive substrate and also serves as a bottom gate electrode; or the substrate is an insulating substrate or a semiconductor substrate, and an independent bottom gate electrode is disposed above or inside the substrate.

8. The method for fabricating an optoelectronic device based on the negative quantum capacitance effect according to claim 1, characterized in that, The source electrode and drain electrode comprise at least one of a Cr / Au composite layer, a Ti / Au composite layer, a Pd / Au composite layer, or a graphene conductive layer.

9. The method for fabricating an optoelectronic device based on the negative quantum capacitance effect according to claim 1, characterized in that, The dielectric layer, floating gate layer, tunneling layer and channel layer are formed by at least one of mechanical stripping, chemical vapor deposition, physical vapor deposition or atomic layer deposition.

10. A photoelectric device based on the negative quantum capacitance effect, characterized in that, The optoelectronic device fabricated by the method for fabricating optoelectronic devices based on the negative quantum capacitance effect according to any one of claims 1-9; comprising: Substrate; A node layer, on which a dielectric layer is formed, is formed on the substrate; A floating gate layer is formed on the dielectric layer, and the floating gate layer is made of a topologically semi-metallic material; A tunneling layer is formed on the floating grid layer; A trench layer is formed on the tunneling layer, and the trench layer is made of a two-dimensional semiconductor material; Source and drain electrodes are formed to make the source and drain electrodes electrically contact the channel layer. Annealing is performed in an inert atmosphere to improve the interfacial contact between layers; The floating gate layer is configured such that, after charge tunneling injection, its Fermi level is tuned to the vicinity of the topological node, thereby generating a negative quantum capacitance effect.

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