Silicon wafers, solar cells and photovoltaic modules

Abstract

This invention discloses a silicon wafer, a solar cell, and a photovoltaic module to address the problem of high silicon wafer breakage rate. The silicon wafer is rectangular, with a length-to-width ratio of 1:0.8 to 1:1. At least one surface of the silicon wafer has multiple arc-shaped cutting marks extending along its length or width. Perpendicular to the cutting mark extension path, from the convex side to the concave side of the arc, the silicon wafer has a first edge region and a second edge region. The first and second edge regions are two edge regions perpendicular to the cutting mark extension path, and their widths in this direction are greater than or equal to 5 mm and less than or equal to 20 mm. The average thickness of the first edge region is less than the average thickness of the second edge region. The second edge region, located on the concave side, is thickened to improve the structural strength in this direction, reducing the risk of breakage and thus lowering the breakage rate.

Description

[0001] This application claims priority to Chinese Patent Application No. 202510170252.7, filed on February 14, 2025, entitled "Silicon Wafers, Solar Cells and Photovoltaic Modules", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of silicon wafer manufacturing technology, and more particularly to a silicon wafer, a solar cell, and a photovoltaic module. Background Technology

[0003] As the photovoltaic industry develops, silicon wafer sizes are continuously increasing. Since silicon is a brittle material, its mechanical strength decreases with increasing size. Under the same external force, stress is more easily concentrated, and brittle materials have limited stress resistance. Once the stress exceeds its fracture limit, it will directly lead to breakage. Furthermore, large silicon wafers are more prone to collisions and friction with the external environment during manufacturing, transportation, handling, and processing, resulting in microcracks. These microcracks become stress concentration points, continuously expanding under the influence of external or internal stresses in subsequent processes, ultimately leading to the entire wafer breaking. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon wafer, a solar cell, and a photovoltaic module to improve the strength of the silicon wafer and reduce the breakage rate.

[0005] In a first aspect, the present invention provides a silicon wafer, the silicon wafer being rectangular, and the length-to-width ratio of the silicon wafer being 1:0.8 to 1:1; the silicon wafer comprising two opposing surfaces and four side surfaces located between the two surfaces; at least one of the surfaces having multiple dicing marks extending along the length or width direction of the silicon wafer, and the dicing marks being arc-shaped; in a direction perpendicular to the extension path of the dicing marks, along the direction from the arc-shaped convex side to the arc-shaped concave side of the dicing marks, the silicon wafer having a first edge region and a second edge region; the first edge region and the second edge region being two edge regions in a direction perpendicular to the extension path of the dicing marks, the width of the first edge region and the second edge region in the direction perpendicular to the extension path of the dicing marks being greater than or equal to 5 mm and less than or equal to 20 mm; wherein, the average thickness of the first edge region is less than the average thickness of the second edge region.

[0006] When the above technical solution is adopted, on the one hand, since the length-to-width ratio of the rectangular silicon wafer is 1:0.8 to 1:1, the shape of the silicon wafer is approximately square. When the silicon wafer is cut, transported, or inspected, the stress should be mainly concentrated at the four corners of the silicon wafer. The cutting mark is a mechanical damage generated on the surface of the silicon wafer during the cutting process. The cutting mark extends from one side of the silicon wafer to the other side, and its extension path will inevitably penetrate or approach the stress concentration area of ​​the silicon wafer. In addition, the cutting mark is arc-shaped. When the stress at the corner is transmitted to the cutting mark, the force will converge along the arc-shaped surface towards the center of curvature on the concave side, making the arc-shaped concave side the weakest area. In this application, the silicon wafer is divided into a first edge region and a second edge region in the direction perpendicular to the extension path of the cutting mark, along the direction from the arc-shaped convex side to the arc-shaped concave side of the cutting mark. By controlling the average thickness of the first edge region to be less than the average thickness of the second edge region, i.e., thickening the second edge region located in the arc-shaped concave direction, the structural strength in the arc-shaped concave direction is improved, thereby effectively enhancing the strength of the silicon wafer and reducing the risk of breakage in the arc-shaped concave direction, thus reducing the fragmentation rate. On the other hand, during the silicon rod cutting process, the silicon rod is fixed on the resin plate. When the cutting line cuts the last silicon rod, it needs to further cut into the resin plate. The silicon rod is a brittle material, while the resin plate is a plastic material. At the moment of transition from cutting the silicon rod to the resin plate, the stress state changes abruptly, which can easily cause the silicon wafer to break at this time. By thickening the corresponding edge region (i.e., the second edge region at the junction of the silicon rod and the resin plate), this stress transition can be alleviated, further reducing the risk of fragmentation and improving the overall cutting yield.

[0007] Optionally, the difference between the average thickness of the second edge region and the average thickness of the first edge region is greater than 0.3 μm and less than or equal to 10 μm. If the difference is less than 0.3 μm, the thickening of the second edge region is too small, which cannot effectively improve the structural strength of the edge located in the arcuate concave direction of the cutting mark S, and cannot effectively reduce the risk of breakage of the edge in the arcuate concave direction, thus failing to effectively reduce the fragmentation rate of the silicon wafer. If the difference is greater than 10 μm, the difference in average thickness between the first edge region and the second edge region is too large, resulting in an excessively large strength difference between the first edge region and the second edge region, which is not conducive to improving the overall strength of the silicon wafer.

[0008] Optionally, the difference between the average thickness of the second edge region and the average thickness of the first edge region is greater than 0.3 μm and less than 5 μm.

[0009] Optionally, a first central region is further provided on the silicon wafer along the direction from the arc-shaped convex side to the arc-shaped concave side of the cutting mark. The first central region is located between the first edge region and the second edge region. The average thickness of the first central region is greater than the average thickness of the first edge region and less than the average thickness of the second edge region. By controlling the average thickness of the first central region to be between the two, the stress gradient within the entire region is effectively reduced, the overall strength of the silicon wafer is improved, and the risk of the silicon wafer breaking is further reduced.

[0010] Optionally, the difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.1 μm and less than or equal to 5 μm. Setting the average thickness difference between the first central region and the first edge region and / or the second edge region within this range allows for a significant increase in the thickness of the second edge region located in the concave direction of the S-shaped cut mark. This improves the strength of the second edge region while preventing excessive thickness differences between regions, thereby enhancing the overall strength of the silicon wafer. Furthermore, setting the average thickness difference between the first central region and the first edge region and / or the second edge region within this range also minimizes stress differences between silicon wafers during mass production, thereby reducing the breakage rate and the probability of microcracks during processing.

[0011] Optionally, the difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.15 μm and less than or equal to 3 μm.

[0012] Optionally, a first central region is further provided on the silicon wafer along the direction from the arc-shaped convex side to the arc-shaped concave side of the cutting mark. The first central region is located between the first edge region and the second edge region, and the average thickness of the first central region is less than the average thickness of the first edge region and the average thickness of the second edge region. Since the silicon wafer is approximately square, the stress is mainly concentrated at the four corners, which are located at the corners of the first edge region and the second edge region. Therefore, by increasing the average thickness of the first edge region and the second edge region relative to the average thickness of the first central region, the structural strength of the four corners and the edge structure can be improved, which can effectively reduce the breakage rate of the silicon wafer and the probability of microcracks.

[0013] Optionally, the difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.1 μm and less than or equal to 5 μm. Setting the average thickness difference between the first central region and the first edge region and / or the second edge region within this range allows for a significant increase in the thickness of the second edge region located on the concave side of the S-shaped dicing mark. This improves the strength of the second edge region while simultaneously enhancing the structural strength of the four corners of the rectangular silicon wafer, without excessively large thickness differences between regions, thereby improving the overall strength of the silicon wafer. Furthermore, setting the average thickness difference between the first central region and the first edge region and / or the second edge region within this range also minimizes stress differences between silicon wafers during mass production, thereby reducing the breakage rate and the probability of microcracks during processing.

[0014] Preferably, the difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.15 μm and less than or equal to 3 μm.

[0015] Optionally, all four corners of the silicon wafer are chamfered; the chamfers are either curved or straight. Chamfering the four corners of the silicon wafer reduces stress concentration at the corners, thereby lowering the risk of the silicon wafer fragmenting at the corners.

[0016] Optionally, the projected length of each chamfer on the edge of the silicon wafer is greater than or equal to 0.05 mm and less than or equal to 9 mm.

[0017] Optionally, along a direction parallel to the dicing path, the silicon wafer is provided with a third edge region, a second central region, and a fourth edge region. The third and fourth edge regions are two edge regions along a direction parallel to the dicing path. The width of the third and fourth edge regions in a direction perpendicular to the dicing path is greater than or equal to 5 mm and less than or equal to 20 mm. The second central region is located between the third and fourth edge regions. The average thickness of at least one of the third and fourth edge regions is greater than the average thickness of the second central region. Setting the average thickness of at least one of the third and fourth edge regions to be greater than the average thickness of the second central region in the first direction L1 allows the average thickness of at least one edge region of the silicon wafer disposed opposite each other in the first direction L1 to be greater than the average thickness of its central region. This improves the strength of the edge region, making it less prone to breakage when subjected to external impact, further enhancing the overall strength of the silicon wafer.

[0018] Optionally, the average thickness of both the third edge region and the fourth edge region is greater than the average thickness of the second central region. This allows for the enhancement of the strength of the third or fourth edge region of the silicon wafer while simultaneously reducing the strength difference between the third or fourth edge region and the second central region by controlling the thickness difference between them, thereby improving the overall strength of the silicon wafer.

[0019] Optionally, the difference between the average thickness of the third edge region and the fourth edge region and the average thickness of the second central region is greater than 0.3 μm and less than or equal to 2 μm.

[0020] Optionally, the average thickness of the second central region is between the average thickness of the third edge region and the average thickness of the fourth edge region. By sequentially increasing the average thickness of the third edge region, the second central region, and the fourth edge region, the overall strength of the silicon wafer can be improved while simultaneously enhancing the strength of one edge. This control over the average thickness difference between adjacent regions further reduces the risk of wafer breakage.

[0021] Optionally, the difference between the average thickness of the third edge region or the fourth edge region and the average thickness of the second central region is greater than 0.15 μm and less than or equal to 1 μm.

[0022] Optionally, the length of the silicon wafer is 166mm-230mm; and / or, the width of the silicon wafer is 166mm-230mm; and / or, the number of dicing marks is greater than 1 and less than 50; and / or, the spacing between adjacent dicing marks is greater than 1mm; and / or, the arc height of the dicing mark is greater than 1mm and less than 17mm; and / or, the depth of the dicing mark is greater than 1μm and less than 15μm.

[0023] In a second aspect, the present invention also provides a battery cell comprising a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is a silicon wafer as described in any of the preceding claims, and has the same beneficial effects as the first aspect.

[0024] Thirdly, the present invention also provides a photovoltaic module comprising a plurality of interconnected solar cells, wherein the solar cells are those described above, and has the same beneficial effects as the second aspect. Attached Figure Description

[0025] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1This is a schematic diagram of the structure of a silicon wafer (full wafer) provided in an embodiment of this application; Figure 2 This is a schematic diagram for measuring the thickness of various parts of the silicon wafer provided in the embodiments of this application; Figure 3 for Figure 1 A schematic diagram showing the positional relationship between the third edge region, the second central region, and the fourth edge region of a silicon wafer.

[0026] The reference numerals in the attached figures are as follows: 100. Silicon wafers; 10. Third edge region; 20. Second central region; 30. Fourth edge region; 40. First edge region; 50. First central region; 60. Second edge region; S. Cutting mark; L1, first direction; L2, second direction. Detailed Implementation

[0027] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0028] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0030] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0031] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0032] like Figure 1 As shown, this embodiment of the invention provides a silicon wafer 100, which is rectangular. The ratio of the length to the width of the silicon wafer 100 is 1:0.8 to 1:1, and the specific ratio can be 1:0.8, 1:0.9, 1:1, etc. The silicon wafer 100 is approximately square. When the ratio of the length to the width is 1:1, the silicon wafer 100 is a square with equal length and width. In this application, the length of the silicon wafer 100 is 166mm-230mm, and the width of the silicon wafer 100 is 166mm-230mm. For example, the dimensions of silicon wafer 100 can be 166mm×166mm; 182mm×182mm; 182mm×183.75mm; 182mm×192mm; 182mm×210mm; 210mm×210mm; 215mm×215mm; 218mm×218mm; 220mm×220mm; 230mm×230mm.

[0033] The silicon wafer 100 includes two opposing surfaces and four side surfaces located between the two surfaces; at least one surface has multiple dicing marks S extending along the width direction of the silicon wafer 100; the dicing marks S are arc-shaped; the dicing marks S are arc-shaped cutting marks formed along the surface of the silicon wafer 100 and approximately parallel to the short edge of the silicon wafer 100, and these cutting marks generally penetrate the two long sides of the entire silicon wafer 100. Because flexible cutting wires (such as diamond wire, steel wire, tungsten wire, etc.) are used to cut the silicon rod during the cutting process, there are tension differences at the inlet, middle and outlet ends of the flexible cutting wires, resulting in uneven cutting force at different positions of the cutting wires, which in turn causes the cutting wires to form an arc-shaped cutting trajectory on the surface of the silicon rod. This trajectory is retained on the surface of the silicon wafer after the silicon rod is cut into a silicon wafer, thus forming the arc-shaped cutting marks S. The number of dicing marks S is typically greater than 10; the spacing between adjacent dicing marks S is greater than 1 mm; the arc height (distance from the bottom to the top of the arc) of dicing mark S is generally greater than 1 mm; the depth of dicing mark S is greater than 1 μm and less than 15 μm. It should be noted that dicing marks S form a protruding structure on the silicon wafer surface, and its depth refers to the vertical distance between the bottom of the recessed area and the apex of the protrusion. Because the depth of dicing marks S affects the subsequent cell fabrication, existing technologies control the depth of dicing marks S. If the depth of dicing mark S is greater than or equal to 15 μm, it is considered a defective product. The number of dicing marks S, the spacing between adjacent dicing marks S, and the arc height of dicing marks S are not controlled in normal products. The parameters of the number of dicing marks S, the spacing between adjacent dicing marks S, the arc height, and the depth can be measured using optical microscopy, SEM (scanning electron microscopy), AFM (atomic force microscopy), surface roughness testers, laser scanning microscopy, and image analysis software. Figure 1 Only a portion of the cut marks S are shown.

[0034] In this application, the extension direction of the cleavage S on the surface of the silicon wafer 100 is used as a reference. The extension direction of the cleavage S parallel to the surface of the silicon wafer 100 is set as the first direction L1; the extension direction of the cleavage S perpendicular to the surface of the silicon wafer 100 is set as the second direction L2; in the second direction L2, along the direction from the arcuate convex side to the arcuate concave side of the cleavage S, the silicon wafer 100 is divided into a first edge region 40 and a second edge region 60. The first edge region 40 and the second edge region 60 are two edge regions perpendicular to the extension path of the dicing mark S (second direction L2), that is, the first edge region 40 and the second edge region 60 are two edge regions parallel to the first direction L1 of the silicon wafer 100. The first edge region 40 is actually a portion extending a certain size from the first edge of the silicon wafer 100 parallel to the first direction L1 along the second direction L2, and the second edge region 60 is actually a portion extending a certain size from the second edge of the silicon wafer 100 parallel to the first direction L1 along the second direction L2. The first edge and the second edge are two opposite edges of the silicon wafer 100 in the second direction L2. The width of the first edge region 40 and the second edge region 60 in the direction perpendicular to the extension path of the dicing mark S is greater than or equal to 5 mm and less than or equal to 20 mm. In this application, the average thickness of the first edge region 40 of the silicon wafer 100 is less than the average thickness of the second edge region 60.

[0035] Specifically, the width of the first edge region 40 or the second edge region 60 in the direction perpendicular to the extension path of the cutting mark S is greater than or equal to 5 mm and less than or equal to 20 mm. That is, the size of the first edge region 40 in the second direction L2 is 5mm-20mm, and the size of the second edge region 60 in the second direction L2 is 5mm-20mm. In other words, the first edge region 40 is actually a region greater than or equal to 5mm and less than or equal to 20mm from the first edge of the silicon wafer 100, such as a region 6mm, 7mm, 8mm, 9mm, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, or 20mm from the first edge; the second edge region 60 is actually a region greater than or equal to 5mm and less than or equal to 20mm from the second edge of the silicon wafer 100, such as a region 6mm, 7mm, 8mm, 9mm, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, or 20mm from the second edge. The first central region 50 comprises all regions other than the first edge region 40 and the second edge region 60. The width of the first edge region 40 or the second edge region 60 is set within the range described above, ensuring that the widths of the two edge regions are neither too wide nor too narrow, thereby effectively improving the structural strength of the two opposing edge regions in the second direction.

[0036] It is worth noting that, as mentioned earlier, the arc-shaped cutting mark S is an arc-shaped cutting trajectory formed by the uneven cutting separation caused by the tension difference of the flexible cutting wire at the inlet, middle, and outlet ends. The tension at the inlet and outlet ends is greater than that at the middle end, causing the cutting trajectory formed in the middle section to be closer to the ground than at the inlet and outlet ends. Therefore, the arc-shaped convex side of the cutting mark S corresponds to the first edge region, i.e., the inlet end; while the arc-shaped concave side of the cutting mark S corresponds to the second edge region, i.e., the outlet end; the outlet end is also the edge region where the silicon rod and the resin board are bonded.

[0037] When using the above technical solution, on the one hand, since the length-to-width ratio of the rectangular silicon wafer is 1:0.8 to 1:1, the shape of the silicon wafer 100 is approximately square. During the wafer removal, transportation, or inspection process after cutting, the stress should mainly concentrate at the four corners of the silicon wafer 100. The cutting mark S, as mechanical damage generated on the surface of the silicon wafer 100 during the cutting process, extends along one side of the silicon wafer 100 to the opposite side, and its extension path inevitably penetrates or approaches the stress concentration area of ​​the silicon wafer 100. Furthermore, the cutting mark S is arc-shaped; when the stress at the corner is transmitted to the cutting mark S, the force will travel along... The curved surface converges towards the center of curvature on the concave side, making the concave side the weakest region. In this application, the silicon wafer 100 is divided into a first edge region 40 and a second edge region 60 in the direction perpendicular to the extension path of the cut mark S, along the direction from the convex side of the cut mark S to the concave side. The average thickness of the first edge region 40 is controlled to be less than the average thickness of the second edge region 60, that is, the second edge region 60 located in the direction of the concave side is thickened, thereby improving the edge structure strength in the direction of the concave side, thereby effectively enhancing the strength of the silicon wafer, reducing the risk of breakage in the direction of the concave side of the silicon wafer, and thus reducing the fragmentation rate. On the other hand, during the silicon rod cutting process, the silicon rod is fixed on the resin plate. When the cutting line cuts the last silicon rod, it needs to cut further into the resin plate. The silicon rod is a brittle material, while the resin plate is a plastic material. At the moment of transition from cutting the silicon rod to the resin plate, the stress state changes abruptly, which can easily cause the silicon wafer to break. By thickening the corresponding edge area (i.e., the second edge area 60 at the junction of the silicon rod and the resin plate), this stress transition can be alleviated, further reducing the risk of fragmentation and improving the overall cutting yield.

[0038] It should be noted that the thickness of each part in this application can be measured using the following measuring equipment and methods. Please refer to [link / reference]. Figure 2 The device used is a high-precision laser displacement sensor. Three detection lines M1, M2, and M3 are spaced apart along the first direction L1 on the silicon wafer 100. These three detection lines correspond to three sets of laser probes (two probes per set, for a total of six probes). The starting detection point on each detection line (e.g., ...) Figure 2 (at n=1 in the middle) and end detection points (such as Figure 2 At n=5, the two nearest edges of the silicon wafer are 8mm apart, and the other three points are evenly distributed between the starting and ending detection points.

[0039] Specifically, at least 1000 points are measured on each detection line, and these 1000 points are divided into 5 equal parts. An average is calculated for each part, resulting in 5 averages per detection line; a total of 15 averages are obtained. The average thicknesses of the first edge region 40, the first central region 50, and the second edge region 60 are respectively the average of the first point of M1, M2, and M3, and the average of the third point of M1, M2, and M3 (i.e.,...) Figure 2 The average of the 5th points of M1, M2, and M3, which is the midpoint between the first point (n=1) and the fifth point (n=5).

[0040] like Figure 1 As shown, in some embodiments, the difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 is greater than 0.3 μm and less than or equal to 10 μm. Exemplarily, the difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 can be 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc. If the difference is less than 0.3 μm, the thickness of the second edge region 60 is too small, which cannot effectively improve the structural strength of the edge located in the arc-shaped concave direction of the cutting mark S, and cannot effectively reduce the risk of breakage of the edge in the arc-shaped concave direction, thus failing to effectively reduce the fragmentation rate of the silicon wafer 100. If the difference is greater than 10 μm, the average thickness difference between the first edge region 40 and the second edge region 60 is too large, resulting in an excessively large strength difference between the first edge region 40 and the second edge region 60, which is not conducive to improving the overall strength of the silicon wafer 100. Therefore, selecting the average thickness difference range in this application can improve the structural strength of the second edge region 60 while controlling the structural strength difference between the first edge region 40 and the second edge region 60, thereby improving the overall structural strength of the silicon wafer 100 and reducing the fragmentation rate of the silicon wafer 100.

[0041] Preferably, the difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 is greater than 0.3 μm and less than or equal to 5 μm. Exemplarily, the difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 can be 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, etc.

[0042] More preferably, the difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 can be greater than 1 and less than 3 μm. For example, the difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 can be 0.2 μm, 0.5 μm, 0.8 μm, 0.9 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, etc.

[0043] like Figure 1 As shown, in some embodiments, a first central region 50 is further provided on the silicon wafer 100 along the direction from the arcuate convex side to the arcuate concave side of the cut mark S. The first central region 50 is located between the first edge region 40 and the second edge region 60. The average thickness of the first central region 50 is greater than the average thickness of the first edge region 40 and less than the average thickness of the second edge region 60. Then, in the second direction L2, along the direction from the arcuate convex side to the arcuate concave side, the average thicknesses of the first edge region 40, the first central region 50, and the second edge region 60 are sequentially increased. By controlling the average thickness of the first central region 50 to be between the two, the stress gradient within the entire region is effectively reduced, improving the overall strength of the silicon wafer 100 and further reducing the risk of the silicon wafer 100 breaking. Furthermore, based on the improved overall strength of the silicon wafer 100, the breakage rate and the probability of microcracks in the silicon wafer 100 are greatly reduced during mass production.

[0044] In some embodiments, based on the configuration where the average thicknesses of the first edge region 40, the first central region 50, and the second edge region 60 are sequentially increased, the difference between the average thickness of the first central region 50 and the average thicknesses of the first edge region 40 and / or the second edge region 60 is greater than 0.1 μm and less than or equal to 5 μm. That is, the difference between the average thickness of the first central region 50 and the average thickness of the first edge region 40 is only greater than 0.1 μm and less than or equal to 5 μm; or, the difference between the average thickness of the first central region 50 and the average thickness of the second edge region 60 is only greater than 0.1 μm and less than or equal to 5 μm; or, the difference between the average thickness of the first central region 50 and the average thicknesses of the first edge region 40 and the second edge region 60 is simultaneously greater than 0.1 μm and less than or equal to 5 μm. For example, the difference between the average thickness of the first central region 50 and the average thickness of the first edge region 40 and / or the second edge region 60 can be 0.2μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 1μm, 1.5μm, 1.8μm, 2μm, 2.5μm, 2.8μm, 3μm, 3.5μm, 4μm, 4.5μm, 5μm, etc.

[0045] Preferably, the difference between the average thickness of the first central region 50 and the average thickness of the first edge region 40 and / or the second edge region 60 is greater than 0.15 μm and less than or equal to 3 μm. Specifically, the average thickness difference can be 0.16 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc.

[0046] In this embodiment, setting the average thickness difference between the first central region 50 and the first edge region 40 and / or the second edge region 60 within the aforementioned range allows for a significant increase in the thickness of the second edge region 60 located in the concave direction of the cut mark S. This satisfies the requirement of increasing the strength of the second edge region 60 while preventing excessive thickness differences between regions, thereby enhancing the overall strength of the silicon wafer 100. Furthermore, setting the average thickness difference between the first central region 50 and the first edge region 40 and / or the second edge region 60 within the aforementioned range also minimizes the stress differences between silicon wafers 100 during mass production, thereby reducing the breakage rate and the probability of microcracks during the processing of the silicon wafer 100.

[0047] like Figure 1 As shown, in some other embodiments, the average thickness of the first central region 50 is less than the average thickness of the first edge region 40 and the average thickness of the second edge region 60. That is, the average thickness of the first central region 50 is less than the average thickness of the first edge region 40 and also less than the average thickness of the second edge region 60. The average thickness of the first edge region 40 and the average thickness of the second edge region 60 are relatively thick. Since the silicon wafer 100 is approximately square, the stress is mainly concentrated at the four corners, which are located at the corners of the first edge region 40 and the second edge region 60. Therefore, by increasing the average thickness of the first edge region 40 and the second edge region 60 relative to the average thickness of the first central region 50, the structural strength of the four corners and the structural strength of the edges can be improved, which can effectively reduce the breakage rate of the silicon wafer 100 and the probability of microcracks.

[0048] Furthermore, based on the premise that the average thickness of the first central region 50 is less than the average thickness of the first edge region 40 and the average thickness of the second edge region 60, the difference between the average thickness of the first central region 50 and the average thickness of the first edge region 40 and / or the second edge region 60 is greater than 0.1 μm and less than or equal to 5 μm. For example, the difference in average thickness can be 0.2 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 1 μm, 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, etc.

[0049] Preferably, the difference between the average thickness of the first central region 50 and the average thickness of the first edge region 40 and / or the second edge region 60 is greater than 0.15 μm and less than or equal to 3 μm. Exemplarily, the average thickness difference can be 0.16 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc.

[0050] In this embodiment, setting the average thickness difference between the first central region 50 and the first edge region 40 and / or the second edge region 60 within the aforementioned range allows for a significant increase in the thickness of the second edge region 60 located on the concave side of the cut S arc. This improves the strength of the second edge region 60 while simultaneously enhancing the structural strength of the four corners of the rectangular silicon wafer, without causing excessive thickness differences between the regions, thereby improving the overall strength of the silicon wafer 100. Furthermore, setting the average thickness difference between the first central region 50 and the first edge region 40 and / or the second edge region 60 within the aforementioned range also minimizes the stress differences between the silicon wafers 100 during mass production, thereby reducing the breakage rate and the probability of microcracks during the processing of the silicon wafers 100.

[0051] like Figure 1 and Figure 3As shown, in some embodiments, the silicon wafer 100 has chamfered corners at all four corners. Specifically, the silicon wafer 100 has a first side and a second side positioned opposite each other along a second direction L2, and a third side and a fourth side positioned opposite each other along a first direction L1, with chamfers formed between adjacent sides. Both ends of the first edge region 40 and the second edge region 60 have chamfers in a direction parallel to the extension path of the dicing mark S. These chamfers can be either curved or straight. In one alternative embodiment, the four chamfers are of equal size. Since the silicon wafer 100 is approximately square, stress is mainly concentrated at the four corners. Therefore, setting the four corners of the silicon wafer 100 as chamfers can reduce stress concentration at the corners, thereby reducing the risk of the silicon wafer 100 fragmenting at the corners. The four chamfers can be of equal size, which on the one hand unifies and simplifies the processing technology, and on the other hand improves the uniformity of stress distribution at the four corners, reducing the risk of fragmentation due to uneven stress distribution.

[0052] In some embodiments, the projected length of each chamfer on the side length of the silicon wafer 100 is greater than or equal to 0.05 mm and less than or equal to 9 mm. For example, the projected length of each chamfer on the side length of the silicon wafer 100 can be 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, or 9 mm.

[0053] In one alternative approach, the four chamfers are not of equal size; along the direction parallel to the extension path of the cut mark S, the dimensions of the two chamfers in the second edge region 60 are larger than the dimensions of the two chamfers in the first edge region 40; in some embodiments, the projected length of the dimensions of the two chamfers in the second edge region 60 onto the wafer edge is greater than or equal to 0.05 mm and less than or equal to 9 mm; the projected length of the dimensions of the two chamfers in the first edge region 40 onto the wafer edge is less than or equal to 8.5 mm. The chamfering reduces stress concentration, thereby reducing the risk of fragmentation.

[0054] In one alternative approach, the four chamfers are not of equal size; along the direction parallel to the extension path of the cut mark S, the dimensions of the two chamfers in the second edge region 60 are smaller than the dimensions of the two chamfers in the first edge region 40; in some embodiments, the projected length of the dimensions of the two chamfers in the second edge region 60 on the wafer edge is less than or equal to 8.5 mm; the projected length of the dimensions of the two chamfers in the first edge region 40 on the wafer edge is greater than or equal to 0.05 mm and less than or equal to 9 mm. The chamfering reduces stress concentration, thereby reducing the risk of fragmentation.

[0055] In one alternative approach, the four chamfers are not of equal size; perpendicular to the direction of the cut line S, two chamfers on the same side of the first edge region 40 and the second edge region 60 have larger dimensions than the chamfer on the other side. In some embodiments, the projected length of the two chamfers on the same side of the first edge region 40 and the second edge region 60 on the wafer edge is less than or equal to 8.5 mm; the projected length of the two chamfers on the other side of the first edge region 40 and the second edge region 60 on the wafer edge is greater than or equal to 0.05 mm and less than or equal to 9 mm. The chamfering reduces stress concentration, thereby reducing the risk of fragmentation.

[0056] If the projected length of the chamfer is less than 0.05 mm, the chamfer size is too small, failing to effectively reduce stress concentration and resulting in an excessively large area to be removed from the silicon ingot, reducing silicon ingot utilization and increasing processing difficulty. If the projected length of the chamfer is greater than 9 mm, the chamfer size is too large, reducing the effective usable area of ​​the silicon wafer 100. Therefore, chamfering within the above range can reduce stress concentration at the corners of the silicon wafer 100, reducing the risk of chipping or microcracks at the corners, while also improving silicon ingot utilization and the effective usable area of ​​the silicon wafer 100, and reducing the difficulty of chamfering processing.

[0057] It should be noted that the projected length of the chamfer on the side of the silicon wafer 100 refers to the projected length of the chamfer on either the long or short side of the silicon wafer 100, and the projected lengths of all chamfers on the same silicon wafer 100 are uniformly the projected lengths of the chamfers on the side of the same direction on the silicon wafer. The projected length of a chamfer on the long side of the silicon wafer 100 can be equal to its projected length on the short side of the silicon wafer 100. Alternatively, when the projected length of a chamfer on the long side of the silicon wafer 100 is not equal to its projected length on the short side, the longer of the two projected lengths can be used as the projected length of the chamfer on the side of the silicon wafer 100.

[0058] like Figure 3 As shown, in some embodiments, the silicon wafer 100 is divided into a third edge region 10, a second central region 20, and a fourth edge region 30 along a direction parallel to the extension path of the dicing mark S, i.e., along the first direction L1. The third edge region 10 and the fourth edge region 30 are two edge regions along a direction parallel to the extension path of the dicing mark S. The width of the third edge region 10 and the fourth edge region 30 in a direction perpendicular to the extension path of the dicing mark S is greater than or equal to 5 mm and less than or equal to 20 mm. The second central region 20 is located between the third edge region 10 and the fourth edge region 30. The average thickness of at least one of the third edge region 10 and the fourth edge region 30 is greater than the average thickness of the second central region 20.

[0059] It should be noted that, since the cutting mark S is an arc-shaped structure, if the convex or concave side of the arc is uncertain, the orientation of the third edge region 10 and the fourth edge region 30 relative to the convex or concave side of the arc will change accordingly. In this application, it is not necessary to limit the specific orientation relationship between the third edge region 10 and the fourth edge region 30 and the convex or concave side of the arc of the cutting mark; it is only necessary to limit that they are two edge regions arranged parallel to each other along the extension path of the cutting mark S.

[0060] Specifically, only the average thickness of the third edge region 10 is greater than the average thickness of the second central region 20, or only the average thickness of the fourth edge region 30 is greater than the average thickness of the second central region 20, or both the average thickness of the third edge region 10 and the fourth edge region 30 are greater than the average thickness of the second central region 20.

[0061] Therefore, in this application, by setting the average thickness of at least one of the third edge region 10 and the fourth edge region 30 in the first direction L1 to be greater than the average thickness of the second central region 20, the average thickness of at least one edge region of the silicon wafer 100 disposed opposite each other in the first direction L1 is greater than the average thickness of the central region, thereby improving the strength of the edge region (so that when the edge region is subjected to external impact, it is not easy to break in the edge region due to its increased strength), further improving the overall strength of the silicon wafer 100, thereby further reducing the risk of the silicon wafer 100 breaking and microcracks, and thus effectively reducing the breakage rate of the silicon wafer 100 in subsequent cell production.

[0062] like Figure 3 As shown, since the third edge region 10 and the fourth edge region 30 are two edge regions of the silicon wafer 100 in the first direction L1, the third edge region 10 is actually a portion extending a certain size from the third edge of the silicon wafer 100 along the first direction L1, and the fourth edge region 30 is actually a portion extending a certain size from the fourth edge of the silicon wafer 100 along the first direction L1. The third edge and the fourth edge are two opposite edges of the silicon wafer 100 in the first direction L1.

[0063] The third edge region 10 has a dimension of 5mm-20mm in the first direction L1. That is, the third edge region 10 is a region in the first direction L1 that is greater than 5mm and less than 20mm from the third side, such as a region 6mm, 7mm, 8mm, 9mm, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, or 20mm from the third side. The fourth edge region 30 has a dimension of 5mm-20mm in the first direction L1. That is, the fourth edge region 30 is a region in the first direction L1 that is greater than 5mm and less than 20mm from the fourth side, such as a region 6mm, 7mm, 8mm, 9mm, 10mm, 11mm, 12mm, 13mm, 14mm, 15mm, 16mm, 17mm, 18mm, 19mm, or 20mm from the fourth side. The second central region 20 comprises all regions other than the third edge region 10 and the fourth edge region 30. The width of the third edge region 10 or the fourth edge region 30 is set within the aforementioned range so that the width of the two edge regions is neither too wide nor too narrow, thereby effectively improving the structural strength of the two opposite edge regions in the first direction.

[0064] It should be noted that the average thickness of the third edge region 10, the second central region 20, and the fourth edge region 30 is measured using the same method as that of the first edge region 40, the first central region 50, and the second edge region 60. Figure 2 As shown, the average thicknesses of the third edge region 10, the second central region 20, and the fourth edge region 30 are the average values ​​of the five points on M1, the average values ​​of the five points on M2, and the average values ​​of the five points on M3, respectively.

[0065] like Figure 3 As shown, in some embodiments, the average thickness difference between the third edge region 10 or the fourth edge region 30 and the second central region 20 is greater than 0.3 μm and less than or equal to 2 μm. Exemplarily, the average thickness difference can be 0.31 μm, 0.4 μm, 0.5 μm, 1 μm, 1.1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 1.9 μm, 2 μm, etc.

[0066] Preferably, the average thickness difference between the third edge region 10 or the fourth edge region 30 and the second central region 20 is greater than 0.5 μm and less than or equal to 1 μm. Exemplarily, the average thickness difference can be 0.51 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, 0.85 μm, 0.9 μm, 0.95 μm, 1 μm, etc.

[0067] In this embodiment, by setting the average thickness difference between the third edge region 10 or the fourth edge region 30 and the second central region 20 within the aforementioned range, the strength of the third edge region 10 or the fourth edge region 30 of the silicon wafer 100 can be improved while simultaneously reducing the strength difference between the third edge region 10 or the fourth edge region 30 and the second central region 20 by controlling the thickness difference, thereby enhancing the overall strength of the silicon wafer 100. Furthermore, during the mass production of the silicon wafer 100, the stress on each part of the silicon wafer 100 can be made as uniform as possible, thereby reducing the breakage rate and the probability of microcracks during the processing of the silicon wafer 100.

[0068] like Figure 3 As shown, in some embodiments, the average thickness of the second central region 20 is between the average thickness of the third edge region 10 and the average thickness of the fourth edge region 30. Specifically, when the average thickness of the third edge region 10 is less than the average thickness of the fourth edge region 30, the average thickness of the second central region 20 is greater than the average thickness of the third edge region 10 and less than the average thickness of the fourth edge region 30; or, when the average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, the average thickness of the second central region 20 is greater than the average thickness of the fourth edge region 30 and less than the average thickness of the third edge region 10. Therefore, by sequentially increasing the average thickness of the third edge region 10, the second central region 20, and the fourth edge region 30 in the first direction L1, the overall strength of the silicon wafer 100 can be improved while controlling the average thickness difference between adjacent regions, thereby further reducing the risk of the silicon wafer 100 breaking. Furthermore, based on the increased overall strength of the silicon wafer 100, the breakage rate and the probability of microcracks in the silicon wafer 100 are greatly reduced during mass production.

[0069] In some embodiments, the difference between the average thickness of the third edge region 10 or the fourth edge region 30 and the average thickness of the second central region 20 is greater than 0.15 μm and less than or equal to 1 μm. Exemplarily, the difference between the average thickness of the third edge region 10 or the fourth edge region 30 and the average thickness of the second central region 20 can be 0.16 μm, 0.18 μm, 0.2 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, etc.

[0070] Preferably, the difference between the average thickness of the third edge region 10 or the fourth edge region 30 and the average thickness of the second central region 20 is greater than 0.25 μm and less than or equal to 0.5 μm. Specifically, the average thickness difference can be 0.26 μm, 0.28 μm, 0.3 μm, 0.32 μm, 0.34 μm, 0.36 μm, 0.38 μm, 0.4 μm, 0.42 μm, 0.45 μm, 0.47 μm, 0.5 μm, etc.

[0071] In this embodiment, the difference between the average thickness of the third edge region 10 or the fourth edge region 30 and the average thickness of the second central region 20 is set within the aforementioned range. This significantly increases the average thickness of the two edge regions of the silicon wafer parallel to the second direction L2, thereby improving the structural strength of the silicon wafer edge and reducing the likelihood of breakage in that edge region. Simultaneously, the average thickness difference between the regions is not excessive, thus enhancing the overall strength of the silicon wafer 100. Furthermore, setting the difference between the average thickness of the third edge region 10 or the fourth edge region 30 and the average thickness of the second central region 20 within the aforementioned range also minimizes the stress differences between the silicon wafers 100 during mass production, thereby reducing the breakage rate and the probability of microcracks during the processing of the silicon wafers 100.

[0072] The silicon wafer in this application can be prepared by the following method, including steps S100 and S200.

[0073] S100 provides single-crystal rectangular silicon rods. Specifically, single-crystal rectangular silicon rods can be formed by Czochralski pulling of single crystals, truncating, squaring, and chamfering.

[0074] The process of Czochralski single crystal growth is as follows: raw materials and dopants are placed in a quartz crucible; the crystal growth furnace containing the quartz crucible is then evacuated; the raw materials are then melted by heating with an electric power source; after the raw materials have melted, a circular Czochralski single crystal silicon rod is obtained through crystal pulling, necking, constant diameter growth and tailing.

[0075] The cutting process is as follows: the head and tail of the Czochralski single crystal silicon rod are removed by cutting equipment (such as a diamond wire single crystal silicon rod cutting machine), and the long Czochralski single crystal silicon rod is cut into multiple short single crystal silicon rods.

[0076] The squaring process is as follows: the squaring machine feeds the short monocrystalline silicon rod along its length and cuts four parallel planes in the circumferential direction of the monocrystalline silicon rod, so that the monocrystalline silicon rod is in the shape of a cuboid or a cuboid-like shape.

[0077] The chamfering process: The length of the single-crystal silicon rod after square rooting is chamfered by a grinding wheel to obtain a single-crystal rectangular silicon rod with rounded or straight chamfered corners.

[0078] S200 involves bonding the monocrystalline rectangular silicon rod and then fixing it onto a cutting device for cutting.

[0079] Specifically, the cutting equipment can be a diamond wire cutter, which forms a diamond wire cutting mesh on the main roller through the guidance of guide rollers. The diamond wire cutting mesh is then allowed to penetrate the interior of the single-crystal rectangular silicon rod through friction by the raising or lowering of the equipment, until the silicon wafer 100 in the above embodiment is obtained. During the cutting process, by controlling the wire diameter of the cutting mesh at different positions on the single-crystal rectangular silicon rod in the cutting direction, the single-crystal rectangular silicon rod can be cut sequentially along the cutting direction using cutting meshes of different diameters. This allows the thickness of the silicon wafer 100 at the corresponding exit position (second edge region 60) to be greater than the thickness at the corresponding entry position (first edge region 40). That is, the second edge region 60 in the direction of the concave side of the arc is thickened, which can improve the structural strength in the direction of the concave side of the arc, thereby effectively enhancing the strength of the silicon wafer 100, reducing the risk of breakage in the direction of the concave side of the silicon wafer, and thus reducing the fragmentation rate.

[0080] In one specific embodiment, the wire diameter of the cutting mesh at different positions on the single-crystal rectangular silicon rod controlled by the cutting equipment includes S210-S230.

[0081] S210, at the infeed position of a single-crystal rectangular silicon rod, uses a cutting wire mesh of the first wire diameter and performs cutting by adjusting its feed and return wire amounts.

[0082] S220 cuts a single-crystal rectangular silicon rod between the infeed and outfeed positions using a second-diameter cutting wire mesh, adjusting its feed and return wire amounts.

[0083] S230, at the exit position of the single-crystal rectangular silicon rod, a cutting wire mesh with a third wire diameter is used to cut the silicon wafer 100 by adjusting its feed and return wire amounts. The first wire diameter is larger than the third wire diameter.

[0084] During the fabrication process, by controlling the third wire diameter of the cutting wire mesh at the exit position to be smaller than the first wire diameter at the infeed position, the thickness of the silicon wafer at the exit position is improved. This allows the thickness of the second edge region 60 of the silicon wafer 100 to be greater than the thickness of the first edge region 40, thereby increasing the structural strength in the concave direction of the arc, effectively enhancing the strength of the silicon wafer, reducing the risk of breakage in the concave direction of the silicon wafer 100, and thus reducing the fragmentation rate. Furthermore, based on the overall improved strength of the silicon wafer 100, the fragmentation rate and the probability of microcracks in the silicon wafer 100 are greatly reduced during mass production.

[0085] Furthermore, the second wire diameter is smaller than the first wire diameter and larger than the third wire diameter. Therefore, in the second direction L2, the average thickness of the first edge region 40, the first central region 50, and the second edge region 60 of the silicon wafer 100 can be sequentially increased. This improves the strength of the second edge region 60 of the silicon wafer 100 while simultaneously enhancing the overall strength of the silicon wafer 100 by controlling the thickness difference between adjacent parts, thereby reducing the risk of the silicon wafer 100 breaking.

[0086] In some embodiments, at the infeed position, the exit position, and between the infeed position and the exit position, the feed rate and the return rate both satisfy one of the following conditions: the ratio of feed rate to return rate is 1.02 to 1.25, the feed rate is 500 to 800 m / min, and the return rate is 450 to 740 m / min.

[0087] In this embodiment, by setting the ratio of incoming wires to outgoing wires within the aforementioned range, setting the incoming wires within the aforementioned range, or setting the outgoing wires within the aforementioned range, the wire diameter difference at different locations of the cut wire mesh can be reduced. This allows for control of the thickness of the silicon wafer 100 at different locations, thereby improving the overall strength of the silicon wafer 100 and reducing the risk of breakage. Furthermore, based on the increased overall strength of the silicon wafer 100, the breakage rate and the probability of microcracks in the silicon wafer 100 are significantly reduced during mass production.

[0088] Furthermore, a single-crystal rectangular silicon rod is placed directly above the dicing wire mesh, and spray devices can be installed on both sides of the single-crystal rectangular silicon rod. The spray devices spray cutting fluid from both sides toward the dicing wire mesh, and the cutting fluid enters the slits at different positions along with the dicing wire mesh to cool the dicing wire mesh.

[0089] By controlling the degree of thermal expansion of the dicing wire mesh in the edge region and the central region of the silicon wafer 100; or by reducing the wire speed of the dicing wire mesh, the amount of dicing heat generated can be reduced, thereby reducing the wire diameter change of the dicing wire mesh due to thermal expansion; thus, the average thickness of at least one of the third edge region 10 and the fourth edge region 30 can be controlled to be greater than the average thickness of the second central region 20.

[0090] Specifically, by setting the spray position or spray angle, for example, by controlling the distance between the single-crystal rectangular silicon rod and the cutting liquid surface, controlling the horizontal distance between the spray device and the silicon rod, or controlling the spray device to spray the cutting liquid from both sides toward the cutting wire mesh at a certain angle, the cutting liquid can be maximized to enter the kerf, thereby making the thermal expansion degree of the central region greater than that of the edge region, and ultimately making the average thickness of at least one of the third edge region 10 and the fourth edge region 30 greater than the average thickness of the second central region 20. Alternatively, by controlling the cutting speed of the wire mesh, for example, by controlling and reducing the wire mesh speed to a certain extent, on the one hand, the amount of wire mesh stretching during cutting is reduced, avoiding the wire diameter in the central region becomes thinner; on the other hand, the heat of cutting is reduced, preventing excessive thermal expansion of the wire diameter, and ultimately making the average thickness of the first edge region 40 and / or the second edge region 60 less than the average thickness of the first central region 50.

[0091] In addition, after the silicon wafer 100 is obtained by cutting and before it is transported to the cell end, the silicon wafer 100 can be cleaned, sorted and inspected.

[0092] Specifically, the cleaning process involves using various acid and alkali tanks inside the cleaning machine to clean the dirt, damaged layers, and other impurities and defects on the cut silicon wafers, ultimately resulting in clean silicon wafers.

[0093] The sorting and inspection process involves measuring the resistivity, minority carrier lifetime, thickness, TTV, edge chipping, and microcracks of the silicon wafers using sorting and inspection equipment. Silicon wafers 100 with different properties are then graded to obtain the final silicon wafer product. Because this application uses the above-mentioned preparation method, the overall strength of the silicon wafer 100 is improved, thereby reducing the risk of breakage during subsequent battery fabrication.

[0094] To make the objectives, technical solutions, and beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments 1-4 and comparative example 1. However, the specific embodiments described are only used to explain the present invention and are not intended to limit the present invention.

[0095] Examples 1-4 and Comparative Example 1 are all normal silicon wafers that have been sorted and tested for defects such as resistivity, minority carrier lifetime, thickness, TTV, edge chipping, and microcracks using the same sorting machine. They can be divided into two groups based on their size and thickness: The first group consists of 10,000 wafers, each silicon wafer 100 measuring 182mm × 182mm. Each silicon wafer 100 includes four chamfers of the same size. The projected length of each chamfer on the side of the silicon wafer 100 is greater than or equal to 0.05mm and less than or equal to 9mm. The average thickness of each silicon wafer 100 is between 125-135μm.

[0096] The second group consists of 10,000 wafers, each silicon wafer 100 measuring 182mm × 182mm. Each silicon wafer 100 includes four chamfers of the same size. The projected length of each chamfer on the side of the silicon wafer 100 is greater than or equal to 0.05mm and less than or equal to 9mm. The average thickness of each silicon wafer 100 is between 105-115μm.

[0097] In Examples 1-4 and Comparative Example 1, both sets of silicon wafers 100 are again passed through the high-precision laser displacement sensor on the sorting machine. A first edge region 40, a first central region 50, and a second edge region 60 are set along the direction perpendicular to the extension path of the cutting mark S, from the convex side to the concave side of the arcuate shape of the cutting mark S. A third edge region 10, a second central region 20, and a fourth edge region 30 are set in the direction parallel to the extension path of the cutting mark S. The third edge region 10 is within 8 mm of the third edge, the fourth edge region 30 is within 8 mm of the fourth edge, the first edge region 40 is within 8 mm of the first edge, and the second edge region 60 is within 8 mm of the second edge. The number of cutting marks S is between 10 and 50, the arc height of the cutting mark S is greater than 1 mm and less than 17 mm, and the depth of the cutting mark S is greater than 1 μm and less than 15 μm. Using the above... Figure 2 The average thickness of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 was measured using the test method. Furthermore, the average thicknesses of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 of the two sets of silicon wafers 100 in Examples 1-4 and Comparative Example 1 are slightly different.

[0098] Example 1 In the two sets of silicon wafers 100 in this embodiment, each silicon wafer 100 is obtained by sorting according to the following criteria: The average thicknesses of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 all exhibit the following pattern: The average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, with a difference greater than 0.3 μm and less than 2 μm; the average thickness of the fourth edge region 30 is greater than the average thickness of the second central region 20, with a difference greater than 0.15 μm and less than 1 μm; (or, the average thickness of the fourth edge region 30 is greater than the average thickness of the third edge region 10, with a difference greater than 0.3 μm and less than 2 μm; the average thickness of the third edge region 10 is greater than the average thickness of the second central region 20, with a difference greater than 0.15 μm and less than 1 μm;) The average thickness of the first edge region 40 is less than the average thickness of the second edge region 60, and the difference is greater than 0.3 μm and less than 5 μm. The average thickness of the first edge region 40 is less than the average thickness of the first central region 50; the difference is greater than 0.15 μm and less than 3 μm. The average thickness of the first central region 50 is less than the average thickness of the second edge region 60; the difference is greater than 0.15 μm and less than or equal to 3 μm. It is understood that, since this application does not specify the correspondence between the third edge region 10 and the fourth edge region 30 and the arcuate convex or concave side of the cutting mark S, they are simply two edge regions arranged parallel to each other along the extension direction of the cutting mark S. Therefore, the third edge region 10 and the fourth edge region 30 are structurally equivalent. Thus, in all embodiments or comparative examples, they only need to satisfy the relationship of absolute difference; it is not necessary to limit the third edge region 10 to be larger than the fourth edge region 30 or vice versa.

[0099] Example 2 In the two sets of silicon wafers 100 in this embodiment, each silicon wafer 100 is obtained by sorting according to the following criteria: The average thicknesses of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 all exhibit the following pattern: The average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, with a difference greater than 0.3 μm and less than 2 μm; the average thickness of the fourth edge region 30 is greater than the average thickness of the second central region 20, with a difference greater than 0.15 μm and less than 1 μm; (or, the average thickness of the fourth edge region 30 is greater than the average thickness of the third edge region 10, with a difference greater than 0.3 μm and less than 2 μm; the average thickness of the third edge region 10 is greater than the average thickness of the second central region 20, with a difference greater than 0.15 μm and less than 1 μm;) The average thickness of the first edge region 40 is less than the average thickness of the second edge region 60, and the difference is greater than 0.3 μm and less than 5 μm. The average thickness of the first central region 50 is less than the average thickness of the first edge region 40, and the difference is greater than 0.15 μm and less than 3 μm.

[0100] Example 3 In the two sets of silicon wafers 100 in this embodiment, each silicon wafer 100 is obtained by sorting according to the following criteria: The average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, the average thickness of the second central region 20 is less than the average thickness of the third edge region 10, and the average thickness of the second central region 20 of each silicon wafer 100 is greater than the average thickness of the fourth edge region 30; (or, when the average thickness of the fourth edge region 30 is greater than the average thickness of the third edge region 10, the average thickness of the second central region 20 is less than the average thickness of the fourth edge region 30, and the average thickness of the second central region 20 of each silicon wafer 100 is greater than the average thickness of the third edge region 10), the difference is greater than 0.15 μm and less than 1 μm; The average thickness of the first edge region 40 is less than the average thickness of the second edge region 60, and the difference is greater than 0.3 μm and less than 5 μm. The average thickness of the first edge region 40 is less than the average thickness of the first central region 50; the difference is greater than 0.15 μm and less than 3 μm. The average thickness of the first central region 50 is less than the average thickness of the second edge region 60; the difference is greater than 0.15 μm and less than or equal to 3 μm.

[0101] Example 4 In the two sets of silicon wafers 100 in this embodiment, each silicon wafer 100 is obtained by sorting according to the following criteria: The average thicknesses of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 all exhibit the following pattern: The average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, with a difference greater than 0.3 μm and less than 2 μm; the average thickness of the second central region 20 is less than the average thickness of the third edge region 10, with a difference greater than 0.15 μm and less than 1 μm; and the average thickness of the second central region 20 of each silicon wafer 100 is greater than the average thickness of the fourth edge region 30, with a difference greater than 0.15 μm and less than 1 μm; (The average thickness of the fourth edge region 30 is greater than the average thickness of the third edge region 10, with a difference greater than 0.3 μm and less than 2 μm; the average thickness of the second central region 20 is less than the average thickness of the fourth edge region 30, with a difference greater than 0.15 μm and less than 1 μm; and the average thickness of the second central region 20 of each silicon wafer 100 is greater than the average thickness of the third edge region 10, with a difference greater than 0.15 μm and less than 1 μm;) The average thickness of the first edge region 40 is less than the average thickness of the second edge region 60, and the difference is greater than 0.3 μm and less than 5 μm. The average thickness of the first central region 50 is less than the average thickness of the first edge region 40, and the difference is greater than 0.15 μm and less than 3 μm.

[0102] Comparative Example 1 In the two sets of silicon wafers 100 in this comparative example, the average thickness of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 of each silicon wafer 100 exhibits the following pattern: The average thickness of the fourth edge region 30 is greater than the average thickness of the third edge region 10, with a difference greater than 0.3 and less than 2 μm; the average thickness of the fourth edge region 30 is greater than the average thickness of the second central region 20, with a difference greater than 0.3 and less than 2 μm; the average thickness of the third edge region 10 is greater than the average thickness of the second central region 20, with a difference greater than 0.15 and less than 1 μm; (or, the average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, with a difference greater than 0.3 and less than 2 μm; the average thickness of the third edge region 10 is greater than the average thickness of the second central region 20, with a difference greater than 0.15 and less than 1 μm; the average thickness of the fourth edge region 30 is greater than the average thickness of the second central region 20, with a difference greater than 0.3 and less than 2 μm;) The average thickness of the first edge region 40 is greater than the average thickness of the second edge region 60, and the difference is greater than 0.3 and less than 5 μm. The average thickness of the second edge region 60 is less than the average thickness of the first central region 50; the difference is greater than 0.15 and less than 3 μm. The average thickness of the first central region 50 and the average thickness of the first edge region 40; the difference between them is greater than 0.15 μm and less than or equal to 3 μm; Ten sets of silicon wafers 100 from Examples 1-4 and Comparative Example 1 were transported to a battery workshop for battery cell fabrication under the same conditions. The breakage rate of the ten sets of silicon wafers was calculated. The results showed that, compared with the two sets of silicon wafers in Comparative Example 1, the breakage rate of the two sets of silicon wafers 100 in Examples 1-4 was reduced to varying degrees.

[0103] To further illustrate the reduction, this application presents a relative proportion: using the fragmentation rate of the two groups of silicon wafers 100 in Comparative Example 1 as a baseline (set as 100%), the fragmentation rate ratio of the embodiments relative to this baseline and their reduction ratio are calculated, wherein: The relative proportion of fragmentation rate in the embodiment = (fragmentation rate of each group in the embodiment / fragmentation rate of each group corresponding to Comparative Example 1) × 100%; The reduction rate of fragmentation rate in the embodiment = (fragmentation rate of each group corresponding to Comparative Example 1 - fragmentation rate of each group in the embodiment) / fragmentation rate of each group corresponding to Comparative Example 1 × 100%.

[0104] The results are shown in Table 1 below, with detailed explanations below.

[0105] (1) Compared with the first group of Comparative Example 1, the first group of Examples 1-4 all showed a reduction of nearly 15-40%; compared with the second group of Comparative Example 1, the second group of Examples 1-4 all showed a reduction of nearly 15-50%.

[0106] (2) In the first and second groups, the fragmentation rate of Examples 1-2 is reduced more than that of Examples 3-4, indicating that controlling the average thickness of the second central region 20 of the silicon wafer 100 to be lower than that of the third edge region 10 and the fourth edge region 30 can more effectively reduce the fragmentation rate.

[0107] (3) In the first and second groups, the fragmentation rate of Example 1 is lower than that of Example 2, and the fragmentation rate of Example 3 is lower than that of Example 4. This indicates that making the average thickness of the first central region 50 of the silicon wafer 100 greater than that of the first edge region 40 and less than that of the second edge region 60 can more effectively reduce the fragmentation rate.

[0108] Table 1 The relative proportion of fragmentation rate The percentage reduction in fragmentation rate Comparative Example 1 - Group 1 100% -- Example 1 - Group 1 63% 37% Example 2 - Group 1 68% 32% Example 3 - Group 1 82% 18% Example 4 - Group 1 85% 15% Comparative Example 1 - Group 2 100% -- Example 1 - Group 2 50% 50% Example 2 - Group 2 58% 42% Example 3 - Group 2 82% 18% Example 4 - Group 2 86% 14% The test results show that, in the second direction L1 of the silicon wafer 100, the average thickness of the first edge region 40 of the silicon wafer 100 is less than the average thickness of the second edge region 60. That is, the second edge region 60 located in the arc concave side direction is thickened, which improves the structural strength in the arc concave side direction, thereby effectively enhancing the strength of the silicon wafer, reducing the risk of breakage in the arc concave side direction of the silicon wafer 100, and thus reducing the fragmentation rate.

[0109] In some embodiments, this application also provides a battery cell, the battery cell including a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is the silicon wafer 100 in the above embodiments or the silicon wafer 100 prepared by the above preparation method.

[0110] In some embodiments, this application also provides a photovoltaic module, which includes a plurality of interconnected solar cells, wherein the solar cells are those described in the above embodiments.

[0111] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0112] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A silicon wafer, characterized in that, The silicon wafer is rectangular, and the ratio of its length to its width is 1:0.8 to 1:1; the silicon wafer includes two opposing surfaces and four side surfaces located between the two surfaces; At least one of the surfaces is provided with multiple dicing marks extending along the length or width direction of the silicon wafer; and the dicing marks are arc-shaped; in a direction perpendicular to the extension path of the dicing marks, along the direction from the arc-shaped convex side to the arc-shaped concave side of the dicing marks, the silicon wafer is provided with a first edge region and a second edge region; the first edge region and the second edge region are two edge regions in a direction perpendicular to the extension path of the dicing marks, and the width of the first edge region and the second edge region in a direction perpendicular to the extension path of the dicing marks is greater than or equal to 5 mm and less than or equal to 20 mm; wherein, the average thickness of the first edge region is less than the average thickness of the second edge region.

2. The silicon wafer according to claim 1, characterized in that, The difference between the average thickness of the second edge region and the average thickness of the first edge region is greater than 0.3 μm and less than or equal to 10 μm.

3. The silicon wafer according to claim 1, characterized in that, The difference between the average thickness of the second edge region and the average thickness of the first edge region is greater than 0.3 μm and less than 5 μm.

4. The silicon wafer according to claim 1, characterized in that, Along the direction from the convex side to the concave side of the cut, a first central region is also provided on the silicon wafer. The first central region is located between the first edge region and the second edge region. The average thickness of the first central region is greater than the average thickness of the first edge region and less than the average thickness of the second edge region.

5. The silicon wafer according to claim 4, characterized in that, The difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.1 μm and less than or equal to 5 μm.

6. The silicon wafer according to claim 4, characterized in that, The difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.15 μm and less than or equal to 3 μm.

7. The silicon wafer according to claim 1, characterized in that, Along the direction from the convex side to the concave side of the cut, a first central region is also provided on the silicon wafer. The first central region is located between the first edge region and the second edge region. The average thickness of the first central region is less than the average thickness of the first edge region and the average thickness of the second edge region.

8. The silicon wafer according to claim 7, characterized in that, The difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.1 μm and less than or equal to 5 μm.

9. The silicon wafer according to claim 7, characterized in that, The difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.15 μm and less than or equal to 3 μm.

10. The silicon wafer according to claim 1, characterized in that, The silicon wafer has chamfers at all four corners; the chamfers are either curved or straight.

11. The silicon wafer according to claim 10, characterized in that, The projected length of each chamfer on the edge of the silicon wafer is greater than or equal to 0.05 mm and less than or equal to 9 mm.

12. The silicon wafer according to any one of claims 1-11, characterized in that, Along a direction parallel to the dicing path, the silicon wafer is provided with a third edge region, a second center region, and a fourth edge region. The third edge region and the fourth edge region are two edge regions along a direction parallel to the dicing path. The width of the third edge region and the fourth edge region in a direction perpendicular to the dicing path is greater than or equal to 5 mm and less than or equal to 20 mm. The second center region is located between the third edge region and the fourth edge region. The average thickness of at least one of the third edge region and the fourth edge region is greater than the average thickness of the second center region.

13. The silicon wafer according to claim 12, characterized in that, The average thickness of the third edge region and the fourth edge region is greater than the average thickness of the second central region.

14. The silicon wafer according to claim 13, characterized in that, The difference between the average thickness of the third edge region or the fourth edge region and the average thickness of the second central region is greater than 0.3 μm and less than or equal to 2 μm.

15. The silicon wafer according to claim 12, characterized in that, The average thickness of the second central region is between the average thickness of the third edge region and the average thickness of the fourth edge region.

16. The silicon wafer according to claim 15, characterized in that, The difference between the average thickness of the third edge region or the fourth edge region and the average thickness of the second central region is greater than 0.15 μm and less than or equal to 1 μm.

17. The silicon wafer according to claim 1, characterized in that, The length of the silicon wafer is 166mm-230mm; and / or the width of the silicon wafer is 166mm-230mm; and / or the number of the dicing marks is greater than 10 and less than 50; and / or the spacing between adjacent dicing marks is greater than 1mm; and / or the arc height of the dicing mark is greater than 1mm and less than 17mm; and / or the depth of the dicing mark is greater than 1μm and less than 15μm.

18. A battery cell, characterized in that, It includes a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is a silicon wafer as described in any one of claims 1-17.

19. A photovoltaic module, characterized in that, It includes a plurality of interconnected battery cells, wherein the battery cells are those as described in claim 18.

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