Silicon wafers, solar cells and photovoltaic modules

Abstract

This invention discloses a silicon wafer, a solar cell, and a photovoltaic module to address the problem of high silicon wafer breakage rate. The silicon wafer is rectangular, with a length-to-width ratio of 1:0.8 to 1:1. At least one surface has multiple dicing marks extending along the length or width direction of the wafer, and these dicing marks are arc-shaped. The silicon wafer also includes a first side convex to the dicing marks and a second side opposite to the first side. The silicon wafer has a first edge region and a second edge region. The first edge region is within 8 mm of the first edge, and the second edge region is within 8 mm of the second edge. The average thickness of the first edge region is less than the average thickness of the second edge region. By thickening the second edge region, the strength of the silicon wafer is effectively enhanced, reducing the risk of breakage and thus lowering the breakage rate.

Description

[0001] This application claims priority to Chinese Patent Application No. 202510170252.7, filed on February 14, 2025, entitled "Silicon Wafers, Solar Cells and Photovoltaic Modules", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of silicon wafer manufacturing technology, and more particularly to a silicon wafer, a solar cell, and a photovoltaic module. Background Technology

[0003] With the development of the photovoltaic industry, silicon wafer sizes are constantly increasing. Larger silicon wafers are more prone to collisions and friction with external elements during manufacturing, transport, handling, and processing, leading to microcracks. These microcracks become stress concentration points, which continue to expand under the influence of external or internal stresses in subsequent processes, ultimately causing the silicon wafer to break. Reducing the breakage rate has become a crucial issue in the management of large-size silicon wafer finished products. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon wafer, a solar cell, and a photovoltaic module to improve the strength of the silicon wafer and reduce the breakage rate.

[0005] In a first aspect, the present invention provides a silicon wafer, the silicon wafer being rectangular, and the length-to-width ratio of the silicon wafer being 1:0.8 to 1:1; the silicon wafer comprising two opposing surfaces and four side surfaces located between the two surfaces; at least one of the surfaces having multiple cutting marks extending along the length or width direction of the silicon wafer; and the cutting marks being arc-shaped; the silicon wafer further comprising a first side to which the cutting marks convex and a second side opposite to the first side; the silicon wafer having a first edge region and a second edge region; the first edge region being a region within 8 mm of the first side, and the second edge region being a region within 8 mm of the second side; the average thickness of the first edge region being less than the average thickness of the second edge region.

[0006] When using the above technical solution, on the one hand, since the length-to-width ratio of the rectangular silicon wafer is 1:0.8 to 1:1, the shape of the silicon wafer is square or approximately square. During the wafer picking, transportation, inspection, or cleaning process, the stress on the silicon wafer should mainly be concentrated at the four corners. The cutting marks, as mechanical damage generated on the surface of the silicon wafer during the cutting process, extend from one side of the silicon wafer to the other side, and their extension path inevitably penetrates or approaches the stress concentration area of ​​the silicon wafer. In addition, the cutting marks are arc-shaped. When the stress at the corners is transmitted to the cutting marks, the force will converge along the arc-shaped surface towards the concave side where the center of curvature is located. This makes the concave side the weakest area. In this application, the silicon wafer is divided into a first edge region and a second edge region in a direction perpendicular to the cutting line extension path, along the direction from the convex side of the cutting line away from the curvature center of the arc to the concave side of the arc. The average thickness of the first edge region is controlled to be less than the average thickness of the second edge region, that is, the second edge region (the cutting area, which is the curvature center of the concave side of the arc) is thickened, thereby improving the structural strength of the second edge region, reinforcing the corners of the region and the stress concentration area on the concave side of the cutting line, thereby effectively enhancing the strength of the silicon wafer, reducing the risk of silicon wafer breakage, and thus reducing the fragmentation rate. On the other hand, during the silicon rod cutting process, the silicon rod is fixed on the resin plate. When the cutting line cuts the last silicon rod, it needs to cut further into the resin plate. The silicon rod is a brittle material, while the resin plate is a plastic material. At the moment of transition from cutting the silicon rod to the resin plate, the stress state changes abruptly, which can easily cause the silicon wafer to break. By thickening the second edge area (that is, the junction between the silicon rod and the resin plate), a smooth stress transition can be formed when the cutting process or even the environment where the cutting line is located changes, further reducing the risk of fragmentation and improving the overall cutting yield.

[0007] Optionally, the absolute difference between the average thickness of the second edge region and the average thickness of the first edge region is greater than 0.3 μm and less than or equal to 10 μm. If the absolute difference is less than 0.3 μm, the increase in thickness of the second edge region is too small, which cannot effectively improve the structural strength of the second edge region and thus cannot effectively reduce the fragmentation rate of the silicon wafer. If the absolute difference is greater than 10 μm, the absolute difference in average thickness between the first and second edge regions is too large, resulting in an excessive difference in strength between the first and second edge regions, which will affect the overall strength of the silicon wafer and increase the risk of microcracks in the silicon wafer.

[0008] Optionally, the absolute difference between the average thickness of the second edge region and the average thickness of the first edge region is greater than 0.3 μm and less than 5 μm.

[0009] Optionally, the silicon wafer further includes a first central region located between the first edge region and the second edge region. The average thickness of the first central region is greater than the average thickness of the first edge region and less than the average thickness of the second edge region. By controlling the average thickness of the first central region to be between these two values, a smooth transition from the first edge region to the second edge region is achieved. In low-impact applications, such as during silicon wafer transportation and inspection, this smooth thickness gradient avoids localized stress changes. Furthermore, by enhancing the overall strength of the silicon wafer in the second edge region, the overall stress distribution of the silicon wafer is optimized, reducing the breakage rate.

[0010] Optionally, the absolute difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.1 μm and less than or equal to 5 μm. If the absolute difference is less than 0.1 μm, the average thickness of the first central region and the first edge region and / or the second edge region are too close, failing to form an effective thickness gradient and stress buffer; if the absolute difference is greater than 5 μm, uneven stress between adjacent silicon wafers during the stacking and transportation of silicon wafers will increase the probability of microcracks in the silicon wafers.

[0011] Optionally, the absolute difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.15 μm and less than or equal to 3 μm.

[0012] Optionally, the silicon wafer further includes a first central region located between the first edge region and the second edge region. The average thickness of the first central region is less than the average thickness of both the first and second edge regions. By controlling the location of the first central region between the first and second edge regions, the structural strength of the four corners and edges of the silicon wafer can be enhanced. In applications with medium to high impact, such as wafer removal and cleaning processes, the reinforcement of the corner and edge regions can effectively resist stress impacts from external forces, reduce the generation of microcracks at the corners and edges, and further reduce the breakage rate.

[0013] Optionally, the absolute difference between the average thickness of the first central region and the average thickness of the first edge region is greater than 0.1 μm and less than or equal to 5 μm; and / or, the absolute difference between the average thickness of the first central region and the average thickness of the second edge region is greater than 0.1 μm and less than or equal to 5 μm. If the absolute difference is less than 0.1 μm, the structural strength of the four corners and edges of the silicon wafer cannot be enhanced; if the absolute difference is greater than 5 μm, the uneven stress between adjacent silicon wafers during the stacking and transportation of silicon wafers will increase the probability of microcracks in the silicon wafers.

[0014] Preferably, the absolute difference between the average thickness of the first central region and the average thickness of the first edge region and / or the second edge region is greater than 0.15 μm and less than or equal to 3 μm.

[0015] Optionally, all four corners of the silicon wafer are chamfered; the chamfers are either curved or straight. Chamfering the four corners of the silicon wafer reduces stress concentration at the corners, thereby lowering the risk of the silicon wafer fragmenting at the corners.

[0016] Optionally, the projected length of each chamfer on the edge of the silicon wafer is greater than or equal to 0.05 mm and less than or equal to 9 mm.

[0017] Optionally, along a direction parallel to the cutting line extension path, the silicon wafer is provided with a third edge region, a second central region, and a fourth edge region; the silicon wafer also includes opposing third and fourth sides, the third edge region being close to the third side and within 10 mm of the third side; the fourth edge region being close to the fourth side and within 10 mm of the fourth side; the second central region is located between the third and fourth edge regions. Wherein, the average thickness of at least one of the third and fourth edge regions is greater than the average thickness of the second central region. By increasing the thickness of the third and / or fourth edge regions, the edge strength of the silicon wafer can be further enhanced. In medium-to-high impact applications, such as wafer removal and cleaning processes, the reinforcement of corner and edge regions can effectively resist stress impacts under external forces and reduce the generation of corner and edge microcracks.

[0018] Optionally, the average thickness of both the third and fourth edge regions is greater than the average thickness of the second central region. By enhancing the average thickness of the edges on both sides of the cut extension direction, combined with the enhancement of the average thickness of the second edge, the generation of corner and edge microcracks can be reduced in medium-to-high impact applications, further reducing the fragmentation rate.

[0019] Optionally, the absolute difference between the average thickness of the third and fourth edge regions and the average thickness of the second central region is greater than 0.3 μm and less than or equal to 2 μm. Setting the absolute difference in average thickness between the second central region and the third and fourth edge regions within the above range can minimize the stress differences between silicon wafers during mass production, thereby reducing the breakage rate and the probability of microcracks during silicon wafer processing.

[0020] Optionally, the average thickness of the second central region is between the average thickness of the third edge region and the average thickness of the fourth edge region. By controlling the average thickness of the second central region to be between the two, the thickness of the silicon wafer along the first direction L1 transitions smoothly from the third edge region to the fourth edge region. In low-impact applications, such as during the transportation and inspection of silicon wafers, the smooth thickness gradient can avoid local stress changes, further optimizing the overall stress distribution of the silicon wafer and reducing the breakage rate.

[0021] Optionally, the absolute difference between the average thickness of the third edge region or the fourth edge region and the average thickness of the second central region is greater than 0.15 μm and less than or equal to 1 μm. If the absolute difference is less than 0.15 μm, the average thickness of the first central region is too close to that of the first edge region and / or the second edge region, which cannot enhance the structural strength of the edge or form an effective thickness gradient distribution; if the absolute difference is greater than 1 μm, the uneven stress between adjacent silicon wafers during the stacking and transportation of silicon wafers will increase the probability of microcracks in the silicon wafers.

[0022] Optionally, the length of the silicon wafer is 166mm-230mm; and / or, the width of the silicon wafer is 166mm-230mm; and / or, the number of the dicing marks is greater than 1 and less than 50; and / or, the spacing between adjacent dicing marks is greater than 1mm; and / or, the arc height of the dicing mark is greater than 1mm and less than 17mm.

[0023] In a second aspect, the present invention also provides a battery cell comprising a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is a silicon wafer as described in any of the preceding claims, and has the same beneficial effects as the first aspect.

[0024] Thirdly, the present invention also provides a photovoltaic module comprising a plurality of interconnected solar cells, wherein the solar cells are those described above, and has the same beneficial effects as the second aspect.

[0025] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0026] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of a silicon wafer (full wafer) provided in an embodiment of this application; Figure 2This is a schematic diagram for measuring the thickness of various parts of the silicon wafer provided in the embodiments of this application; Figure 3 for Figure 1 A schematic diagram showing the positional relationship between the third edge region, the second central region, and the fourth edge region of a silicon wafer.

[0027] The reference numerals in the attached figures are as follows: 100. Silicon wafers; 10. Third edge region; 20. Second central region; 30. Fourth edge region; 40. First edge region; 50. First central region; 60. Second edge region; S. Cutting mark; L1, first direction; L2, second direction. Detailed Implementation

[0028] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0029] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0031] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0033] This invention provides a rectangular silicon wafer with a length-to-width ratio of 1:0.8 to 1:1, specifically 1:0.8, 1:0.9, 1:1, etc. When the length and width are different, the silicon wafer is approximately square; when the length-to-width ratio is 1:1, the silicon wafer is a square with equal length and width.

[0034] In this application, the length of the silicon wafer is 166mm-230mm; the width of the silicon wafer is 166mm-230mm. For example, the size of the silicon wafer can be 166mm×166mm; 182mm×182mm; 182mm×183.75mm; 182mm×192mm; 182mm×210mm; 210mm×210mm; 215mm×215mm; 218mm×218mm; 220mm×220mm; 230mm×230mm.

[0035] See Figure 1 The silicon wafer 100 includes two opposing surfaces and four side surfaces located between the two surfaces; at least one surface is provided with multiple cutting marks S extending along the length or width direction of the silicon wafer 100; the cutting marks S are arc-shaped; the cutting marks S are arc-shaped cutting marks formed along the surface of the silicon wafer 100 and approximately parallel to the two edges of one side of the silicon wafer 100, and such cutting marks generally penetrate the two edges of the other side of the entire silicon wafer 100.

[0036] Because the silicon rod is cut using cutting wires (such as diamond wire, steel wire, tungsten wire, etc.), the cutting wires form arc-shaped cutting marks S on the surface of the silicon rod. The number of cutting marks S is usually greater than 10; the distance between adjacent cutting marks S is greater than 1 mm; the arc height of the cutting mark S (the distance from the bottom to the top of the arc) is generally greater than 1 mm. The number of cutting marks S, the distance between adjacent cutting marks S, and the arc height can be measured using optical microscopes, SEM (scanning electron microscope), AFM (atomic force microscope), surface roughness testers, laser scanning microscopes, and image analysis software. It is understood that, for ease of illustration, [the following is omitted as it is not part of the technical description]. Figure 1 Only a portion of the cut marks S are shown.

[0037] For ease of description, the extension direction of the dicing mark S on the surface of the silicon wafer 100 is used as a reference. The extension direction of the dicing mark S parallel to the surface of the silicon wafer 100 is defined as the first direction L1; the extension direction of the dicing mark S perpendicular to the surface of the silicon wafer 100 is defined as the second direction L2. The first and second sides are two sides of the silicon wafer 100 opposite each other in the second direction L2. The third and fourth sides are two sides of the silicon wafer 100 opposite each other in the first direction L1. The first side is the side to which the dicing mark convexes (i.e., the side to which the dicing mark convexes). Figure 1 The bottom line in the middle), the second side is the side opposite to the first side (i.e. Figure 1 (The top line in the middle).

[0038] refer to Figure 1 Along the second direction L2, the silicon wafer 100 is divided into a first edge region 40, a second edge region 60, and a first intermediate region 50. The first edge region 40 and the second edge region 60 are two edge regions along the second direction L2. The first intermediate region 50 is located between the first edge region 40 and the second edge region 60.

[0039] In this application, the area within 8 mm of the first edge is the first edge region 40; the area within 8 mm of the second edge is the second edge region 60. The first center region 50 is any region other than the first edge region 40 and the second edge region 60.

[0040] During the silicon rod cutting process, the first edge region 40 is the region that first contacts the wire mesh (that is, the inlet end region); the second edge region 60 is the region that is about to detach from the wire mesh when the cutting is almost completed (that is, the outlet end region).

[0041] refer to Figure 3 Along the first direction L1, the silicon wafer 100 is divided into a third edge region 10, a second central region 20, and a fourth edge region 30. The third edge region 10 and the fourth edge region 30 are two edge regions along the first direction L1, and the second central region 20 is located between the third edge region 10 and the fourth edge region 30.

[0042] In this application, the third edge region 10 is close to the third side, and the fourth edge region 30 is close to the fourth side. The region within 10mm of the third side is the third edge region 10; the region within 10mm of the fourth side is the fourth edge region 30.

[0043] During the silicon rod cutting process, the cutting fluid is sprayed onto the silicon rod cutting surface from both sides, forming a spray area on both sides of the cutting surface. The cutting fluid enters the silicon rod along the two sides of the cutting surface to cool the cutting line. The edge areas at the distance from the third side and the fourth side are spray enrichment areas, that is, the third edge area 10 and the fourth edge area 30 roughly correspond to two spray enrichment areas.

[0044] For ease of measurement, the average thickness of the first edge region 40, the first central region 50, the second edge region 60, the third edge region 10, the second central region 20, and the fourth edge region 30 in this application can be measured using the following measuring equipment and methods. Please refer to [link / reference]. Figure 2 The equipment used is a high-precision laser displacement sensor. Three detection lines M1, M2, and M3 are spaced apart along the first direction L1 on the silicon wafer 100 (the positions of the detection lines are selected according to the required measurement location). Each of the three detection lines corresponds to one of three sets of laser probes (two laser probes per set, for a total of six laser probes). Due to the limitations of the laser displacement sensor's own measurement accuracy, during the measurement process, when the sensor detects the silicon wafer and begins measurement, the measurement point is usually already a certain distance from the edge. Therefore, in practical operation, the measurement positions for the thickness of each area are set as follows: The average thickness of the first edge region 40 is within a range of 5mm to 8mm from the first edge (e.g., Figure 2 (n=3 in the text) is the selection range. Any continuous area is selected, and data from at least 1000 measurement points are collected to calculate the average value.

[0045] The average thickness of the second edge region 60 is within the range of 5mm to 8mm from the second edge (e.g., Figure 2 The range is defined as n=1 in the data. Any continuous area is selected, and data from at least 1000 measurement points are collected to calculate the average value.

[0046] The average thickness of the first central region 50: Select the region located at the exact midpoint between the first and second sides (e.g., ... Figure 2 The selection range is defined as n=2 in the data. Data from at least 1000 measurement points within this range are collected and the average value is calculated.

[0047] The average thickness of the third edge region 10 is within the range of 8mm to 10mm from the third edge (e.g., Figure 2 The selection range is defined as M1. Any continuous area is selected, and data from at least 1000 measurement points are collected to calculate the average value.

[0048] The average thickness of the fourth edge region 30 is within the range of 8mm to 10mm from the fourth edge (e.g., Figure 2The selection range is defined as M3 in the middle. Any continuous area is selected, and data from at least 1000 measurement points are collected to calculate the average value.

[0049] The average thickness of the second central region 20: The region located at the exact midpoint between the third and fourth sides (e.g., ...) Figure 2 The selected area is M2. Data from at least 1000 measurement points within this area are collected and the average value is calculated.

[0050] Specifically, at least 1000 points are measured on each detection line, and these 1000 points are divided into three equal parts. An average is calculated for each part, resulting in three averages for each detection line; a total of nine averages are obtained. The average thicknesses of the first edge region 40, the first central region 50, and the second edge region 60 are respectively the first points of M1, M2, and M3 (e.g., ...). Figure 2 The average value at n=3 in the data, the second point of M1, M2 and M3 (as shown in the figure) Figure 2 The average value at n=2 in the middle, the third point of M1, M2 and M3 (e.g. Figure 2 The average thickness of the third edge region 10, the second central region 20, and the fourth edge region 30 is the average thickness of lines M1, M2, and M3, respectively. (The locations of n=1, n=2, and n=3 are selected according to the required measurement location.) The average thickness of the first edge region 40 is less than the average thickness of the second edge region 60.

[0051] When using the above technical solution, on the one hand, since the length-to-width ratio of the rectangular silicon wafer is 1:0.8 to 1:1, the shape of the silicon wafer is square or approximately square. During the wafer picking, transportation, inspection, or cleaning process, the stress on the silicon wafer should mainly be concentrated at the four corners. The cutting marks, as mechanical damage generated on the surface of the silicon wafer during the cutting process, extend from one side of the silicon wafer to the other side, and their extension path inevitably penetrates or approaches the stress concentration area of ​​the silicon wafer. In addition, the cutting marks are arc-shaped. When the stress at the corners is transmitted to the cutting marks, the force will converge along the arc-shaped surface towards the concave side where the center of curvature is located. This makes the concave side the weakest area. In this application, the silicon wafer is divided into a first edge region and a second edge region in a direction perpendicular to the cutting line extension path, along the direction from the convex side of the cutting line away from the curvature center of the arc to the concave side of the arc. The average thickness of the first edge region is controlled to be less than the average thickness of the second edge region, that is, the second edge region (the cutting area, which is the curvature center of the concave side of the arc) is thickened, thereby improving the structural strength of the second edge region, reinforcing the corners of the region and the stress concentration area on the concave side of the cutting line, thereby effectively enhancing the strength of the silicon wafer, reducing the risk of silicon wafer breakage, and thus reducing the fragmentation rate. On the other hand, during the silicon rod cutting process, the silicon rod is fixed on the resin plate. When the cutting line cuts the last silicon rod, it needs to cut further into the resin plate. The silicon rod is a brittle material, while the resin plate is a plastic material. At the moment of transition from cutting the silicon rod to the resin plate, the stress state changes abruptly, which can easily cause the silicon wafer to break. By thickening the second edge area (that is, the junction between the silicon rod and the resin plate), a smooth stress transition can be formed when the cutting process or even the environment where the cutting line is located changes, further reducing the risk of fragmentation and improving the overall cutting yield.

[0052] like Figure 1As shown, in some embodiments, the absolute difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 is greater than 0.3 μm and less than or equal to 10 μm. Exemplarily, the absolute difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 can be 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, etc. If the absolute difference is less than 0.3 μm, the increase in thickness of the second edge region is too small, which cannot effectively improve the structural strength of the second edge region and thus cannot effectively reduce the fragmentation rate of the silicon wafer. If the absolute difference is greater than 10μm, the absolute difference in the average thickness of the first edge region and the second edge region is too large, resulting in an excessive difference in strength between the first edge region and the second edge region. This will affect the overall strength improvement of the silicon wafer and increase the risk of microcracks in the silicon wafer.

[0053] Preferably, the absolute difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 is greater than 0.3 μm and less than or equal to 5 μm. Exemplarily, the absolute difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 can be 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, etc.

[0054] More preferably, the absolute difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 can be greater than 1 and less than 3 μm. For example, the absolute difference between the average thickness of the second edge region 60 and the average thickness of the first edge region 40 can be 0.2 μm, 0.5 μm, 0.8 μm, 0.9 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, etc.

[0055] like Figure 1As shown, in some embodiments, the average thickness of the first central region 50 is greater than the average thickness of the first edge region 40 and less than the average thickness of the second edge region 60. Therefore, in the second direction L2, the average thicknesses of the first edge region 40, the first central region 50, and the second edge region 60 are sequentially increased. By controlling the average thickness of the first central region 50 to be between the two, a smooth transition from the first edge region 40 to the second edge region 60 is achieved. In low-impact applications, such as during the transportation and inspection of silicon wafers, this smooth thickness gradient can avoid localized stress changes. While enhancing the overall strength of the silicon wafer in the second edge region 60, the overall stress distribution of the silicon wafer is further optimized, reducing the breakage rate.

[0056] In some embodiments, based on the configuration where the average thicknesses of the first edge region 40, the first central region 50, and the second edge region 60 are sequentially increased, the absolute difference between the average thickness of the first central region 50 and the average thicknesses of the first edge region 40 and / or the second edge region 60 is greater than 0.1 μm and less than or equal to 5 μm. That is, the absolute difference between the average thickness of the first central region 50 and the average thickness of the first edge region 40 is only greater than 0.1 μm and less than or equal to 5 μm; or, the absolute difference between the average thickness of the first central region 50 and the average thickness of the second edge region 60 is only greater than 0.1 μm and less than or equal to 5 μm; or, the absolute difference between the average thickness of the first central region 50 and the average thicknesses of the first edge region 40 and the second edge region 60 is simultaneously greater than 0.1 μm and less than or equal to 5 μm. For example, the absolute difference between the average thickness of the first central region 50 and the average thickness of the first edge region 40 and / or the second edge region 60 can be 0.2 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 1 μm, 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, etc. If the absolute difference is less than 0.1 μm, the average thickness of the first central region 50 and the first edge region 40 and / or the second edge region 60 is too close, and an effective thickness gradient and stress buffer cannot be formed; if the absolute difference is greater than 5 μm, the uneven stress between adjacent silicon wafers during the stacking and transportation of silicon wafers will increase the probability of microcracks in the silicon wafers.

[0057] Preferably, the absolute difference between the average thickness of the first central region 50 and the average thickness of the first edge region 40 and / or the second edge region 60 is greater than 0.15 μm and less than or equal to 3 μm. Specifically, the absolute difference in average thickness can be 0.16 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc.

[0058] like Figure 1 As shown, in some embodiments, the average thickness of the first central region 50 is less than the average thickness of the first edge region 40 and the average thickness of the second edge region 60, that is, the average thickness of the first central region 50 is less than the average thickness of the first edge region 40 and also less than the average thickness of the second edge region 60. Since the silicon wafer 100 is approximately square, in addition to the second edge region 60 being a weak area, the four corners of the first edge region 40 and the second edge region 60 are also relatively weak areas. By controlling the first central region 50 to be located between the first edge region 40 and the second edge region 60, the structural strength of the four corners and edges of the silicon wafer can be enhanced. In medium-to-high impact application scenarios, such as the wafer removal and cleaning process, the reinforcement of the corner and edge regions can effectively resist the stress impact under external force, reduce the generation of microcracks at the corners and edges, and further reduce the breakage rate.

[0059] Furthermore, based on the premise that the average thickness of the first central region 50 is less than the average thickness of the first edge region 40 and the average thickness of the second edge region 60, the absolute difference between the average thickness of the first central region 50 and the average thickness of the first edge region 40 and / or the second edge region 60 is greater than 0.1 μm and less than or equal to 5 μm. For example, the absolute difference in average thickness can be 0.2 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 1 μm, 1.5 μm, 1.8 μm, 2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, 5 μm, etc. If the absolute difference is less than 0.1 μm, the structural strength of the four corners and edges of the silicon wafer cannot be enhanced; if the absolute difference is greater than 5 μm, uneven stress between adjacent silicon wafers during stacking and transportation will increase the probability of microcracks in the silicon wafers.

[0060] Preferably, the absolute difference between the average thickness of the first central region 50 and the average thickness of the first edge region 40 and / or the second edge region 60 is greater than 0.15 μm and less than or equal to 3 μm. Exemplarily, the absolute difference in average thickness can be 0.16 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc.

[0061] like Figure 1 and Figure 3 As shown, in some embodiments, all four corners of the silicon wafer 100 are chamfered, that is, chamfers are formed between adjacent sides. Both ends of the first edge region 40 and the second edge region 60 are chamfered, and the chamfers are either arc-shaped chamfers or straight chamfers.

[0062] It should be noted that the projected length of a chamfer refers to the orthographic projection length of the chamfer onto either of the two adjacent edges of the silicon wafer. For the same chamfer, its projected lengths on the two adjacent edges may be equal or unequal. If they are unequal, the larger projected length is used as the representative value of the projected length of the chamfer.

[0063] In one alternative approach, the projected lengths of the four chamfers are the same.

[0064] In some embodiments, the projected length of each chamfer is greater than or equal to 0.05 mm and less than or equal to 9 mm. For example, the projected length of each chamfer can be 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm, or 9 mm.

[0065] In another alternative approach, the projected lengths of the four chamfers are not the same.

[0066] In some embodiments, the projected length of the two chamfers of the second edge region 60 is greater than the projected length of the two chamfers of the first edge region 40; specifically, the projected length of the two chamfers of the second edge region 60 is equal to 0.05 mm and less than or equal to 9 mm; the projected length of the two chamfers of the first edge region 40 is less than or equal to 8.5 mm.

[0067] In some embodiments, the projected lengths of the two chamfers of the second edge region 60 are less than the projected lengths of the two chamfers of the first edge region 40; specifically, the projected lengths of the two chamfers of the second edge region 60 are less than or equal to 8.5 mm; and the projected lengths of the two chamfers of the first edge region 40 are greater than or equal to 0.05 mm and less than or equal to 9 mm.

[0068] In some embodiments, the projected lengths of the two chamfers on the same side of the first edge region 40 and the second edge region 60 are greater than the projected lengths of the chamfers on the corresponding other side of the first edge region 40 and the second edge region 60. In some embodiments, the projected lengths of the two chamfers on the same side of the first edge region 40 and the second edge region 60 are less than or equal to 8.5 mm; the projected lengths of the two chamfers on the other side of the first edge region 40 and the second edge region 60 are greater than or equal to 0.05 mm and less than or equal to 9 mm.

[0069] If the projected length of the chamfer is less than 0.05 mm, the chamfer size is too small, making it difficult to remove stress concentration at the corner, which can easily lead to microcracks and increase the risk of breakage. If the projected length of the chamfer is greater than 9 mm, the chamfer size is too large, reducing the effective usable area of ​​the silicon wafer. Therefore, chamfering within the above range can reduce stress concentration at the corner of silicon wafer 100, reduce the risk of breakage or microcracks at the corner, improve silicon rod utilization and the effective usable area of ​​silicon wafer 100, and reduce the difficulty of chamfering.

[0070] In one alternative embodiment, the average thickness of at least one of the third edge region 10 and the fourth edge region 30 is greater than the average thickness of the second central region 20. By increasing the thickness of the third edge region 10 and / or the fourth edge region 30, the edge strength of the silicon wafer can be further enhanced. In medium-to-high impact applications, such as wafer removal and cleaning processes, the reinforcement of corner and edge regions can effectively resist stress impacts under external forces and reduce the generation of corner and edge microcracks.

[0071] In some embodiments, the average thickness of the third edge region 10 and the fourth edge region 30 is greater than the average thickness of the second central region 20. By increasing the average thickness of the edges on both sides of the cutting mark extension direction, the generation of corner and edge microcracks can be reduced in medium-to-high impact applications, further reducing the fragmentation rate.

[0072] like Figure 3As shown, in some embodiments, the absolute difference in average thickness between the third edge region 10 or the fourth edge region 30 and the second central region 20 is greater than 0.3 μm and less than or equal to 2 μm. Specifically, the aforementioned absolute difference refers to an absolute difference whether only the third edge region 10, only the fourth edge region 30, or both have an average thickness greater than the second central region, in which case the absolute difference in average thickness between the two is greater than 0.3 μm and less than or equal to 2 μm; for example, the absolute difference can be 0.31 μm, 0.4 μm, 0.5 μm, 1 μm, 1.1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 1.9 μm, 2 μm, etc.

[0073] Preferably, the absolute difference in average thickness between the third edge region 10 or the fourth edge region 30 and the second central region 20 is greater than 0.5 μm and less than or equal to 1 μm. Exemplarily, the absolute difference can be 0.51 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, 0.85 μm, 0.9 μm, 0.95 μm, 1 μm, etc.

[0074] In some embodiments, the average thickness of the second central region 20 is between the average thickness of the third edge region 10 and the average thickness of the fourth edge region 30. Specifically, when the average thickness of the third edge region 10 is less than the average thickness of the fourth edge region 30, the average thickness of the second central region 20 is greater than the average thickness of the third edge region 10 and less than the average thickness of the fourth edge region 30; or, when the average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, the average thickness of the second central region 20 is greater than the average thickness of the fourth edge region 30 and less than the average thickness of the third edge region 10. By controlling the average thickness of the second central region 20 to be between these two values, the thickness of the silicon wafer along the direction parallel to the dicing path transitions smoothly from the third edge region 10 to the fourth edge region 30. In low-impact applications, such as during silicon wafer transportation and inspection, this smooth thickness gradient avoids localized stress changes, further optimizing the overall stress distribution of the silicon wafer and reducing the breakage rate.

[0075] In some embodiments, the absolute difference between the average thickness of the third edge region 10 or the fourth edge region 30 and the average thickness of the second central region 20 is greater than 0.15 μm and less than or equal to 1 μm. Specifically, the above-mentioned absolute difference refers to an absolute difference. For example, the absolute difference can be 0.16 μm, 0.18 μm, 0.2 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, etc.

[0076] Preferably, the absolute difference between the average thickness of the third edge region 10 or the fourth edge region 30 and the average thickness of the second central region 20 is greater than 0.25 μm and less than or equal to 0.5 μm. Specifically, the above-mentioned absolute difference refers to an absolute difference. For example, the absolute difference can be 0.26 μm, 0.28 μm, 0.3 μm, 0.32 μm, 0.34 μm, 0.36 μm, 0.38 μm, 0.4 μm, 0.42 μm, 0.45 μm, 0.47 μm, 0.5 μm, etc.

[0077] The silicon wafer in this application can be prepared by the following method, including steps S100 and S200.

[0078] S100 provides single-crystal rectangular silicon rods. Specifically, single-crystal rectangular silicon rods can be formed by Czochralski pulling of single crystals, truncating, squaring, and chamfering.

[0079] S200 involves bonding the monocrystalline rectangular silicon rod and then fixing it onto a cutting device for cutting.

[0080] The cutting equipment can be a diamond wire cutter, which forms a diamond wire cutting mesh on the main roller through the guidance of guide rollers. By raising or lowering the equipment, the diamond wire cutting mesh can enter the interior of the single crystal rectangular silicon rod through friction. During the cutting process, by controlling the ratio of the amount of wire entering to the amount of wire returning, the average thickness of the first edge region, the first center region and the second edge region of the silicon wafer can be controlled.

[0081] Furthermore, a single-crystal rectangular silicon rod is positioned directly above the dicing wire mesh, and spray devices can be installed on both sides of the single-crystal rectangular silicon rod. The spray devices spray cutting fluid from both sides of the dicing surface toward the dicing wire mesh. The cutting fluid enters the dicing kerf at different positions along with the dicing wire mesh to cool it. By setting the spray position or spray angle, for example, by controlling the distance between the single-crystal rectangular silicon rod and the cutting fluid surface, controlling the horizontal distance between the spray device and the silicon rod, or controlling the spray device to spray the cutting fluid toward the dicing wire mesh from both sides at a certain angle, the cutting fluid can be maximized to enter the kerf. This results in the thermal expansion of the central region being greater than that of the edge region, ultimately making the average thickness of at least one of the third and fourth edge regions greater than the average thickness of the second central region.

[0082] In addition, after the silicon wafers are cut and before they are transported to the cell end, they can be cleaned, sorted and inspected.

[0083] To make the objectives, technical solutions, and beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments 1-4 and comparative example 1. However, the specific embodiments described are only used to explain the present invention and are not intended to limit the present invention.

[0084] Examples 1-4 and Comparative Example 1 all produced silicon wafers with different thickness distributions by controlling the slicing process. It is understood that, in actual production, silicon wafers must simultaneously meet multiple requirements, such as electrical performance (e.g., resistivity, minority carrier lifetime), geometric dimensions (e.g., average thickness, total thickness variation TTV), and appearance quality (e.g., edge chipping, microcracks). Furthermore, silicon wafers with thickness distributions that do not meet design requirements are inevitably produced during the process. Therefore, the silicon wafers involved in Examples 1-4 and Comparative Example 1 all need to be sorted before they can be obtained. Examples 1-4 and Comparative Example 1 are all normal silicon wafers that have been sorted and tested for defects such as resistivity, minority carrier lifetime, average thickness, TTV, edge chipping, and microcracks using the same sorting machine. They can be divided into two groups based on their size and thickness: The first group consists of 10,000 wafers, each measuring 182mm × 182mm. Each wafer has four chamfers of the same size, with a projected length of ≥0.05mm and ≤9mm for each chamfer. The average thickness of each wafer is between 125-135μm.

[0085] The second group consists of 10,000 wafers, each measuring 182mm × 182mm. Each wafer has four chamfers of the same size, with a projected length of ≥0.05mm and ≤9mm for each chamfer. The average thickness of each wafer is between 105-115μm.

[0086] In Examples 1-4 and Comparative Example 1, the two sets of silicon wafers were again passed through the high-precision laser displacement sensor on the sorting machine described above, such as... Figure 1 As shown, in the second direction L2, a first edge region 40, a first center region 50, and a second edge region 60 are provided; in the first direction L1, a third edge region 10, a second center region 20, and a fourth edge region 30 are provided; wherein, the third edge region 10 is the region within 8mm of the third edge, the fourth edge region 30 is the region within 8mm of the fourth edge, and the second center region 20 is located between the third edge region 10 and the fourth edge region 30; the first edge region 40 is the region within 8mm of the first edge, the second edge region 60 is the region within 8mm of the second edge, and the first center region 50 is located between the first edge region 40 and the second edge region 60; the number of cutting marks S is between 10 and 50, the distance between adjacent cutting marks is greater than 1mm, and the arc height of the cutting mark S is greater than 1mm and less than 17mm. Using the above... Figure 2 The average thickness of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 was measured using the test method. Furthermore, the average thicknesses of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 of the two sets of silicon wafers in Examples 1-4 and Comparative Example 1 are slightly different.

[0087] Example 1 In this embodiment, each silicon wafer in the two sets of wafers is sorted according to the following criteria: The average thickness of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 satisfies the following condition: The average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, with an absolute difference greater than 0.3 μm and less than 2 μm; the average thickness of the fourth edge region 30 is greater than the average thickness of the second central region 20, with an absolute difference greater than 0.15 μm and less than 1 μm; (or, the average thickness of the fourth edge region 30 is greater than the average thickness of the third edge region 10, with an absolute difference greater than 0.3 μm and less than 2 μm; the average thickness of the third edge region 10 is greater than the average thickness of the second central region 20, with an absolute difference greater than 0.15 μm and less than 1 μm;) The average thickness of the first edge region 40 is less than the average thickness of the second edge region 60, and the absolute difference is greater than 0.3 μm and less than 5 μm. The average thickness of the first edge region 40 is less than the average thickness of the first central region 50; the absolute difference is greater than 0.15 μm and less than 3 μm. The average thickness of the first central region 50 is less than the average thickness of the second edge region 60; the absolute difference is greater than 0.15 μm and less than 3 μm.

[0088] Example 2 In this embodiment, each silicon wafer in the two sets of wafers is sorted according to the following criteria: The average thickness of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 satisfies the following condition: The average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, with an absolute difference greater than 0.3 μm and less than 2 μm; the average thickness of the fourth edge region 30 is greater than the average thickness of the second central region 20, with an absolute difference greater than 0.15 μm and less than 1 μm; (or, the average thickness of the fourth edge region 30 is greater than the average thickness of the third edge region 10, with an absolute difference greater than 0.3 μm and less than 2 μm; the average thickness of the third edge region 10 is greater than the average thickness of the second central region 20, with an absolute difference greater than 0.15 μm and less than 1 μm;) The average thickness of the first edge region 40 is less than the average thickness of the second edge region 60, and the absolute difference is greater than 0.3 μm and less than 5 μm. The average thickness of the first central region 50 is less than the average thickness of the first edge region 40, and the absolute difference is greater than 0.15 μm and less than 3 μm.

[0089] Example 3 In this embodiment, each silicon wafer in the two sets of wafers is sorted according to the following criteria: The average thickness of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 satisfies the following condition: The average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, the average thickness of the second central region 20 is less than the average thickness of the third edge region 10, and the average thickness of the second central region 20 of each silicon wafer is greater than the average thickness of the fourth edge region 30; (or, when the average thickness of the fourth edge region 30 is greater than the average thickness of the third edge region 10, the average thickness of the second central region 20 is less than the average thickness of the fourth edge region 30, and the average thickness of the second central region 20 of each silicon wafer is greater than the average thickness of the third edge region 10), the absolute difference between the three is greater than 0.15 μm and less than 1 μm; The average thickness of the first edge region 40 is less than the average thickness of the second edge region 60, and the absolute difference is greater than 0.3 μm and less than 5 μm. The average thickness of the first edge region 40 is less than the average thickness of the first central region 50; the absolute difference is greater than 0.15 μm and less than 3 μm. The average thickness of the first central region 50 is less than the average thickness of the second edge region 60; the absolute difference is greater than 0.15 μm and less than 3 μm.

[0090] Example 4 In this embodiment, each silicon wafer in the two sets of wafers is sorted according to the following criteria: The average thickness of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region, the first central region 50, and the second edge region 60 satisfies the following condition: The average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, with an absolute difference greater than 0.3 μm and less than 2 μm; the average thickness of the second center region 20 is less than the average thickness of the third edge region 10, with an absolute difference greater than 0.15 μm and less than 1 μm; and the average thickness of the second center region 20 of each silicon wafer is greater than the average thickness of the fourth edge region 30, with an absolute difference greater than 0.15 μm and less than 1 μm; (The average thickness of the fourth edge region 30 is greater than the average thickness of the third edge region 10, with an absolute difference greater than 0.3 μm and less than 2 μm; the average thickness of the second center region 20 is less than the average thickness of the fourth edge region 30, with an absolute difference greater than 0.15 μm and less than 1 μm; and the average thickness of the second center region 20 of each silicon wafer is greater than the average thickness of the third edge region 10, with an absolute difference greater than 0.15 μm and less than 1 μm;) The average thickness of the first edge region 40 is less than the average thickness of the second edge region 60, and the absolute difference is greater than 0.3 μm and less than 5 μm. The average thickness of the first central region 50 is less than the average thickness of the first edge region 40, and the absolute difference is greater than 0.15 μm and less than 3 μm.

[0091] Comparative Example 1 In the two sets of silicon wafers in this comparative example, the average thickness of the third edge region 10, the second central region 20, the fourth edge region 30, the first edge region 40, the first central region 50, and the second edge region 60 of each silicon wafer exhibits the following pattern: The average thickness of the fourth edge region 30 is greater than the average thickness of the third edge region 10, and the absolute difference is greater than 0.3 and less than 2 μm; the average thickness of the fourth edge region 30 is greater than the average thickness of the second central region 20, and the absolute difference is greater than 0.3 and less than 2 μm; the average thickness of the third edge region 10 is greater than the average thickness of the second central region 20, and the absolute difference is greater than 0.15 and less than 1 μm; (or, the average thickness of the third edge region 10 is greater than the average thickness of the fourth edge region 30, and the absolute difference is greater than 0.3 and less than 2 μm; the average thickness of the third edge region 10 is greater than the average thickness of the second central region 20, and the absolute difference is greater than 0.15 and less than 1 μm; the average thickness of the fourth edge region 30 is greater than the average thickness of the second central region 20, and the absolute difference is greater than 0.3 and less than 2 μm).

[0092] The average thickness of the first edge region 40 is greater than the average thickness of the second edge region 60, and the absolute difference is greater than 0.3 and less than 5 μm. The average thickness of the second edge region 60 is less than the average thickness of the first central region 50; the absolute difference is greater than 0.15 and less than 3 μm. The average thickness of the first central region 50 and the average thickness of the first edge region 40; their absolute difference is greater than 0.15 μm and less than 3 μm.

[0093] Ten sets of silicon wafers from Examples 1-4 and Comparative Example 1 were transported to a battery workshop for battery cell fabrication under the same conditions. The breakage rate of the ten sets of silicon wafers was then calculated. The results showed that, compared with the two sets of silicon wafers in Comparative Example 1, the breakage rate of the two sets of silicon wafers in Examples 1-4 was reduced to varying degrees.

[0094] To further illustrate the reduction, this application presents a relative proportion: using the fragmentation rate of the two groups of silicon wafers in Comparative Example 1 as a baseline (set as 100%), the fragmentation rate ratio of the embodiments relative to this baseline and its reduction ratio were calculated, wherein: The relative proportion of fragmentation rate in the embodiment = (fragmentation rate of each group in the embodiment / fragmentation rate of each group corresponding to Comparative Example 1) × 100%; The reduction rate of fragmentation rate in the embodiment = (fragmentation rate of each group corresponding to Comparative Example 1 - fragmentation rate of each group in the embodiment) / fragmentation rate of each group corresponding to Comparative Example 1 × 100%.

[0095] The results are shown in Table 1 below, with detailed explanations below.

[0096] (1) Compared with the first group of Comparative Example 1, the first group of Examples 1-4 all showed a reduction of nearly 15-40%; compared with the second group of Comparative Example 1, the second group of Examples 1-4 all showed a reduction of nearly 15-50%.

[0097] (2) In the first and second groups, the fragmentation rate of Examples 1-2 was reduced more than that of Examples 3-4, indicating that controlling the average thickness of the second central region 20 of the silicon wafer to be lower than that of the third edge region 10 and the fourth edge region 30 can more effectively reduce the fragmentation rate.

[0098] (3) In the first and second groups, the fragmentation rate of Example 1 is lower than that of Example 2, and the fragmentation rate of Example 3 is lower than that of Example 4. This indicates that making the average thickness of the first central region 50 of the silicon wafer greater than that of the first edge region 40 and less than that of the second edge region 60 can more effectively reduce the fragmentation rate.

[0099] Table 1

[0100] The test results show that, in the second direction L1 of the silicon wafer, the average thickness of the first edge region 40 is less than the average thickness of the second edge region 60. That is, the second edge region 60 in the direction of the arc concave side is thickened, which improves the structural strength in the direction of the arc concave side, thereby effectively enhancing the strength of the silicon wafer, reducing the risk of breakage in the direction of the arc concave side of the silicon wafer, and thus reducing the fragmentation rate.

[0101] In some embodiments, this application also provides a solar cell, which includes a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is the silicon wafer in the above embodiments or the silicon wafer prepared by the above preparation method.

[0102] In some embodiments, this application also provides a photovoltaic module, which includes a plurality of interconnected solar cells, wherein the solar cells are those described in the above embodiments.

[0103] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0104] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A silicon wafer, characterized in that, The silicon wafer is rectangular, and the ratio of its length to its width is 1:0.8 to 1:1; the silicon wafer includes two opposing surfaces and four side surfaces located between the two surfaces; At least one of the surfaces is provided with multiple cutting marks extending along the length or width direction of the silicon wafer; and the cutting marks are arc-shaped; the silicon wafer also includes a first side to which the cutting marks convex and a second side opposite to the first side; The silicon wafer has a first edge region and a second edge region; the first edge region is the region within 8 mm of a first edge, and the second edge region is the region within 8 mm of a second edge; the average thickness of the first edge region is less than the average thickness of the second edge region.

2. The silicon wafer according to claim 1, characterized in that, The absolute difference between the average thickness of the second edge region and the average thickness of the first edge region is greater than 0.3 μm and less than or equal to 10 μm.

3. The silicon wafer according to claim 1, characterized in that, The absolute difference between the average thickness of the second edge region and the average thickness of the first edge region is greater than 0.3 μm and less than 5 μm.

4. The silicon wafer according to claim 1, characterized in that, The silicon wafer also has a first central region, which is located between the first edge region and the second edge region. The average thickness of the first central region is greater than the average thickness of the first edge region and less than the average thickness of the second edge region.

5. The silicon wafer according to claim 4, characterized in that, The absolute difference between the average thickness of the first central region and the average thickness of the first edge region is greater than 0.1 μm and less than or equal to 5 μm; And / or, the absolute difference between the average thickness of the second edge region and the average thickness of the first central region is greater than 0.1 μm and less than or equal to 5 μm.

6. The silicon wafer according to claim 4, characterized in that, The absolute difference between the average thickness of the first central region and the average thickness of the first edge region is greater than 0.15 μm and less than or equal to 3 μm; And / or, the absolute difference between the average thickness of the second edge region and the average thickness of the first central region is greater than 0.15 μm and less than or equal to 3 μm.

7. The silicon wafer according to claim 1, characterized in that, The silicon wafer also has a first central region, which is located between the first edge region and the second edge region. The average thickness of the first central region is less than the average thickness of the first edge region and less than the average thickness of the second edge region.

8. The silicon wafer according to claim 7, characterized in that, The absolute difference between the average thickness of the first central region and the average thickness of the first edge region is greater than 0.1 μm and less than or equal to 5 μm; And / or, the absolute difference between the average thickness of the first central region and the average thickness of the second edge region is greater than 0.1 μm and less than or equal to 5 μm.

9. The silicon wafer according to claim 7, characterized in that, The absolute difference between the average thickness of the first central region and the average thickness of the first edge region is greater than 0.15 μm and less than or equal to 3 μm; And / or, the absolute difference between the average thickness of the first central region and the average thickness of the second edge region is greater than 0.15 μm and less than or equal to 3 μm.

10. The silicon wafer according to claim 1, characterized in that, The silicon wafer has chamfers at all four corners; the chamfers are either curved or straight.

11. The silicon wafer according to claim 10, characterized in that, The projected length of each chamfer is greater than or equal to 0.05 mm and less than or equal to 9 mm.

12. The silicon wafer according to any one of claims 1-11, characterized in that, Along a direction parallel to the extension path of the dicing marks, the silicon wafer has a third edge region, a second central region, and a fourth edge region; The silicon wafer also includes a third edge and a fourth edge, the third edge region being close to the third edge and within 10 mm of the third edge; the fourth edge region being close to the fourth edge and within 10 mm of the fourth edge; the second central region being located between the third edge region and the fourth edge region; wherein, the average thickness of at least one of the third edge region and the fourth edge region is greater than the average thickness of the second central region.

13. The silicon wafer according to claim 12, characterized in that, The average thickness of the third edge region and the fourth edge region is greater than the average thickness of the second central region.

14. The silicon wafer according to claim 13, characterized in that, The absolute difference between the average thickness of at least one of the third edge region or the fourth edge region and the average thickness of the second central region is greater than 0.3 μm and less than or equal to 2 μm.

15. The silicon wafer according to claim 12, characterized in that, The average thickness of the second central region is between the average thickness of the third edge region and the average thickness of the fourth edge region.

16. The silicon wafer according to claim 15, characterized in that, The absolute difference between the average thickness of at least one of the third edge region or the fourth edge region and the average thickness of the second central region is greater than 0.15 μm and less than or equal to 1 μm.

17. The silicon wafer according to claim 1, characterized in that, The length of the silicon wafer is 166mm-230mm; and / or the width of the silicon wafer is 166mm-230mm; and / or the number of the dicing marks is greater than 10 and less than 50; and / or the distance between adjacent dicing marks is greater than 1mm; and / or the arc height of the dicing mark is greater than 1mm and less than 17mm.

18. A battery cell, characterized in that, It includes a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is a silicon wafer as described in any one of claims 1-17.

19. A photovoltaic module, characterized in that, It includes a plurality of interconnected battery cells, wherein the battery cells are those as described in claim 18.

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