Silicon wafers, solar cells and photovoltaic modules

Abstract

This invention discloses a silicon wafer, a solar cell, and a photovoltaic module, relating to the field of silicon wafer manufacturing technology, and is used to solve the problem of high silicon wafer breakage rate. The silicon wafer is rectangular, with a length-to-width ratio of 1:0.4 to 1:0.6. The silicon wafer includes two surfaces and four side surfaces located between the two surfaces. At least one surface has multiple arc-shaped cutting marks extending along the width direction of the silicon wafer. Along a direction parallel to the cutting mark extension path, the silicon wafer includes opposing first and second sides. The silicon wafer is sequentially divided into a first edge region, a central region, and a second edge region. The first edge region is close to the first side and is within 10 mm of the first side. The second edge region is close to the second side and is within 10 mm of the second side. The central region is located between the first edge region and the second edge region, wherein the average thickness of the first edge region and / or the average thickness of the second edge region is greater than the average thickness of the central region.

Description

[0001] This application claims priority to Chinese Patent Application No. 202510170252.7, filed on February 14, 2025, entitled "Silicon Wafers, Solar Cells and Photovoltaic Modules", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of silicon wafer manufacturing technology, and more particularly to a silicon wafer, a solar cell, and a photovoltaic module. Background Technology

[0003] With the development of the photovoltaic industry, half-wafers are widely used in the manufacturing of photovoltaic modules. Compared with full-wafers, half-wafers have a long strip structure, and their fragmentation rate is more prominent. During manufacturing, transmission, handling and processing, they are more likely to collide and rub against the outside world, which can lead to microcracks. These microcracks become stress concentration points, which continue to expand under the external force of subsequent processes, eventually causing the silicon wafer to break. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon wafer, a solar cell, and a photovoltaic module to improve the strength of the silicon wafer and reduce the breakage rate.

[0005] In a first aspect, the present invention provides a silicon wafer, the silicon wafer being rectangular, and the length-to-width ratio of the silicon wafer being 1:0.4 to 1:0.6; the silicon wafer comprising two opposing surfaces and four side surfaces located between the two surfaces; at least one of the surfaces having a plurality of dicing marks extending along the width direction of the silicon wafer; the silicon wafer having a first edge region, a central region, and a second edge region along a direction parallel to the extension path of the dicing marks; the silicon wafer comprising opposing first and second sides; the first edge region being close to the first side and being within 10 mm of the first side; the second edge region being close to the second side and being within 10 mm of the second side; the central region being located between the first edge region and the second edge region; wherein the average thickness of the first edge region and the average thickness of at least one of the second edge regions are greater than the average thickness of the central region.

[0006] With the above technical solution, the length-to-width ratio of the rectangular silicon wafer is 1:0.4 to 1:0.6, and the wafer shape is a rectangular structure, which is a half wafer. The cutting marks are mechanical damage generated on the surface of the silicon wafer during the cutting process. In this application, the cutting marks extend along the width of the silicon wafer to the two opposite long sides. Compared to the size of the long side of the silicon wafer, the size of a single cutting mark is smaller, but it runs through the entire width of the silicon wafer. The starting and ending positions of the cutting marks fall on the edge regions parallel to the long sides (the first edge region and the second edge region). During the manufacturing, transport, handling, and processing of the silicon wafer, the four corners of the silicon wafer and the middle section of the long edge (the first edge region and the second edge region) are critical areas of stress concentration. Multiple cutting marks penetrating the edge regions of the long sides further weaken the structural integrity of the long edge, making the long edge more prone to cracking. In this application, by controlling the average thickness of at least one long edge region (first edge region and / or second edge region) to be greater than the average thickness of the central region located between the first edge region and the second edge region, the structural strength of the long edge is improved, thereby reducing the risk of silicon wafer breakage or microcracks as a whole, and thus reducing the breakage rate.

[0007] Optionally, the average thickness of the central region is between the average thickness of the first edge region and the average thickness of the second edge region. By sequentially increasing the average thickness of the first edge region, the central region, and the second edge region along the first direction L1, the strength of one of the long edges of the silicon wafer can be improved while ensuring overall mechanical uniformity by controlling the smooth transition of thickness between adjacent regions. This allows the wafer to better withstand contact-type external force impacts from robotic arms or inspection equipment during wafer handling and inspection processes, further reducing the risk of silicon wafer breakage and microcracks.

[0008] Optionally, the average thickness of the central region is less than the average thickness of the first edge region and less than the average thickness of the second edge region. By controlling the average thickness of the two long edge regions to be greater than the thickness of the central region, the structural strength of both sides of the silicon wafer can be enhanced simultaneously. Under conditions of medium to high impact vibration during cleaning, transportation, etc., stress concentration in the edge region can be effectively alleviated, and the probability of microcracks or breakage at the edge of the silicon wafer can be significantly reduced.

[0009] Optionally, the absolute difference between the average thickness of the central region and the average thickness of the first edge region is greater than 0.1 μm and less than or equal to 1.5 μm; and / or, the absolute difference between the average thickness of the central region and the average thickness of the second edge region is greater than 0.1 μm and less than or equal to 1.5 μm. Setting the average thickness difference between the central region and the first and / or second edge regions within the above range significantly increases the average thickness of the long edge of the silicon wafer, improving the structural strength of the long edge and reducing the likelihood of cracking in the middle section of the long edge, while also preventing excessive differences in average thickness between regions, thereby enhancing the overall strength of the silicon wafer. Furthermore, setting the average thickness difference between the central region and the first and / or second edge regions within the above range also minimizes the stress differences between silicon wafers during mass production, thereby reducing the breakage rate and the probability of microcracks during processing.

[0010] Optionally, the absolute difference between the average thickness of the central region and the average thickness of the first edge region is greater than 0.3 μm and less than or equal to 0.8 μm; and / or, the absolute difference between the average thickness of the central region and the average thickness of the second edge region is greater than 0.3 μm and less than or equal to 0.8 μm.

[0011] Optionally, all four corners of the silicon wafer are chamfered; the chamfers are either curved or straight. Chamfering the four corners of the silicon wafer reduces stress concentration at the corners, thereby lowering the risk of the silicon wafer fragmenting at the corners.

[0012] Optionally, the projected length of the chamfer on the first edge region is greater than or equal to the projected length of the chamfer on the second edge region.

[0013] Optionally, the projected length on the first edge region is greater than or equal to 0.05 mm and less than or equal to 9 mm; and / or, the projected length of the chamfer on the second edge region is greater than or equal to 0.05 mm and less than or equal to 9 mm; and / or, the projected length of the chamfer on the second edge region is less than or equal to 8.5 mm.

[0014] Optionally, the length of the silicon wafer is 166mm-230mm; and / or, the average thickness of the silicon wafer is 100μm-150μm; and / or, the width of the silicon wafer is 80μm-140mm; and / or, the number of dicing marks is greater than 10; and / or, the spacing between adjacent dicing marks is greater than 1mm; and / or, the arc height of the dicing mark is greater than 1mm and less than 17mm.

[0015] In a second aspect, the present invention also provides a battery cell comprising a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is a silicon wafer as described in any of the preceding claims, and has the same beneficial effects as the first aspect.

[0016] Thirdly, the present invention also provides a photovoltaic module comprising a plurality of interconnected solar cells, wherein the solar cells are those described above, and has the same beneficial effects as the second aspect.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of a silicon wafer (half-wafer) provided in an embodiment of this application; Figure 2 This is a schematic diagram for measuring the thickness of a silicon wafer provided in an embodiment of this application.

[0019] The reference numerals in the attached figures are as follows: 100. Silicon wafers; 10. First edge region; 20. Central region; 30. Second edge region; S. Cutting mark; L1, first direction; L2, second direction. Detailed Implementation

[0020] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0021] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0023] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0024] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0025] like Figure 1 As shown, this embodiment of the invention provides a silicon wafer 100, which is rectangular. The length-to-width ratio of the silicon wafer 100 is 1:0.4 to 1:0.6, and the specific ratio can be 1:0.4, 1:0.5, 1:0.6, etc. The silicon wafer 100 is rectangular, and the difference between the length and width of the silicon wafer 100 is relatively large, which is called a half wafer. In this application, the length of the silicon wafer 100 is 166mm-230mm, and the width of the silicon wafer 100 is 80mm-140mm. For example, the dimensions of silicon wafer 100 can be 166mm×83mm; 166mm×91mm; 182mm×91mm; 182mm×105mm; 210mm×91mm; 210mm×105mm; 210mm×110mm; 220mm×105mm; 220mm×110mm; 230mm×110mm; 230mm×115mm; 230mm×120mm. The average thickness of silicon wafer 100 is between 100μm and 150μm, for example, it can be 100μm, 105μm, 110μm, 115μm, 120μm, 125μm, 130μm, 135μm, 140μm, 145μm, or 150μm.

[0026] The silicon wafer 100 provided by the present invention includes two opposing surfaces and four side surfaces located between the two surfaces; at least one surface is provided with multiple cutting marks S extending along the width direction of the silicon wafer 100; the cutting marks S are arc-shaped; the cutting marks S are a kind of arc-shaped cutting mark formed along the surface of the silicon wafer 100 and approximately parallel to the short edge of the silicon wafer 100, and such cutting marks generally penetrate through the two long sides of the entire silicon wafer 100.

[0027] Because the silicon rod is cut using cutting wires (such as diamond wire, steel wire, tungsten wire, etc.), the cutting wires form arc-shaped cutting marks S on the surface of the silicon rod. The number of cutting marks S is usually greater than 10; the distance between adjacent cutting marks S is greater than 1 mm; the arc height of the cutting mark S (the distance from the bottom to the top of the arc) is generally greater than 1 mm. Parameters such as the number of cutting marks S and the distance between adjacent cutting marks S can be measured using optical microscopes, SEM (scanning electron microscope), AFM (atomic force microscope), surface roughness testers, laser scanning microscopes, and image analysis software. It is understood that, for ease of illustration, [the following is omitted as it is not part of the technical description]. Figure 1 Only a portion of the cut marks S are shown.

[0028] For ease of description, the extension direction of the dicing marks S on the surface of the silicon wafer 100 is used as a reference. The extension direction of the dicing marks S parallel to the surface of the silicon wafer 100 is defined as the first direction L1, i.e., the width direction of the silicon wafer; the extension direction of the dicing marks S perpendicular to the surface of the silicon wafer 100 is defined as the second direction L2, i.e., the length direction of the silicon wafer. In the first direction L1, the silicon wafer 100 is provided with a first edge region 10, a central region 20, and a second edge region 30. The first edge region 10 and the second edge region 30 are two edge regions parallel to the direction of the cutting mark S (first direction L1). Specifically, the first edge region 10 and the second edge region 30 are two edge regions parallel to the long side of the silicon wafer 100. The first edge region 10 is actually a portion extending a certain length from the first side of the silicon wafer 100 parallel to the second direction L2 along the first direction L1. The second edge region 30 is actually a portion extending a certain length from the second side of the silicon wafer 100 parallel to the second direction L2 along the first direction L1. The first side and the second side are two opposite sides of the silicon wafer 100 in the first direction L1. The first edge region 10 is closer to the first side, and the second edge region 30 is closer to the second side.

[0029] refer to Figure 1 Along the first direction L1, the silicon wafer 100 is divided into a first edge region 10, a central region 20, and a second edge region 30. The first edge region 10 and the second edge region 30 are two edge regions along the first direction L1, and the central region 20 is located between the first edge region 10 and the second edge region 30.

[0030] During the silicon rod cutting process, the cutting fluid is sprayed onto the silicon rod cutting surface from both sides, forming a spray area on both sides of the cutting surface. The cutting fluid enters the silicon rod along the two sides of the cutting surface to cool the cutting line. The edge areas far from the first side and far from the second side are spray enrichment areas, that is, the first edge area 10 and the second edge area 30 roughly correspond to two spray enrichment areas.

[0031] For ease of measurement, the average thickness of the first edge region 10, the central region 20, and the second edge region 30 in this application can be measured using the following measuring equipment and methods. Please refer to [link / reference]. Figure 2 The equipment used is a high-precision laser displacement sensor. Three detection lines M1, M2, and M3 are spaced apart along the first direction L1 on the silicon wafer 100 (the positions of the detection lines are selected according to the required measurement location). Each detection line corresponds to one of three sets of laser probes (two probes per set, for a total of six probes). Due to limitations in the measurement accuracy of the laser displacement sensor itself, during the measurement process, when the sensor detects the silicon wafer and begins measurement, the measurement point is usually already a certain distance from the edge. Therefore, in practical operation, the measurement positions for the thickness of each area are set as follows: The average thickness of the first edge region 10 is within a range of 8mm to 10mm from the first edge (e.g., Figure 2 Using M1 as the measurement object, arbitrarily select a continuous area and collect data from at least 1000 measurement points to calculate the average value.

[0032] The average thickness of the second edge region 30 is within the range of 8mm to 10mm from the second edge (e.g., Figure 2 Using M3 as the measurement object, arbitrarily select a continuous area and collect data from at least 1000 measurement points to calculate the average value.

[0033] Average thickness of central region 20: Select the area at the exact midpoint between the third and fourth sides (e.g., Figure 2 The measurement object is located at point M3 in the middle of the area. Data from at least 1,000 measurement points in this area are collected and the average value is calculated.

[0034] Specifically, at least 1,000 points are measured on each detection line, and the average thicknesses of the first edge region 10, the central region 20, and the second edge region 30 are the average values ​​of the three lines M1, M2, and M3, respectively.

[0035] The average thickness of the first edge region 10 and / or the average thickness of the second edge region 30 is greater than the average thickness of the central region 20.

[0036] With the above technical solution, the length-to-width ratio of the rectangular silicon wafer is 1:0.4 to 1:0.6, and the wafer shape is a rectangular structure, which is a half wafer. Cutting marks are mechanical damage generated on the surface of the silicon wafer during the cutting process. In this application, the direction of the cutting marks extends along the width of the silicon wafer to the two opposite long sides. Compared to the size of the long side of the silicon wafer, the size of a single cutting mark is smaller, but it runs through the entire width direction of the silicon wafer. The starting and ending positions of the cutting marks fall on the edge regions parallel to the long sides (the first edge region and the second edge region). During the manufacturing, transport, handling, and processing of the silicon wafer, the four corners of the silicon wafer and the middle section of the long side edges (the first edge region and the second edge region) are critical areas of stress concentration. Multiple cutting marks penetrating the edge regions of the long sides further weaken the structural integrity of the long side edges, making them more prone to cracking. In this application, by controlling the average thickness of at least one long edge region (first edge region and / or second edge region) to be greater than the average thickness of the central region located between the first edge region and the second edge region, the structural strength of the long edge is improved, thereby reducing the risk of silicon wafer breakage or microcracks as a whole, and thus reducing the breakage rate.

[0037] In some embodiments, the average thickness of the central region 20 is between the average thickness of the first edge region 10 and the average thickness of the second edge region 30. Specifically, when the average thickness of the first edge region 10 is less than the average thickness of the second edge region 30, the average thickness of the central region 20 is greater than the average thickness of the first edge region 10 and less than the average thickness of the second edge region 30; or, when the average thickness of the first edge region 10 is greater than the average thickness of the second edge region 30, the average thickness of the central region 20 is greater than the average thickness of the second edge region 30 and less than the average thickness of the first edge region 10. By sequentially increasing the average thickness of the first edge region, the central region, and the second edge region in the first direction L1, the strength of one of the long edges of the silicon wafer can be improved while ensuring overall mechanical uniformity by controlling the smooth transition of thickness between adjacent regions. This allows the wafer to better resist contact-type external force impacts from robotic arms or inspection equipment during wafer handling and inspection processes, further reducing the risk of silicon wafer breakage and microcracks.

[0038] In other embodiments, the average thickness of the central region 20 is less than the average thickness of the first edge region 10 and the average thickness of the second edge region 30. By controlling the average thickness of both long edge regions to be greater than the thickness of the central region, the structural strength of both sides of the silicon wafer can be enhanced simultaneously. Under conditions of medium to high impact vibration such as during cleaning and transportation, stress concentration in the edge regions can be effectively alleviated, and the probability of microcracks or breakage at the edges of the silicon wafer can be significantly reduced.

[0039] In some embodiments, the absolute difference between the average thickness of the central region 20 and the average thickness of the first edge region 10 is greater than 0.1 μm and less than or equal to 1.5 μm; the difference can be 0.11 μm, 0.2 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, etc.; and / or, the absolute difference between the average thickness of the central region 20 and the average thickness of the second edge region 30 is greater than 0.1 μm and less than or equal to 1.5 μm; the difference can be 0.11 μm, 0.2 μm, 0.3 μm, 0.5 μm, 0.7 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, etc.

[0040] Preferably, the absolute difference between the average thickness of the central region 20 and the average thickness of the first edge region 10 is greater than 0.3 μm and less than or equal to 0.8 μm; the difference can be 0.31 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, etc. And / or, the absolute difference between the average thickness of the central region 20 and the average thickness of the second edge region 30 is greater than 0.3 μm and less than or equal to 0.8 μm; the difference can be 0.31 μm, 0.4 μm, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, etc.

[0041] In this embodiment, setting the average thickness difference between the central region 20 and the first edge region 10 and / or the second edge region 30 within the aforementioned range can improve the structural strength of the long edge of the silicon wafer, making it less prone to cracking in the middle section of the long edge, while also preventing excessive differences in average thickness between regions, thereby enhancing the overall strength of the silicon wafer 100. Furthermore, setting the absolute difference in average thickness between the central region 20 and the first edge region 10 and / or the second edge region 30 within the aforementioned range can also minimize the stress differences between silicon wafers during mass production, thereby reducing the breakage rate and the probability of microcracks during processing.

[0042] like Figure 1 As shown, in some embodiments, all four corners of the silicon wafer are chamfered; the chamfers are either rounded or straight. Chamfering the four corners of the silicon wafer reduces stress concentration at the corners, thereby lowering the risk of the silicon wafer fragmenting at the corners.

[0043] It should be noted that the projected length of a chamfer refers to the orthographic projection length of the chamfer onto either of the two adjacent edges of the silicon wafer. For the same chamfer, its projected lengths on the two adjacent edges may be equal or unequal. If they are unequal, the larger projected length is used as the representative value of the projected length of the chamfer.

[0044] In some embodiments, the projected length of the chamfer on the first edge region is equal to the projected length of the chamfer on the second edge region.

[0045] In some more specific embodiments, the projected length on the first edge region is greater than or equal to 0.05 mm and less than or equal to 9 mm; and / or, the projected length of the chamfer on the second edge region is greater than or equal to 0.05 mm and less than or equal to 9 mm; the projected length can be 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm or 9 mm.

[0046] In other embodiments, the projected length of the chamfer on the first edge region is greater than the projected length of the chamfer on the second edge region. Since the silicon wafer is a half-wafer, obtained by halving the entire square silicon rod along a direction parallel to the slicing direction (i.e., vertically halving) and then slicing it again, a larger chamfer is typically formed on the original surface of the square silicon rod, while a smaller chamfer is formed on the new cut surface obtained after vertically halving the square silicon rod. On the one hand, a larger chamfer on the silicon wafer can reduce the amount of material removed from the original silicon rod, improving the utilization rate of the silicon rod; on the other hand, a smaller chamfer on the silicon wafer can save grinding time, improve processing efficiency, and increase the effective utilization area of ​​the silicon wafer.

[0047] In some more specific embodiments, the projected length on the first edge region is greater than or equal to 0.05 mm and less than or equal to 9 mm; the projected length can be 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm or 9 mm. The projected length of the chamfer on the second edge region is less than or equal to 8.5 mm; the projected length can be 0.05 mm, 0.06 mm, 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.2 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 4 mm, 5 mm, 6 mm, 7 mm, 8 mm or 8.5 mm.

[0048] If the projected length of the chamfer is less than 0.05 mm, the chamfer size is too small, making it difficult to remove stress concentration at the corner, which can easily lead to microcracks and increase the risk of breakage. If the projected length of the chamfer is greater than 9 mm, the chamfer size is too large, reducing the effective usable area of ​​the silicon wafer. Therefore, chamfering within the above range can reduce stress concentration at the corner of silicon wafer 100, reduce the risk of breakage or microcracks at the corner, improve silicon rod utilization and the effective usable area of ​​silicon wafer 100, and reduce the difficulty of chamfering.

[0049] The silicon wafer 100 described above in this application can be prepared by the following method, including steps S100 and S200.

[0050] S100 provides single-crystal rectangular silicon rods. Specifically, single-crystal rectangular silicon rods can be formed by Czochralski pulling of single crystals, truncating, squaring, and chamfering.

[0051] The squaring process is as follows: A squaring machine feeds the truncated short monocrystalline silicon rod along its length and cuts four parallel planes around its circumference, making the monocrystalline silicon rod into a cuboid or cuboid shape. Then, the corresponding monocrystalline rectangular silicon rod is cut along the second direction L2, i.e., vertically halved, to obtain two monocrystalline rectangular silicon rods. The newly cut ends of each monocrystalline rectangular silicon rod are then chamfered again to obtain rounded or right-angled chamfers, thus obtaining the corresponding half-wafer monocrystalline rectangular silicon rod. It is understood that there are no actual cutting marks during the squaring process; therefore, the L2 direction is actually a pre-planned processing direction in subsequent processes based on target requirements.

[0052] In one optional embodiment, in the single-crystal rectangular silicon rod corresponding to the vertically cut half, the projected length of the chamfer of the second edge region 30 can be less than the projected length of the chamfer on the first edge region 10, such as... Figure 1 As shown.

[0053] The chamfering process: The length of the single-crystal silicon rod after square rooting is chamfered by a grinding wheel to obtain a single-crystal rectangular silicon rod with rounded or straight chamfered corners.

[0054] S200 involves bonding the monocrystalline rectangular silicon rod and then fixing it onto a cutting device for cutting.

[0055] Specifically, the cutting equipment can be a diamond wire cutter, which forms a diamond wire cutting mesh on the main roller through the guidance of guide rollers. The diamond wire cutting mesh is then guided into the interior of the monocrystalline rectangular silicon rod through friction by the raising or lowering of the equipment, until the silicon wafer described in the above embodiment is obtained. The monocrystalline rectangular silicon rod is positioned directly above the cutting mesh, and spray devices can be installed on both sides of the rod. These spray devices spray cutting fluid from both sides towards the cutting mesh, and the cutting fluid enters the kerf at different locations along with the mesh to cool it.

[0056] By setting the spray position or spray angle, for example, by controlling the distance between the single-crystal rectangular silicon rod and the cutting liquid surface, controlling the horizontal distance between the spray device and the silicon rod, or controlling the spray device to spray the cutting liquid from both sides toward the cutting wire mesh at a certain angle, the cutting liquid can be maximized to enter the cut, thereby making the thermal expansion degree of the central region greater than that of the edge region, and ultimately making the average thickness of at least one of the first edge region 10 and the second edge region 30 greater than the average thickness of the central region 20.

[0057] In addition, after the silicon wafer 100 is obtained by cutting and before it is transported to the cell end, the silicon wafer 100 can be cleaned, sorted and inspected.

[0058] Specifically, the cleaning process involves using various acid and alkali tanks inside the cleaning machine to clean the dirt, damaged layers, and other impurities and defects on the cut silicon wafers, ultimately resulting in clean silicon wafers.

[0059] To make the objectives, technical solutions, and beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments 1-2 and comparative example 1. However, the specific embodiments described are only used to explain the present invention and are not intended to limit the present invention.

[0060] Examples 1-2 and Comparative Example 1 both produced silicon wafers with different thickness distributions through controlled slicing processes. It is understood that, in actual production, silicon wafers must simultaneously meet multiple requirements, including electrical properties (such as resistivity and minority carrier lifetime), geometric dimensions (such as average thickness and total thickness variation (TTV), and appearance quality (such as edge chipping and microcracks). Furthermore, the process inevitably produces silicon wafers with thickness distributions that do not meet design requirements. Therefore, the silicon wafers involved in Examples 1-2 and Comparative Example 1 all require sorting before they can be obtained.

[0061] Examples 1-2 and Comparative Example 1 are half-wafers of silicon wafers that have been sorted and inspected using the same sorting machine to determine defects such as resistivity, minority carrier lifetime, thickness, TTV, edge chipping, and microcracks. They can be grouped according to their size and average thickness: The first group consists of 10,000 vertically sliced ​​halves, such as... Figure 1 As shown, each silicon wafer 100 has a size of 182mm × 91mm. The direction of the extension path of the dicing mark S is along the width direction of the silicon wafer 100. The silicon wafer 100 includes 4 chamfers. The dimensions of the two chamfers in the first edge region 10 are greater than the dimensions of the two chamfers in the second edge region 30. The dimensions of the two chamfers in the first edge region 10 are greater than or equal to 0.05mm and less than or equal to 9mm. The projected length of the dimensions of the two chamfers in the second edge region 30 on the side length of the silicon wafer 100 is greater than 0 and less than or equal to 8.5mm. The average thickness of each silicon wafer 100 is between 130-135μm.

[0062] The second group consists of 10,000 vertically sliced ​​halves, such as... Figure 1 As shown, each silicon wafer 100 has a size of 182mm × 91mm. The direction of the extension path of the dicing mark S is along the width direction of the silicon wafer 100. The silicon wafer 100 includes 4 chamfers. The dimensions of the two chamfers in the first edge region 10 are larger than the dimensions of the two chamfers in the second edge region 30. The dimensions of the two chamfers in the first edge region 10 are greater than or equal to 0.05mm and less than or equal to 9mm. The projected length of the dimensions of the two chamfers in the second edge region 30 on the side length of the silicon wafer 100 is greater than 0 and less than or equal to 8.5mm. The average thickness of each silicon wafer 100 is between 105-115μm.

[0063] In Examples 1-2 and Comparative Example 1, both sets of silicon wafers are again passed through a high-precision laser displacement sensor on the sorting machine. A first edge region 10, a central region 20, and a second edge region 30 are defined along a direction parallel to the cutting path. The first edge region 10 of the first and second sets of vertically cut halves is within 8 mm of the adjacent long side, and the second edge region 30 is within 8 mm of the adjacent long side. The central region 20 is located between the first edge region 10 and the second edge region 30. The number of cutting marks is between 10 and 50, the distance between adjacent cutting marks is greater than 1 mm, and the arc height of the cutting marks is greater than 1 mm and less than 17 mm. Using the above... Figure 2 The average thickness of the first edge region 10, the central region 20, and the second edge region 30 was measured using the test method. Furthermore, the average thicknesses of the first edge region 10, the central region 20, and the second edge region 30 of the two sets of silicon wafers in Examples 1-3 and Comparative Example 1 are slightly different.

[0064] Example 1 In this embodiment, each silicon wafer in the two sets of vertically slicing halves is obtained according to the following criteria: The average thickness of the first edge region 10, the central region 20, and the second edge region 30 satisfies the following condition: The average thickness of the first edge region 10 is greater than the average thickness of the second edge region 30, and the difference is greater than 0.3 μm and less than 1.5 μm. The average thickness of the second edge region 30 is greater than the average thickness of the central region 20, and the difference is greater than 0.1 μm and less than 1 μm.

[0065] Example 2 In this embodiment, each silicon wafer in the two sets of vertically slicing halves is obtained according to the following criteria: The average thickness of the first edge region 10, the central region 20, and the second edge region 30 satisfies the following condition: The average thickness of the first edge region 10 is greater than the average thickness of the second edge region 30, and the difference is greater than 0.3 μm and less than 1.5 μm. The average thickness of the first edge region 10 is greater than the average thickness of the central region 20, and the difference is greater than 0.1 μm and less than 1 μm. The average thickness of the second edge region 30 is less than the average thickness of the central region 20, and the difference is greater than 0.1 μm and less than 1 μm.

[0066] Comparative Example 1 In this embodiment, each silicon wafer in the two sets of vertically slicing halves is obtained according to the following criteria: The average thickness of the first edge region 10, the central region 20, and the second edge region 30 satisfies the following condition: The average thickness of the central region 20 is greater than the average thickness of the first edge region 10, and the difference is greater than 0.1 μm and less than 1 μm.

[0067] The average thickness of the central region 20 is greater than the average thickness of the second edge region 30, and the difference is greater than 0.1 μm and less than 1 μm.

[0068] The three groups of silicon wafers from Examples 1-2 and Comparative Example 1 were transported to the battery workshop for battery cell fabrication, and the fragmentation rate of the three groups of silicon wafers was counted. The results showed that, compared with the two groups of vertically cut half wafers in Comparative Example 1, the fragmentation rate of the two groups of vertically cut half wafers in Examples 1-2 was reduced to varying degrees.

[0069] To further illustrate the reduction, this application presents a relative proportion: using the fragmentation rate of the two groups of silicon wafers 100 in Comparative Example 1 as a baseline (set as 100%), the fragmentation rate ratio of the embodiments relative to this baseline and their reduction ratio are calculated, wherein: The relative proportion of fragmentation rate in the embodiment = (fragmentation rate of each group in the embodiment / fragmentation rate of each group corresponding to Comparative Example 1) × 100%; The reduction rate of fragmentation rate in the embodiment = (fragmentation rate of each group corresponding to Comparative Example 1 - fragmentation rate of each group in the embodiment) / fragmentation rate of each group corresponding to Comparative Example 1 × 100%.

[0070] The results are shown in Table 1 below, with detailed explanations below.

[0071] (1) Compared with the first group of vertically cut half pieces in Comparative Example 1, the first group of vertically cut half pieces in Examples 1-2 have a reduction of nearly 15-40%; compared with the second group of vertically cut half pieces in Comparative Example 1, the second group of vertically cut half pieces in Examples 1-2 have a reduction of nearly 15-50%.

[0072] (2) In the first and second groups, the fragmentation rate of Example 1 compared with Example 2 shows that the average thickness of the central region 20 of the vertically cut half is greater than that of the second edge region 30 and less than that of the first edge region 10, which can more effectively reduce the fragmentation rate.

[0073] Table 1

[0074] The test results above show that for vertically cut half wafers, by controlling the average thickness of at least one long edge region (first edge region 10 and / or second edge region 30) to be greater than the average thickness of the central region 20, the structural strength of the long edge is improved, thereby reducing the risk of silicon wafer breakage or microcracks as a whole, and thus reducing the breakage rate.

[0075] In some embodiments, this application also provides a solar cell, which includes a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is the silicon wafer in the above embodiments or the silicon wafer prepared by the above preparation method.

[0076] In some embodiments, this application also provides a photovoltaic module, which includes a plurality of interconnected solar cells, wherein the solar cells are those described in the above embodiments.

[0077] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0078] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A silicon wafer, characterized in that, The silicon wafer is rectangular, and the ratio of its length to its width is 1:0.4 to 1:0.6; the silicon wafer includes two opposing surfaces and four side surfaces located between the two surfaces; At least one of the surfaces has multiple slits extending along the width direction of the silicon wafer; Along a direction parallel to the extension path of the cutting mark, the silicon wafer is provided with a first edge region, a central region, and a second edge region; The silicon wafer includes a first edge and a second edge opposite to each other; the first edge region is close to the first edge and is within 10 mm of the first edge; the second edge region is close to the second edge and is within 10 mm of the second edge; the central region is located between the first edge region and the second edge region; wherein the average thickness of the first edge region and the average thickness of at least one of the second edge regions are greater than the average thickness of the central region.

2. The silicon wafer according to claim 1, characterized in that, The average thickness of the central region is between the average thickness of the first edge region and the average thickness of the second edge region; or, The average thickness of the central region is less than the average thickness of the first edge region and the average thickness of the second edge region.

3. The silicon wafer according to claim 2, characterized in that, The absolute difference between the average thickness of the central region and the average thickness of the first edge region is greater than 0.1 μm and less than or equal to 1.5 μm; And / or, The absolute difference between the average thickness of the central region and the average thickness of the second edge region is greater than 0.1 μm and less than or equal to 1.5 μm.

4. The silicon wafer according to claim 3, characterized in that, The absolute difference between the average thickness of the central region and the average thickness of the first edge region is greater than 0.3 μm and less than or equal to 0.8 μm; And / or, the absolute difference between the average thickness of the central region and the average thickness of the second edge region is greater than 0.3 μm and less than or equal to 0.8 μm.

5. The silicon wafer according to claim 1, characterized in that, The silicon wafer has chamfers at all four corners; the chamfers are either arc-shaped or straight chamfers.

6. The silicon wafer according to claim 5, characterized in that, The projected length of the chamfer on the first edge region is greater than or equal to the projected length of the chamfer on the second edge region.

7. The silicon wafer according to claim 6, characterized in that, The projected length on the first edge region is greater than or equal to 0.05 mm and less than or equal to 9 mm; and / or, the projected length of the chamfer on the second edge region is greater than or equal to 0.05 mm and less than or equal to 9 mm; and / or, the projected length of the chamfer on the second edge region is less than or equal to 8.5 mm.

8. The silicon wafer according to any one of claims 1-7, characterized in that, The length of the silicon wafer is 166mm-230mm; and / or, the average thickness of the silicon wafer is 100μm-150μm; and / or, the width of the silicon wafer is 80μm-140mm; and / or, the number of dicing marks is greater than 10; and / or, the distance between adjacent dicing marks is greater than 1mm; and / or, the arc height of the dicing mark is greater than 1mm and less than 17mm.

9. A type of battery cell, characterized in that, It includes a silicon substrate and electrodes formed on the silicon substrate, wherein the silicon substrate is a silicon wafer as described in any one of claims 1-8.

10. A photovoltaic module, characterized in that, It includes a plurality of interconnected battery cells, wherein the battery cells are those described in claim 9.

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