A tbc cell and method of making the same

Abstract

The application belongs to the technical field of photovoltaics, and provides a TBC cell and a preparation method thereof. The TBC cell comprises a silicon substrate, wherein the silicon substrate has opposite front and back surfaces; the back surface of the silicon substrate comprises N and P regions arranged alternately and spaced apart in a first direction, and an isolation groove is arranged between the N and P regions; the first direction is perpendicular to the thickness direction of the silicon substrate; and along the direction away from the thickness direction of the silicon substrate, a silicon oxynitride layer, an aluminum oxide transition layer and a silicon carbon nitride layer are sequentially arranged in the isolation groove. The silicon oxynitride layer, the aluminum oxide transition layer and the silicon carbon nitride layer realize excellent electrical insulation performance, interface passivation quality and long-term environmental reliability through synergistic effect, and the long-term use stability of the TBC cell is significantly improved.

Description

Technical Field

[0001] This invention belongs to the field of photovoltaic technology, specifically relating to a TBC cell and its preparation method. Background Technology

[0002] Tunneling oxide passivated back contact (TBC) cells have become one of the mainstream technologies for high-efficiency N-type cells due to their advantages such as full back contact, no grid line obstruction, and high passivation quality. Since the electrodes of TBC cells are all distributed on the back of the cell and the P+ / N+ structure is distributed in a forked tooth pattern, a more reliable insulating isolation structure is required to isolate the P / N region to prevent lateral leakage loss.

[0003] The existing TBC battery separators mainly employ the following method: wet etching of trenches → deposition of SiO2 / Al. x O y / Si x N y As an insulating isolation structure for the trench region, this structure has the following main defects: 1) It uses a single SiO2 / Al x O y / Si x N y As an isolation medium, it has defects such as insufficient insulation strength, high interface defects, and easy formation of pinhole leakage channels; 2) In the conventional preparation process, the top silicon nitride structure has insufficient ability to block impurity ions and insufficient resistance to PID in harsh environments. The silicon nitride band gap is about 5eV, which can effectively shield UVC (<280nm), but has weak absorption of UV-A / B (320-400nm), which leads to a large amount of UV penetrating into the interior, breaking Si-H bonds and causing damage to the interface.

[0004] Therefore, improving the insulation strength, interface passivation quality, and UV / PID resistance of the TBC battery isolation trench area is a technical challenge that urgently needs to be addressed. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a TBC battery and its preparation method. This invention employs a stack of silicon oxynitride, alumina transition layer, and silicon carbon nitride layers sequentially arranged within an isolation tank as an insulating isolation structure for insulation barrier and interface passivation. The silicon oxynitride layer, as the bottom interface passivation layer, possesses excellent thermal / chemical stability, precise charge control, low stress, compatibility with low-temperature PEALD / PECVD processes, and high barrier ion capacity, providing excellent interface passivation and effectively preventing impurity ions from diffusing into the silicon substrate. The alumina transition layer, as an insulating transition layer, further enhances the insulation withstand voltage characteristics of the insulating isolation structure and protects the silicon oxynitride layer. The silicon carbon nitride layer, as the top insulating passivation layer, exhibits excellent thermal stability and insulation properties. It belongs to a ternary strong covalent network containing mixed Si-C, Si-N, and CN bonds, with high bond energy, strong structural rigidity, and small porosity. It is compatible with PECVD / ALD processes, allows for precise composition control, enables low-defect, high-coverage deposition, and effectively shields high-energy photons, possessing excellent resistance to UV-induced decay and potential-induced decay, and strong photostability. In summary, this insulating structure achieves excellent electrical insulation performance, interface passivation quality, and long-term environmental reliability through the synergistic effect of the silicon oxynitride layer, aluminum oxide transition layer, and silicon carbon nitride layer, significantly improving the long-term stability of TBC batteries.

[0006] To achieve this objective, the present invention adopts the following technical solution: In a first aspect, the present invention provides a TBC battery, the TBC battery comprising a silicon substrate having opposing front and back sides.

[0007] The back side of the silicon substrate includes alternating N-regions and P-regions along a first direction, with an isolation groove between the N-regions and P-regions; the first direction is perpendicular to the thickness direction of the silicon substrate.

[0008] Along the thickness direction away from the silicon substrate, the isolation trench contains a silicon oxynitride layer, an aluminum oxide transition layer, and a silicon carbon nitride layer in sequence.

[0009] This invention employs a stack of silicon oxynitride, alumina transition layer, and silicon carbon nitride layers sequentially arranged within an isolation tank as an insulating isolation structure for insulation barrier and interface passivation. The silicon oxynitride layer, as the bottom interface passivation layer, possesses excellent thermal / chemical stability, precise charge control, low stress, compatibility with low-temperature PEALD / PECVD processes, and high barrier ion capacity, providing excellent interface passivation and effectively preventing impurity ions from diffusing into the silicon substrate. The alumina transition layer, as an insulating transition layer, further enhances the insulation withstand voltage characteristics of the insulating isolation structure and protects the silicon oxynitride layer. The silicon carbon nitride layer, as the top insulating passivation layer, exhibits excellent thermal stability and insulation properties. It belongs to a ternary strong covalent network containing mixed Si-C, Si-N, and CN bonds, with high bond energy, strong structural rigidity, and small porosity. It is compatible with PECVD / ALD processes, allows for precise composition control, enables low-defect, high-coverage deposition, and effectively shields high-energy photons, possessing excellent resistance to UV-induced decay and potential-induced decay, and strong photostability. In summary, this insulating structure achieves excellent electrical insulation performance, interface passivation quality, and long-term environmental reliability through the synergistic effect of the silicon oxynitride layer, aluminum oxide transition layer, and silicon carbon nitride layer, significantly improving the long-term stability of TBC batteries.

[0010] For example, the silicon substrate may be an N-type monocrystalline silicon wafer, etc.

[0011] Preferably, the interface state density of the silicon oxynitride layer is 4 × 10⁻⁶. 11 cm -2 ·eV -1 -1×10 12 cm -2 ·eV -1 For example, it could be 4×10 11 cm -2 ·eV -1 6×10 11 cm -2 ·eV -1 8×10 11 cm -2 ·eV -1 Or 1×10 12 cm -2 ·eV -1 wait.

[0012] In this invention, the interface state density of the silicon oxynitride layer is basically equivalent to that of silicon oxide, but it has excellent thermal / chemical stability, precise control over fixed charge, low stress, low-temperature PEALD / PECVD compatible process, and high barrier insulator capability, which can provide good interface passivation effect and effectively block the diffusion of impurity ions into the silicon substrate.

[0013] It should be noted that the interface state density of the silicon oxynitride layer is publicly known data and can be obtained from public sources. Preferably, the thickness of the silicon oxynitride layer is 5-30 nm, for example, it can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm or 30 nm, and more preferably 10-25 nm.

[0014] Preferably, the breakdown field strength of the alumina transition layer is 10-15 mV / cm, for example, it can be 10 MV / cm, 11 MV / cm, 12 MV / cm, 13 MV / cm, 14 MV / cm or 15 MV / cm, etc.

[0015] In this invention, the breakdown field strength of the alumina transition layer is more suitable for the silicon-carbon-nitrogen layer.

[0016] It should be noted that the breakdown field strength is tested using either the voltage ramp method or the current ramp method, and the equipment used includes a Keysight B1500A semiconductor parameter analyzer and a Keithley 4200-SCS parameter analyzer.

[0017] Preferably, the thickness of the alumina transition layer is 5-30 nm, for example, it can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm or 30 nm, and is preferably 5-20 nm.

[0018] Preferably, the breakdown field strength of the silicon-carbon-nitrogen layer is 12-18 mV / cm, for example, it can be 12 MV / cm, 13 MV / cm, 14 MV / cm, 15 MV / cm, 16 MV / cm, 17 MV / cm or 18 MV / cm, etc.

[0019] In this invention, the breakdown field strength of the alumina transition layer and the breakdown field strength of the silicon carbon nitride layer work together to make the overall insulation structure have a high critical breakdown voltage. There will be no sudden accumulation of electric field at the interface of the two dielectric layers. The alumina relies on its high breakdown field strength to block the strong electric field from penetrating the substrate, while the silicon carbon nitride blocks the leakage path of defects with its dense and non-porous structure. The two complement each other to make up for the intrinsic insulation shortcomings of the materials.

[0020] Preferably, the band gap of the silicon-carbon-nitrogen layer is 2.5-5 eV, for example, it can be 2.5 eV, 2.7 eV, 3.0 eV, 3.2 eV, 3.5 eV, 3.7 eV, 4.0 eV, 4.5 eV or 5.0 eV.

[0021] In this invention, the silicon-carbon-nitrogen layer has a suitable band gap, which can form a stepped band structure with the alumina transition layer, smoothing the interface band shift, reducing the accumulation of interface trap charges, and giving full play to the synergistic advantages of the two media.

[0022] It should be noted that the band gap of the silicon-carbon-nitrogen layer is publicly known data and can be obtained from public information. Preferably, the thickness of the silicon-carbon-nitrogen layer is 60-300 nm, for example, it can be 60 nm, 100 nm, 150 nm, 200 nm, 250 nm or 300 nm, etc., preferably 120-200 nm.

[0023] Preferably, along the thickness direction away from the silicon substrate, the silicon carbon nitride layer includes a first silicon nitride sublayer and a second silicon nitride sublayer; the carbon content of the first silicon nitride sublayer is greater than the carbon content of the second silicon nitride sublayer; the thickness ratio of the first silicon nitride sublayer and the second silicon nitride sublayer is (10-100):(50-200), wherein the selection range of the first silicon nitride sublayer "10-100" can be, for example, 10, 20, 40, 60, 80 or 100, etc., and the selection range of the second silicon nitride sublayer "50-200" can be, for example, 50, 80, 110, 140, 170 or 200, etc., preferably (30-60):(90-140).

[0024] In this invention, a first silicon nitride sublayer and a second silicon nitride sublayer are stacked as a silicon carbon nitride layer. Furthermore, the carbon content of the first silicon nitride sublayer is greater than that of the second silicon nitride sublayer, and the thickness ratio of the first silicon nitride sublayer and the second silicon nitride sublayer is (10-100):(50-200). This allows the silicon carbon nitride layer to form a continuously and gradually changing stepped band structure, which can smooth the cross-layer band shift and reduce the interface defect state density.

[0025] It should be noted that the C content of the first silicon nitride sublayer or the second silicon nitride sublayer can be obtained by X-ray photoelectron spectroscopy (XPS) or SEM-EDS.

[0026] Preferably, the total thickness of the silicon oxynitride layer, the aluminum oxide transition layer, and the silicon carbon nitride layer is 70-360 nm, for example, it can be 70 nm, 120 nm, 180 nm, 240 nm, 300 nm, or 360 nm.

[0027] Preferably, along the thickness direction away from the silicon substrate, the N region includes a first tunneling layer and an n-type doped polycrystalline silicon layer disposed sequentially.

[0028] Preferably, along the thickness direction away from the silicon substrate, the P-region includes a second tunneling layer and a p-type doped polycrystalline silicon layer disposed sequentially.

[0029] Preferably, the N-region, the P-region, and the isolation trench have a back passivation layer on the side surface facing away from the silicon substrate.

[0030] For example, the thickness of the back passivation layer can be 65-85nm, such as 65nm, 75nm or 85nm.

[0031] Except for the specific composite isolation film layer in the isolation area, the alumina + silicon nitride thin film passivation layers on the front and back sides are consistent with the production line. This is not necessarily related to the high insulating dielectric system of the physical isolation area to be described in this patent. The thickness of the back passivation layer is usually 65-85nm, and the front side is basically the same. Preferably, the front side of the silicon substrate is provided with a front passivation layer.

[0032] For example, the thickness of the front passivation layer can be 65-85nm, such as 65nm, 75nm or 85nm.

[0033] Preferably, the back passivation layer and the front passivation layer each independently comprise an aluminum oxide layer and / or a silicon nitride layer.

[0034] Preferably, the first tunneling layer and the second tunneling layer are each independently a tunneling oxide layer.

[0035] Preferably, the tunneling oxide layer comprises a silicon oxide layer.

[0036] For example, the thickness of the first tunneling layer and the second tunneling layer can each be independently 1.2-2nm, such as 1.2nm, 1.4nm, 1.6nm, 1.8nm or 2nm, etc.

[0037] Preferably, the TBC battery further includes: A first electrode and a second electrode; the first electrode is located in the N region, passes through the back passivation layer, and contacts the n-type doped polysilicon layer; the second electrode is located in the P region, passes through the back passivation layer, and contacts the p-type doped polysilicon layer.

[0038] For example, the materials of the first electrode and the second electrode can be, for example, silver or aluminum.

[0039] In a second aspect, the present invention provides a method for preparing a TBC battery as described in the first aspect, the method comprising the following steps: Provides silicon substrate.

[0040] Alternating N-regions, isolation trenches, and P-regions are formed on the back side of the silicon substrate.

[0041] A silicon oxynitride layer, an aluminum oxide transition layer, and a silicon carbon nitride layer are sequentially deposited in the isolation tank, followed by thermal annealing.

[0042] Preferably, the deposition method of the silicon oxynitride layer includes plasma-enhanced chemical vapor deposition, and the process parameters meet the following conditions: The process temperature is 90-250℃, for example, 90℃, 120℃, 150℃, 180℃, 210℃ or 250℃, etc.; the process pressure is 0.5-5Pa, for example, 0.5Pa, 1.0Pa, 2.0Pa, 3.0Pa, 4.0Pa or 5.0Pa, etc.; the RF power is 100-500W, for example, 100W, 200W, 300W, 400W or 500W, etc.; and the reaction gas source includes silicon source, oxygen source and nitrogen source.

[0043] For example, the silicon source may be silane, the oxygen source may be oxygen, and the nitrogen source may be ammonia.

[0044] Preferably, the deposition method of the alumina transition layer includes plasma-enhanced chemical vapor deposition, and the process parameters meet the following conditions: The process temperature is 90-250℃, for example, 90℃, 120℃, 150℃, 180℃, 210℃ or 250℃, etc.; the process pressure is 0.1-5Pa, for example, 0.1Pa, 0.5Pa, 1.0Pa, 2.0Pa, 3.0Pa, 4.0Pa or 5.0Pa, etc.; the radio frequency power is 100-500W, for example, 100W, 200W, 300W, 400W or 500W, etc.; and the reaction gas source includes aluminum source and oxygen source.

[0045] For example, the aluminum source may be trimethylaluminum (TMA) or the oxygen source may be oxygen or the like.

[0046] Preferably, the deposition method of the silicon-carbon-nitrogen layer includes plasma-enhanced chemical vapor deposition, and the process parameters meet the following conditions: The process temperature is 200-400℃, for example, 200℃, 240℃, 280℃, 320℃, 360℃ or 400℃, etc.; the process pressure is 50-500Pa, for example, 50Pa, 100Pa, 200Pa, 300Pa, 400Pa or 500Pa, etc.; the radio frequency power is 200-700W, for example, 200W, 300W, 400W, 500W, 600W or 700W, etc.; and the reaction gas source includes silicon source, nitrogen source and carbon source.

[0047] For example, the silicon source may be silane, the nitrogen source may be ammonia, and the carbon source may be methane.

[0048] Preferably, the temperature of the heat annealing is 400-460℃, for example, it can be 400℃, 410℃, 420℃, 430℃, 440℃, 450℃ or 460℃, etc.

[0049] Preferably, the heat annealing time is 25-35 minutes, for example, it can be 35 minutes, 30 minutes or 35 minutes.

[0050] Preferably, the atmosphere for the thermal annealing is an inert atmosphere, such as a nitrogen atmosphere.

[0051] Preferably, the preparation method includes the following steps: (1) Provide a silicon substrate.

[0052] A first tunneling layer and a p-type doped polycrystalline silicon layer are sequentially deposited on the back side of the silicon substrate.

[0053] Remove the p-type doped polysilicon layer and the first tunneling layer in the non-P region to expose the silicon substrate.

[0054] (2) A second tunneling layer and an n-type doped polycrystalline silicon layer are sequentially deposited on the back side of the silicon substrate.

[0055] Remove the n-type doped polysilicon layer and the second tunneling layer located in the P region.

[0056] (3) The predetermined area of ​​the isolation trench is etched to expose the silicon substrate.

[0057] A mask layer is deposited on the back side of the silicon substrate, and then the mask layer in the isolation trench is removed.

[0058] (4) A silicon oxynitride layer is deposited in the isolation tank using plasma-enhanced chemical vapor deposition.

[0059] (5) An aluminum oxide transition layer is deposited on the silicon oxynitride layer using plasma-enhanced chemical vapor deposition.

[0060] (6) A first silicon nitride sublayer with a thickness of 10-100 nm and a second silicon nitride sublayer with a thickness of 50-200 nm are sequentially deposited on the alumina transition layer to form a silicon nitride sublayer; the C content of the first silicon nitride sublayer is greater than the C content of the second silicon nitride sublayer.

[0061] (7) In an inert atmosphere, the silicon semi-finished product obtained in step (6) is subjected to thermal annealing at a temperature of 400-460°C for 25-35 minutes.

[0062] (8) Remove the mask layer, and then deposit passivation layers on the front and back sides of the silicon substrate to form a front passivation layer and a back passivation layer, respectively.

[0063] A first electrode and a second electrode are fabricated on the back side of the silicon substrate.

[0064] Preferably, the preparation method includes the following steps: (1) Provide a silicon substrate; A first tunneling layer and a p-type doped polycrystalline silicon layer are sequentially deposited on the back side of the silicon substrate.

[0065] Remove the p-type doped polysilicon layer and the first tunneling layer in the non-P region to expose the silicon substrate.

[0066] (2) A second tunneling layer and an n-type doped polycrystalline silicon layer are sequentially deposited on the back side of the silicon substrate.

[0067] Remove the n-type doped polysilicon layer and the second tunneling layer located in the P region.

[0068] (3) The predetermined area of ​​the isolation trench is etched to expose the silicon substrate.

[0069] A mask layer is deposited on the back side of the silicon substrate, and then the mask layer in the isolation trench is removed.

[0070] (4) A silicon oxynitride layer with a thickness of 5-30 nm is deposited in the isolation tank using plasma-enhanced chemical vapor deposition; the deposition steps of the silicon oxynitride layer include: A silicon substrate is placed in a reaction chamber at a process temperature of 90-250℃ and a process pressure of 0.5-5Pa, and then the deposition cycle is repeated 100-300 times (e.g., 100, 140, 180, 220, 260, or 300 times). Each deposition cycle includes the following steps: introducing silicon source gas into the reaction chamber, controlling the RF power at 100-500W, and the deposition time at 0.2-1s (e.g., 0.2s, 0.3s, 0.5s, 0.7s, 0.9s, or 1.0s); purging; introducing oxygen source gas into the reaction chamber, controlling the RF power at 100-500W, and the deposition time at 1-10s (e.g., 1s, 3s, 5s, 7s, 9s, or 10s); purging; introducing nitrogen source gas into the reaction chamber, controlling the RF power at 100-500W, and deposition... The time is 1-10s (e.g., 1s, 3s, 5s, 7s, 9s, or 10s, etc.); purging; wherein, the flow rate of the silicon source gas is 400-2000 sccm (e.g., 400 sccm, 700 sccm, 1000 sccm, 1300 sccm, 1600 sccm, or 2000 sccm, etc.), the flow rate of the oxygen source gas is 100-1000 sccm (e.g., 100 sccm, 250 sccm, 400 sccm, 550 sccm, 700 sccm, 850 sccm, or 1000 sccm, etc.), and the flow rate of the nitrogen source gas is 1000-5000 sccm (e.g., 1000 sccm, 1800 sccm, 2600 sccm, 3400 sccm, 4200 sccm, or 5000 sccm, etc.).

[0071] (5) An alumina transition layer with a thickness of 5-30 nm is deposited on the silicon oxynitride layer using plasma-enhanced chemical vapor deposition; the deposition steps of the alumina transition layer include: The process temperature of the reaction chamber is controlled at 90-250℃, and the process pressure is 0.1-5Pa. Then, 50-150 deposition cycles (e.g., 50, 75, 100, 125, or 150 cycles) are repeated. Each deposition cycle includes the following steps: introducing aluminum source gas into the reaction chamber, controlling the RF power at 100-500W, and the deposition time at 0.1-5s (e.g., 0.1s, 0.5s, 1.0s, 2.0s, 3.0s, 4.0s, or 5.0s); purging; introducing oxygen source gas into the reaction chamber, controlling the RF power at 100-500W, and deposition... The accumulation time is 2-20s (e.g., 2s, 5s, 8s, 11s, 14s, 17s, or 20s, etc.); purging; wherein the flow rate of the aluminum source gas is 500-2500 sccm (e.g., 500 sccm, 900 sccm, 1300 sccm, 1700 sccm, 2100 sccm, or 2500 sccm, etc.), and the flow rate of the oxygen source gas is 100-1000 sccm (e.g., 100 sccm, 250 sccm, 400 sccm, 550 sccm, 700 sccm, 850 sccm, or 1000 sccm, etc.).

[0072] (6) Using plasma-enhanced chemical vapor deposition, a first nitride silicon carbide sublayer with a thickness of 10-100 nm (e.g., 10 nm, 25 nm, 40 nm, 55 nm, 70 nm, 85 nm, or 100 nm, etc.) and a second nitride silicon carbide sublayer with a thickness of 50-200 nm (e.g., 50 nm, 80 nm, 110 nm, 140 nm, 170 nm, or 200 nm, etc.) are sequentially deposited on the alumina transition layer to form a silicon carbon nitride layer with a thickness of 60-300 nm; the deposition step of the silicon oxynitride layer includes: The process temperature of the reaction chamber is controlled at 200-400℃, and the process pressure at 50-500Pa. Then, silicon source gas, nitrogen source gas, and carbon source gas are introduced into the reaction chamber at a flow ratio of (0.5-1.5):(0.6-1.8):(0.7-2.3) (where the silicon source gas selection range "0.5-1.5" can be, for example, 0.5, 0.7, 0.9, 1.1, 1.3, or 1.5, etc.; the nitrogen source gas selection range "0.6-1.8" can be, for example, 0.6, 0.8, 1.0, 1.2, 1.4, 1.6, or 1.8, etc.; and the carbon source gas selection range "0.7-2.3" can be, for example, 0.7, 1.0, 1.3, 1.6, 1.9, 2.1, or 2.3, etc.). Simultaneously, the RF power is controlled at 100-500W for deposition. A first nitride silicon carbide sublayer with a thickness of 10-100 nm is obtained; wherein the flow rate of the silicon source gas is 500-2000 sccm (e.g., 500 sccm, 800 sccm, 1100 sccm, 1400 sccm, 1700 sccm, or 2000 sccm, etc.), the flow rate of the nitrogen source gas is 500-2000 sccm (e.g., 500 sccm, 800 sccm, 1100 sccm, 1400 sccm, 1700 sccm, or 2000 sccm, etc.), and the flow rate of the carbon source gas is 500-2000 sccm (e.g., 500 sccm, 800 sccm, 1100 sccm, 1400 sccm, 1700 sccm, or 2000 sccm, etc.).

[0073] The process temperature of the reaction chamber is controlled at 200-400℃, and the process pressure at 50-500Pa. Then, silicon source gas, nitrogen source gas, and carbon source gas are introduced into the reaction chamber at a flow ratio of (0.5-1.5):(0.6-1.8):(0.5-1.7) (where the silicon source gas selection range "0.5-1.5" can be, for example, 0.5, 0.7, 0.9, 1.1, 1.3, or 1.5, etc.; the nitrogen source gas selection range "0.6-1.8" can be, for example, 0.6, 0.8, 1.0, 1.2, 1.4, 1.6, or 1.8, etc.; and the carbon source gas selection range "0.5-1.7" can be, for example, 0.5, 0.7, 0.9, 1.1, 1.3, 1.5, or 1.7, etc.). Simultaneously, the RF power is controlled at 100-500W, resulting in the deposition of a first-phase gas with a thickness of 50-200nm. The first silicon nitride sublayer has a carbon content greater than that of the second silicon nitride sublayer. The carbon content of the first silicon nitride sublayer is greater than that of the second silicon nitride sublayer. The flow rate of the silicon source gas is 500-2000 sccm (e.g., 500 sccm, 800 sccm, 1100 sccm, 1400 sccm, 1700 sccm, or 2000 sccm), the flow rate of the nitrogen source gas is 500-2000 sccm (e.g., 500 sccm, 800 sccm, 1100 sccm, 1400 sccm, 1700 sccm, or 2000 sccm), and the flow rate of the carbon source gas is 500-2000 sccm (e.g., 500 sccm, 800 sccm, 1100 sccm, 1400 sccm, 1700 sccm, or 2000 sccm).

[0074] (7) In an inert atmosphere, the silicon semi-finished product obtained in step (6) is subjected to thermal annealing at a temperature of 400-460°C for 25-35 minutes.

[0075] (8) Remove the mask layer, and then deposit passivation layers on the front and back sides of the silicon substrate to form a front passivation layer and a back passivation layer, respectively.

[0076] A first electrode and a second electrode are fabricated on the back side of the silicon substrate. The first electrode is located in the N region and contacts the n-type doped polysilicon layer through the back passivation layer. The second electrode is located in the P region and contacts the p-type doped polysilicon layer through the back passivation layer.

[0077] The numerical range described in this invention includes not only the point values ​​listed above, but also any point values ​​within the numerical ranges not listed above. Due to space limitations and for the sake of brevity, this invention will not exhaustively list all the specific point values ​​included in the range.

[0078] Compared with the prior art, the present invention has the following beneficial effects: This invention employs a stack of silicon oxynitride, alumina transition layer, and silicon carbon nitride layers sequentially arranged within an isolation tank as an insulating isolation structure for insulation barrier and interface passivation. The silicon oxynitride layer, as the bottom interface passivation layer, possesses excellent thermal / chemical stability, precise charge control, low stress, compatibility with low-temperature PEALD / PECVD processes, and high barrier ion capacity, providing excellent interface passivation and effectively preventing impurity ions from diffusing into the silicon substrate. The alumina transition layer, as an insulating transition layer, further enhances the insulation withstand voltage characteristics of the insulating isolation structure and protects the silicon oxynitride layer. The silicon carbon nitride layer, as the top insulating passivation layer, exhibits excellent thermal stability and insulation properties. It belongs to a ternary strong covalent network containing mixed Si-C, Si-N, and CN bonds, with high bond energy, strong structural rigidity, and small porosity. It is compatible with PECVD / ALD processes, allows for precise composition control, enables low-defect, high-coverage deposition, and effectively shields high-energy photons, possessing excellent resistance to UV-induced decay and potential-induced decay, and strong photostability. In summary, this insulating structure achieves excellent electrical insulation performance, interface passivation quality, and long-term environmental reliability through the synergistic effect of the silicon oxynitride layer, aluminum oxide transition layer, and silicon carbon nitride layer, significantly improving the long-term stability of TBC batteries. Attached Figure Description

[0079] Figure 1 This is a schematic diagram of the back structure of the TBC battery provided in Embodiment 1 of the present invention.

[0080] Figure 2 This is a schematic diagram of the back structure of the TBC battery provided in Comparative Example 1 of this invention.

[0081] Among them, 1-silicon substrate; 2-P region; 3-N region; 4-isolation trench; 5-silicon oxynitride layer; 6-alumina transition layer; 7-silicon carbon nitride layer; 8-back aluminum oxide layer; 9-back silicon nitride layer. Detailed Implementation

[0082] The technical solution of the present invention will be further illustrated below through specific embodiments. Those skilled in the art should understand that the embodiments described are merely illustrative of the present invention and should not be construed as limiting the invention in any way.

[0083] The scope of this invention can be defined by lower and upper limits. The selected lower and upper limits define the boundaries of a specific range. The range defined in this way can be defined by the inclusion or exclusion of endpoints. Any endpoint can be independently selected for inclusion or exclusion, and all lower and upper limits can be arbitrarily combined to form new ranges. That is, any lower limit can be combined with any upper limit to form an effective range. For example, if the ranges of 60~120 and 80~110 are listed for specific parameters, it should be understood that the ranges of 60~110 and 80~120 also fall within the scope of this invention. In addition, if the minimum range values ​​1 and 2 are listed, and the maximum range values ​​3, 4 and 5 are also listed, then all ranges of 1~3, 1~4, 1~5, 2~3, 2~4 and 2~5 fall within the scope of this invention. In this invention, the numerical range "a~b" represents a shortened representation of any combination of real numbers between a and b, where a and b are both real numbers. For example, the numerical range "0~5" means that all real numbers between 0 and 5 have been fully listed in this document, and "0~5" is only a shortened representation of this set of numerical combinations. When a parameter is expressed as an integer ≥2, it is equivalent to listing positive integers that meet the requirements, such as 2, 3, 4, 5, 6, 7, 8, 9, 10, etc. When a parameter is expressed as an integer selected from "2~10", it is equivalent to listing any integer among 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0084] In this invention, "a combination of at least two" refers to a quantity greater than or equal to 2 unless otherwise specified. For example, "any one or a combination of at least two" means that any one of the listed items can be selected, or a combination of at least two of the listed items formed in a manner that does not conflict and enables the implementation of this invention. In this invention, unless otherwise specified, the features or solutions corresponding to "and / or" cover any one of two or more related listed items, as well as any and all combinations of the related listed items. The arbitrary and all combinations include any two related listed items, any more related listed items, or a combination of all related listed items. For example, "A and / or B" means a set consisting of A, B, and combinations of A and B, where "containing A and / or B" can be understood, depending on the context of the statement, as containing A, containing B, or simultaneously containing both A and B. In this invention, "optional" means that the corresponding feature, component, step or solution is not necessary, that is, it is selected from either "with" or "without". If there are multiple "optional" limitations in a technical solution, unless otherwise specified and there is no technical conflict or mutual constraint, each "optional" limitation is independent and does not affect the others.

[0085] In this invention, technical features or solutions described using open-ended terms such as "comprising" or "including" do not exclude additional non-conflicting elements beyond the listed elements unless otherwise specified. They are considered to disclose both closed-ended features or solutions consisting solely of the listed elements and open-ended features or solutions that may include additional non-conflicting elements beyond the listed elements. For example, if A includes a1, a2, and a3, unless otherwise specified, this means that A can consist only of a1, a2, and a3, or it can include other non-conflicting elements based on a1, a2, and a3. This corresponds to the disclosure of technical solutions such as "A consists of a1, a2, and a3," "A is selected from a1, a2, and a3," and "A not only includes a1, a2, and a3, but may also include other non-conflicting elements." All embodiments and optional embodiments of this invention, unless otherwise specified and without technical conflict, can be combined to form new technical solutions, and such combinations fall within the scope of this invention. The term "embodiment" as used in this invention means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment or implementation of the invention. The appearance of this phrase in various locations throughout the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand, explicitly and implicitly, that the embodiments described in this invention can be combined with other embodiments that do not conflict with the technology. The ordinal numbers "first," "second," "third," and "fourth," etc., used in the expressions "first aspect," "second aspect," "third aspect," and "fourth aspect" in this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly specifying the importance or quantity of the indicated technical features. They serve only as a non-exhaustive enumeration and do not constitute a closed limitation on quantity.

[0086] In this invention, the order in which the steps are written in the methods described in each embodiment does not imply a strict execution order. The actual execution order of each step should be determined based on its function and possible internal logic. Unless otherwise specified, all steps of this invention can be executed in the order they are written, or in any order without technical conflict. For example, if the method includes steps (a) and (b), it means that the method may include steps (a) and (b) executed sequentially, or it may include steps (b) and (a) executed sequentially. If the method also includes step (c), then step (c) can be added to the method in any order without conflict, including but not limited to the execution order of steps (a), (b), and (c), steps (a), (c), and (b), steps (c), (a), and (b), etc.

[0087] Example 1 This embodiment provides a TBC battery, which includes a silicon substrate having opposing front and back sides.

[0088] Rear structure diagram as shown Figure 1 As shown, the back surface of the silicon substrate 1 includes alternating N-regions 3 and P-regions 2 along a first direction, and an isolation groove 4 is provided between the N-regions 3 and P-regions 2; the first direction is perpendicular to the thickness direction of the silicon substrate 1.

[0089] Along the thickness direction away from the silicon substrate 1, the isolation trench 4 is provided with a silicon oxynitride layer 5, an aluminum oxide transition layer 6 and a silicon carbon nitride layer 7 in sequence; the isolation trench 4 has a width of 90 μm and a depth of 400 nm.

[0090] The N region 3, the P region 2, and the isolation trench 4 have a back passivation layer on the side surface facing away from the silicon substrate 1.

[0091] The silicon substrate has a front passivation layer on its front side.

[0092] The TBC battery also includes: A first electrode and a second electrode; the first electrode is located in the N region, passes through the back passivation layer, and contacts the n-type doped polysilicon layer; the second electrode is located in the P region, passes through the back passivation layer, and contacts the p-type doped polysilicon layer.

[0093] The interface state density of the silicon oxynitride layer is 5 × 10⁻⁶. 11 cm -2 ·eV -1 The thickness of the silicon oxynitride layer is 15 nm; the breakdown field strength of the alumina transition layer is 12 mV / cm; the thickness of the alumina transition layer is 15 nm; the breakdown field strength of the silicon carbon nitride layer is 15 mV / cm; the band gap of the silicon carbon nitride layer is 4.5 eV; the thickness of the silicon carbon nitride layer is 170 nm; along the thickness direction away from the silicon substrate, the silicon carbon nitride layer includes a first silicon nitride sublayer and a second silicon nitride sublayer, the carbon content of the first silicon nitride sublayer is greater than the carbon content of the second silicon nitride sublayer; the thickness ratio of the first silicon nitride sublayer and the second silicon nitride sublayer is 50:120.

[0094] Wherein, the silicon substrate is an N-type single-crystal silicon wafer; along the thickness direction away from the silicon substrate, the N-region includes a first silicon oxide layer and an n-type doped polycrystalline silicon layer disposed sequentially, the thickness of the first silicon oxide layer being 1.5 nm; along the thickness direction away from the silicon substrate, the P-region includes a second silicon oxide layer and a p-type doped polycrystalline silicon layer disposed sequentially, the thickness of the second silicon oxide layer being 1.5 nm; the thickness of the back passivation layer is 82 nm, including a stacked aluminum oxide layer and a silicon nitride layer; the thickness of the front passivation layer is 78 nm, including a stacked aluminum oxide layer and a silicon nitride layer; the first electrode and the second electrode are made of silver.

[0095] This embodiment also provides a method for preparing the above-mentioned TBC battery, the method comprising the following steps: (1) Provide a silicon substrate.

[0096] A first silicon oxide layer and a p-type doped polycrystalline silicon layer are sequentially deposited on the back side of the silicon substrate.

[0097] Remove the p-type doped polysilicon layer and the first silicon oxide layer from the non-P region to expose the silicon substrate.

[0098] (2) A second silicon oxide layer and an n-type doped polysilicon layer are sequentially deposited on the back side of the silicon substrate.

[0099] Remove the n-type doped polysilicon layer and the second silicon oxide layer located in the P region.

[0100] (3) Perform chemical etching on the predetermined area of ​​the isolation trench to expose the silicon substrate.

[0101] A mask layer is deposited on the back side of the silicon substrate, and then the mask layer in the isolation trench is removed.

[0102] (4) A silicon oxynitride layer with a thickness of 5-30 nm is deposited in the isolation tank using plasma-enhanced chemical vapor deposition; the deposition steps of the silicon oxynitride layer include: A silicon substrate was placed in a reaction chamber at a process temperature of 150°C and a process pressure of 2 Pa, and then the deposition cycle was repeated 210 times. Each deposition cycle included the following steps: introducing silane gas at a flow rate of 400-2000 sccm into the reaction chamber, controlling the RF power at 270W, and the deposition time at 0.8s; purging with nitrogen gas at a flow rate of 2000 sccm for 2.5s; introducing oxygen gas at a flow rate of 500 sccm into the reaction chamber, controlling the RF power at 270W, and the deposition time at 3s; purging with nitrogen gas at a flow rate of 2000 sccm for 2.5s; introducing ammonia gas at a flow rate of 3000 sccm into the reaction chamber, controlling the RF power at 270W, and the deposition time at 3s; purging with nitrogen gas at a flow rate of 2000 sccm for 2.5s.

[0103] (5) An alumina transition layer with a thickness of 5-30 nm is deposited on the silicon oxynitride layer using plasma-enhanced chemical vapor deposition; the deposition steps of the alumina transition layer include: The process temperature of the reaction chamber was controlled at 120°C and the process pressure at 0.3 Pa. Then, 80 deposition cycles were repeated. Each deposition cycle included the following steps: introducing TMA at a flow rate of 1000 sccm into the reaction chamber, controlling the RF power at 250 W, and the deposition time at 0.1 s; purging with nitrogen at a flow rate of 2000 sccm for 4 s; introducing oxygen at a flow rate of 500 sccm into the reaction chamber, controlling the RF power at 250 W, and the deposition time at 4 s; and purging with nitrogen at a flow rate of 2000 sccm for 4 s.

[0104] (6) Using plasma-enhanced chemical vapor deposition, a first silicon nitride sublayer with a thickness of 10-100 nm and a second silicon nitride sublayer with a thickness of 50-200 nm are sequentially deposited on the alumina transition layer to form a silicon nitride layer with a thickness of 60-300 nm; the deposition step of the silicon nitride layer includes: The process temperature of the reaction chamber is controlled at 300℃ and the process pressure at 300Pa. Then, silane gas, ammonia gas, and methane gas with a flow ratio of 1:1.2:1.5 are introduced into the reaction chamber, while the radio frequency power is controlled at 500W. Deposition is carried out for 120s to obtain a first nitride silicon carbide sublayer with a thickness of 10-100nm. The flow rate of the silane gas is 1000sccm, the flow rate of the ammonia gas is 1200sccm, and the flow rate of the methane gas is 1500sccm.

[0105] Nitrogen gas with a flow rate of 2000 sccm was used for cleaning for 10 seconds.

[0106] The process temperature of the reaction chamber is controlled at 300℃ and the process pressure at 300Pa. Then, silane gas, ammonia gas, and methane gas with a flow ratio of 1:1.2:1.1 are introduced into the reaction chamber, while the radio frequency power is controlled at 100-500W. Deposition is carried out for 240s to obtain a second nitride silicon carbide sublayer with a thickness of 50-200nm. The flow rate of the silane gas is 1000sccm, the flow rate of the ammonia gas is 1200sccm, and the flow rate of the methane gas is 1100sccm. The carbon content of the first nitride silicon carbide sublayer is greater than that of the second nitride silicon carbide sublayer. Nitrogen gas with a flow rate of 2000 sccm was used for cleaning for 10 seconds.

[0107] (7) The silicon semi-finished product obtained in step (6) is subjected to thermal annealing at 430°C for 30 minutes in a nitrogen atmosphere.

[0108] (8) Remove the mask layer, and then deposit aluminum oxide layers on the front and back sides of the silicon substrate using atomic layer deposition. Then, deposit silicon nitride layers on the aluminum oxide layers using plasma-enhanced chemical vapor deposition, thereby forming a front passivation layer and a back passivation layer, respectively.

[0109] A first electrode and a second electrode are fabricated on the back side of the silicon substrate. The first electrode is located in the N region and contacts the n-type doped polysilicon layer through the back passivation layer. The second electrode is located in the P region and contacts the p-type doped polysilicon layer through the back passivation layer.

[0110] The total thickness and thickness uniformity of the silicon oxynitride layer, aluminum oxide transition layer and silicon carbon nitride layer provided in this embodiment were tested. The test method was to use a full-spectrum ellipsometer to test the sample, which was divided into 5 parts: the four corners and the center.

[0111] The test results are shown in Table 1.

[0112] Table 1

[0113] As shown in Table 1, the film thickness uniformity of the insulating isolation structure deposited in this embodiment is good (thickness uniformity <8%), and the thickness is not much different from the thickness of the doped polysilicon layer in the P / N region, with no large height difference.

[0114] Example 2 The difference between this embodiment and Embodiment 1 is that the process parameters are adjusted so that the thickness ratio of the first silicon nitride sublayer and the second silicon nitride sublayer is 10:220.

[0115] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0116] Example 3 The difference between this embodiment and Embodiment 1 is that the process parameters are adjusted so that the thickness ratio of the first silicon nitride sublayer and the second silicon nitride sublayer is 100:40.

[0117] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0118] Example 4 The difference between this embodiment and Embodiment 1 is that the process parameters are adjusted so that the second silicon nitride sublayer is replaced with a first silicon nitride sublayer of equal thickness.

[0119] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0120] Example 5 The difference between this embodiment and Embodiment 1 is that the process parameters are adjusted so that, along the thickness direction away from the silicon substrate, the silicon carbon nitride layer includes a second silicon nitride sublayer and a first silicon nitride sublayer.

[0121] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0122] Example 6 The difference between this embodiment and Embodiment 1 is that the process parameters are adjusted so that the thickness of the silicon oxynitride layer is 3nm.

[0123] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0124] Example 7 The difference between this embodiment and Embodiment 1 is that the process parameters are adjusted so that the thickness of the silicon oxynitride layer is 35nm.

[0125] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0126] Example 8 The difference between this embodiment and Embodiment 1 is that the process parameters are adjusted so that the thickness of the alumina transition layer is 3nm.

[0127] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0128] Example 9 The difference between this embodiment and Embodiment 1 is that the process parameters are adjusted so that the thickness of the alumina transition layer is 35nm.

[0129] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0130] Comparative Example 1 The difference between this comparative example and Example 1 is that the isolation tank does not contain a silicon oxide layer, an aluminum oxide transition layer, or a silicon carbon nitride layer.

[0131] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0132] The schematic diagram of the back structure of the TBC battery provided in this comparative example is as follows: Figure 2 As shown, the back side of the silicon substrate 1 includes alternating N-regions 3 and P-regions 2 along a first direction, and an isolation trench 4 is provided between the N-regions 3 and P-regions 2; the first direction is perpendicular to the thickness direction of the silicon substrate 1; along the thickness direction away from the silicon substrate 1, a back aluminum oxide layer 8 and a back silicon nitride layer 9 are sequentially provided in the isolation trench 4.

[0133] The passivation performance of the insulating isolation structure located in the isolation trench in the TBC battery provided in Example 1 and Comparative Example 1 was tested. The test steps included: 1) Preparation of test samples: ① Experimental group: The silicon wafer was polished on both sides, and then the silicon oxynitride layer, aluminum oxide transition layer, silicon carbon nitride layer, aluminum oxide layer and silicon nitride layer were deposited sequentially on both sides of the silicon wafer as shown in Example 1. After thermal annealing, the experimental group test sample was obtained.

[0134] ② Control group: The silicon wafer was polished on both sides, and then an aluminum oxide layer and a silicon nitride layer as shown in Comparative Example 1 were deposited on both sides of the silicon wafer in sequence. After that, thermal annealing was performed to obtain the control group test sample.

[0135] 2) The passivation performance of the prepared test samples was tested using a Sinton tester.

[0136] The test results are shown in Table 2.

[0137] Table 2

[0138] As shown in Table 2, the minority carrier lifetime and dark-state saturation current density of the experimental group were significantly better than those of the control group; carrier recombination was reduced and the implicit fill factor (iFF) was improved.

[0139] Comparative Example 2 The difference between this comparative example and Example 1 is that there is no silicon oxynitride layer in the isolation trench.

[0140] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0141] Comparative Example 3 The difference between this comparative example and Example 1 is that there is no aluminum oxide transition layer in the isolation groove.

[0142] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0143] Comparative Example 4 The difference between this comparative example and Example 1 is that there is no silicon carbon nitride layer in the isolation tank.

[0144] The remaining structures, preparation methods, and parameters are consistent with those in Example 1.

[0145] Performance testing The TBC batteries provided in the above embodiments and comparative examples were subjected to photoelectric performance testing and UV resistance testing. The photoelectric performance testing conditions were: AM1.5G, 1000W / m 2The test conditions for UV resistance were: 25℃; spectral range 280-455nm, irradiance 30kWh / m². 2 Ultraviolet radiation 200-250W / m 2 The temperature was 60±5℃ and the relative humidity was 85±5%RH.

[0146] The test results are shown in Table 3.

[0147] Table 3

[0148] analyze: As shown in Table 3, the present invention employs a stack of silicon oxynitride, aluminum oxide transition layer, and silicon carbon nitride layer sequentially within the isolation tank as an insulating isolation structure for insulation barrier and interface passivation. The silicon oxynitride layer, as the bottom interface passivation layer, possesses excellent thermal / chemical stability, precise charge control, low stress, compatibility with low-temperature PEALD / PECVD processes, and high barrier ion capacity, providing excellent interface passivation and effectively preventing impurity ions from diffusing into the silicon substrate. The aluminum oxide transition layer, as an insulating transition layer, further enhances the insulation withstand voltage characteristics of the insulating isolation structure and protects the silicon oxynitride layer. The silicon carbon nitride layer, as the top insulating passivation layer, exhibits excellent thermal stability and insulation properties. It belongs to a ternary strong covalent network containing mixed Si-C, Si-N, and CN bonds, with high bond energy, strong structural rigidity, and small porosity. It is compatible with PECVD / ALD processes, allows for precise composition control, and enables low-defect, high-coverage deposition. Furthermore, this layer effectively shields high-energy photons, possesses excellent resistance to UV-induced decay and potential-induced decay, and exhibits strong photostability. In summary, this insulating structure achieves excellent electrical insulation performance, interface passivation quality, and long-term environmental reliability through the synergistic effect of the silicon oxynitride layer, aluminum oxide transition layer, and silicon carbon nitride layer, significantly improving the long-term stability of TBC batteries.

[0149] As can be seen from the comparison between Example 1 and Examples 2-3, if the thickness ratio of the first silicon nitride sublayer and the second silicon nitride sublayer is too small, the thermal / chemical stability during thermal cycling will deteriorate and the electrical performance parameters will decrease; if the thickness ratio of the first silicon nitride sublayer and the second silicon nitride sublayer is too large, the band gap will narrow and the insulation performance will decrease.

[0150] A comparison of Examples 1 and 4-5 shows that if the second silicon nitride sublayer is replaced with a first silicon nitride sublayer of equal thickness, i.e., no gradient change in C content is set in the silicon nitride sublayer, the band gap transition is not smooth enough, the band abrupt bending is severe, the interface state density increases, and the passivation performance decreases; if the C content in the silicon nitride sublayer is first small and then large along the thickness direction away from the silicon substrate, the band abrupt bending is severe, the interface state density increases, and the passivation performance decreases.

[0151] As can be seen from the comparison between Example 1 and Examples 6-7, if the thickness of the silicon oxynitride layer is too small, the insulation performance will decrease and the UV attenuation will be more severe; if the thickness of the silicon oxynitride layer is too large, stress accumulation will occur, which will not have much impact on efficiency and attenuation, but the warpage of the cell will increase.

[0152] As can be seen from the comparison between Example 1 and Examples 8-9, if the thickness of the alumina transition layer is too small, the chemical stability decreases, the passivation performance decreases, and the opening pressure loss increases; if the thickness of the alumina transition layer is too large, the stress accumulation increases, the thermal cycling defects occur, and the attenuation increases.

[0153] As can be seen from the comparison between Example 1 and Comparative Example 1, if the insulating isolation structure consisting of silicon oxynitride layer, aluminum oxide transition layer and silicon carbon nitride layer is not provided, the passivation effect becomes worse and the overall attenuation becomes larger.

[0154] As can be seen from the comparison between Example 1 and Comparative Example 2, if no silicon oxynitride layer is provided, the direct deposition of aluminum oxide onto the silicon surface will generate a loose, defective native silicon oxide thin layer with a large number of dangling bonds at the interface, resulting in a decrease in passivation performance.

[0155] As can be seen from the comparison between Example 1 and Comparative Example 3, if the alumina transition layer is not provided, there is no high dielectric density alumina layer to buffer it, which leads to a decrease in the overall equivalent insulation density of the insulation isolation structure, a significant decrease in breakdown voltage under the same total film thickness, an increase in current loss, and an increase in synchronous decay.

[0156] As can be seen from the comparison between Example 1 and Comparative Example 4, if the silicon-carbon-nitrogen layer is not provided, the ability to block metal ions decreases, resulting in a decrease in passivation ability and anti-attenuation ability.

[0157] It should be noted that the present invention is illustrated through the above embodiments, but the present invention is not limited to the above process steps, that is, it does not mean that the present invention must rely on the above process steps to be implemented. Those skilled in the art should understand that any improvements to the present invention, equivalent substitutions of the raw materials used in the present invention, additions of auxiliary components, selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

Claims

1. A TBC battery, characterized in that, The TBC battery includes a silicon substrate having opposing front and back sides; The back side of the silicon substrate includes alternating N-regions and P-regions along a first direction, with an isolation groove between the N-regions and P-regions; the first direction is perpendicular to the thickness direction of the silicon substrate. Along the thickness direction away from the silicon substrate, the isolation trench is sequentially provided with a silicon oxynitride layer, an aluminum oxide transition layer, and a silicon carbon nitride layer; Along the thickness direction away from the silicon substrate, the silicon carbon nitride layer includes a first silicon nitride sublayer and a second silicon nitride sublayer; the carbon content of the first silicon nitride sublayer is greater than the carbon content of the second silicon nitride sublayer; the thickness ratio of the first silicon nitride sublayer and the second silicon nitride sublayer is (10-100):(50-200).

2. The TBC battery according to claim 1, characterized in that, The interface state density of the silicon oxynitride layer is 4 × 10⁻⁶. 11 cm -2 ·eV -1 -1×10 12 cm -2 ·eV -1 ; And / or, the thickness of the silicon oxynitride layer is 5-30 nm.

3. The TBC battery according to claim 1, characterized in that, The breakdown field strength of the alumina transition layer is 10-15 mV / cm; And / or, the thickness of the alumina transition layer is 5-30 nm.

4. The TBC battery according to claim 1, characterized in that, The breakdown field strength of the silicon-carbon-nitrogen layer is 12-18 mV / cm; And / or, the band gap of the silicon-carbon-nitrogen layer is 2.5-5 eV; And / or, the thickness of the silicon-carbon-nitrogen layer is 60-300 nm; And / or, the total thickness of the silicon oxynitride layer, the aluminum oxide transition layer and the silicon carbon nitride layer is 70-360 nm.

5. The TBC battery according to claim 1, characterized in that, Along the thickness direction away from the silicon substrate, the N region includes a first tunneling layer and an n-type doped polycrystalline silicon layer disposed sequentially. And / or, along the thickness direction away from the silicon substrate, the P-region includes a second tunneling layer and a p-type doped polycrystalline silicon layer disposed sequentially; And / or, the N region, the P region, and the isolation trench have a back passivation layer on the side surface facing away from the silicon substrate; And / or, the front side of the silicon substrate is provided with a front passivation layer.

6. The TBC battery according to claim 5, characterized in that, The back passivation layer and the front passivation layer each independently include an aluminum oxide layer and / or a silicon nitride layer; And / or, the first tunneling layer and the second tunneling layer are each independently a tunneling oxide layer; And / or, the TBC battery further includes: A first electrode and a second electrode; the first electrode is located in the N region, passes through the back passivation layer, and contacts the n-type doped polysilicon layer; the second electrode is located in the P region, passes through the back passivation layer, and contacts the p-type doped polysilicon layer.

7. A method for preparing a TBC battery as described in any one of claims 1-6, characterized in that, The preparation method includes the following steps: Provide silicon substrate; Alternating N-regions, isolation trenches, and P-regions are formed on the back side of the silicon substrate; A silicon oxynitride layer, an aluminum oxide transition layer, and a silicon carbon nitride layer are sequentially deposited in the isolation tank, followed by thermal annealing.

8. The preparation method according to claim 7, characterized in that, The deposition method for the silicon oxynitride layer includes plasma-enhanced chemical vapor deposition, and the process parameters meet the following conditions: Process temperature 90-250℃, process pressure 0.5-5Pa, RF power 100-500W, reaction gas source includes silicon source, oxygen source and nitrogen source; And / or, the deposition method of the alumina transition layer includes plasma-enhanced chemical vapor deposition, and the process parameters meet the following conditions: Process temperature 90-250℃, process pressure 0.1-5Pa, RF power 100-500W, reaction gas source includes aluminum source and oxygen source; And / or, the deposition method of the silicon-carbon-nitrogen layer includes plasma-enhanced chemical vapor deposition, and the process parameters meet the following conditions: The process temperature is 200-400℃, the process pressure is 50-500Pa, the radio frequency power is 200-700W, and the reaction gas source includes silicon source, nitrogen source and carbon source.

9. The preparation method according to claim 7, characterized in that, The temperature for heat annealing is 400-460℃; And / or, the heat annealing time is 25-35 min; And / or, the atmosphere for the heat annealing is an inert atmosphere.

10. The preparation method according to claim 7, characterized in that, The preparation method includes the following steps: (1) Provide a silicon substrate; A first tunneling layer and a p-type doped polycrystalline silicon layer are sequentially deposited on the back side of the silicon substrate; Remove the p-type doped polysilicon layer and the first tunneling layer from the non-P region to expose the silicon substrate; (2) A second tunneling layer and an n-type doped polycrystalline silicon layer are sequentially deposited on the back side of the silicon substrate; Remove the n-type doped polysilicon layer and the second tunneling layer located in the P region; (3) The predetermined area of ​​the isolation trench is etched to expose the silicon substrate; A mask layer is deposited on the back side of the silicon substrate, and then the mask layer in the isolation trench is removed; (4) A silicon oxynitride layer is deposited in the isolation tank using plasma-enhanced chemical vapor deposition. (5) An alumina transition layer is deposited on the silicon oxynitride layer using plasma-enhanced chemical vapor deposition. (6) A first nitrile silicon carbide sublayer with a thickness of 10-100 nm and a second nitrile silicon carbide sublayer with a thickness of 50-200 nm are sequentially deposited on the alumina transition layer to form a nitrile silicon carbide layer; the C content of the first nitrile silicon carbide sublayer is greater than the C content of the second nitrile silicon carbide sublayer. (7) In an inert atmosphere, the silicon semi-finished product obtained in step (6) is subjected to thermal annealing at a temperature of 400-460℃ for 25-35 minutes; (8) Remove the mask layer, and then deposit passivation layers on the front and back sides of the silicon substrate to form a front passivation layer and a back passivation layer, respectively; A first electrode and a second electrode are fabricated on the back side of the silicon substrate.

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