Gallium arsenide solar cells with composite stress buffer structure and their manufacturing method

Abstract

This invention relates to the field of solar cell technology, specifically to a gallium arsenide solar cell with a composite stress buffer structure and its manufacturing method. The gallium arsenide solar cell, from top to bottom, comprises an antireflection film layer, an N-electrode, an ohmic contact layer, a triple-junction GaAs epitaxial layer, a first metal connection layer, a thermal stress buffer layer, a second metal connection layer, a discrete metal base layer, an elastomer filling layer, and an insulating protective layer. The discrete metal base layer is formed by vertically arraying metals on the second metal connection layer. The elastomer filling layer fills the metal gaps in the discrete metal base layer. The solar cell of this invention effectively alleviates high-voltage damage and thermal mismatch stress, exhibits good mechanical properties and reliability, and demonstrates excellent overall performance.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and specifically to a gallium arsenide solar cell with a composite stress buffer structure and its manufacturing method. Background Technology

[0002] Gallium arsenide (GaAs) solar cells, with their high photoelectric conversion efficiency, excellent high-temperature resistance, and radiation resistance, have become core energy devices for high-end equipment such as spacecraft, near-space vehicles, and high-altitude long-endurance unmanned aerial vehicles. To meet the requirements of flexible applications such as rollable storage, lightweight design, and conformal curved surfaces, the industry generally adopts epitaxial layer lift-off and transfer technology to transfer the optoelectronic functional layers grown on rigid GaAs substrates to flexible supports.

[0003] However, existing flexible gallium arsenide solar cell technology still faces the following bottlenecks in practical engineering applications, severely restricting its long-term reliability in extreme space environments: First, high-pressure metal bonding easily causes damage to the epitaxial layer. Traditional methods use metal layers such as Cr, Ti, Au, and Ag, pressing the metal-plated epitaxial wafer with a metal-plated flexible substrate under high pressure to achieve permanent bonding between the metals. The high-pressure process itself easily causes irreversible mechanical damage to the brittle GaAs epitaxial layer, affecting manufacturing yield. If electroplating is used to prepare the metal substrate, although high pressure can be avoided, the thermal expansion coefficients between the electroplated metal and the GaAs epitaxial layer are severely mismatched, resulting in significant warping after cooling and directly causing cracking of the epitaxial layer. Second, thermal mismatch stress continues to accumulate during temperature alternation. The thermal expansion coefficient of GaAs is approximately 5.73 × 10⁻⁶. -6 The coefficient of thermal expansion of GaAs is k, while that of conventional metal substrates is typically several times higher. In the drastically alternating temperature environment of space, the accumulated thermal stress at the interface, once exceeding the fracture strength of the GaAs epitaxial layer, will trigger large-area cracking and peeling, causing a sharp decline in cell efficiency. Third, mechanical bending stress concentration leads to structural damage. When the continuous metal substrate is bent or rolled, the strain is directly transferred to the brittle GaAs epitaxial layer. The fracture strain of GaAs is only about 0.1%, and once the local strain exceeds this limit, irreversible crack propagation occurs. Even with an island-bridge structure to separate the cell units, the flexible substrate region suspended between islands remains a weak point, easily fractured by vibration and impact during launch or by non-uniform bending in orbit. Therefore, developing a novel stress-buffering structure that can simultaneously alleviate high-voltage damage, thermal mismatch stress, mechanical bending stress, and localized impact damage has become an urgent need to improve the overall reliability of flexible gallium arsenide solar cells. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides a gallium arsenide solar cell with a composite stress buffer structure and its manufacturing method. This gallium arsenide solar cell can effectively alleviate high-voltage damage and thermal mismatch stress, has good mechanical properties and reliability, and excellent overall performance.

[0005] The first objective of this invention is to provide a gallium arsenide solar cell with a composite stress buffer structure, wherein the gallium arsenide solar cell comprises, from top to bottom, an antireflection film layer, an N electrode, an ohmic contact layer, a triple-junction GaAs epitaxial layer, a first metal connection layer, a thermal stress buffer layer, a second metal connection layer, a discrete metal base layer, an elastomer filling layer, and an insulating protective layer. The discrete metal base layer is formed by vertically arranging metals in a second metal connecting layer; The elastomeric filling layer fills the metal gaps in the discrete metal base layer.

[0006] Existing gallium arsenide (GaAs) solar cells use a single metal substrate. During continuous bending, the strain is directly transmitted to the triple-junction GaAs epitaxial layer, easily causing high-voltage damage and affecting yield. This invention addresses this by fabricating discrete metal bases from the metal substrate. During bending, each base tilts or shifts slightly independently, without interference, absorbing stress independently and preventing stress concentration on a continuous interface. This significantly reduces the stress on the triple-junction GaAs epitaxial layer. An elastomer filler layer is placed between the discrete metal bases, providing back support and separating them to prevent stress concentration and absorb localized impacts, compensating for the impact resistance shortcomings of the suspended areas in the discrete structure. Simultaneously, a thermal stress buffer layer is placed between the triple-junction GaAs epitaxial layer and the metal base. When temperature changes cause asynchronous expansion and contraction between the metal base and the GaAs epitaxial layer, the buffer layer effectively absorbs the thermal stress caused by thermal expansion mismatch through elastic shear deformation, buffering the thermal mismatch stress. These three elements work together to form a complete stress management system, improving the overall reliability of flexible GaAs solar cells.

[0007] Furthermore, the material of the first metal interconnect layer is a stack of Au / Ag / Au / Cr in sequence from the direction away from the triple-junction GaAs epitaxial layer.

[0008] Furthermore, the material of the thermal stress buffer layer is any one of PI (polyimide), BCB (benzocyclobutene), or SOG (spin-coated glass / silane glass); the Young's modulus of the thermal stress buffer layer is 1 GPa-100 GPa; and the material of the discrete metal base layer is Ni. In this technical solution, the material selection for the thermal stress buffer layer balances buffering effect, process compatibility, and low cost. Simultaneously, the Young's modulus of the thermal stress buffer layer is lower than that of GaAs and the discrete metal base, forming an elastic buffer layer sandwiched between them. When temperature changes cause asynchronous expansion and contraction of the discrete metal base and the GaAs epitaxial layer, the buffer layer absorbs the misalignment through elastic shear deformation, rather than concentrating stress at the GaAs interface. If a material with a thermal expansion coefficient matching that of GaAs (such as SOG) is selected, the amount of thermal stress generated can be reduced from the source.

[0009] Furthermore, the second metal interconnect layer consists of a stack of Cr / Ti / Ni layers arranged sequentially from the direction away from the triple-junction GaAs epitaxial layer.

[0010] Furthermore, the material of the elastomer filling layer is PDMS (polydimethylsiloxane), silicone gel, or polyurethane elastomer, or PDMS, silicone gel, or polyurethane elastomer filled with light-reflecting particles and thermally conductive fillers; the Young's modulus of the elastomer filling layer is two to three orders of magnitude lower than that of the thermal stress buffer layer. In this technical solution, the elastic filling layer can serve as both a filler and a functional carrier. Backlight management can be achieved by incorporating light-reflecting particles, heat dissipation can be improved by incorporating thermally conductive fillers, and long-term reliability can be further enhanced by selecting a self-healing polymer. Simultaneously, the Young's modulus of the elastomer is much lower than that of the buffer layer, providing uniform back support to the suspended area, and the elastomer is soft enough not to reconnect the bases and disrupt the stress dispersion effect.

[0011] A second objective of this invention is to provide a method for manufacturing a gallium arsenide solar cell with a composite stress-buffering structure, comprising the following steps: S1. On a GaAs substrate, a triple-junction GaAs epitaxial layer is epitaxially grown and then cleaned; S2. A first metal interconnect layer is deposited on the front side of the triple-junction GaAs epitaxial layer by vapor deposition; S3. A flexible buffer medium precursor is spin-coated onto the surface of the first metal connection layer and cured by stepped heating to form a thermal stress buffer layer. S4. Deposit a second metal bonding layer on the surface of the thermal stress buffer layer; S5. First, a sacrificial layer is fabricated on the second metal connection layer, and the array metal seeds are exposed by RIE etching. Metal is electroplated on the metal seeds to form a vertical metal base that is 2μm-3μm higher than the sacrificial layer. The metal base is flattened by CMP and the sacrificial layer is removed to complete the fabrication of the discrete metal base layer. S6. The elastomer precursor is filled between the metal spacers of the discrete metal base layer and cured to form an elastomer filling layer; S7. An insulating protective layer is formed on the surface of the elastomer filler layer; S8. Fabricate the N-electrode, ohmic contact layer, and antireflective coating layer; cut and test to complete battery fabrication.

[0012] The discrete metal base of this invention is grown entirely by electroplating. The triple-junction GaAs epitaxial layer does not bear high pressure during the fabrication of the support structure, thus eliminating the risk of mechanical damage to the epitaxial layer caused by high-pressure bonding. The thermal stress buffer layer is formed by spin coating and curing. The metal base is grown by electroplating and bonded to the buffer layer through a second metal connecting layer. The entire structure does not involve a high-pressure pressing process, which can effectively avoid high-pressure damage. By using sacrificial mask electroplating and CMP leveling, a highly consistent discrete base array with coplanar top surfaces is obtained, which can make more uniform contact with the subsequent PI film and has good stability.

[0013] Furthermore, in S3, the stepped temperature curing process is as follows: under a nitrogen atmosphere, the first stage is baked at 150±10℃ for 30±5min, the second stage is baked at 250±10℃ for 30±5min, and the third stage is baked at 350±60℃ for 60±5min. Whether to perform the three-stage curing is selected according to the thermal stability of the material used. The thickness of the cured thermal stress buffer layer is 2μm-10μm. Specifically, when the material of the thermal stress buffer layer is PI, the step-temperature curing process is as follows: under a nitrogen atmosphere, bake at 150°C for 30 min, at 250°C for 30 min, and at 350°C for 60 min; when the material of the thermal stress buffer layer is BCB, the step-temperature curing process is as follows: under a nitrogen atmosphere, bake at 200°C for 30 min, and at 250°C for 30 min; when the material of the thermal stress buffer layer is SOG, the step-temperature curing process is as follows: under a nitrogen atmosphere, bake at 150°C for 30 min, at 250°C for 30 min, and at 400°C for 60 min.

[0014] Furthermore, in S5, the material of the sacrificial layer is SiO2, and the thickness matches the target base; the RIE etching (reactive ion etching) uses a CF4 / O2 mixed gas, and the array is arranged in a square grid with a spacing of 150±2μm.

[0015] Furthermore, in S7, the insulating protective layer is silicon nitride, silicon oxide, or photosensitive PI.

[0016] Furthermore, in S8, the N electrode is a stack of Pd / Ge / Au / Ag / Au; the antireflective coating is TiO2 / Al2O3 or SiO2 / SiN. x The stacked layers, including SiN. x In silicon nitride, the value of x ranges from 1.2 to 1.6.

[0017] Compared with the prior art, the present invention has the following advantages: 1. This invention replaces the existing full-surface metal support of gallium arsenide solar cells with a discrete array of independent bases, each of which undergoes slight displacement or tilting during bending, thus solving the stress concentration problem during bending. Elastic fillers are filled within the gaps between the discrete metal bases to compensate for the impact resistance shortcomings of the suspended areas in the discrete structure, enabling the cell to withstand vibration and impact during launch and localized forces in orbit. A thermal stress buffer layer is placed between the triple-junction GaAs epitaxial layer and the metal base, which can effectively absorb thermal stress caused by thermal expansion mismatch through elastic shear deformation, buffering thermal mismatch stress. The above structures work together to form a complete stress management system, which can improve the overall reliability of flexible gallium arsenide solar cells.

[0018] 2. The discrete metal base of this invention is grown entirely by electroplating. The triple-junction GaAs epitaxial layer does not bear high pressure during the fabrication of the support structure, thus eliminating the risk of mechanical damage to the epitaxial layer caused by high-pressure bonding. The thermal stress buffer layer is formed by spin coating and curing. The metal base is grown by electroplating and bonded to the buffer layer through a second metal connecting layer. The entire structure does not involve a high-pressure pressing process, which can effectively avoid high-pressure damage. By using sacrificial mask electroplating and CMP leveling, the height of each base is consistent and the load is evenly distributed, avoiding the problem of excessive local stress caused by a few bases bearing the load alone due to being higher.

[0019] 3. This invention has high manufacturing precision and good compatibility. CMP and sacrificial mask etching are both mature semiconductor processes that can be completed on existing production lines. The entire manufacturing process is compatible with the conventional processes of epitaxial layer stripping and transfer technology. The material selection is flexible, which can take into account process compatibility and low cost. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure after the discrete metal base layer of the present invention has been fabricated; Figure 2 This is a schematic diagram of the structure after the insulation protective layer of the present invention has been fabricated; Figure 3 This is a schematic diagram of the structure after the sapphire substrate is fabricated according to the present invention; Figure 4 This is a schematic diagram of the structure after the antireflective coating layer of this invention has been fabricated; Figure 5 This is a schematic diagram of the structure of the gallium arsenide solar cell of the present invention.

[0021] Explanation of the labels in the diagram: 1. Triple-junction GaAs epitaxial layer; 2. First metal interconnect layer; 3. Thermal stress buffer layer; 4. Second metal interconnect layer; 5. Discrete metal base layer; 6. Elastomer filling layer; 7. Insulator protective layer; 8. Sapphire substrate; 9. Ohmic contact layer; 10. N-electrode; 11. Antireflective coating layer. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this application or its application or use. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0023] In the description of this application, it should be understood that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application.

[0024] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0025] Please see Figures 1 to 5 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0026] One embodiment of the present invention provides a gallium arsenide solar cell with a composite stress buffer structure, the schematic diagram of which is shown below. Figure 5As shown, the gallium arsenide solar cell, from top to bottom, includes an antireflection film layer 11, an N electrode 10, an ohmic contact layer 9, a triple-junction GaAs epitaxial layer 1, a first metal connection layer 2, a thermal stress buffer layer 3, a second metal connection layer 4, a discrete metal base layer 5, an elastomer filling layer 6, and an insulating protective layer 7. The discrete metal base layer is formed by vertically arranging metals on the second metal connecting layer; the surface metal of the second metal connecting layer also serves as the electroplating seed layer of the discrete metal base layer; the elastomer filling layer fills the metal gaps of the discrete metal base layer, and the two are located in the same plane, together forming a composite support structure.

[0027] In some embodiments, the materials of the first metal interconnect layer are stacked in the order of Au / Ag / Au / Cr from the direction away from the triple-junction GaAs epitaxial layer.

[0028] In some embodiments, the material of the thermal stress buffer layer is any one of PI, BCB or SOG; the material of the discrete metal base layer is Ni.

[0029] In some embodiments, the second metal interconnect layer is a stack of Cr / Ti / Ni sequentially from the direction away from the triple-junction GaAs epitaxial layer.

[0030] In some embodiments, the material of the elastomer filler layer is PDMS, silicone gel, or polyurethane elastomer, or PDMS, silicone gel, or polyurethane elastomer filled with light-reflecting particles and thermally conductive fillers.

[0031] Another embodiment of the present invention provides a method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure, comprising the following steps: S1. On a GaAs substrate, a triple-junction GaAs epitaxial layer is epitaxially grown and then cleaned; Specifically, on a GaAs substrate, an InGaP etching stop layer, a GaInP subcell, a GaAs subcell, and an InGaAs subcell are sequentially epitaxially grown using MOCVD (metal-organic chemical vapor deposition) to form a flip-chip triple-junction gallium arsenide epitaxial wafer. Then, the wafer is ultrasonically cleaned with acetone for 5-10 minutes, ultrasonically cleaned with isopropanol for 5-10 minutes, rinsed with deionized water, and dried with nitrogen.

[0032] S2. A first metal interconnect layer is deposited on the front side of the triple-junction GaAs epitaxial layer by vapor deposition; Specifically, an Au / Ag / Au / Cr stack (with thicknesses of 200nm / 2000nm / 100nm / 20nm, respectively) is electron beam deposited on the side surface of the InGaAs sub-cell as the first metal bonding layer.

[0033] S3. A flexible buffer medium precursor is spin-coated onto the surface of the first metal connection layer and cured by stepped heating to form a thermal stress buffer layer. Specifically, a flexible buffer medium precursor, which can be any of PI, BCB or SOG, is spin-coated onto the side surface of the first metal bonding layer at a speed of 4000 r / min-5000 r / min to obtain a uniform wet film; the film is then cured in a nitrogen atmosphere by stepwise temperature increase: the first stage is baked at 150±10℃ for 30±5 min, the second stage is baked at 250±10℃ for 30±5 min, and the third stage is baked at 350±60℃ for 60±5 min. Whether to perform the three-stage curing is selected according to the thermal stability of the material used. More specifically, when the material of the thermal stress buffer layer is PI, the stepped temperature curing process is as follows: under a nitrogen atmosphere, baking at 150℃ for 30 min, 250℃ for 30 min, and 350℃ for 60 min; when the material of the thermal stress buffer layer is BCB, the stepped temperature curing process is as follows: under a nitrogen atmosphere, baking at 200℃ for 30 min, and 250℃ for 30 min; when the material of the thermal stress buffer layer is SOG, the stepped temperature curing process is as follows: under a nitrogen atmosphere, baking at 150℃ for 30 min, 250℃ for 30 min, and 400℃ for 60 min. The thickness of the cured thermal stress buffer layer is 2μm-10μm, and the Young's modulus is 1GPa-100GPa.

[0034] S4. Deposit a second metal bonding layer on the surface of the thermal stress buffer layer; Specifically, Cr / Ti / Ni stacks are sequentially deposited on the surface of the thermal stress buffer layer by electron beam thermal evaporation, wherein the Cr layer enhances adhesion, the Ti layer blocks diffusion, and the Ni layer serves as a seed layer for electroplating.

[0035] S5. First, a sacrificial layer is fabricated on the second metal connection layer, and the array metal seeds are exposed by RIE etching. Metal is electroplated on the metal seeds to form a vertical metal base that is 2μm-3μm higher than the sacrificial layer. The metal base is flattened by CMP and the sacrificial layer is removed to complete the fabrication of the discrete metal base layer. Specifically, a SiO2 layer is first deposited on the second metal bonding layer using PECVD (Plasma Enhanced Chemical Vapor Deposition), with a thickness matching the height of the target substrate (10μm-20μm). Photolithography is used to create the pattern, and RIE etching is performed on the SiO2 to expose the underlying Ni seed layer, forming a patterned sacrificial mask. This exposes the Ni seed layer in the area to be electroplated (arranged in square, rectangular, or regular polygonal arrays with a spacing of 150±2μm), and the resist is removed. Then, using the SiO2 mask as a template, nickel is electroplated onto the exposed Ni seed layer. The nickel grows longitudinally within each opening to a height slightly above the SiO2 surface by 2μm-3μm (the excess is reserved for CMP). CMP is then used to grind the electroplated nickel layer until it is flush with the surface of the SiO2 mask, ensuring that the top surfaces of all substrates are coplanar and of uniform height. Finally, a fluorinated acid solution (such as diluted HF) is used for selective etching to remove the SiO2 sacrificial mask, completely separating the metal substrates from each other.

[0036] S6. The elastomer precursor is filled between the metal gaps of the discrete metal base layer and cured to form an elastomer filling layer; Specifically, elastomer precursors such as PDMS, silicone gel, or polyurethane elastomers are filled into the gaps between metal bases using a scraping or etching method and then cured in an oven at 80±5℃ for 2-4 hours. Their Young's modulus is less than that of the thermal stress buffer layer. After filling, the top surface of the elastomer is flush with the bottom surface of the base, and the bottom surface of the base is exposed.

[0037] S7. An insulating protective layer is formed on the surface of the elastomer filler layer; Specifically, an insulating protective layer, such as silicon nitride, silicon oxide, or photosensitive PI, is vapor-deposited or coated on the back side.

[0038] S8. Fabricate the N electrode, ohmic contact layer, and antireflective coating layer; cut and test to complete battery fabrication. Specifically, the epitaxial wafer with the composite substrate side (the anti-reflection film side has not yet been fabricated, and at this time it is the first metal connection layer side or the thermal stress buffer layer side) is temporarily bonded to the sapphire substrate 8 with temporary bonding adhesive to provide support for subsequent substrate thinning and removal. Then, the GaAs substrate is mechanically thinned to about 20μm-80μm, and then the remaining GaAs substrate is completely removed by selective wet etching (such as citric acid-hydrogen peroxide system or ammonia-hydrogen peroxide system), stopping at the InGaP etching stop layer. Next, negative photoresist lithography is used to define the N-side electrode pattern, N-side electrode metal (such as a Pd / Ge / Au / Ag / Au stack) is deposited by evaporation, excess metal is removed by stripping, and an alloy is formed to form ohmic contacts; selective etching is used to remove the GaAs cap layer outside the gate lines, and then an anti-reflection film (such as TiO2 / Al2O3 or SiO2 / SiN) is deposited on the front side. x(Layer stacking); overlay and etching to remove the antireflective film on the N electrode surface and the epitaxial layer region above the first metal interconnect layer, exposing the N electrode and the first metal interconnect layer (P electrode); thermal sliding debonding to remove the sapphire substrate and temporary bonding adhesive, performing alloy annealing to optimize ohmic contact performance; cutting the completed flexible solar cell to the required size and performing photoelectric performance testing.

[0039] The following is a further explanation with reference to specific embodiments: Example 1 A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure includes the following steps: S1. On a GaAs substrate, an InGaP etching stop layer, GaInP subcell, GaAs subcell, and InGaAs subcell are sequentially epitaxially grown using MOCVD to form a flip-chip triple-junction gallium arsenide epitaxial wafer. Then, the wafer is ultrasonically cleaned with acetone for 5 min, ultrasonically cleaned with isopropanol for 5 min, rinsed with deionized water, and dried with nitrogen.

[0040] S2. Electron beam evaporation of Au / Ag / Au / Cr stacks (thicknesses of 200nm / 2000nm / 100nm / 20nm respectively) on the side surface of the InGaAs sub-cell is used as the first metal bonding layer.

[0041] S3. Spin-coat the PI precursor solution (HD Microsystems PI-2610) on the side surface of the first metal bonding layer at a speed of 4000 r / min to obtain a uniform wet film; cure under nitrogen atmosphere by step temperature increase: bake at 150℃ for 30 min, bake at 250℃ for 30 min, bake at 350℃ for 60 min. After curing, the PI film thickness is 5 μm and the Young's modulus is about 2.5 GPa.

[0042] S4. Electron beam thermal evaporation is used to sequentially deposit Cr / Ti / Ni stacks on the surface of the thermal stress buffer layer, wherein the Cr layer is 20nm to enhance adhesion, the Ti layer is 50nm to block diffusion, and the Ni layer is 100nm and serves as a seed layer for electroplating. The substrate temperature is controlled below 150℃ to protect the PI film from thermal damage.

[0043] S5. First, a 15μm SiO2 layer is deposited on the second metal interconnect layer using PECVD at a deposition temperature of 120℃. Positive photoresist is then coated, and the layer is exposed and developed using a pre-designed mask to define the base array pattern (base unit size 80μm×80μm, spacing 150μm, square array arrangement). Using the photoresist as a mask, RIE (CF4 / O2 mixed gas) is used to etch the SiO2 until the underlying Ni layer is fully exposed. The photoresist is then removed with acetone to obtain a patterned SiO2 sacrificial mask, exposing the Ni seed layer at the opening. Next, a nickel sulfamate electroplating solution is prepared (nickel sulfamate 400g / L, boric acid 30g / L, pH approximately 4.0). Using a nickel plate as the anode and the sample as the cathode, the current density is approximately 2A / dm³. 2 The plating bath temperature was 50℃, and magnetic stirring was used to allow nickel to grow vertically upwards from the bottom Ni seed layer within each opening. The plating time was controlled so that the nickel layer was approximately 2μm-3μm above the SiO2 surface (to allow for CMP removal). After plating, the sample was rinsed with deionized water and dried with nitrogen. Then, the nickel-plated side of the sample was subjected to CMP using commercial nickel polishing solution until the nickel layer was completely flush with the SiO2 surface. At this point, all bases were of uniform height (15μm), with flat and coplanar top surfaces. The rough and oxide layers were removed. The sample was then immersed in a diluted hydrofluoric acid solution (HF to deionized water volume ratio 1:10) at room temperature for 3 minutes. HF selectively etched away all SiO2, leaving the nickel base, Cr, Ti, Ni layers, and PI film unaffected by significant corrosion. The sample was then thoroughly rinsed with deionized water and dried with nitrogen. At this point, all metal bases were completely separated, maintaining a flexible connection to the epitaxial layer only through the upper PI film and metal layers. The base gap was 150μm, and the depth was 15μm. The structure is as follows: Figure 1 As shown.

[0044] S6. Using a scraping method, prepare the PDMS precursor (Dow Corning Sylgard 184, main agent to curing agent mass ratio 10:1), add an appropriate amount of n-hexane for dilution (volume ratio approximately 1:1) to reduce viscosity, and stir thoroughly. Place the sample base side up on a horizontal platform, drop in the diluted precursor to cover the entire back side, and place in a vacuum desiccant for 10 minutes to degas and allow the liquid to fully penetrate the gaps. Use a polyester scraper to scrape along the bottom surface of the base at a uniform speed in one direction to remove excess precursor, filling the gaps and exposing the bottom surface of the base. Place in an oven at 80℃ for 2 hours to cure. The resulting elastomer has a Young's modulus of 2 MPa, and the PI film has a Young's modulus of 2.5 GPa. The elastomer modulus is about three orders of magnitude lower than that of the PI film, thus avoiding reconnecting the bases into a continuous stress transfer surface and maintaining the stress dispersion effect of the discrete design.

[0045] S7. A 500nm silicon nitride insulating protective layer is deposited on the back side, covering the surface of the elastomer filling layer and the lower part of the base sidewall. Its structure is as follows: Figure 2 As shown.

[0046] S8. First, place the sample face down (at this point, the side with the first metal bonding layer / PI film) and bond it to the sapphire substrate at 150°C and 0.3 MPa pressure using thermoplastic temporary bonding adhesive. The bonding adhesive is approximately 10 μm thick and provides mechanical support for subsequent substrate removal. Its structure is as follows: Figure 3 As shown; Then, the GaAs substrate was mechanically thinned to 50 μm, and the remaining GaAs substrate was removed by selective wet etching with ammonia-hydrogen peroxide-water solution (ammonia, 30% H2O2 and water volume ratio 1:5:5). The etching stopped at the InGaP etching stop layer, and the endpoint was determined by the abrupt change in etching rate. The substrate was then soaked in hydrochloric acid at room temperature for 30 s to remove the InGaP etching stop layer, exposing the N-type contact layer surface of the GaInP sub-cell. The substrate was then rinsed with deionized water and dried with nitrogen. Next, negative photoresist is coated, pre-baked, exposed using an N-electrode mask, post-baked, and developed to define the gate-shaped N-electrode pattern. Pd / Ge / Au / Ag / Au (thicknesses of 300nm / 650nm / 200nm / 4000nm / 300nm respectively) are deposited by electron beam evaporation as the N-electrode metal layer. Acetone is used for immersion and stripping to remove the photoresist and excess metal above it, leaving the gate-shaped N-electrode. The GaAs cap layer outside the gate line (if there is a cap layer in the epitaxial structure) is removed using a selective etching solution (such as a citric acid-hydrogen peroxide-water system). Then, TiO2 / Al2O3 double-layer antireflection film (thicknesses of 300nm / 620nm respectively) is deposited by electron beam evaporation. Photoresist is coated, and overlay exposure is performed to define the area where the N-electrode and the first metal interconnect layer need to be exposed. First, use RIE (CF4 / O2) etching to remove the antireflective coating above the electrode, then use dry etching to remove the underlying epitaxial layer until the Au surface of the first metal interconnect layer is exposed. Remove the resist; the structure is as follows. Figure 4 As shown, the sample was heated to the softening temperature of the temporary bonding adhesive (180°C), and the sapphire substrate was separated from the flexible solar cell using a mechanical sliding method. Residual bonding adhesive was removed by cleaning with a special solvent, and the sample was then subjected to alloy annealing again (RTA 240°C, 30s, nitrogen atmosphere) to ensure the ohmic contact performance of the N-electrode. The flexible solar cell was then cut to the target size using laser cutting or a precision blade. IV characteristics were tested under an AM0 solar simulator, and the open-circuit voltage, short-circuit current density, fill factor, and photoelectric conversion efficiency were recorded.

[0047] Test results: The flexible triple-junction gallium arsenide solar cell prepared in this embodiment has an open-circuit voltage of 3.0V and a short-circuit current density of 16.0mA / cm² measured using a solar simulator under AM0 spectrum. 2With a fill factor of 0.85, the photoelectric conversion efficiency is 31.0%; after repeated bending with a bending radius of 5mm for 1000 cycles, the efficiency decreases by about 1.5%; after 500 thermal cycles from -100℃ to +150℃, there is no peeling or cracking at any interface, and the efficiency decreases by about 2.5%.

[0048] Example 2 A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure differs from Example 1 in that, in step S3, a spin-coating BCB precursor (Dow Cyclotene 3022-46) is used at a rotation speed of 3000 r / min, and the step-curing procedure is: baking at 200°C for 30 min under a nitrogen atmosphere, followed by baking at 250°C for 30 min, resulting in a film thickness of approximately 10 μm. Other steps are the same as in Example 1. Testing showed that the performance of this flexible triple-junction gallium arsenide solar cell is comparable to that of Example 1, with an open-circuit voltage of 3.0 V and a short-circuit current density of 15.9 mA / cm². 2 The fill factor is 0.84, the photoelectric conversion efficiency is 30.4%, the attenuation is about 1.8% after 1000 bending cycles at 5mm, and the attenuation is about 2.7% after 500 thermal cycles.

[0049] Example 3 A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure differs from Example 1 in that, in S3, a spin-coated SOG precursor (Honeywell Accuglass 512B) is used at a rotation speed of 2500 r / min. The stepped curing process is as follows: baking at 150°C for 30 min, 250°C for 30 min, and 400°C for 60 min under a nitrogen atmosphere, resulting in a film thickness of approximately 6 μm. The coefficient of thermal expansion of SOG is approximately 3 × 10⁻⁶. -6 / K, with GaAs (5.73×10 -6 The thermal mismatch stress is significantly reduced from the source, with an SOG modulus of approximately 70 GPa and an elastic deformation capacity lower than that of the polymer buffer layer. Other aspects are the same as in Example 1. Testing showed that the performance of this flexible triple-junction gallium arsenide solar cell is comparable to that in Example 1, with an open-circuit voltage of 2.99 V and a short-circuit current density of 15.8 mA / cm². 2 The fill factor is 0.83, the photoelectric conversion efficiency is 29.8%, and the decay is about 2.0% after 500 thermal cycles.

[0050] Example 4 A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure differs from Example 1 in that, in step S5, the base array pattern is changed to regular hexagonal units (60 μm side length, 120 μm spacing, hexagonally close-packed). Other steps are the same as in Example 1. Testing showed that the performance of this flexible triple-junction gallium arsenide solar cell is comparable to that of Example 1, with an open-circuit voltage of 3.0 V and a short-circuit current density of 16.0 mA / cm². 2The fill factor is 0.84, the photoelectric conversion efficiency is 30.6%, the attenuation after 1000 bending cycles of 5mm is about 1.4%, the attenuation after 500 thermal cycles is about 2.2%, and the in-plane bending stiffness of the battery is isotropic.

[0051] Example 5 A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure differs from Example 1 in that, in step S5, the base array pattern is changed to elongated units (50 μm wide, 200 μm long, and 150 μm spacing). Other steps are the same as in Example 1. Testing showed that the performance of this flexible triple-junction gallium arsenide solar cell is comparable to that of Example 1, with an open-circuit voltage of 3.0 V and a short-circuit current density of 15.9 mA / cm². 2 The fill factor is 0.83, the photoelectric conversion efficiency is 30.1%, the attenuation after 1000 bends of 5mm is about 1.6%, and the attenuation after 500 thermal cycles is about 2.4%. The in-plane bending stiffness of the battery is anisotropic. In addition, as can be seen from Examples 1, 4, and 5, the technical solution of the present invention has differentiated bending direction characteristics, and can be designed accordingly by changing the base array pattern according to different bending direction requirements or stress distribution requirements.

[0052] Example 6 A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure differs from Example 1 in that a self-healing polyurethane elastomer based on Diels-Alder dynamic covalent bonds is used in step S6. The rest is the same as in Example 1. Testing showed that the performance of this flexible triple-junction gallium arsenide solar cell is comparable to that of Example 1, with an open-circuit voltage of 3.0V and a short-circuit current density of 15.8mA / cm². 2 The fill factor is 0.84, the photoelectric conversion efficiency is 30.2%; the attenuation after 1000 bending cycles of 5mm is about 1.7%; the attenuation after 500 thermal cycles is about 2.5%; when the elastomer filler layer is mechanically damaged and microcracks are generated, the battery can be heated to 80℃ and kept at that temperature for 30 minutes, and the cracks can heal themselves, and the battery's electrical performance can be restored to the level before the damage.

[0053] Finally, it should be emphasized that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A gallium arsenide solar cell with a composite stress buffer structure, characterized in that, The gallium arsenide solar cell, from top to bottom, includes an anti-reflection coating, an N-electrode, an ohmic contact layer, a triple-junction GaAs epitaxial layer, a first metal connection layer, a thermal stress buffer layer, a second metal connection layer, a discrete metal base layer, an elastomer filling layer, and an insulating protective layer. The discrete metal base layer is formed by vertically arranging metals on a second metal connecting layer; The elastomeric filling layer fills the metal gaps in the discrete metal base layer.

2. A gallium arsenide solar cell with a composite stress buffer structure according to claim 1, characterized in that, The material of the first metal interconnect layer is a stack of Au / Ag / Au / Cr in sequence from the direction away from the triple-junction GaAs epitaxial layer.

3. A gallium arsenide solar cell with a composite stress buffer structure according to claim 1, characterized in that, The material of the thermal stress buffer layer is any one of PI, BCB or SOG; the Young's modulus of the thermal stress buffer layer is 1GPa-100GPa; the material of the discrete metal base layer is Ni.

4. A gallium arsenide solar cell with a composite stress buffer structure according to claim 1, characterized in that, The second metal interconnect layer consists of a stack of Cr / Ti / Ni layers arranged sequentially from the direction away from the triple-junction GaAs epitaxial layer.

5. A gallium arsenide solar cell with a composite stress buffer structure according to claim 1, characterized in that, The material of the elastomer filling layer is PDMS, silicone gel or polyurethane elastomer, or PDMS, silicone gel or polyurethane elastomer filled with light-reflecting particles and thermally conductive fillers; the Young's modulus of the elastomer filling layer is two to three orders of magnitude lower than that of the thermal stress buffer layer.

6. A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure according to any one of claims 1-5, characterized in that, Includes the following steps: S1. On a GaAs substrate, a triple-junction GaAs epitaxial layer is epitaxially grown and then cleaned; S2. A first metal interconnect layer is deposited on the front side of the triple-junction GaAs epitaxial layer by vapor deposition; S3. A flexible buffer medium precursor is spin-coated onto the surface of the first metal connection layer and cured by stepped heating to form a thermal stress buffer layer. S4. Deposit a second metal bonding layer on the surface of the thermal stress buffer layer; S5. First, a sacrificial layer is fabricated on the second metal connection layer, and the array metal seeds are exposed by RIE etching. Metal is electroplated on the metal seeds to form a vertical metal base that is 2μm-3μm higher than the sacrificial layer. The metal base is flattened by CMP and the sacrificial layer is removed to complete the fabrication of the discrete metal base layer. S6. The elastomer precursor is filled between the metal spacers of the discrete metal base layer and cured to form an elastomer filling layer; S7. An insulating protective layer is formed on the surface of the elastomer filler layer; S8. Fabricate the N-electrode, ohmic contact layer, and antireflective coating layer; cut and test to complete battery fabrication.

7. A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure according to claim 6, characterized in that, In S3, the stepped temperature curing process is as follows: under a nitrogen atmosphere, the first stage is baked at 150±10℃ for 30±5min, the second stage is baked at 250±10℃ for 30±5min, and the third stage is baked at 350±60℃ for 60±5min. Whether to perform the three-stage curing is selected according to the thermal stability of the material used. The thickness of the cured thermal stress buffer layer is 2μm-10μm.

8. A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure according to claim 6, characterized in that, In S5, the sacrificial layer is made of SiO2 and its thickness matches that of the target substrate. The RIE etching uses a CF4 / O2 mixed gas and the array is arranged in square, rectangular or regular polygonal grids with a spacing of 150±2μm.

9. A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure according to claim 6, characterized in that, In S7, the insulating protective layer is silicon nitride, silicon oxide, or photosensitive PI.

10. A method for manufacturing a gallium arsenide solar cell with a composite stress buffer structure according to claim 6, characterized in that, In S8, the N electrode is a stack of Pd / Ge / Au / Ag / Au; the antireflective coating is TiO2 / Al2O3 or SiO2 / SiN. x The stacked layers, where x takes values ​​ranging from 1.2 to 1.6.

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