Back-contact solar cells and their fabrication methods, tandem solar cells, photovoltaic modules

Abstract

This application provides a back-contact solar cell and its fabrication method, a tandem solar cell, and a photovoltaic module. The back-contact solar cell includes an N-type semiconductor substrate with a first surface and a second surface. The first surface has a first textured structure. The second surface includes alternating first and second conductive portions with a height difference between them. The first conductive portion has a flat structure, and the second conductive portion has a second textured structure. A tunneling layer is disposed on one side of the first conductive portion. A first polycrystalline semiconductor layer is disposed on one side of the tunneling layer. A second amorphous semiconductor layer is disposed on one side of the second conductive portion. A first electrode is electrically connected to the first polycrystalline semiconductor layer, and a second electrode is electrically connected to the second amorphous semiconductor layer. This application utilizes the microstructural differences between the front and back surfaces to improve the reflectivity of incident light and enhance the photogenerated carrier collection capability, thereby improving the photoelectric conversion performance of the solar cell.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and in particular to back-contact solar cells and their preparation methods, tandem cells, and photovoltaic modules. Background Technology

[0002] A photovoltaic (PV) cell is a clean power generation system that uses sunlight to generate electricity. The core component of a PV cell power generation system is a solar cell (also known as a solar cell), which can directly convert sunlight into electrical energy.

[0003] Back-contact solar cells are those where the light-facing side of the cell has no electrodes, and both the positive and negative electrodes are located on the back-facing side. This reduces electrode shading, increases short-circuit current, and improves energy conversion efficiency. However, current back-contact solar cells still have relatively high incident light reflectivity, resulting in low photoelectric conversion efficiency. Summary of the Invention

[0004] This application proposes a back-contact solar cell and its fabrication method, a tandem cell, and a photovoltaic module. The back-contact solar cell of this application can improve the reflectivity of incident light and enhance the photogenerated carrier collection capability by utilizing the microstructural differences between the front and back light surfaces, thereby improving the photoelectric conversion efficiency of the solar cell.

[0005] In a first aspect, this application provides a back-contact solar cell, the back-contact solar cell comprising: An N-type semiconductor substrate has a first surface and a second surface. The first surface has a first textured structure, which includes a plurality of first substructures. The second surface includes alternately arranged first and second conductive portions, with a height difference between the first and second conductive portions. The first conductive portion has a flat structure, which includes a plurality of base structures. The second conductive portion has a second textured structure, which includes a plurality of second substructures. The one-dimensional dimension of the bottom surface of each base structure is greater than the one-dimensional dimensions of the bottom surfaces of the first and second substructures, and the depth dimension of each base structure is less than the height dimensions of the first and second substructures. The one-dimensional dimension of the bottom surface of each second substructure is greater than the one-dimensional dimension of the bottom surface of the first substructure. A tunneling layer is disposed on the side of the first conductive portion away from the N-type semiconductor substrate; A first polycrystalline semiconductor layer is disposed on the side of the tunneling layer opposite to the N-type semiconductor substrate; The second amorphous semiconductor layer is disposed on the side of the second conductive portion away from the N-type semiconductor substrate; The first electrode is electrically connected to the first polycrystalline semiconductor layer; The second electrode is electrically connected to the second amorphous semiconductor layer.

[0006] In some embodiments, the one-dimensional dimension of the bottom surface of the tower base structure is 5 μm to 15 μm; the depth dimension of the tower base structure along the thickness direction of the N-type semiconductor substrate is 0.1 to 1 μm.

[0007] In some embodiments, the one-dimensional dimension of the bottom surface of the first substructure is 1 μm to 3 μm; the height dimension from the top to the bottom of the first substructure along the thickness direction of the N-type semiconductor substrate is 1 μm to 3 μm; and the first included angle between the sidewall of the first substructure and the bottom of the first substructure is 20° to 70°.

[0008] In some embodiments, the one-dimensional dimension of the bottom surface of the second substructure is 1.2 μm to 4 μm; the height dimension from the top to the bottom of the second substructure along the thickness direction of the N-type semiconductor substrate is 1.2 μm to 4 μm; and the second included angle between the sidewall of the second substructure and the bottom of the second substructure is 30° to 80°.

[0009] In some embodiments, the thickness of the second amorphous semiconductor layer located at the bottom of the second substructure is greater than the thickness of the second amorphous semiconductor layer located at the top of the second substructure.

[0010] In some embodiments, the height difference between the first conductive part and the second conductive part is 3μm to 10μm.

[0011] In some embodiments, the height of the first electrode is 6 μm to 12 μm; the height of the second electrode is 7 μm to 18 μm; and the height difference between the first electrode and the second electrode is 2 μm to 12 μm.

[0012] In some embodiments, the first polycrystalline semiconductor layer is an N-type doped polycrystalline silicon layer; the second amorphous semiconductor layer includes a first amorphous silicon layer and a first P-type doped amorphous silicon layer stacked together, wherein the first P-type doped amorphous silicon layer is located on the side of the first amorphous silicon layer away from the N-type semiconductor substrate.

[0013] In some embodiments, the back-contact solar cell further includes: a first transparent conductive layer located between the first polycrystalline semiconductor layer and the first electrode; the first electrode being electrically connected to the first transparent conductive layer; and a second transparent conductive layer located between the second amorphous semiconductor layer and the second electrode; the second electrode being electrically connected to the second transparent conductive layer.

[0014] In some embodiments, the back-contact solar cell further includes: a third amorphous semiconductor layer, the third amorphous semiconductor layer comprising a second amorphous silicon layer and a second P-type doped amorphous silicon layer stacked together, the second amorphous silicon layer being located on the side of the first polycrystalline semiconductor layer away from the tunneling layer; the third amorphous semiconductor layer having an opening region, the thickness of the third amorphous semiconductor layer being 10nm~100nm; at least a portion of the first transparent conductive layer being disposed in the opening region and connected to the first polycrystalline semiconductor layer.

[0015] In some embodiments, the distribution ratio of the first conductive portion on the second surface of the N-type semiconductor substrate is 20%-50%; the distribution ratio of the second conductive portion on the second surface of the N-type semiconductor substrate is 50%-80%.

[0016] Secondly, this application provides a method for fabricating a back-contact solar cell, the method comprising: An N-type semiconductor substrate is provided, the N-type semiconductor substrate having a first surface and a second surface; The second surface of the N-type semiconductor substrate is texturized and polished to form a tower base structure. A tunneling layer and a first polycrystalline semiconductor layer are formed on the second surface; A mask layer is formed on the surface of the first polycrystalline semiconductor layer; An N-type semiconductor substrate having the mask layer is etched to expose at least a portion of the N-type semiconductor substrate, and an alternating first conductive portion and a second conductive portion are formed on the second surface, with a height difference between the first conductive portion and the second conductive portion. The surfaces of the first surface and the second conductive portion of the N-type semiconductor substrate are respectively texturized, forming a first textured structure on the first surface and a second textured structure on the second conductive portion. The first textured structure includes multiple first substructures, and the second textured structure includes multiple second substructures. The one-dimensional dimension of the bottom surface of the second substructure is larger than the one-dimensional dimension of the bottom surface of the first substructure. The one-dimensional dimension of the bottom surface of the tower base structure is larger than both the one-dimensional dimensions of the bottom surfaces of the first and second substructures. The depth dimension of the tower base structure is smaller than both the height dimensions of the first and second substructures. Remove the mask layer from the surface of the first conductive part; At least a second amorphous semiconductor layer is formed in the second conductive portion; Metallization is performed on the first polycrystalline semiconductor layer and the second amorphous semiconductor layer to form a first electrode and a second electrode, respectively. The first electrode is electrically connected to the first polycrystalline semiconductor layer, and the second electrode is electrically connected to the second amorphous semiconductor layer.

[0017] In some embodiments, the step of forming at least a second amorphous semiconductor layer in the second conductive portion includes: An amorphous silicon layer and a P-type doped amorphous silicon layer are formed on the first conductive portion and the second conductive portion; a portion of the amorphous silicon layer and the P-type doped amorphous silicon layer stacked on the surface of the first conductive portion are removed, so that an opening interval is formed on the surface of the first conductive portion, and the depth of the opening interval is greater than the total thickness of the amorphous silicon layer and the P-type doped amorphous silicon layer.

[0018] In some embodiments, the preparation method further includes: forming a transparent conductive film on the first conductive portion and the second conductive portion, partially filling the opening interval with the transparent conductive film to form a first transparent conductive layer, and partially placing the transparent conductive film on the second semiconductor layer to form a second transparent conductive layer; forming an insulating region at the junction of the first transparent conductive layer and the second transparent conductive layer; performing metallization treatment on the first transparent conductive layer and the second transparent conductive layer to form a first electrode and a second electrode, respectively, wherein the first electrode is electrically connected to the first transparent conductive layer, and the second electrode is electrically connected to the second transparent conductive layer.

[0019] In some embodiments, after removing the mask layer from the surface of the first conductive portion and polishing, and before forming at least a second semiconductor layer on the second conductive portion, the method further includes: A first passivation layer is formed on the first surface of the N-type semiconductor substrate; an anti-reflection layer is formed on the surface of the first passivation layer.

[0020] Thirdly, this application provides a tandem solar cell, including a perovskite top cell and a crystalline silicon bottom cell stacked together, wherein the crystalline silicon bottom cell is a back-contact solar cell as described in the first aspect or a back-contact solar cell prepared by the preparation method described in the second aspect.

[0021] Fourthly, this application provides a photovoltaic module, comprising: a battery string, the battery string being formed by connecting back-contact solar cells as described in the first aspect, back-contact solar cells prepared by the preparation method described in the second aspect, or stacked cells as described in the third aspect; an encapsulation layer covering the surface of the battery string; and a cover plate covering the surface of the encapsulation layer away from the battery string.

[0022] The technical solution of this application has at least the following beneficial effects: In this back-contact solar cell, the one-dimensional dimension of the bottom surface of the first substructure in the first textured structure of the light-receiving surface is smaller than the one-dimensional dimension of the bottom surface of the second substructure in the second textured structure of the back-lighting surface. This means the light-receiving surface has a higher roughness, allowing more light to be refracted through the first textured structure into the N-type semiconductor substrate, resulting in lower incident light reflectivity and improved light absorption and photoelectric conversion efficiency of the solar cell. The roughness of the second textured structure on the back-lighting surface is smaller than that of the first textured structure, improving the contact area between the second electrode and the second amorphous semiconductor layer and reducing the contact resistance between them. The first conductive portion of the back-lighting surface has a flat structure, and the one-dimensional dimension of the tower base structure is larger than the one-dimensional dimension of the bottom surface of either the first or second substructure. This greater flatness of the first conductive portion allows the first polycrystalline semiconductor layer to have a good morphology, thereby improving the photogenerated carrier mobility, which is beneficial for increasing carrier concentration and thus improving the photoelectric conversion performance of the solar cell. This application utilizes the differences in the three different microstructures of the front and back surfaces to improve the incident light reflectivity and enhance the photogenerated carrier collection capability, thereby improving the photoelectric conversion performance of the solar cell. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of the N-type semiconductor substrate of the back-contact solar cell provided in an embodiment of this application; Figure 2aElectron micrograph of the planar structure of the N-type semiconductor substrate of the back-contact solar cell provided in the embodiments of this application; Figure 2b An electron microscope image of the second texture structure of the N-type semiconductor substrate of the back-contact solar cell provided in an embodiment of this application; Figure 3 This is a schematic diagram of the back-contact solar cell structure provided in an embodiment of this application; Figure 4 This is a schematic diagram of another structure of the back-contact solar cell provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of the stacked battery provided in the embodiments of this application; Figure 6 This is a schematic diagram of the structure of a photovoltaic module provided in an embodiment of this application.

[0025] Figure label: 100-back contact solar cell; 1-N type semiconductor substrate; 10 - First surface; 101 - First passivation layer; 102 - Antireflection layer; 11-First texture structure; 111 - First substructure; 111a - Top of the first substructure; 111b - Bottom of the first substructure; 111c - Side wall of the first substructure; 20 - Second surface; 21-First conductive part; 22-Second conductive part; 221 - Second texture structure; 222 - Second substructure; 222a - Top of the second substructure; 222b - Bottom of the second substructure; 222c - Side wall of the second substructure; 211-Flat structure; 211a-Tower base structure; 2-Tunneling layer; 3-Second polycrystalline semiconductor layer; 4-Second amorphous semiconductor layer; 41 - First amorphous silicon layer; 42 - First P-type doped amorphous silicon layer; 5 - First electrode; 6-Second electrode; 7-First transparent conductive layer; 8-Second transparent conductive layer; 9 - Third amorphous semiconductor layer; 91 - Second amorphous silicon layer; 92 - Second P-type doped amorphous silicon layer; 200 - First cover plate; 300 - First encapsulating adhesive layer; 400 - Second encapsulating adhesive layer; 500 - Second cover plate.

[0026] 2000-Stacked Battery; 2001-Top Battery; 2002-bottom battery. Detailed Implementation

[0027] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0028] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0029] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0030] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0031] It should be noted that the directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this application are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this application. Furthermore, in the context, it should be understood that when it is mentioned that an element is connected "upper" or "lower" to another element, it can be directly connected to the other element "upper" or "lower," or indirectly connected to the other element "upper" or "lower" through an intermediate element.

[0032] In related technologies, BC (Back Contact) cells are a type of back-contact solar cell where all electrodes are located on the back surface of a semiconductor substrate. Because there are no electrodes obstructing the front surface of the semiconductor substrate, the entire front surface area can receive sunlight, resulting in high photoelectric conversion efficiency for BC cells. However, the photoelectric conversion efficiency of existing BC cells still needs improvement. Reducing the reflectivity of incident light, improving the contact area between the electrodes and the cell, and lowering the contact resistance remain areas requiring further development.

[0033] In view of this, this application proposes a back-contact solar cell and its preparation method, a tandem cell, and a photovoltaic module. The back-contact solar cell of this application can improve the reflectivity of incident light and enhance the photogenerated carrier collection capability by utilizing the microstructural differences between the front and back light surfaces, thereby improving the photoelectric conversion efficiency of the solar cell.

[0034] Figure 1 This is a schematic diagram of the structure of the N-type semiconductor substrate of the back-contact solar cell provided in an embodiment of this application; Figure 2a Electron micrograph of the planar structure of the N-type semiconductor substrate of the back-contact solar cell provided in the embodiments of this application; Figure 2b An electron microscope image of the second texture structure of the N-type semiconductor substrate of the back-contact solar cell provided in an embodiment of this application; Figure 3 This is a schematic diagram of the back-contact solar cell structure provided in an embodiment of this application; as shown. Figures 1 to 3 As shown, the back-contact solar cell 100 includes: N-type semiconductor substrate 1, the N-type semiconductor substrate 1 having a first surface 10 and a second surface 20; The first surface 10 has a first texture structure 11, which includes a plurality of first substructures 111.

[0035] The second surface 20 includes alternating first conductive portions 21 and second conductive portions 22, with a height difference between the first conductive portions 21 and the second conductive portions 22; wherein, the first conductive portion 21 has a flat structure 211, the flat structure 211 includes a plurality of tower base structures 211a; the second conductive portion 22 has a second texture structure 221, the second texture structure 221 includes a plurality of second substructures 222.

[0036] The one-dimensional dimension of the bottom surface of the tower base structure 211a is larger than the one-dimensional dimension of the bottom surface of the first substructure 111 and the one-dimensional dimension of the bottom surface of the second substructure 222; the depth dimension of the tower base structure 211a is smaller than the height dimension of the first substructure 111 and the height dimension of the second substructure 222; the one-dimensional dimension of the bottom surface of the second substructure 222 is larger than the one-dimensional dimension of the bottom surface of the first substructure 111. The tunneling layer 2 is disposed on the side of the first conductive portion 21 that is away from the N-type semiconductor substrate 1; The first polycrystalline semiconductor layer 3 is disposed on the side of the tunneling layer 2 away from the N-type semiconductor substrate 1; The second amorphous semiconductor layer 4 is disposed on the side of the second conductive portion 22 away from the N-type semiconductor substrate 1; The first electrode 5 is electrically connected to the first polycrystalline semiconductor layer 3; The second electrode 6 is electrically connected to the second amorphous semiconductor layer 4.

[0037] In this application, the one-dimensional dimension of the bottom surface of the first substructure 111 in the first texture structure 11 of the first surface 10 (i.e., the light-receiving surface) of the back-contact solar cell is smaller than the one-dimensional dimension of the bottom surface of the second substructure 222 in the second texture structure 221 of the second surface 20 (i.e., the back-lighting surface). That is, the roughness of the light-receiving surface is higher, and more light is refracted through the first texture structure 11 into the N-type semiconductor substrate 1. The incident light reflectivity of the light-receiving surface is lower, thereby improving the light absorption rate and photoelectric conversion rate of the solar cell. The roughness of the second texture structure 221 of the back-lighting surface is smaller than that of the first texture structure 11, which can improve the contact area between the second electrode 6 and the second amorphous semiconductor layer 4 and reduce the contact resistance between the second electrode 6 and the second amorphous semiconductor layer 4. The first conductive portion 21 on the backlight surface has a flat structure. The one-dimensional dimension of the base structure 211a is larger than the one-dimensional dimension of the bottom surface of the first substructure 111 or the second substructure 222. The first conductive portion 21 has greater flatness, which allows the first polycrystalline semiconductor layer 3 to have a good morphology, thereby improving the mobility of photogenerated carriers and increasing the carrier concentration, thus improving the photoelectric conversion performance of the solar cell. This application utilizes the differences in the three different microstructures of the front and backlight surfaces to improve the reflectivity of incident light and enhance the photogenerated carrier collection capability, thereby improving the photoelectric conversion performance of the solar cell.

[0038] It should be noted that the first conductive portion 21 and the second conductive portion 22 are not formed as additional layer structures on the N-type semiconductor substrate 1, but are located within the second surface 20 region of the N-type semiconductor substrate 1. That is, the first conductive portion 21 and the second conductive portion 22 are part of the N-type semiconductor substrate 1, and there is no substantial interface between the first conductive portion 21 and the second conductive portion 22 and the N-type semiconductor substrate 1.

[0039] Please continue reading. Figure 1 The N-type semiconductor substrate 1 can be an N-type crystalline silicon substrate (or silicon wafer), which is doped with an N-type dopant element. The N-type dopant element can be at least one of group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). The crystalline silicon substrate (silicon substrate) can be, for example, a polycrystalline silicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate.

[0040] like Figure 1As shown, the N-type semiconductor substrate 1 includes a first surface 10 and a second surface 20 disposed opposite to each other. Exemplarily, the first surface 10 refers to the front surface of the N-type semiconductor substrate (also called the light-receiving surface), i.e., the surface that receives sunlight, and the second surface 20 refers to the surface opposite to the front surface, i.e., the rear surface (also called the back-lighting surface). Both the first surface 10 and the second surface 20 can receive sunlight and convert light energy into electrical energy. The first surface 10 has a first textured structure 11, the first conductive portion 21 of the second surface 20 has a flat structure 211, and the second conductive portion 22 of the second surface 20 has a second textured structure 221.

[0041] It should be noted that "textured structure" refers to a micro-nano-scale structure that can scatter or reflect light to enhance light absorption. The textured structure of this application can be formed by chemical etching, laser etching, mechanical etching, or plasma etching on at least one surface of the semiconductor substrate. "Flat structure" is a relative concept, referring to a structural morphology in which the first conductive part 21 has no obvious protrusions or depressions at both the macroscopic and microscopic scales relative to the microscopic undulations of the first surface. The "flat structure" of this application does not require absolute flatness at the atomic level, but allows for minor undulations or intrinsic roughness caused by substrate preparation processes (such as cutting and polishing) or subsequent treatments (such as cleaning and passivation).

[0042] like Figure 1 As shown, the first surface 10 has a first texture structure 11, which includes multiple first substructures 111. The first substructures 111 can be pyramidal microstructures or non-pyramidal microstructures. Non-pyramidal microstructures can be understood as base / frustum-shaped or stepped morphologies formed by the destruction of the main body of the pyramidal microstructure. Non-pyramidal microstructures can be formed by processes such as chemical etching, laser etching, mechanical etching, or plasma etching on the N-type semiconductor substrate 1. The first texture structure 11 of this application reduces the reflectivity of incident light and improves the photoelectric conversion efficiency of the solar cell.

[0043] In some specific embodiments, the one-dimensional dimension D of the bottom surface of the first substructure 111 is 1μm to 3μm, specifically 1μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, 2.2μm, 2.5μm, or 3μm, etc., or other values ​​within the above range, which are not limited here. Optionally, the one-dimensional dimension D of the bottom surface of the first substructure 111 is 1.2μm to 2.8μm.

[0044] The bottom surface morphology of the first substructure 111 includes at least one of rhombus, rectangle, square, trapezoid, approximate rhombus, approximate square, approximate rectangle, and approximate trapezoid.

[0045] In some instances, when measuring the one-dimensional dimensions, height, and angle between the sidewalls and the bottom of the bottom surface characterizing the first substructure 111 or the second substructure 222, the film surface calibration can be directly measured using testing instruments (optical microscope, atomic force microscope, scanning electron microscope, transmission electron microscope, etc.). The one-dimensional dimension can specifically be the side length, diagonal, etc., of the surface, and is not limited here. It should be noted that the "~" between two values ​​in this application represents the endpoint values ​​including both values.

[0046] like Figure 1 As shown, along the thickness direction of the N-type semiconductor substrate 1, the height h of the first substructure 111 from top to bottom is 1μm to 3μm; specifically, it can be 1μm, 1.2μm, 1.5μm, 1.8μm, 2.0μm, 2.2μm, 2.5μm, or 3μm, etc., or other values ​​within the above range, which are not limited here. Controlling the height h of the first substructure 111 within the above range can improve the light-trapping effect of the first textured structure, ensuring that more light is refracted into the N-type semiconductor substrate 1 through the first textured structure, thereby improving the photoelectric conversion efficiency of the solar cell.

[0047] In some embodiments, the first substructure 111 includes a top 111a of the first substructure away from the first surface, a bottom 111b of the first substructure close to the first surface, and a sidewall 111c of the first substructure connecting them. The first included angle between the sidewall 111c of the first substructure 111 and the bottom 111b of the first substructure is 20° to 70°, specifically 20°, 25°, 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, or 70°, or other values ​​within the above range, which are not limited here. Optionally, the first included angle is 30° to 60°. The sidewall of the first substructure 111 is more gently sloping than the sidewall of the second substructure 222, which can improve the absorption rate of incident light and improve the surface passivation quality of the first surface 10.

[0048] In this application, the first surface 10 has a rough first textured structure 11, which can effectively improve the absorption rate of short-wavelength light and maximize the capture of short-wavelength incident light. Compared with a first surface with a flat structure, it significantly reduces the reflectivity of incident light. Secondly, the first surface (light-receiving surface) with the first textured structure 11 expands the generation area of ​​photogenerated carriers and improves the photoelectric conversion efficiency.

[0049] like Figure 3As shown, the first surface 10 of the N-type semiconductor substrate 1 is provided with a first passivation layer 101 and an antireflection layer 102 stacked together. Compared with a first surface 10 having a flat structure, the technical solution of this application can improve the adhesion and film uniformity of the first passivation layer 101 and the antireflection layer 102. The increased specific surface area of ​​the first surface can disperse the stress of the deposited film, reduce coating defects, and synergistically improve the photoelectric conversion stability of the solar cell.

[0050] In some embodiments, the first passivation layer 101 may be, but is not limited to, a single-layer oxide layer or a multi-layer structure such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. Of course, other types of passivation layers may also be used, and this application is not limited thereto. The first passivation layer 101 serves to passivate the first surface (light-receiving surface) of the N-type semiconductor substrate 1. In some specific embodiments, the first passivation layer 101 may be an aluminum oxide layer.

[0051] In some embodiments, the antireflection layer 102 can prevent and reduce light reflection, thereby achieving the goal of fully utilizing solar energy. The antireflection layer 102 can be formed on the first passivation layer 101 by methods such as chemical vapor deposition, physical vapor deposition, and high-temperature nitriding. In some specific embodiments, the antireflection layer 102 can be a silicon nitride layer (SiN). x ).

[0052] Please continue reading. Figure 1 ,like Figure 1 As shown, the second surface 20 of the N-type semiconductor substrate 1 includes an alternately arranged first conductive portion 21 and a second conductive portion 22, with a height difference H1 between the first conductive portion 21 and the second conductive portion 22.

[0053] In some embodiments, the height difference H1 between the first conductive portion 21 and the second conductive portion 22 is 3μm to 10μm, specifically 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, or 10μm, etc., and of course, other values ​​within the above range are also possible, which are not limited here. In this application, the second conductive portion 22 is closer to the interior of the N-type semiconductor substrate 1, and the first conductive portion 21 is farther away from the interior of the N-type semiconductor substrate 1. Through the height difference design, the P-conductive region and the N-conductive region can be staggered vertically, and the lateral contact boundary can be separated by a step, which can achieve electrical isolation, reduce edge leakage current, shorten the carrier transport path, and improve the fill factor of the solar cell.

[0054] The first conductive portion 21 has a flat structure 211, which is formed by polishing the second surface 20 of the semiconductor substrate with an alkaline solution. The flat structure 211 formed by polishing is essentially the base portion of a pyramid-shaped microstructure or a non-pyramid-shaped microstructure, and is not a completely flat surface. The low surface roughness of the flat structure 211 facilitates greater flatness during the deposition of the tunneling layer 2 and the first polycrystalline semiconductor layer 3. This results in better morphology and stability of the contact interface between the passivation contact structure and the N-type semiconductor substrate 1, improving the mobility of photogenerated carriers and thus increasing the carrier concentration, thereby improving the photoelectric conversion performance of the solar cell.

[0055] like Figure 2a As shown, the flat structure 211 includes multiple tower base structures 211a. The one-dimensional dimension D1 of the bottom surface of the tower base structure 211a is 5μm to 15μm; specifically, it can be 5μm, 6μm, 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, or 15μm, etc., or other values ​​within the above range, which are not limited here. The one-dimensional dimension of the bottom surface of the tower base structure 211a can specifically be the side length, diagonal, etc. of the surface. In some embodiments, along the thickness direction of the N-type semiconductor substrate, the depth dimension of the tower base structure 211a is 0.1 to 1μm, specifically, it can be 0.1μm, 0.2μm, 0.3μm, 0.4μm, 0.5μm, 0.6μm, 0.7μm, 0.8μm, 0.9μm, or 1μm, etc., or other values ​​within the above range, which are not limited here. The depth dimension of the tower base structure 211a can be defined as the height difference between the bottom of the tower base structure 211a near the interior of the N-type semiconductor substrate and the top of the tower base structure 211a away from the interior of the N-type semiconductor substrate along the thickness direction of the semiconductor substrate. The depth dimension of the tower base structure 211a can also be defined as the height dimension of the tower base structure 211a.

[0056] In this application, the one-dimensional dimension of the bottom surface of the tower base structure 211a is greater than the one-dimensional dimension of the bottom surface of the first substructure 111 and the one-dimensional dimension of the bottom surface of the second substructure 222; the depth dimension of the tower base structure 211a is less than the height dimension of the first substructure 111 and the height dimension of the second substructure 222.

[0057] In some embodiments, the tower base structure 211a can be partially stacked. In the technical solution of this application, the bottom dimension of the tower base structure 211a is larger and the height is extremely small, which can reduce the surface roughness of the first conductive part 21, reduce surface defects, and help improve the surface passivation effect.

[0058] like Figure 1 and Figure 2bAs shown, the second conductive portion 22 has a second texture structure 221, which includes multiple second substructures 222. The second substructures 222 can be pyramidal microstructures or non-pyramidal microstructures. A non-pyramidal microstructure can be understood as a base / frustum-shaped or stepped morphology formed by the destruction of the main body of the pyramidal microstructure. Non-pyramidal microstructures can be formed by processes such as chemical etching, laser etching, mechanical etching, or plasma etching on the N-type semiconductor substrate 1.

[0059] In some specific embodiments, the one-dimensional dimension D2 of the bottom surface of the second substructure 222 is 1.2μm to 4μm, specifically 1.2μm, 1.5μm, 1.8μm, 2.0μm, 2.2μm, 2.5μm, 3μm, 3.5μm, 3.9μm, or 4μm, etc., and of course, other values ​​within the above range are also possible, without limitation. The bottom surface morphology of the second substructure 222 includes at least one of rhombus, rectangle, square, trapezoid, approximately rhombus, approximately square, approximately rectangular, and approximately trapezoidal. The one-dimensional dimension of the bottom surface of the second substructure 222 can specifically be the side length, diagonal, etc. Along the thickness direction of the N-type semiconductor substrate 1, the height h2 of the second substructure 222 from top to bottom is 1.2μm to 4μm, specifically it can be 1.2μm, 1.5μm, 1.8μm, 2.0μm, 2.2μm, 2.5μm, 3μm, 3.5μm, 3.9μm or 4μm, etc., and of course it can also be other values ​​within the above range, which are not limited here.

[0060] In some embodiments, the second substructure 222 includes a top 222a of the second substructure away from the second surface, a bottom 222b of the second substructure near the second surface, and a sidewall 222c of the second substructure connecting them. The second included angle between the sidewall 222c and the bottom 222b of the second substructure is 30° to 80°, specifically 30°, 35°, 40°, 45°, 50°, 55°, 60°, 65°, 70°, 75°, or 80°, or other values ​​within the above range, which are not limited here. In some specific embodiments, at least part of the second included angle is greater than the first included angle, that is, the sidewall of the second substructure 222 is steeper, which can increase the contact area between the second textured structure and the electrode.

[0061] In the technical solution of this application, the bottom dimension of the bottom surface of the second substructure 222 is larger than that of the bottom surface of the first substructure 111, and the first included angle is smaller than the second included angle. The second substructure is large and sharp, making the surface roughness of the second conductive part 22 less than that of the first surface 10. On the one hand, this can improve the reabsorption efficiency of long-wavelength back-reflected light and reduce the back-side escape of long-wavelength light. On the other hand, it improves the uniformity of film deposition on the surface of the second conductive part 22. Compared with a flat structure, the second textured structure can expand the contact area between the second amorphous semiconductor layer deposited on its surface and the N-type semiconductor substrate 1, expand the PN junction area, and enhance the collection capability of photogenerated carriers. In addition, the second textured structure with appropriate roughness can also reduce the risk of film cracking at the corner between the first conductive part 21 and the second conductive part 22, making the film more continuous and complete, reducing edge leakage, and lowering the parallel resistance; it can also optimize the ohmic contact between the film and the second electrode, reduce the series resistance, and improve the fill factor of the solar cell.

[0062] In some embodiments, the height from the top of the second substructure 222 to the tower base structure 211a of the flat structure 211 is 2μm to 8μm, specifically 2μm, 3μm, 4μm, 5μm, 5.5μm, 6μm, 7μm, 7.5μm or 8μm, etc., or other values ​​within the above range, which are not limited here.

[0063] like Figure 3 As shown, the distribution ratio of the first conductive portion 21 (N-type conductive region) on the second surface of the N-type semiconductor substrate 1 is 20%-50%, specifically 50%, 45%, 40%, 35%, 30%, 25% or 20%, and of course other values ​​within the above range are also possible, which are not limited here.

[0064] In some embodiments, the distribution ratio of the second conductive portion 22 (P-type conductive region) on the second surface of the N-type semiconductor substrate 1 is 50%-80%, specifically 50%, 55%, 60%, 65%, 70%, 75% or 80%, etc., and of course, other values ​​within the above range are also possible, which are not limited here.

[0065] Understandably, by limiting the distribution ratio of the first conductive portion 21 (N-type conductive region) and the second conductive portion 22 (P-type conductive region) on the second surface of the N-type semiconductor substrate 1, a PN junction with excellent conductivity can be formed on the N-type semiconductor substrate 1 during the fabrication of the solar cell, thereby improving the photoelectric performance of the fabricated solar cell.

[0066] Please continue reading. Figure 3A tunneling layer 2 and a first polycrystalline semiconductor layer 3 are stacked on the side of the first conductive portion 21 opposite to the N-type semiconductor substrate 1. The stacked tunneling layer 2 and the first polycrystalline semiconductor layer 3 can form a passivation contact structure, which can achieve surface passivation and ohmic contact, improve the open-circuit voltage and fill factor, and improve the conversion efficiency of the back contact solar cell 100.

[0067] In some embodiments, the tunneling layer 2 can be made of a dielectric material, such as silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, silicon oxynitride, etc. The thickness of the tunneling layer 2 is generally between 0.5 nm and 2 nm, and can be set according to actual needs, without limitation. In some feasible embodiments, the tunneling layer 2 can be formed on the second surface of the N-type semiconductor substrate 1 using ozone oxidation, high-temperature thermal oxidation, nitric acid oxidation, chemical vapor deposition, or low-pressure chemical vapor deposition.

[0068] In some embodiments, the first polycrystalline semiconductor layer 3 is an N-type doped polycrystalline silicon layer, and the doping element in the N-type doped polycrystalline silicon layer includes at least one of phosphorus, arsenic, and tellurium. The doping element in the N-type doped polycrystalline silicon layer is the same as that in the N-type semiconductor substrate 1, and a concentration difference is formed between the N-type doped polycrystalline silicon layer and the N-type semiconductor substrate 1, thereby forming a high-low junction. This allows the N-type doped polycrystalline silicon layer to form good contact with the first electrode and to form band bending on the surface of the N-type semiconductor substrate 1, thereby achieving selective carrier transport and reducing recombination losses.

[0069] Please continue reading. Figure 3 The second conductive part 22 has a second amorphous semiconductor layer 4 on the side opposite to the N-type semiconductor substrate 1, and the second electrode 6 is electrically connected to the second amorphous semiconductor layer 4.

[0070] In some embodiments, the second amorphous semiconductor layer 4 includes a first amorphous silicon layer 41 and a first P-type doped amorphous silicon layer 42 stacked together. The first P-type doped amorphous silicon layer 42 is located on the side of the first amorphous silicon layer 41 away from the N-type semiconductor substrate 1, and the second electrode 6 is electrically connected to the first P-type doped amorphous silicon layer 42.

[0071] In some embodiments, the thickness d1 of the second amorphous semiconductor layer 4 at the bottom of the second substructure is greater than the thickness d2 of the second amorphous semiconductor layer 4 at the top of the second substructure. This can significantly reduce the lateral transport resistance of charge carriers, open up the current channel at the bottom of the pyramid-shaped microstructure, make current transport more efficient, and improve the fill factor of the solar cell.

[0072] Figure 4 This is a schematic cross-sectional view of the back-contact solar cell provided in Embodiment 2 of this application, as shown below. Figure 4 As shown, the back-contact solar cell also includes a first transparent conductive layer 7 and a second transparent conductive layer 8.

[0073] The first transparent conductive layer 7 is located between the first polycrystalline semiconductor layer 3 and the first electrode 5; the first electrode 5 is electrically connected to the first transparent conductive layer 7.

[0074] The second transparent conductive layer 8 is located between the second amorphous semiconductor layer 4 and the second electrode 6; the second electrode 6 is electrically connected to the second transparent conductive layer 8.

[0075] The first transparent conductive layer 7 can reduce the contact resistance between the first electrode 5 and the first polycrystalline semiconductor layer 3, thereby improving the efficiency of the first electrode 5 in collecting charge carriers. The material of the first transparent conductive layer 7 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide.

[0076] The second transparent conductive layer 8 can reduce the contact resistance between the second electrode 6 and the second amorphous semiconductor layer 4, thereby improving the efficiency of the second electrode 6 in collecting charge carriers. The material of the second transparent conductive layer 8 may include at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide.

[0077] like Figure 4 As shown, the back-contact solar cell also includes a third amorphous semiconductor layer 9. The thickness of the third amorphous semiconductor layer 9 is 10nm~100nm, specifically 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, or 100nm, or other values ​​within the above range, which are not limited here. Optionally, the thickness of the third amorphous semiconductor layer 9 is 20nm~60nm.

[0078] In some embodiments, the third amorphous semiconductor layer 9 includes a second amorphous silicon layer 91 and a second p-type doped amorphous silicon layer 92 stacked together, with the second amorphous silicon layer 91 located on the side of the first polycrystalline semiconductor layer 3 facing away from the tunneling layer 2. In actual fabrication, the second amorphous semiconductor layer 4 and the third amorphous semiconductor layer 9 can be deposited together, and an insulating region can be formed by etching to reduce lateral electron flow.

[0079] Specifically, the third amorphous semiconductor layer 9 has an opening region, at least a portion of the first transparent conductive layer 7 is disposed in the opening region, and is connected to the first polycrystalline semiconductor layer 3.

[0080] In some embodiments, the first electrode 5 and the second electrode 6 are formed by screen printing a conductive paste. The metal in the conductive paste can be one or more of aluminum, silver, gold, nickel, molybdenum, or copper, and is not limited thereto. Optionally, both the first electrode 5 and the second electrode 6 are silver electrodes.

[0081] The grid line height of the first electrode 5 is 6μm to 8μm, specifically 6μm, 6.2μm, 6.5μm, 7μm, 7.5μm, 7.8μm or 8μm, etc., and of course it can also be other values ​​within the above range, which are not limited here.

[0082] The grid line height of the second electrode 6 is 7μm to 18μm, specifically 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, 13μm, 14μm, 15μm, 16μm or 18μm, etc., and of course it can also be other values ​​within the above range, which are not limited here.

[0083] The height difference H2 between the first electrode 5 and the second electrode 6 is 2μm to 12μm, specifically 2μm, 3μm, 4μm, 5μm, 7μm, 8μm, 10μm, or 12μm, or other values ​​within the above range, which are not limited here. This grid height difference design significantly reduces metal short circuits, especially bridging leakage between adjacent anode and cathode grid lines. The grid lines are staggered longitudinally, so even if there is a small amount of lateral metal spread, they will not come into contact with each other, physically blocking the metal conduction of the PN region electrode and improving current collection capability.

[0084] This application also provides a method for preparing the above-mentioned back-contact solar cell, including the following steps: An N-type semiconductor substrate is provided, the N-type semiconductor substrate having a first surface and a second surface; The second surface of the N-type semiconductor substrate is texturized and polished to form a tower-based structure. A tunneling layer and a first polycrystalline semiconductor layer are formed on the second surface; A mask layer is formed on the surface of the first polycrystalline semiconductor layer; An N-type semiconductor substrate with a mask layer is etched to expose at least a portion of the N-type semiconductor substrate, and a second surface is formed with alternating first conductive portions and second conductive portions, with a height difference between the first conductive portions and the second conductive portions. The surfaces of the first surface and the second conductive portion of the N-type semiconductor substrate are textured, forming a first textured structure on the first surface and a second textured structure on the second conductive portion. The first textured structure includes multiple first substructures, and the second textured structure includes multiple second substructures. The one-dimensional dimension of the bottom surface of the second substructure is larger than the one-dimensional dimension of the bottom surface of the first substructure. The one-dimensional dimension of the bottom surface of the tower base structure is larger than the one-dimensional dimensions of the bottom surfaces of the first and second substructures. The depth dimension of the tower base structure is smaller than the height dimensions of the first and second substructures. Remove the mask layer from the surface of the first conductive part; At least a second amorphous semiconductor layer is formed in the second conductive portion; Metallization is performed on the first polycrystalline semiconductor layer and the second amorphous semiconductor layer to form a first electrode and a second electrode, respectively. The first electrode is electrically connected to the first polycrystalline semiconductor layer, and the second electrode is electrically connected to the second amorphous semiconductor layer.

[0085] In the above scheme, by combining different texturing processes, the roughness of the light-receiving surface of the back-contact solar cell is increased. The roughness of the second textured structure on the back-light surface is smaller than that of the first textured structure, which can improve the contact area between the second electrode and the second amorphous semiconductor layer and reduce the contact resistance between the second electrode and the second amorphous semiconductor layer. The first conductive part of the back-light surface has a flat structure, and the one-dimensional dimension of the tower base structure is larger than the one-dimensional dimension of the bottom surface of the first substructure or the second substructure. The first conductive part has greater flatness, which gives the first polycrystalline semiconductor layer a good morphology, thereby improving the mobility of photogenerated carriers and thus improving the carrier concentration, thereby improving the photoelectric conversion performance of the solar cell. This application utilizes the differences in the three different microstructures of the front and back surfaces to improve the reflectivity of incident light and improve the photogenerated carrier collection capability, thereby improving the photoelectric conversion performance of the solar cell. The fabrication process of this application is simple and compatible with existing production lines.

[0086] The preparation method of the back-contact solar cell of this application is described in detail below.

[0087] S100 provides an N-type semiconductor substrate.

[0088] In some embodiments, the N-type semiconductor substrate has a first surface and a second surface disposed opposite to each other. For example, the first surface of the N-type semiconductor substrate corresponds to the front side of the battery, which is the surface facing the sun (i.e., the light-receiving surface), and the second surface of the N-type semiconductor substrate corresponds to the back side of the battery, which is the surface facing away from the sun (i.e., the back-lighting surface).

[0089] In some embodiments, the N-type semiconductor substrate is an N-type crystalline silicon substrate (or silicon wafer). The crystalline silicon substrate (silicon substrate) is, for example, a polycrystalline silicon substrate, a monocrystalline silicon substrate, a microcrystalline silicon substrate, or a silicon carbide substrate, and is not limited thereto.

[0090] S200: The second surface of the N-type semiconductor substrate is texturized and polished to form a tower base structure on the second surface; In some embodiments, the N-type semiconductor substrate is further cleaned and dried after being provided.

[0091] In some embodiments, the second surface of the N-type semiconductor substrate is wet-etched with a 1% to 3% potassium hydroxide solution for 8 to 12 minutes. After cleaning, the second surface of the N-type semiconductor substrate is polished to form a tower-based structure on the second surface of the silicon wafer.

[0092] S300, a tunneling layer and a first polycrystalline semiconductor layer are formed on the second surface.

[0093] In some embodiments, the tunneling layer can be made of one or more dielectric materials with tunneling properties, such as silicon oxide, silicon nitride, silicon oxynitride, molybdenum oxide, hafnium oxide, silicon carbide, magnesium fluoride, nanocrystalline silicon, intrinsic amorphous silicon, and intrinsic polycrystalline silicon, forming a single-layer or multi-layer structure. The tunneling layer can be formed using chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes.

[0094] In some embodiments, a polycrystalline silicon layer is formed on the surface of the tunneling layer using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Then, a diffusion process is employed to highly dope a gas containing a dopant source, forming a first polycrystalline semiconductor layer. The diffusion process causes the N-type dopant source (such as phosphorus, arsenic, or tellurium sources) to react with the surface of the polycrystalline silicon layer, forming doped atoms that diffuse into the interior of the polycrystalline silicon layer. Specifically, the first polycrystalline semiconductor layer is an N-type doped polycrystalline silicon layer, and the N-type doped polycrystalline silicon layer has the same conductivity type as the dopant elements in the N-type semiconductor substrate.

[0095] It is understandable that while forming the first polycrystalline semiconductor layer, a layer of silicon phosphide glass (PSG) is formed on the first surface of the N-type semiconductor substrate and the surface of the first polycrystalline semiconductor layer. This layer of silicon phosphide glass is of very poor quality and needs to be removed later, for example, by rinsing and etching with hydrofluoric acid solution.

[0096] S400, a mask layer is formed on the surface of the first polycrystalline semiconductor layer.

[0097] In some embodiments, the mask layer can be made of silicon oxide, silicon nitride, silicon oxynitride, etc. The method for forming the mask layer can be chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc.

[0098] S500, an etching process is performed on an N-type semiconductor substrate having a mask layer, such that at least a portion of the N-type semiconductor substrate is exposed, and a first conductive portion and a second conductive portion are formed alternately on the second surface, with a height difference between the first conductive portion and the second conductive portion.

[0099] In some embodiments, a local laser processing technique can be used to etch the N-type semiconductor substrate with a mask layer, with the etching depth being greater than the total thickness of the tunneling layer, the first polycrystalline semiconductor layer, and the mask layer, thereby exposing the N-type semiconductor substrate.

[0100] In some embodiments, the laser used for local laser processing is red light, and the power of the local laser processing is 520W to 1650W, specifically 520W, 550W, 600W, 700W, 800W, 900W, 1000W, 1100W, 1200W, 1300W, 1400W, 1500W, 1600W, 1650W, or any value within the range of any two of the above values.

[0101] Understandably, the phosphosilicate glass (PSG) in this area can be removed by etching. The area corresponding to the second conductive part can be formed after laser etching, so that the second surface has alternating first and second conductive parts with a height difference.

[0102] Following step S500, the fabrication method further includes: acid etching to remove the phosphosilicate glass (PSG) from the first surface of the N-type semiconductor substrate 1. Exemplarily, the PSG can be removed by single-sided rinsing and etching of the first surface of the N-type semiconductor substrate 1 using a hydrofluoric acid solution.

[0103] S600, texturing is performed on the first surface and the surface of the second conductive part of the N-type semiconductor substrate, respectively, so that the first surface forms a first texture structure and the second conductive part forms a second texture structure.

[0104] In some embodiments, a 2.5% potassium hydroxide solution is used to etch the first surface of the N-type semiconductor substrate for 500-600 seconds to form a first textured structure.

[0105] In some embodiments, the second surface of the N-type semiconductor substrate is wet-etched using a 3% to 4% potassium hydroxide solution for 150 to 250 seconds to form a second textured structure.

[0106] S700, remove the mask layer from the surface of the first conductive part.

[0107] In some implementations, the mask layer on the surface of the first conductive part can be removed by laser etching.

[0108] Following S700, the preparation methods also include: A first passivation layer and an anti-reflection layer are formed on the first surface of an N-type semiconductor substrate; Remove the plating around the second surface of the N-type semiconductor substrate.

[0109] In some embodiments, the material of the first passivation layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, etc. Of course, other types of passivation layers may also be used, and this application does not limit them.

[0110] In some implementations, the first passivation layer can be deposited using plasma-enhanced chemical vapor deposition.

[0111] In some implementations, a chain magnetron sputtering process can be used to form the antireflection layer on the surface of the first passivation layer. Other methods, such as organic chemical vapor deposition, can also be used. The material of the antireflection layer can include silicon nitride, silicon oxynitride, silicon oxide, etc.

[0112] In some embodiments, the method of removing the back-side plating from the second surface of the N-type semiconductor substrate can be achieved by sequentially performing etching solution spraying, etching to remove the back-side plating, washing with water, and drying under chain conveyor.

[0113] S800, at least a second amorphous semiconductor layer is formed in the second conductive portion; In some embodiments, an amorphous silicon layer can be simultaneously deposited on the first and second conductive portions on the back side of an N-type semiconductor substrate using chemical vapor deposition, physical vapor deposition, or atomic layer deposition. A boron source is then used to diffuse boron into the amorphous silicon layer to form a P-type doped amorphous silicon layer. The boron source includes at least one of boron trichloride, boron tribromide, and diborane, and the boron diffusion method includes any one or more methods such as high-temperature diffusion or ion implantation. That is, the second amorphous semiconductor layer comprises a stacked amorphous silicon layer and a P-type doped amorphous silicon layer.

[0114] In some embodiments, an amorphous silicon layer and a P-type doped amorphous silicon layer are formed on the first conductive portion and the second conductive portion on the back side of the N-type semiconductor substrate; then, a portion of the stacked amorphous silicon layer and the P-type doped amorphous silicon layer on the surface of the first conductive portion are removed, so that an opening interval is formed on the surface of the first conductive portion, thereby achieving insulation isolation between the first conductive portion and the second conductive portion.

[0115] In some implementations, the depth of the opening interval is greater than the total thickness of the amorphous silicon layer and the P-type doped amorphous silicon layer, thereby exposing the first polycrystalline semiconductor layer.

[0116] S900, metallization is performed on the first polycrystalline semiconductor layer and the second amorphous semiconductor layer to form a first electrode and a second electrode, respectively. The first electrode is electrically connected to the first polycrystalline semiconductor layer, and the second electrode is electrically connected to the second amorphous semiconductor layer.

[0117] Specifically, in this step, a first electrode and a second electrode are obtained by metallizing the first polycrystalline semiconductor layer and the second amorphous semiconductor layer. Exemplarily, the electrodes can be fabricated using screen printing and then sintered. Alternatively, at least one of metal evaporation and electroplating methods can be used to form the first and second electrodes.

[0118] In other embodiments, the preparation method further includes: A transparent conductive film is formed on the first conductive portion and the second conductive portion. A portion of the transparent conductive film fills the opening interval to form a first transparent conductive layer, and a portion of the transparent conductive film is located on the second semiconductor layer to form a second transparent conductive layer. An insulating region is formed at the junction of the first transparent conductive layer and the second transparent conductive layer; Metallization is performed on the first transparent conductive layer and the second transparent conductive layer to form a first electrode and a second electrode, respectively. The first electrode is electrically connected to the first transparent conductive layer, and the second electrode is electrically connected to the second transparent conductive layer.

[0119] In some embodiments, the materials of the first transparent conductive layer and the second transparent conductive layer may include at least one selected from fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide. The first transparent conductive layer and the second transparent conductive layer may be a single-layer structure or a multi-layer stacked structure.

[0120] In some implementations, the insulating region at the interface can be formed by wet acid washing to remove part of the transparent conductive film, thus forming a PN isolation region.

[0121] The present invention will be further described below with reference to the scheme of this application and the scheme of the comparative example.

[0122] Example 1 (1) Provide an N-type silicon wafer with a length and width of 210cm. At 183cm, the silicon wafer is subjected to standard RCA cleaning. The back side of the N-type silicon wafer is wet-etched with a 1%~3% potassium hydroxide solution for 8-12 minutes. After cleaning, the back side of the silicon wafer is polished to give it a flat structure.

[0123] (2) A silicon oxide tunneling layer and a phosphorus-doped polycrystalline silicon layer are sequentially formed on the back side of an N-type silicon wafer.

[0124] (3) A silicon oxide mask layer is formed on the surface of the phosphorus-doped polycrystalline silicon layer.

[0125] (4) A red laser is used to perform local laser etching on the back of the N-type silicon wafer to remove part of the mask layer. The laser power is 520W~1650W and the laser etching depth is 5μm.

[0126] (5) The PSG layer on the front side of the N-type silicon wafer was removed by wet etching with hydrofluoric acid.

[0127] (6) Use a 2.5% potassium hydroxide solution to etch the front side of the N-type silicon wafer for 500-600 seconds to form the first texture structure on the front side of the N-type silicon wafer; use a 3%~4% potassium hydroxide solution to wet etch the back side of the N-type silicon wafer for 150-250 seconds to form the second texture structure on the back side.

[0128] (7) Use hydrofluoric acid to remove the mask layer and PSG layer of the N-type conductive area on the back of the N-type silicon wafer, clean and dry.

[0129] (8) A first passivation layer and an anti-reflection layer are sequentially formed on the front side of an N-type silicon wafer.

[0130] (9) Use hydrofluoric acid to remove the back coating of the N-type silicon wafer, clean and dry.

[0131] (10) An amorphous silicon layer and a P-type doped amorphous silicon layer are sequentially formed on the back side of an N-type silicon wafer; (11) A red laser is used to perform local laser etching on the N-type conductive area on the back of the N-type silicon wafer, forming an opening in the first conductive part. The laser etching depth is greater than the total thickness of the amorphous silicon layer and the P-type doped amorphous silicon layer.

[0132] (12) A TCO film is deposited on the back side of an N-type silicon wafer, and the TCO film at the junction of the N-type conductive region and the P-type conductive region is removed to form an insulating region.

[0133] (13) A first electrode and a second electrode are formed on the back side of an N-type silicon wafer. The first electrode is electrically connected to a first transparent conductive film in the N-type conductive region, and the second electrode is electrically connected to a second transparent conductive film in the P-type conductive region.

[0134] Comparative Example 1 Unlike Example 1, N-type silicon wafers have a flat structure on both the front and back sides.

[0135] Testing showed that the surface area of ​​the back-contact solar cell prepared in Example 1 was approximately 1.73 times larger than that of the back-contact solar cell prepared in Comparative Example 1. This increased the contact opportunity between light and the back-contact solar cell, while also expanding the PN junction area and enhancing the collection capability of photogenerated carriers, thereby improving the photoelectric conversion efficiency. The different textured surface designs on the front and back sides can increase the contact area of ​​the electrodes and reduce contact resistance.

[0136] Based on the same inventive concept, this application also provides a stacked battery. Figure 5 This is a schematic diagram of the structure of a tandem battery, as shown below. Figure 5As shown, the stacked solar cell 2000 includes a perovskite top cell 2001 and a crystalline silicon bottom cell 2002 stacked along a predetermined direction; wherein, the crystalline silicon bottom cell 2002 includes the back-contact solar cell provided in the above embodiments of the present invention. It should be noted that the stacked solar cell 2000 provided by the present invention has the technical effects of the back-contact solar cell of the present invention, and repeated descriptions will not be repeated here.

[0137] Based on the same inventive concept, this application also provides a photovoltaic module, which includes: A battery string is formed by electrically connecting multiple back-contact solar cells or tandem cells prepared by the above-described preparation method. Encapsulation layer, which covers the surface of the battery string; Cover plate, used to cover the surface of the encapsulation layer away from the battery string.

[0138] Specifically, Figure 6 A schematic diagram of a photovoltaic module structure is shown, such as... Figure 6 As shown, the photovoltaic module 1000 includes a first cover plate 200, a first encapsulating layer 300, a solar cell string, a second encapsulating layer 400, and a second cover plate 500.

[0139] In some embodiments, the solar cell string includes multiple back-contact solar cells 100 or tandem cells 2000 as described above, connected by conductive strips. The connection between the back-contact solar cells 100 can be partial stacking or splicing. Similarly, the connection between the tandem cells 2000 can be partial stacking or splicing.

[0140] In some embodiments, the first cover plate 200 and the second cover plate 500 can be transparent or opaque covers, such as glass covers or plastic covers.

[0141] The first encapsulating adhesive layer 300 is in contact with and bonded to the first cover plate 200 and the battery string on both sides, respectively. The second encapsulating adhesive layer 400 is in contact with and bonded to the second cover plate 500 and the battery string on both sides, respectively. The first encapsulating adhesive layer 300 and the second encapsulating adhesive layer 400 can be ethylene-vinyl acetate copolymer (EVA) film, polyethylene octene coelastomer (POE) film, or polyethylene terephthalate (PET) film, respectively.

[0142] The photovoltaic module 1000 can also be fully encapsulated on the sides, that is, the sides of the photovoltaic module 1000 are completely covered and encapsulated with encapsulating tape to prevent lamination shift during the lamination process.

[0143] The photovoltaic module 1000 also includes an edge sealing component, which is fixedly encapsulated on a portion of the edge of the photovoltaic module 1000. This edge sealing component can be fixedly encapsulated on the edge of the photovoltaic module 1000 near a corner. The edge sealing component can be a high-temperature resistant tape. This high-temperature resistant tape has excellent high-temperature resistance properties and will not decompose or detach during lamination, ensuring reliable encapsulation of the photovoltaic module 1000. The two ends of the high-temperature resistant tape are respectively fixed to the second cover plate 500 and the first cover plate 200. The two ends of the high-temperature resistant tape can be bonded to the second cover plate 500 and the first cover plate 200 respectively, while the middle portion can limit the side of the photovoltaic module 1000, preventing lamination displacement of the photovoltaic module 1000 during the lamination process.

[0144] The above description is merely a specific embodiment of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the protection scope of this application. The protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A back-contact solar cell, characterized in that, The back-contact solar cell includes: An N-type semiconductor substrate has a first surface and a second surface. The first surface has a first textured structure, which includes a plurality of first substructures. The second surface includes alternately arranged first and second conductive portions, with a height difference between the first and second conductive portions. The first conductive portion has a flat structure, which includes a plurality of base structures. The second conductive portion has a second textured structure, which includes a plurality of second substructures. The one-dimensional dimension of the bottom surface of each base structure is greater than the one-dimensional dimensions of the bottom surfaces of the first and second substructures, and the depth dimension of each base structure is less than the height dimensions of the first and second substructures. The one-dimensional dimension of the bottom surface of each second substructure is greater than the one-dimensional dimension of the bottom surface of the first substructure. A tunneling layer is disposed on the side of the first conductive portion away from the N-type semiconductor substrate; A first polycrystalline semiconductor layer is disposed on the side of the tunneling layer opposite to the N-type semiconductor substrate; The second amorphous semiconductor layer is disposed on the side of the second conductive portion away from the N-type semiconductor substrate; The first electrode is electrically connected to the first polycrystalline semiconductor layer; The second electrode is electrically connected to the second amorphous semiconductor layer.

2. The back-contact solar cell according to claim 1, characterized in that, The bottom surface of the tower base structure has a one-dimensional dimension of 5μm to 15μm; along the thickness direction of the N-type semiconductor substrate, the depth dimension of the tower base structure is 0.1 to 1μm.

3. The back-contact solar cell according to claim 1, characterized in that, The one-dimensional dimension of the bottom surface of the first substructure is 1μm to 3μm; the height dimension from the top to the bottom of the first substructure along the thickness direction of the N-type semiconductor substrate is 1μm to 3μm; the first included angle between the sidewall of the first substructure and the bottom of the first substructure is 20° to 70°.

4. The back-contact solar cell according to claim 1, characterized in that, The one-dimensional dimension of the bottom surface of the second substructure is 1.2μm to 4μm; the height dimension from the top to the bottom of the second substructure along the thickness direction of the N-type semiconductor substrate is 1.2μm to 4μm; the second included angle between the sidewall of the second substructure and the bottom of the second substructure is 30° to 80°.

5. The back-contact solar cell according to claim 4, characterized in that, The thickness of the second amorphous semiconductor layer located at the bottom of the second substructure is greater than the thickness of the second amorphous semiconductor layer located at the top of the second substructure.

6. The back-contact solar cell according to claim 1, characterized in that, The height difference between the first conductive part and the second conductive part is 3μm~10μm.

7. The back-contact solar cell according to claim 1, characterized in that, The height of the first electrode is 6μm to 12μm; the height of the second electrode is 7μm to 18μm; and the height difference between the first electrode and the second electrode is 2μm to 12μm.

8. The back-contact solar cell according to any one of claims 1 to 7, characterized in that, The first polycrystalline semiconductor layer is an N-type doped polycrystalline silicon layer; The second amorphous semiconductor layer includes a first amorphous silicon layer and a first P-type doped amorphous silicon layer stacked together, wherein the first P-type doped amorphous silicon layer is located on the side of the first amorphous silicon layer away from the N-type semiconductor substrate.

9. The back-contact solar cell according to claim 1, characterized in that, The back-contact solar cell also includes: A first transparent conductive layer is located between the first polycrystalline semiconductor layer and the first electrode; the first electrode is electrically connected to the first transparent conductive layer. A second transparent conductive layer is located between the second amorphous semiconductor layer and the second electrode; the second electrode is electrically connected to the second transparent conductive layer.

10. The back-contact solar cell according to claim 9, characterized in that, The back-contact solar cell also includes: The third amorphous semiconductor layer includes a second amorphous silicon layer and a second P-type doped amorphous silicon layer stacked together. The second amorphous silicon layer is located on the side of the first polycrystalline semiconductor layer away from the tunneling layer. The third amorphous semiconductor layer has an opening region and a thickness of 10 nm to 100 nm. At least a portion of the first transparent conductive layer is disposed in the opening region and is connected to the first polycrystalline semiconductor layer.

11. The back-contact solar cell according to any one of claims 1 to 7, characterized in that, The first conductive portion accounts for 20%-50% of the distribution on the second surface of the N-type semiconductor substrate; the second conductive portion accounts for 50%-80% of the distribution on the second surface of the N-type semiconductor substrate.

12. A method for fabricating a back-contact solar cell, characterized in that, The preparation method includes: An N-type semiconductor substrate is provided, the N-type semiconductor substrate having a first surface and a second surface; The second surface of the N-type semiconductor substrate is texturized and polished to form a tower base structure. A tunneling layer and a first polycrystalline semiconductor layer are formed on the second surface; A mask layer is formed on the surface of the first polycrystalline semiconductor layer; An N-type semiconductor substrate having the mask layer is etched to expose at least a portion of the N-type semiconductor substrate, and an alternating first conductive portion and a second conductive portion are formed on the second surface, with a height difference between the first conductive portion and the second conductive portion. The surfaces of the first surface and the second conductive portion of the N-type semiconductor substrate are respectively texturized, forming a first textured structure on the first surface and a second textured structure on the second conductive portion. The first textured structure includes multiple first substructures, and the second textured structure includes multiple second substructures. The one-dimensional dimension of the bottom surface of the second substructure is larger than the one-dimensional dimension of the bottom surface of the first substructure. The one-dimensional dimension of the bottom surface of the tower base structure is larger than both the one-dimensional dimensions of the bottom surfaces of the first and second substructures. The depth dimension of the tower base structure is smaller than both the height dimensions of the first and second substructures. Remove the mask layer from the surface of the first conductive part; At least a second amorphous semiconductor layer is formed in the second conductive portion; Metallization is performed on the first polycrystalline semiconductor layer and the second amorphous semiconductor layer to form a first electrode and a second electrode, respectively. The first electrode is electrically connected to the first polycrystalline semiconductor layer, and the second electrode is electrically connected to the second amorphous semiconductor layer.

13. The preparation method according to claim 12, characterized in that, The step of forming at least a second amorphous semiconductor layer in the second conductive portion includes: An amorphous silicon layer and a P-type doped amorphous silicon layer are formed on the first conductive portion and the second conductive portion respectively; The amorphous silicon layer and the P-type doped amorphous silicon layer, which are partially stacked on the surface of the first conductive portion, are removed, so that an opening interval is formed on the surface of the first conductive portion, and the depth of the opening interval is greater than the total thickness of the amorphous silicon layer and the P-type doped amorphous silicon layer.

14. The preparation method according to claim 13, characterized in that, The preparation method further includes: A transparent conductive film is formed on the first conductive portion and the second conductive portion, a portion of the transparent conductive film fills the opening interval to form a first transparent conductive layer, and a portion of the transparent conductive film is located on the second semiconductor layer to form a second transparent conductive layer; An insulating region is formed at the junction of the first transparent conductive layer and the second transparent conductive layer; Metallization is performed on the first transparent conductive layer and the second transparent conductive layer to form a first electrode and a second electrode, respectively. The first electrode is electrically connected to the first transparent conductive layer, and the second electrode is electrically connected to the second transparent conductive layer.

15. The preparation method according to claim 12, characterized in that, After removing the mask layer from the surface of the first conductive portion and polishing it, and before forming a second semiconductor layer at least on the second conductive portion, the method further includes: A first passivation layer is formed on the first surface of the N-type semiconductor substrate; An antireflection layer is formed on the surface of the first passivation layer.

16. A stacked battery, characterized in that, The invention includes a perovskite top cell and a crystalline silicon bottom cell stacked together, wherein the crystalline silicon bottom cell is a back-contact solar cell according to any one of claims 1 to 11 or a back-contact solar cell prepared by the preparation method according to any one of claims 12 to 15.

17. A photovoltaic module, characterized in that, include: A battery string, wherein the battery string is formed by connecting a plurality of back-contact solar cells as described in any one of claims 1 to 11, or back-contact solar cells prepared by the preparation method of any one of claims 12 to 15, or tandem cells as described in claim 16. An encapsulation layer that covers the surface of the battery string; A cover plate that covers the surface of the encapsulation layer away from the battery string.

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