A light-emitting chip and its fabrication method

Abstract

This invention discloses a light-emitting chip and its fabrication method, relating to the field of display technology. The light-emitting chip includes: an epitaxial layer having at least one light-emitting stage protruding from a second surface on its first surface; a first reflective layer disposed on the top surface of the light-emitting stage; a passivation layer formed on the sidewall of the light-emitting stage, the surface of the first reflective layer away from the light-emitting stage, and the first surface outside the area where the light-emitting stage is located; a second reflective layer disposed on the side of the passivation layer away from the epitaxial layer, the second reflective layer having an opening that exposes the passivation layer located on the top surface of the light-emitting stage; and a polished surface of the portion of the second reflective layer located on the sidewall of the light-emitting stage being coplanar with the upper surface of the portion of the passivation layer located on the top surface of the light-emitting stage. The technical solution provided by this invention effectively avoids the short-circuit problem between the top of the light-emitting stage and the sidewall reflective layer, while providing sufficient process windows for conductive components, meeting the integration requirements of small-sized micro-display devices.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a light-emitting chip and its fabrication method. Background Technology

[0002] Micro-LED (Micro Light Emitting Diode) is a new display technology. Compared with the current mainstream display technologies OLED (Organic Light-Emitting Diode) and LCD (Liquid Crystal Display), it has a simpler structure and more obvious performance advantages, such as high brightness, wide color gamut, low energy consumption, long lifespan, and fast response speed.

[0003] Figure 1 This is a schematic diagram of the structure of a light-emitting chip provided in the prior art, for reference. Figure 1 In the manufacturing process of micro-light-emitting chips, to improve light extraction efficiency, a reflective metal structure 2 is usually placed on the side wall of the light-emitting stage (Mesa) and a reflective metal structure 1 is placed on the top of the light-emitting stage. In the field of small-size micro-displays, the influence of overlay accuracy needs to be considered, which results in the etched area usually being smaller than the width of the top surface of the light-emitting stage. In order to prevent the reflective metal structure 1 on the top of the light-emitting stage from short-circuiting with the reflective metal structure 2 on the side wall, and to consider the overlay accuracy, the etching window of the passivation layer 3 needs to be further reduced, which leads to the extreme compression of the size of the electrode conductive component 4, or even no space to place it.

[0004] Therefore, how to effectively avoid short circuits between the top and sidewall reflective layers of the light-emitting stage without relying on stringent overlay precision, while providing sufficient process windows for conductive components to meet the integration requirements of small-sized micro-display devices, is an urgent problem to be solved. Summary of the Invention

[0005] This invention provides a light-emitting chip and its fabrication method, which effectively avoids the short-circuit problem between the top of the light-emitting stage and the side wall reflective layer without relying on strict overlay precision, while providing sufficient process windows for conductive components to meet the integration requirements of small-sized micro-display devices.

[0006] According to one aspect of the present invention, a light-emitting chip is provided, comprising: The epitaxial layer includes a first surface and a second surface disposed opposite to each other, and the first surface has at least one light-emitting stage protruding away from the second surface; A first reflective layer is disposed on the top surface of the light-emitting stage and is used to reflect the light emitted by the light-emitting stage; wherein, the top surface of the light-emitting stage is located on one side of the backlight surface of the light-emitting chip; A passivation layer is formed on the sidewall of the light-emitting stage, the surface of the first reflective layer away from the light-emitting stage, and the first surface outside the area where the light-emitting stage is located; A second reflective layer is disposed on the side of the passivation layer away from the epitaxial layer, and the second reflective layer has an opening that exposes the passivation layer located on the top surface of the light-emitting stage; wherein, the polished surface of the portion of the second reflective layer located on the sidewall of the light-emitting stage is coplanar with the upper surface of the portion of the passivation layer located on the top surface of the light-emitting stage.

[0007] Optionally, the light-emitting chip further includes: A first conductive element penetrates the passivation layer and is electrically connected to the first reflective layer; wherein, the material of the first reflective layer is a conductive material, and the first reflective layer is reused as the first electrode of the light-emitting chip; And / or, a second conductive element is electrically connected to the second reflective layer; wherein the material of the second reflective layer is a conductive material.

[0008] Optionally, the light-emitting chip further includes: A planarization layer is disposed on the side of the second reflective layer away from the epitaxial layer and covers the passivation layer on the top surface of the light-emitting stage exposed by the opening; The first conductive element passes through the planarization layer and the passivation layer in sequence to be electrically connected to the first reflective layer; the second conductive element passes through the planarization layer to be electrically connected to the second reflective layer.

[0009] Optionally, the second surface has a first groove; The light-emitting chip further includes a second electrode, which is located in the first groove; The epitaxial layer includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked sequentially; the light-emitting stage includes at least the quantum well layer and the second semiconductor layer; the second surface is the surface of the first semiconductor layer away from the light-emitting stage; the first conductive element is electrically connected to the second semiconductor layer through the first reflective layer; and the second electrode is electrically connected to the first semiconductor layer.

[0010] Optionally, the orthographic projection of the second electrode on the first surface is arranged around the light-emitting stage; Alternatively, the orthographic projection of the second electrode onto the first surface is located on opposite sides of the light-emitting stage.

[0011] Optionally, the epitaxial layer includes a plurality of planarly arranged light-emitting stages; The second electrode is a common electrode of the plurality of light-emitting stages; the second electrode has a mesh structure or a ladder structure.

[0012] Optionally, the second surface also has a second groove; The light-emitting chip further includes a third conductive element, which is located in the second groove and extends toward the second reflective layer until it is electrically connected to the second reflective layer; the third conductive element is electrically connected to the second conductive element through the second reflective layer; the third conductive element is also electrically connected to the second electrode.

[0013] Optionally, the orthographic projection of the third conductive element on the first surface at least partially overlaps with the orthographic projection of the second conductive element on the first surface.

[0014] Optionally, the light-emitting chip further includes: The driving substrate is located on the side of the planarization layer away from the epitaxial layer; The driving substrate includes a first driving electrode and a second driving electrode, the first driving electrode and the second driving electrode being exposed on the surface of the driving substrate near the planarization layer; wherein, the first driving electrode is electrically connected to the first conductive element, and the second driving electrode is electrically connected to the second conductive element.

[0015] According to another aspect of the present invention, a method for fabricating a light-emitting chip is provided, for fabricating the light-emitting chip described in any embodiment of the present invention, the method comprising: An epitaxial layer is formed, the epitaxial layer including a first surface and a second surface disposed opposite to each other, and the first surface having at least one light-emitting stage protruding toward the side opposite to the second surface; A first reflective layer is formed on the top surface of the light-emitting stage, the first reflective layer being used to reflect the light emitted by the light-emitting stage; wherein, the top surface of the light-emitting stage is located on one side of the backlight surface of the light-emitting chip; A passivation layer is formed on the sidewall of the light-emitting stage, the surface of the first reflective layer opposite to the light-emitting stage, and the area of ​​the first surface outside the light-emitting stage. A second reflective layer is formed on the side of the passivation layer away from the epitaxial layer, and the second reflective layer above the passivation layer on the top surface of the light-emitting stage is ground to form an opening in the second reflective layer that exposes the passivation layer on the top surface of the light-emitting stage; wherein the polished surface of the portion of the second reflective layer located on the sidewall of the light-emitting stage is coplanar with the upper surface of the portion of the passivation layer located on the top surface of the light-emitting stage.

[0016] Optionally, forming the epitaxial layer includes: Provide substrate; An initial epitaxial layer is formed on one side of the substrate; the initial epitaxial layer includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer sequentially away from the substrate; Based on the first mask layer, the second semiconductor layer and the quantum well layer are patterned sequentially to form at least one light-emitting stage.

[0017] Optionally, forming a first reflective layer on the top surface of the light-emitting stage includes: An initial first reflective layer is formed on the surface of the initial epitaxial layer away from the substrate; Based on the first mask layer, the initial first reflective layer is patterned to form the first reflective layer.

[0018] Optionally, after forming a second reflective layer on the side of the passivation layer away from the epitaxial layer and grinding the second reflective layer above the passivation layer on the top surface of the light-emitting stage to form an opening in the second reflective layer, the method further includes: A planarization layer is formed, which is disposed on the side of the second reflective layer away from the epitaxial layer and covers the passivation layer on the top surface of the light-emitting stage exposed by the opening; A first conductive element and a second conductive element are formed; the first conductive element passes through the planarization layer and the passivation layer in sequence to be electrically connected to the first reflective layer, and the second conductive element passes through the planarization layer to be electrically connected to the second reflective layer.

[0019] Optionally, after forming the first conductive element and the second conductive element, the method further includes: A driving substrate is provided, the driving substrate including a first driving electrode and a second driving electrode; The driving substrate is bonded to the planarization layer on the side away from the epitaxial layer, so that the first driving electrode is electrically connected to the first conductive element and the second driving electrode is electrically connected to the second conductive element. Remove the substrate to expose the second surface of the epitaxial layer; A first groove is formed on the second surface, and a second electrode is formed in the first groove; wherein, the epitaxial layer includes a first semiconductor layer, a quantum well layer and a second semiconductor layer stacked sequentially; the light-emitting stage includes at least the quantum well layer and the second semiconductor layer; the second surface is the surface of the first semiconductor layer facing away from the light-emitting stage; the first conductive element is electrically connected to the second semiconductor layer through the first reflective layer, and the second electrode is electrically connected to the first semiconductor layer.

[0020] Optionally, the method for manufacturing the light-emitting chip further includes: A second groove is formed on the second surface; A third conductive element is formed in the second groove; the third conductive element is electrically connected to the second electrode, and the third conductive element extends toward the second reflective layer until it is electrically connected to the second reflective layer, so as to be electrically connected to the second conductive element through the second reflective layer.

[0021] The technical solution provided by this invention improves the light extraction efficiency of the light-emitting chip by setting a first reflective layer on the top surface of the light-emitting stage and a second reflective layer on the side wall of the light-emitting stage. Furthermore, the second reflective layer has an opening that exposes the passivation layer located on the top surface of the light-emitting stage, and the polished surface of the portion of the second reflective layer located on the side wall of the light-emitting stage is coplanar with the upper surface of the portion of the passivation layer located on the top surface of the light-emitting stage. This means that the second reflective layer on the top surface of the light-emitting stage is directly removed by a chemical mechanical polishing (CMP) process, resulting in a coplanar structure between the second reflective layer on the side wall and the top passivation layer after CMP. This ensures electrical isolation between the second reflective layer on the side wall and the first reflective layer on the top surface, while completely avoiding the problem of reduced etching window size due to insufficient overlay precision. This provides ample lateral space for the arrangement of conductive electrodes, ensuring sufficient critical dimensions for the conductive components even at pixel pitches of 2.5 μm or smaller. Simultaneously, the flat top surface facilitates uniform coverage of subsequent film layers, significantly improving the manufacturability and integration yield of small-sized micro-display devices.

[0022] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of the structure of a light-emitting chip provided in the prior art; Figure 2 This is a schematic diagram of the structure of a light-emitting chip provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another light-emitting chip provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another light-emitting chip provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of another light-emitting chip provided in an embodiment of the present invention; Figure 6 This is a top view of the second surface of a light-emitting chip provided in an embodiment of the present invention; Figure 7 This is a top view of the second surface in another light-emitting chip provided in an embodiment of the present invention; Figure 8 This is a top view of the second surface in another light-emitting chip provided in an embodiment of the present invention; Figure 9 This is a flowchart of a method for fabricating a light-emitting chip according to an embodiment of the present invention; Figure 10 This is a flowchart of another method for preparing a light-emitting chip provided in an embodiment of the present invention; Figure 11 This is a schematic cross-sectional view of step S220 in a method for fabricating a light-emitting chip according to an embodiment of the present invention. Figure 12 This is a schematic cross-sectional view of step S230 in a method for fabricating a light-emitting chip according to an embodiment of the present invention. Figure 13 This is a schematic cross-sectional view of the structure after the first mask layer is formed in a method for fabricating a light-emitting chip according to an embodiment of the present invention. Figure 14 This is a schematic cross-sectional view of step S250 in a method for fabricating a light-emitting chip according to an embodiment of the present invention. Figure 15 This is a schematic cross-sectional view of step S270 in a method for fabricating a light-emitting chip according to an embodiment of the present invention. Figure 16 This is a schematic cross-sectional view of step S280 in a method for fabricating a light-emitting chip according to an embodiment of the present invention. Figure 17 This is a schematic cross-sectional view of step S290 in a method for fabricating a light-emitting chip according to an embodiment of the present invention. Figure 18 This is a schematic cross-sectional view of the structure after the formation of the first and second openings in a method for fabricating a light-emitting chip according to an embodiment of the present invention. Figure 19 This is a cross-sectional structural diagram corresponding to step S2100 in a method for preparing a light-emitting chip according to an embodiment of the present invention; Figure 20 A schematic cross-sectional view of step S2110 in a method for fabricating a light-emitting chip according to an embodiment of the present invention; Figure 21 A schematic cross-sectional view of step S2120 in a method for fabricating a light-emitting chip according to an embodiment of the present invention; Figure 22A schematic cross-sectional view of step S2130 in a method for fabricating a light-emitting chip according to an embodiment of the present invention; Figure 23 A cross-sectional structural diagram corresponding to step S2140 in a method for fabricating a light-emitting chip provided in this embodiment of the invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] This invention provides a light-emitting chip. Figure 2 This is a schematic diagram of the structure of a light-emitting chip provided in an embodiment of the present invention, for reference. Figure 2 The light-emitting chip includes: The epitaxial layer 10 includes a first surface S11 and a second surface S12 disposed opposite to each other, and the first surface S11 has at least one light-emitting stage 100 protruding toward the second surface S12. The first reflective layer 20 is disposed on the top surface of the light-emitting stage 100 and is used to reflect the light emitted by the light-emitting stage 100; wherein, the top surface of the light-emitting stage 100 is located on one side of the back light surface of the light-emitting chip. A passivation layer 30 is formed on the sidewall of the light-emitting stage 100, the surface of the first reflective layer 20 away from the light-emitting stage 100, and the first surface S11 outside the area where the light-emitting stage 100 is located. The second reflective layer 40 is disposed on the side of the passivation layer 30 away from the epitaxial layer 10, and the second reflective layer 40 has an opening that exposes the passivation layer 30 located on the top surface of the light-emitting stage 100; wherein, the polished surface S2 of the portion of the second reflective layer 40 located on the side wall of the light-emitting stage 100 is coplanar with the upper surface S1 of the portion of the passivation layer 30 located on the top surface of the light-emitting stage 100.

[0028] Specifically, the epitaxial layer 10 is the basic functional layer of the light-emitting chip, and it has a first surface S11 and a second surface S12 disposed opposite to each other. The side containing the second surface S12 is the light-emitting side of the epitaxial layer 10, and the side containing the first surface S11 is the backlight side of the epitaxial layer 10. The epitaxial layer 10 has at least one light-emitting platform 100, which is a platform-shaped structure protruding from the epitaxial layer 10 in a direction away from the second surface S12. The light-emitting platform 100 serves as the active light-emitting region of the light-emitting chip.

[0029] A first reflective layer 20 is disposed on the top surface of the light-emitting stage 100 (i.e., the flat surface of the light-emitting stage 100 away from the second surface S12). This first reflective layer 20 is made of a highly reflective metal (such as aluminum or silver), and its function is to reflect the light emitted by the light-emitting stage 100 towards the top surface back to the second surface S12, thereby allowing the light to exit from the light-emitting surface of the light-emitting chip and improving the light extraction efficiency. The first reflective layer 20 only covers the top surface of the light-emitting stage 100 and does not cover the sidewalls of the light-emitting stage 100 or other areas of the epitaxial layer 10.

[0030] The passivation layer 30 simultaneously covers three areas: the entire sidewall of the light-emitting stage 100, the upper surface of the first reflective layer 20 (i.e., the surface of the first reflective layer 20 away from the light-emitting stage 100), and the uncovered first surface S11 of the light-emitting stage 100 (i.e., the flat area of ​​the epitaxial layer 10 exposed between the light-emitting stages 100). The passivation layer 30 can be made of insulating materials such as silicon dioxide or silicon nitride, and is formed by deposition or other processes, serving to protect the sidewall of the light-emitting stage 100, prevent leakage current, and isolate the second reflective layer 40.

[0031] A second reflective layer 40 is disposed on the side of the passivation layer 30 away from the epitaxial layer 10. This second reflective layer 40 can also be made of a highly reflective metallic material to further reflect laterally propagated light back to the light-emitting direction. Specifically, an opening is formed in the second reflective layer 40, positioned opposite the top surface of the light-emitting stage 100, so that the passivation layer 30 located on the top surface of the light-emitting stage 100 is exposed within the opening and not covered by the second reflective layer 40. Furthermore, the portion of the second reflective layer 40 located on the sidewall of the light-emitting stage 100 has a polished upper surface S2, which is coplanar with the upper surface S1 of the passivation layer 30 located on the top surface of the light-emitting stage 100. In some embodiments, this coplanarity is a horizontal plane; in other embodiments, it is an inclined plane forming an angle with the horizontal plane.

[0032] This coplanar structure is achieved through a chemical mechanical polishing (CMP) process. After the passivation layer 30 and the second reflective layer 40 are deposited sequentially, due to the protrusion at the top of the light-emitting stage 100, the second reflective layer 40 in the protruding area is preferentially removed during CMP of the entire surface until the passivation layer 30 at the top of the light-emitting stage 100 is exposed. This allows the upper surface of the second reflective layer 40 on the sidewall of the light-emitting stage 100 to be polished flush with the exposed upper surface of the passivation layer 30. In this way, the opening is naturally formed without the need for additional photolithography masks and etching steps, completely avoiding the problems of top metal residue or sidewall metal protrusions caused by insufficient overlay precision. Simultaneously, it provides ample lateral space for subsequent electrode connections on the top surface of the light-emitting stage 100. In other embodiments, during CMP of the entire surface, CMP is performed after the passivation layer 30 at the top of the light-emitting stage 100 is exposed, i.e., the passivation layer 30 is further thinned.

[0033] In the light-emitting chip structure provided by this invention, the CMP process is used to remove only the second reflective layer 40 at the top of the light-emitting stage 100, while retaining the passivation layer 30 intact or partially polished. The advantages of this configuration include: First, the CMP process has a very high selectivity for metals (such as Al) and oxides (such as SiO2), and the passivation layer 30 can act as a natural stop layer, effectively preventing the polishing process from continuing downwards during the polishing of the second reflective layer 40, thus avoiding short circuits between the sidewall reflective metal and the epitaxial layer 10 or other conductive structures after the passivation layer 30 is removed; second, retaining the passivation layer 30 without polishing ensures excellent surface flatness and uniformity across the entire wafer after the CMP process, greatly improving product yield; simultaneously, the presence of the passivation layer 30 significantly expands the CMP process window, ensuring that even with some over-polishing, the underlying first reflective layer 20 and epitaxial layer 10 will not be damaged, further guaranteeing the reliability of the light-emitting chip.

[0034] The technical solution provided by the present invention improves the light emission efficiency of the light-emitting chip by setting a first reflective layer 20 on the top surface of the light-emitting stage 100 and a second reflective layer 40 on the side wall of the light-emitting stage 100. Based on this, the second reflective layer 40 is provided with an opening that exposes the passivation layer 30 located on the top surface of the light-emitting stage 100. The polished surface S2 of the second reflective layer 40 located on the side wall of the light-emitting stage 100 is coplanar with the upper surface of the passivation layer 30 located on the top surface of the light-emitting stage 100. That is, the second reflective layer 40 on the top surface of the light-emitting stage 100 is directly removed by chemical mechanical polishing. This makes the second reflective layer 40 located on the side wall of the light-emitting stage 100 form a coplanar structure with the top passivation layer 30 after chemical mechanical polishing. While ensuring that the side wall second reflective layer 40 is isolated from the top surface first reflective layer 20, the problem of etching window shrinkage caused by insufficient overlay accuracy is completely avoided. This releases sufficient lateral space for the arrangement of electrode conductive components, ensuring that the conductive components have sufficient critical dimensions even at a pixel pitch of 2.5μm or even smaller. At the same time, the flat top surface is conducive to the uniform coverage of subsequent film layers, significantly improving the manufacturability and integration yield of small-sized micro-display devices.

[0035] Based on the above embodiments, refer to Figure 2 Optionally, the epitaxial layer 10 may include multiple stacked semiconductor layers. For example, the epitaxial layer 10 includes a first semiconductor layer 11, a quantum well layer 13, and a second semiconductor layer 12 stacked sequentially. The second surface S12 is the surface of the first semiconductor layer 11 away from the quantum well layer 13. The first semiconductor layer 11 and the second semiconductor layer 12 have different semiconductor types. The first semiconductor layer 11 can be an N-type semiconductor layer, and the second semiconductor layer 12 can be a P-type semiconductor layer. Alternatively, the first semiconductor layer 11 can be a P-type semiconductor layer, and the second semiconductor layer 12 can be an N-type semiconductor layer. The light-emitting stage 100 includes at least a quantum well layer 13 and a second semiconductor layer 12. Each light-emitting stage 100 and the first semiconductor layer 11 below the light-emitting stage 100 are used to form an LED unit.

[0036] Optionally, the light-emitting stage 100 has a trapezoidal cross-section. When the light-emitting stage 100 is subsequently flip-chip connected to the driving substrate, the cross-section of the light-emitting stage 100 is an inverted trapezoid, making the area of ​​the light-emitting surface of each light-emitting stage 100 larger than the area of ​​the backlight surface, which is beneficial for improving the light extraction efficiency of the light-emitting chip. For example, the three-dimensional structure of the light-emitting stage 100 can be a frustum or a truncated cone shape.

[0037] Based on the above embodiments, refer to Figure 3 Optionally, the light-emitting chip also includes a current spreading layer 50, which can be disposed at least at one location on the surface of the first semiconductor layer 11 away from the quantum well layer 13 and on the surface of the second semiconductor layer 12 away from the quantum well layer 13. Figure 3The illustrated structure exemplifies that the first semiconductor layer 11 is an N-type semiconductor layer, the second semiconductor layer 12 is a P-type semiconductor layer, and the current spreading layer 50 is disposed between the first reflective layer 20 and the second semiconductor layer 12, and is in contact with the surface of the second semiconductor layer 12. The injected current can be laterally spread within the current spreading layer 50 and then uniformly injected into the lower light-emitting stage 100. The material of the current spreading layer 50 may include indium tin oxide.

[0038] Based on the above embodiments, refer to Figure 4 Optionally, the light-emitting chip further includes a first conductive element T1, which penetrates the passivation layer 30 and is electrically connected to the first reflective layer 20. The first reflective layer 20 is made of a conductive material and is reused as the first electrode 81 of the light-emitting chip. When the light-emitting chip includes multiple light-emitting stages 100, the number of first conductive elements T1 can be multiple. The reflective layer on the top surface of each light-emitting stage 100 is electrically connected to a first conductive element T1, providing a driving voltage to the light-emitting stage 100.

[0039] Specifically, the first reflective layer 20 not only reflects the light emitted from the light-emitting stage 100, but also serves as an electrical connection structure, achieving electrical conductivity with an external driving circuit or pad through the first conductive element T1. Since the first reflective layer 20 is directly disposed on the top surface of the light-emitting stage 100 and electrically connected to the semiconductor layer (e.g., the second semiconductor layer 12) inside the light-emitting stage 100, the step of separately fabricating the first electrode 81 can be eliminated, simplifying the stacked structure of the light-emitting chip. The material of the first conductive element T1 can be a metal (such as gold, tin, copper, titanium, aluminum, or their alloys) or a conductive composite material. The other end of the first conductive element T1 can be further connected to an electrode on the driving substrate to realize the input of external electrical signals.

[0040] The technical solution provided in this embodiment reuses the first reflective layer 20 as the first electrode 81, which not only reduces the additional electrode manufacturing process, but also shortens the current transmission path since the first reflective layer 20 is directly located on the top surface of the light-emitting stage 100, which is beneficial to reduce the operating voltage and improve the luminous efficiency.

[0041] Furthermore, the light-emitting chip also includes a second electrode, which can be located on the second surface S12 of the epitaxial layer 10, thereby forming an ohmic contact with the first semiconductor layer 11. The first electrode 81 and the second electrode are used to provide a driving voltage for the light-emitting stage 100. The first electrode 81 can be the anode of the light-emitting chip, and the second electrode can be the cathode of the light-emitting chip; or, the second electrode can be the anode of the light-emitting chip, and the first electrode 81 can be the cathode of the light-emitting chip.

[0042] Based on the above embodiments, refer to Figure 4Optionally, the light-emitting chip also includes a second conductive element T2, which is electrically connected to the second reflective layer 40; wherein the material of the second reflective layer 40 is a conductive material.

[0043] Specifically, during the etching process to form the light-emitting stage 100, damage to the active region material at the sidewalls of the light-emitting stage 100 is inevitable. Subsequent processing steps also introduce defects and contamination into the exposed active region. These defects, damage, and contamination become non-radiative recombination centers and leakage channels for charge carriers, leading to a decrease in the luminous efficiency of the light-emitting chip. In this embodiment of the invention, the material of the second reflective layer 40 is a conductive material, and a second conductive element T2 electrically connected to the second reflective layer 40 can apply a voltage signal to the second reflective layer 40, giving it a preset potential. This utilizes the electric field effect to move charge carriers in the quantum well layer 13 away from the etching edge, suppressing non-radiative recombination of charge carriers at the sidewalls and effectively improving the luminous efficiency of the light-emitting chip. The voltage signal applied by the second conductive element T2 to the second reflective layer 40 can be the same as or different from the voltage signal applied by the second conductive element T2 to the first reflective layer 20.

[0044] Based on the above embodiments, refer to Figure 4 Optionally, the light-emitting chip also includes a planarization layer 60, which is disposed on the side of the second reflective layer 40 away from the epitaxial layer 10 and covers the passivation layer 30 on the top surface of the light-emitting stage 100 exposed by the opening. The first conductive element T1 passes through the planarization layer 60 and the passivation layer 30 in sequence to be electrically connected to the first reflective layer 20; the second conductive element T2 passes through the planarization layer 60 to be electrically connected to the second reflective layer 40.

[0045] Specifically, the planarization layer 60 can be made of organic materials (such as polyimide or benzocyclobutene) or inorganic materials (such as silicon dioxide or silicon nitride), formed through spin coating, deposition, and chemical mechanical polishing processes. Its function is to form a flat upper plane on the chip surface with bumps and depressions, providing a good foundation for subsequent fabrication processes. The first conductive element T1 and the second conductive element T2 are respectively connected to the first reflective layer 20 and the second reflective layer 40. The two can be insulated by the planarization layer 60 and the passivation layer 30, without the need for additional isolation structures.

[0046] Based on the above embodiments, refer to Figure 5 Optionally, the second surface S12 of the epitaxial layer 10 has a first groove K3; the second electrode 82 is located in the first groove K3.

[0047] Specifically, a first groove K3 is formed on the second surface S12 of the epitaxial layer 10. The second electrode 82 is disposed in the first groove K3. The depth of the first groove K3 is less than the thickness of the first semiconductor layer 11. The epitaxial layer 10 includes a first semiconductor layer 11, a quantum well layer 13, and a second semiconductor layer 12 stacked sequentially; the light-emitting stage 100 includes at least a quantum well layer 13 and a second semiconductor layer 12; the second surface S12 is the surface of the first semiconductor layer 11 away from the light-emitting stage 100; the second electrode 82 is electrically connected to the first semiconductor layer 11, thereby forming a positive and negative electrode pair of the light-emitting chip together with the first conductive element T1, realizing current injection into the quantum well layer 13.

[0048] In this embodiment of the invention, a first groove K3 is provided on the second surface S12 of the epitaxial layer 10, and a second electrode 82 is disposed in the first groove K3, so that the second electrode 82 is electrically connected to the first semiconductor layer 11, which effectively shortens the lateral current diffusion distance and reduces the operating voltage; moreover, the first groove K3 provides the second electrode 82 with precise positioning and sufficient process space, reducing the thickness of the light-emitting chip.

[0049] Furthermore, by placing the second electrode 82 in the first groove K3 of the second surface S12 of the epitaxial layer 10, the second electrode 82 is transformed from lateral wiring to vertical space. Specifically, traditional metal wiring schemes require a large lateral area on the light-emitting surface of the light-emitting chip to arrange electrodes, resulting in a compression of the effective light-emitting area. In contrast, this embodiment of the invention utilizes the first groove K3 to embed the second electrode 82 into the epitaxial layer 10, extending the electrode structure vertically. This ensures sufficient contact area between the second electrode 82 and the first semiconductor layer 11, guaranteeing good ohmic contact and uniform current injection efficiency, while significantly reducing the lateral space occupied by the second electrode 82 on the light-emitting surface. Consequently, the actual light-emitting area of ​​the light-emitting stage 100 is significantly increased within the same pixel size. This effectively alleviates the encroachment of electrode wiring on the light-emitting area, improving the aperture ratio and brightness output.

[0050] Based on the above embodiments, Figure 6 This is a top view of the second surface of a light-emitting chip provided in an embodiment of the present invention. Figure 6 A cross-sectional view of the structure shown along line AA1 can be found in [reference needed]. Figure 5 ,refer to Figure 6 and combined Figure 5 Optionally, the orthographic projection of the second electrode 82 on the first surface S11 is located on opposite sides of the light-emitting stage.

[0051] In this embodiment of the invention, the second electrode 82 injects current into the interior of the stage from both sides of the light-emitting stage, forming a symmetrical transverse current path. This effectively avoids the problems of current congestion and excessively high local current density that are easily caused by the single-sided electrode arrangement, thereby significantly improving the recombination uniformity of charge carriers and the uniformity of light emission in the active region.

[0052] Based on the above embodiments, Figure 7 This is a top view of the second surface of a light-emitting chip provided in an embodiment of the present invention. Figure 7 A cross-sectional view of the structure shown along line BB1 ​​can be found in [reference needed]. Figure 5 ,refer to Figure 7 and combined Figure 5 Optionally, the orthographic projection of the second electrode 82 on the first surface S11 is arranged around the light-emitting stage 100.

[0053] Specifically, by arranging the second electrode 82 in a ring around the light-emitting stage 100, the current injected from the second electrode 82 can diffuse evenly from the periphery of the light-emitting stage 100 to the central region, further effectively avoiding the current congestion and local heat generation problems that are easily caused by the traditional single-sided electrode layout, thereby improving the uniformity of current distribution and luminous efficiency of the light-emitting stage 100; at the same time, this surrounding layout can ensure that the light emitted by the light-emitting stage 100 is not blocked by the second electrode 82 on the second surface S12, which is beneficial to improving the aperture ratio and brightness output of the chip.

[0054] Optional, see reference Figure 6 and Figure 7 The epitaxial layer 10 may include multiple planar light-emitting stages 100; the second electrode 82 is the common electrode of the multiple light-emitting stages 100. Specifically, the second electrode 82 is located in the first groove K3 of the second surface S12 of the epitaxial layer 10 and is electrically connected to the first semiconductor layer 11 (such as an N-type layer), and the multiple light-emitting stages 100 share one second electrode 82.

[0055] refer to Figure 6 The second electrode 82 has a ladder-shaped structure and includes multiple electrode strips extending along the first direction X and arranged along the second direction Y, and two electrode strips extending along the second direction Y. Each electrode strip extending along the first direction X has its two ends electrically connected to an electrode strip extending along the second direction Y. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular to each other.

[0056] refer to Figure 7 The second electrode 82 has a mesh structure and includes a plurality of electrode strips extending along the first direction X and arranged along the second direction Y, as well as a plurality of electrode strips extending along the second direction Y and arranged along the first direction X.

[0057] Specifically, by setting the second electrode 82 as a mesh or ladder structure and using it as the common electrode for multiple light-emitting stages 100, on the one hand, the area occupied by the second electrode 82 on the light-emitting surface is significantly reduced, thereby maximizing the effective light-emitting area of ​​each light-emitting stage 100 under limited pixel spacing, improving the overall aperture ratio and brightness output; on the other hand, the mesh or ladder structure can uniformly cover the gaps between all light-emitting stages 100, providing equipotential connection and a balanced current injection path for each light-emitting stage 100, effectively suppressing brightness differences and local heat generation problems caused by uneven electrode distribution, and improving the uniformity and reliability of array light emission; in addition, setting the second electrode 82 as a mesh or ladder structure can also reduce the parasitic capacitance of the light-emitting chip, which is beneficial for realizing high frame rate micro-display devices.

[0058] Based on the above embodiments, refer to Figures 5-7 Optionally, the second surface S12 also has a second groove K4; the light-emitting chip also includes a third conductive element T3, which is located in the second groove K4 and extends toward the second reflective layer 40 until it is electrically connected to the second reflective layer 40; the third conductive element T3 is electrically connected to the second conductive element T2 through the second reflective layer 40; the third conductive element T3 is also electrically connected to the second electrode 82.

[0059] Specifically, the second surface S12 of the epitaxial layer 10 also has a second groove K4. The depth of the second groove K4 is greater than the thickness of the first semiconductor layer 11, and the first groove K3 is connected to the second groove K4. The depth of the second groove K4 can be equal to the sum of the thicknesses of the first semiconductor layer 11 and the passivation layer 30. The light-emitting chip also includes a third conductive element T3, which is disposed in the second groove K4 and extends towards the second reflective layer 40 until it is electrically connected to the second reflective layer 40, so as to form an electrical connection between the second conductive element T2 and the second reflective element T2 through the second reflective layer 40. In addition, the third conductive element T3 is also electrically connected to the second electrode 82 located in the first groove K3, so that the electrical signal of the second conductive element T2 can be transmitted to the second electrode 82 through the second reflective layer 40 and the third conductive element T3.

[0060] In this embodiment of the invention, since the second electrode 82 and the second reflective layer 40 are connected at the same potential through the third conductive element T3, the second reflective layer 40 can receive the same voltage signal as the second electrode 82, thereby making the sidewall reflective layer and the second electrode 82 at the same potential. The first electrode 81 can be the anode of the light-emitting chip, and the second electrode 82 can be the cathode of the light-emitting chip. The cathode is electrically connected to the second reflective layer 40, so a low potential is formed in the second reflective layer 40. Then, the electric field effect is used to make the electrons in the quantum well layer 13 move away from the etching edge position, thereby reducing the nonradiative recombination probability of electrons at the etching edge in the defect.

[0061] Figure 6 and Figure 7 The structures shown all demonstrate that the end of the outermost electrode strip extending along the second direction Y contacts the third conductive element T3 to achieve electrical connection. In other embodiments of the invention, Figure 8 This is a top view of the second surface of another light-emitting chip provided in an embodiment of the present invention. Figure 8 A cross-sectional view of the structure shown along line CC1 can be found in [reference needed]. Figure 5 ,refer to Figure 8 and combined Figure 5 The outermost electrode strip extending along the second direction Y is electrically connected to multiple third conductive elements T3 along its extension path, thereby further improving the uniformity of the potential on the second electrode 82.

[0062] In some other embodiments of the invention, optionally, the outermost electrode strip extending along the first direction X may be electrically connected to at least one third conductive element T3.

[0063] By placing the third conductive element T3 in the edge region of the second surface metal layer, it is possible to prevent the number of light-emitting stages 100 in the light-emitting chip from being affected when the third conductive element T3 is placed in the inner region.

[0064] Based on the above embodiments, refer to Figure 5 Optionally, the light-emitting chip also includes a driving substrate 70, which may be located on the side of the planarization layer 60 away from the epitaxial layer 10. The driving substrate 70 includes a first driving electrode 71 and a second driving electrode 72, which are exposed on the surface of the driving substrate 70 near the planarization layer 60.

[0065] The first driving electrode 71 is electrically connected to the first conductive element T1 to transmit a first driving voltage to the first electrode 81 of the light-emitting chip through the first conductive element T1. The second driving electrode 72 is electrically connected to the second conductive element T2. The second conductive element T2, the second reflective layer 40, and the third conductive element T3 form an electrical bridge between the second electrode 82 and the driving substrate 70 in the vertical direction to transmit a second driving voltage to the second electrode 82 of the light-emitting chip through the second conductive element T2, the second reflective layer 40, and the third conductive element T3, thereby driving the light-emitting chip to emit light.

[0066] This embodiment achieves a vertical power supply architecture for the light-emitting chip by placing the driving substrate 70 on one side of the planarization layer 60 and perpendicularly connecting the first driving electrode 71 and the second driving electrode 72 to the first conductive element T1 and the second conductive element T2, respectively. Simultaneously, a complete electrical bridge is constructed vertically from the driving substrate 70 to the second electrode 82 using the second conductive element T2, the second reflective layer 40, and the third conductive element T3. Compared to traditional solutions that require wiring to run around the chip's side or surface, this structure transfers all electrical connections to the vertical direction, significantly reducing the lateral area occupied by the light-emitting surface, thereby maintaining a higher aperture ratio and brightness output even with a small pixel pitch.

[0067] Further reference Figure 5 The orthographic projection of the third conductive element T3 on the first surface S11 at least partially overlaps with the orthographic projection of the second conductive element T2 on the first surface S11. By making the orthographic projection of the third conductive element T3 on the first surface S11 at least partially overlap with the orthographic projection of the second conductive element T2 on the first surface S11, the vertical alignment and interconnection of the second conductive element T2 and the third conductive element T3 are achieved. This overlapping design effectively shortens the lateral transmission distance of current from the second conductive element T2 through the second reflective layer 40 to the third conductive element T3, reducing parasitic resistance and power loss; at the same time, it helps to reduce the lateral space occupied by the chip, thereby further reducing the spacing between the light-emitting stages 100 and increasing the pixel density.

[0068] This invention also provides a method for fabricating a light-emitting chip, used to prepare the light-emitting chip described in any embodiment of this invention. Figure 9 This is a flowchart of another method for fabricating a light-emitting chip provided in an embodiment of the present invention, see reference. Figure 9 The methods for fabricating light-emitting chips include: S110. An epitaxial layer is formed, the epitaxial layer including a first surface and a second surface disposed opposite to each other, and the first surface has at least one light-emitting stage protruding toward the side opposite to the second surface.

[0069] S120. A first reflective layer is formed on the top surface of the light-emitting stage. The first reflective layer is used to reflect the light emitted by the light-emitting stage. The top surface of the light-emitting stage is located on one side of the back surface of the light-emitting chip.

[0070] S130. A passivation layer is formed on the sidewall of the light-emitting stage, the surface of the first reflective layer opposite to the light-emitting stage, and the area outside the light-emitting stage in the first surface.

[0071] S140. A second reflective layer is formed on the side of the passivation layer away from the epitaxial layer, and the second reflective layer above the passivation layer on the top surface of the light-emitting stage is ground to form an opening in the second reflective layer, the opening exposing the passivation layer on the top surface of the light-emitting stage; wherein, the polished surface of the portion of the second reflective layer located on the side wall of the light-emitting stage is coplanar with the upper surface of the portion of the passivation layer located on the top surface of the light-emitting stage.

[0072] The method for fabricating a light-emitting chip provided by this invention improves the light extraction efficiency of the light-emitting chip by setting a first reflective layer 20 on the top surface of the light-emitting stage 100 and a second reflective layer 40 on the sidewall of the light-emitting stage 100. Furthermore, the second reflective layer 40 has an opening that exposes the passivation layer 30 located on the top surface of the light-emitting stage 100. The polished surface of the portion of the second reflective layer 40 located on the sidewall of the light-emitting stage 100 is coplanar with the upper surface of the portion of the passivation layer 30 located on the top surface of the light-emitting stage 100. This means that the second reflective layer 40 on the top surface of the light-emitting stage 100 is directly removed by a chemical mechanical polishing process. This results in the second reflective layer 40 on the sidewall of the light-emitting stage 100 forming a coplanar structure with the top passivation layer 30 after chemical mechanical polishing. While ensuring the isolation between the sidewall second reflective layer 40 and the top surface first reflective layer 20, this method completely avoids the problem of reduced etching window size due to insufficient overlay precision. Simultaneously, the flat top surface facilitates uniform coverage of subsequent film layers, significantly improving the manufacturability and integration yield of small-sized micro-display devices.

[0073] Figure 10 This is a flowchart of another method for fabricating a light-emitting chip provided in an embodiment of the present invention, see reference. Figure 10 The methods for fabricating light-emitting chips include: S210, provides a substrate.

[0074] S220. An initial epitaxial layer is formed on one side of the substrate; the initial epitaxial layer includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer, which are sequentially located away from the substrate.

[0075] For details, please refer to Figure 11 An initial epitaxial layer 101 is formed by sequentially epitaxially forming a first semiconductor layer 11, a quantum well layer 13, and a second semiconductor layer 12 on one side of a substrate 01. The first semiconductor layer 11 and the second semiconductor layer 12 have different conductivity types. The first semiconductor layer 11 can be an N-type semiconductor layer, and the second semiconductor layer 12 can be a P-type semiconductor layer. Alternatively, the first semiconductor layer 11 can be a P-type semiconductor layer, and the second semiconductor layer 12 can be an N-type semiconductor layer.

[0076] S230. An initial first reflective layer is formed on the surface of the initial epitaxial layer away from the substrate.

[0077] For details, please refer to Figure 12Before etching the initial epitaxial layer 101 to form the light-emitting stage 100, an initial first reflective layer 201 can be formed on the surface of the initial epitaxial layer 101 away from the substrate 01. This allows the initial first reflective layer 201 and the initial epitaxial layer 101 to be patterned based on the same mask layer, thereby forming the light-emitting stage 100 and the first reflective layer 20 on the top surface of the light-emitting stage 100. The material of the first reflective layer 20 includes a metallic material.

[0078] Further reference Figure 12 When the first semiconductor layer 11 is an N-type semiconductor layer and the second semiconductor layer 12 is a P-type semiconductor layer, an initial current spreading layer 501 can be formed on the surface of the initial epitaxial layer 101 away from the substrate 01 before the initial first reflective layer 201 is formed on the surface of the initial epitaxial layer 101 away from the substrate 01, so that the current spreading layer 50 can be formed on the top surface of the light-emitting stage 100 after the subsequent patterning step.

[0079] S240. Based on the first mask layer, pattern the initial first reflective layer to form the first reflective layer.

[0080] S250. Based on the first mask layer, the second semiconductor layer and the quantum well layer are patterned sequentially to form at least one light-emitting stage.

[0081] For details, please refer to Figure 13 A first mask layer F is formed on the side of the initial first reflective layer 201 away from the substrate 01. The first mask layer F is located in the region where the initial epitaxial layer 101 and the initial first reflective layer 201 need to be retained. The material of the first mask layer F can be photoresist. (Reference) Figure 14 Based on the first mask layer F, the initial first reflective layer 201 is patterned to form the first reflective layer 20. Then, based on the first mask layer F, the second semiconductor layer 12 and the quantum well layer 13 are patterned sequentially to form at least one light-emitting stage 100. After the light-emitting stage 100 is formed, the first mask layer F is removed.

[0082] S260. A passivation layer is formed on the sidewall of the light-emitting stage, the surface of the first reflective layer opposite to the light-emitting stage, and the area of ​​the first surface not covered by the light-emitting stage.

[0083] S270, A second reflective layer is formed on the side of the passivation layer away from the epitaxial layer.

[0084] For details, please refer to Figure 15 A passivation layer 30 is formed on the sidewall of the light-emitting stage 100, the surface of the first reflective layer 20 facing away from the light-emitting stage 100, and the area of ​​the first surface S11 not covered by the light-emitting stage 100; a second reflective layer 40 is formed on the side of the passivation layer 30 away from the epitaxial layer 10. The material of the passivation layer 30 can be SiO2, and the material of the second reflective layer 40 can be a metallic material, such as Al.

[0085] S280. Grind the second reflective layer above the passivation layer on the top surface of the light-emitting stage to form an opening in the second reflective layer, the opening exposing the passivation layer on the top surface of the light-emitting stage; wherein the polished surface of the portion of the second reflective layer located on the side wall of the light-emitting stage is coplanar with the upper surface of the portion of the passivation layer located on the top surface of the light-emitting stage.

[0086] For details, please refer to Figure 16 After the passivation layer 30 and the second reflective layer 40 are deposited sequentially, the second reflective layer 40, located above the passivation layer 30 on the top surface of the light-emitting stage 100, is polished using a chemical mechanical polishing (CMP) process. Because the top of the light-emitting stage 100 is convex, the second reflective layer 40 in the convex area is preferentially removed during CMP polishing of the entire surface until the passivation layer 30 on the top of the light-emitting stage 100 is exposed. This allows the upper surface of the second reflective layer 40 on the sidewall of the light-emitting stage 100 to be polished flush with the exposed upper surface of the passivation layer 30. In this way, the opening is naturally formed without the need for additional photolithography masks and etching steps, completely avoiding the problems of top metal residue or sidewall metal protrusions caused by insufficient overlay precision. Simultaneously, sufficient lateral space is released on the top surface of the light-emitting stage 100 for subsequent electrode connections.

[0087] In this embodiment of the invention, the specific steps for forming the epitaxial layer 10 include: providing a substrate 01; forming an initial epitaxial layer 101 on one side of the substrate 01; the initial epitaxial layer 101 includes a first semiconductor layer 11, a quantum well layer 13, and a second semiconductor layer 12 sequentially away from the substrate 01; and patterning the second semiconductor layer 12 and the quantum well layer 13 sequentially based on a first mask layer F to form at least one light-emitting stage 100. The specific steps for forming a first reflective layer 20 on the top surface of the light-emitting stage 100 include: forming an initial first reflective layer 201 on the surface of the initial epitaxial layer 101 away from the substrate 01; and patterning the initial first reflective layer 201 based on the first mask layer F to form the first reflective layer 20. This is achieved by using the same first mask layer F to sequentially pattern the first reflective layer 20, the second semiconductor layer 12, and the quantum well layer 13 when forming the epitaxial layer 10 and the first reflective layer 20. This self-alignment process based on the same mask layer enables the first reflective layer 20 to automatically align with the top of the light-emitting stage 100, eliminating the need for a separate photolithography mask, simplifying the manufacturing process and reducing costs.

[0088] Furthermore, since the area between the light-emitting stages 100 does not require patterning, global processes such as full-area evaporation or full-area etching can be used, thus maintaining the spacing between adjacent light-emitting stages within a very small range. Especially in chips with small pixel pitches (e.g., 2.5 μm), the process of this invention allows the stage size to remain around 2 μm, thereby achieving a duty cycle of over 60% (i.e., the ratio of the stage area to the total pixel area). This significantly improves the area utilization of the light-emitting region, which is beneficial for achieving higher brightness and better light extraction efficiency in small-size micro-display devices.

[0089] Furthermore, a second reflective layer 40 is formed on the side of the passivation layer 30 away from the epitaxial layer 10, and the second reflective layer 40 above the passivation layer 30 on the top surface of the light-emitting stage 100 is ground to form an opening in the second reflective layer 40, and the process further includes: S290, a planarization layer 60 is formed. The planarization layer 60 is disposed on the side of the second reflective layer 40 away from the epitaxial layer 10 and covers the passivation layer 30 on the top surface of the light-emitting stage 100 exposed by the opening. Specifically, refer to... Figure 17 The planarization layer 60 can be made of organic materials (such as polyimide, benzocyclobutene) or inorganic materials (such as silicon dioxide, silicon nitride), and is formed by spin coating, deposition and chemical mechanical polishing processes. Its function is to form an integrally flat upper plane on the chip surface with protrusions and depressions, providing a good foundation for subsequent fabrication processes.

[0090] S2100, forming a first conductive element T1 and a second conductive element T2; the first conductive element T1 sequentially penetrates the planarization layer 60 and the passivation layer 30 to be electrically connected to the first reflective layer 20, and the second conductive element T2 penetrates the planarization layer 60 to be electrically connected to the second reflective layer 40. (Reference) Figure 18 and Figure 19 A first opening K1 and a second opening K2 are formed in the planarization layer 60. The first opening K1 exposes the first reflective layer 20, and the second opening K2 exposes the second reflective layer 40. After depositing a metal material, chemical mechanical polishing is performed to form a first conductive element T1 in the first opening K1 and a second conductive element T2 in the second opening K2. The first conductive element T1 is electrically connected to the second semiconductor layer 12 through the first reflective layer 20.

[0091] S2110. A driving substrate 70 is provided, the driving substrate 70 including a first driving electrode 71 and a second driving electrode 72; and the driving substrate 70 is bonded to the side of the planarization layer 60 away from the epitaxial layer 10, so that the first driving electrode 71 is electrically connected to the first conductive element T1, and the second driving electrode 72 is electrically connected to the second conductive element T2. (Reference) Figure 20 ) S2120, Remove substrate 01 to expose the second surface S12 of epitaxial layer 10. (Reference) Figure 21 ) S2130, a first groove K3 and a second groove K4 are formed on the second surface S12. For details, refer to... Figure 22 The second surface S12 of the epitaxial layer 10 can be etched using an etching process to form a first groove K3 and a second groove K4. The first groove K3 and the second groove K4 can be connected.

[0092] S2140: A second electrode 82 is formed in the first groove K3, and the second electrode 82 is electrically connected to the first semiconductor layer 11; and a third conductive element T3 is formed in the second groove K4, the third conductive element T3 is electrically connected to the second electrode 82, and the third conductive element T3 extends towards the second reflective layer 40 until it is electrically connected to the second reflective layer 40, so as to be electrically connected to the second conductive element T2 through the second reflective layer 40. Specifically, refer to... Figure 23 and Figure 5 A metal material is deposited on the side of the first semiconductor layer 11 away from the driving substrate 70 to form an electrode layer 90. The electrode layer 90 is chemically and mechanically polished to remove the electrode layer 90 located on the second surface S12. The electrode layer 90 retained in the first groove K3 forms the second electrode 82, and the electrode layer 90 retained in the second groove K4 forms the third conductive element T3.

[0093] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A light-emitting chip, characterized in that, include: The epitaxial layer includes a first surface and a second surface disposed opposite to each other, and the first surface has at least one light-emitting stage protruding away from the second surface; A first reflective layer is disposed on the top surface of the light-emitting stage and is used to reflect the light emitted by the light-emitting stage; wherein, the top surface of the light-emitting stage is located on one side of the backlight surface of the light-emitting chip; A passivation layer is formed on the sidewall of the light-emitting stage, the surface of the first reflective layer away from the light-emitting stage, and the first surface outside the area where the light-emitting stage is located; A second reflective layer is disposed on the side of the passivation layer away from the epitaxial layer, and the second reflective layer has an opening that exposes the passivation layer located on the top surface of the light-emitting stage; wherein, the polished surface of the portion of the second reflective layer located on the sidewall of the light-emitting stage is coplanar with the upper surface of the portion of the passivation layer located on the top surface of the light-emitting stage.

2. The light-emitting chip according to claim 1, characterized in that, Also includes: A first conductive element penetrates the passivation layer and is electrically connected to the first reflective layer; wherein, the material of the first reflective layer is a conductive material, and the first reflective layer is reused as the first electrode of the light-emitting chip; And / or, a second conductive element is electrically connected to the second reflective layer; wherein the material of the second reflective layer is a conductive material.

3. The light-emitting chip according to claim 2, characterized in that, Also includes: A planarization layer is disposed on the side of the second reflective layer away from the epitaxial layer and covers the passivation layer on the top surface of the light-emitting stage exposed by the opening; The first conductive element passes through the planarization layer and the passivation layer in sequence to be electrically connected to the first reflective layer; the second conductive element passes through the planarization layer to be electrically connected to the second reflective layer.

4. The light-emitting chip according to claim 2, characterized in that, The second surface has a first groove; The light-emitting chip further includes a second electrode, which is located in the first groove; The epitaxial layer includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer stacked sequentially; the light-emitting stage includes at least the quantum well layer and the second semiconductor layer; the second surface is the surface of the first semiconductor layer away from the light-emitting stage; the first conductive element is electrically connected to the second semiconductor layer through the first reflective layer; and the second electrode is electrically connected to the first semiconductor layer.

5. The light-emitting chip according to claim 4, characterized in that, The orthographic projection of the second electrode on the first surface is arranged around the light-emitting stage; Alternatively, the orthographic projection of the second electrode onto the first surface is located on opposite sides of the light-emitting stage.

6. The light-emitting chip according to claim 4, characterized in that, The epitaxial layer includes multiple planarly arranged light-emitting platforms; The second electrode is a common electrode of the plurality of light-emitting stages; the second electrode has a mesh structure or a ladder structure.

7. The light-emitting chip according to claim 4, characterized in that, The second surface also has a second groove; The light-emitting chip further includes a third conductive element, which is located in the second groove and extends toward the second reflective layer until it is electrically connected to the second reflective layer; the third conductive element is electrically connected to the second conductive element through the second reflective layer; the third conductive element is also electrically connected to the second electrode.

8. The light-emitting chip according to claim 7, characterized in that, The orthographic projection of the third conductive element on the first surface at least partially overlaps with the orthographic projection of the second conductive element on the first surface.

9. The light-emitting chip according to any one of claims 2 to 8, characterized in that, Also includes: The driving substrate is located on the side of the planarization layer away from the epitaxial layer; The driving substrate includes a first driving electrode and a second driving electrode, the first driving electrode and the second driving electrode being exposed on the surface of the driving substrate near the planarization layer; wherein, the first driving electrode is electrically connected to the first conductive element, and the second driving electrode is electrically connected to the second conductive element.

10. A method for fabricating a light-emitting chip, characterized in that, For preparing the light-emitting chip according to any one of claims 1 to 9, comprising: An epitaxial layer is formed, the epitaxial layer including a first surface and a second surface disposed opposite to each other, and the first surface having at least one light-emitting stage protruding toward the side opposite to the second surface; A first reflective layer is formed on the top surface of the light-emitting stage, the first reflective layer being used to reflect the light emitted by the light-emitting stage; wherein, the top surface of the light-emitting stage is located on one side of the backlight surface of the light-emitting chip; A passivation layer is formed on the sidewall of the light-emitting stage, the surface of the first reflective layer opposite to the light-emitting stage, and the area of ​​the first surface outside the light-emitting stage. A second reflective layer is formed on the side of the passivation layer away from the epitaxial layer, and the second reflective layer above the passivation layer on the top surface of the light-emitting stage is ground to form an opening in the second reflective layer that exposes the passivation layer on the top surface of the light-emitting stage; wherein the polished surface of the portion of the second reflective layer located on the sidewall of the light-emitting stage is coplanar with the upper surface of the portion of the passivation layer located on the top surface of the light-emitting stage.

11. The method for preparing a light-emitting chip according to claim 10, characterized in that, The formation of the epitaxial layer includes: Provide substrate; An initial epitaxial layer is formed on one side of the substrate; the initial epitaxial layer includes a first semiconductor layer, a quantum well layer, and a second semiconductor layer sequentially away from the substrate; Based on the first mask layer, the second semiconductor layer and the quantum well layer are patterned sequentially to form at least one light-emitting stage.

12. The method for preparing a light-emitting chip according to claim 11, characterized in that, The formation of a first reflective layer on the top surface of the light-emitting stage includes: An initial first reflective layer is formed on the surface of the initial epitaxial layer away from the substrate; Based on the first mask layer, the initial first reflective layer is patterned to form the first reflective layer.

13. The method for preparing a light-emitting chip according to claim 11, characterized in that, After forming a second reflective layer on the side of the passivation layer away from the epitaxial layer, and grinding the second reflective layer above the passivation layer on the top surface of the light-emitting stage to form an opening in the second reflective layer, the method further includes: A planarization layer is formed, which is disposed on the side of the second reflective layer away from the epitaxial layer and covers the passivation layer on the top surface of the light-emitting stage exposed by the opening; A first conductive element and a second conductive element are formed; the first conductive element passes through the planarization layer and the passivation layer in sequence to be electrically connected to the first reflective layer, and the second conductive element passes through the planarization layer to be electrically connected to the second reflective layer.

14. The method for preparing a light-emitting chip according to claim 13, characterized in that, After forming the first conductive element and the second conductive element, the process also includes: A driving substrate is provided, the driving substrate including a first driving electrode and a second driving electrode; The driving substrate is bonded to the planarization layer on the side away from the epitaxial layer, so that the first driving electrode is electrically connected to the first conductive element and the second driving electrode is electrically connected to the second conductive element. Remove the substrate to expose the second surface of the epitaxial layer; A first groove is formed on the second surface, and a second electrode is formed in the first groove; wherein, the epitaxial layer includes a first semiconductor layer, a quantum well layer and a second semiconductor layer stacked sequentially; the light-emitting stage includes at least the quantum well layer and the second semiconductor layer; the second surface is the surface of the first semiconductor layer facing away from the light-emitting stage; the first conductive element is electrically connected to the second semiconductor layer through the first reflective layer, and the second electrode is electrically connected to the first semiconductor layer.

15. The method for preparing a light-emitting chip according to claim 14, characterized in that, Also includes: A second groove is formed on the second surface; A third conductive element is formed in the second groove; The third conductive element is electrically connected to the second electrode, and the third conductive element extends toward the second reflective layer until it is electrically connected to the second reflective layer, so as to be electrically connected to the second conductive element through the second reflective layer.

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