A flip-chip light-emitting diode and its fabrication method

Abstract

This invention provides a flip-chip light-emitting diode (LED) and its fabrication method. The flip-chip includes a substrate; a semiconductor layer sequence located on the substrate, having a mesa; a metal reflective layer; and an electric field modulation structure disposed between the edge of the mesa and the edge of the metal reflective layer, comprising a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer stacked sequentially from bottom to top. The thickness of the third insulating layer is greater than the thickness of the second insulating layer, and the thickness of the second insulating layer is greater than the thickness of the first insulating layer. The width of the first metal layer is greater than the width of the second metal layer, and the projection centers of the second metal layer and the first metal layer coincide. The two opposite edges of the first metal layer in its width direction have equal horizontal distances from the edge of the metal reflective layer and the edge of the mesa, respectively, significantly improving the chip's ESD resistance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a flip-chip light-emitting diode and its fabrication method. Background Technology

[0002] Flip-chip LEDs are widely used in automotive lighting, displays, and other lighting applications due to their advantages such as excellent heat dissipation, high light extraction efficiency, and high packaging density. In particular, automotive-grade LED chips have extremely high requirements for reliability and anti-static capabilities, typically needing to meet an electrostatic discharge (ESD) withstand voltage of 6kV or higher in human body discharge mode (HBM).

[0003] In the production, testing, and application of flip-chip LEDs, ESD is one of the main causes of chip failure. Extensive failure analysis has revealed a significant concentration of ESD failures in flip-chip LEDs: failure points are concentrated in the region between the mesa edge and the edge of the metal reflective layer. The core cause of failure in this region is its inherent electric field concentration effect—during ESD testing, high-voltage pulses preferentially create current concentration in the edge region where the electric field is strongest, leading to localized avalanche breakdown or Joule thermal damage, becoming the "breakthrough point" for electrostatic discharge, severely reducing the chip's ESD resistance and reliability. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a flip-chip light-emitting diode and its fabrication method, thereby resolving the technical issues described in the background section.

[0005] On the one hand, the invention provides the following technical solution: a flip-chip light-emitting diode, comprising: Substrate; A semiconductor sequence, located on the substrate, having a mesa exposing the semiconductor sequence; A metal reflective layer is located on the semiconductor sequence; An electric field control structure is provided in the region between the edge of the tabletop and the edge of the metal reflective layer. The electric field control structure includes a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer stacked sequentially from bottom to top. Wherein, the thickness of the third insulating layer is greater than the thickness of the second insulating layer, and the thickness of the second insulating layer is greater than the thickness of the first insulating layer; The width of the first metal layer is greater than the width of the second metal layer, and the projection center of the second metal layer on the first metal layer coincides with the projection center of the first metal layer; The two opposite edges of the first metal layer in its width direction have equal horizontal distances from the edge of the metal reflective layer and the edge of the platform, respectively.

[0006] Compared with existing technologies, the beneficial effects of this invention are as follows: By setting an electric field modulation structure in the electric field concentration region between the edge of the mesa and the edge of the metal reflective layer, and utilizing the stacked cooperation of a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer, the electric field is dispersed across multiple regions. Specifically, by making the thickness of the third insulating layer greater than the thickness of the second insulating layer, and the thickness of the second insulating layer greater than the thickness of the first insulating layer, the electric field intensity at each metal layer is gradually weakened based on the principle that the thickness of the insulating layer is inversely proportional to the electric field strength. Furthermore, by making the width of the first metal layer greater than the width of the second metal layer, and ensuring that their projection centers coincide and are equidistant from the two side edges, a symmetrical stepped voltage-dividing structure is formed. The synergistic effect of these structures decomposes the strong electric field originally concentrated at the edge of the mesa and the edge of the metal reflective layer into a multi-level, gradually attenuating electric field distribution, effectively avoiding excessive concentration of the electric field at a single location. This fundamentally suppresses local avalanche breakdown and Joule thermal damage caused by ESD high voltage, significantly improving the chip's ESD resistance.

[0007] Furthermore, it also includes N-type pads, which are electrically connected to the portion of the semiconductor layer exposed by the mesa; The electric field control structure has a through hole, which is filled with a connecting metal layer. The first metal layer, the second metal layer, and the semiconductor layer sequence exposed on the mesa are electrically connected to the N-type pad through the connecting metal layer.

[0008] Furthermore, it also includes P-type pads and a fourth insulating layer; The connecting metal layer includes a P-type connecting metal layer and an N-type connecting metal layer. The P-type connecting metal layer is connected to the metal reflective layer through a through-hole penetrating the electric field control structure. The fourth insulating layer covers the connecting metal layer and has an opening. The P-type pad is connected to the P-type connecting metal layer through the opening, and the N-type pad is connected to the N-type connecting metal layer through the opening.

[0009] Furthermore, the equal horizontal distance is 2-3 micrometers; the width of the first metal layer is 8-10 micrometers, and the width of the second metal layer is 4-6 micrometers.

[0010] Furthermore, the thickness of the third insulating layer is 12,000-15,000 angstroms, the thickness of the second insulating layer is 10,000-12,000 angstroms, and the thickness of the first insulating layer is 8,000-10,000 angstroms.

[0011] Furthermore, the first metal layer and the second metal layer have the same thickness and are both composed of a Ni layer, an Au layer and a Ti layer from bottom to top, wherein the thickness of the Ni layer is 1000-2000 angstroms, the thickness of the Au layer is 2000-5000 angstroms, and the thickness of the Ti layer is 30-50 angstroms; the first insulating layer includes an Al2O3 film and a SiO2 film from bottom to top, and the second insulating layer and the third insulating layer are both SiO2 films.

[0012] Furthermore, the semiconductor layer sequence includes, from bottom to top, an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer, with the mesa penetrating the P-type semiconductor layer and the active light-emitting layer, exposing the N-type semiconductor layer; the metal reflective layer contains Ag.

[0013] On the other hand, the present invention also proposes a method for fabricating a flip-chip light-emitting diode, the method comprising the following steps: A substrate is provided on which a semiconductor sequence is formed; The semiconductor sequence is etched to form a mesa that exposes the semiconductor sequence; A metal reflective layer is formed on the semiconductor sequence; An electric field modulation structure is formed in the region between the edge of the platform and the edge of the metal reflective layer. The electric field modulation structure includes a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer stacked sequentially from bottom to top. Wherein, the thickness of the third insulating layer is greater than the thickness of the second insulating layer, and the thickness of the second insulating layer is greater than the thickness of the first insulating layer; The width of the first metal layer is greater than the width of the second metal layer, and the projection center of the second metal layer on the first metal layer coincides with the projection center of the first metal layer; The two opposite edges of the first metal layer in its width direction have equal horizontal distances from the edge of the metal reflective layer and the edge of the platform, respectively.

[0014] Furthermore, depositing the first insulating layer includes: depositing an Al2O3 film with a thickness of 500-1000 angstroms using an atomic layer deposition process, and then depositing a SiO2 film with a thickness of 7500-9000 angstroms using a plasma-enhanced chemical vapor deposition process. Both the second insulating layer and the third insulating layer are formed by depositing SiO2 thin films using plasma-enhanced chemical vapor deposition.

[0015] Furthermore, forming both the first metal layer and the second metal layer includes: sequentially depositing a Ni layer, an Au layer, and a Ti layer, wherein the thickness of the Ni layer is 1000-2000 angstroms, the thickness of the Au layer is 2000-5000 angstroms, and the thickness of the Ti layer is 30-50 angstroms. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the flip-chip light-emitting diode in the first embodiment of the present invention; Figure 2 This is a schematic diagram of the structure corresponding to step S01 in the second embodiment of the present invention; Figure 3 This is a schematic diagram of the structure corresponding to step S02 in the second embodiment of the present invention; Figure 4 This is a schematic diagram of the structure corresponding to step S03-1 in the second embodiment of the present invention; Figure 5 This is a schematic diagram of the structure corresponding to step S03-2 in the second embodiment of the present invention; Figure 6 This is a schematic diagram of the structure corresponding to step S03-3 in the second embodiment of the present invention; Figure 7 This is a schematic diagram of the structure corresponding to steps S03-4 in the second embodiment of the present invention; Figure 8 This is a schematic diagram of the structure corresponding to steps S03-5 in the second embodiment of the present invention; Figure 9 This is a schematic diagram of the structure corresponding to steps S04-1 to S04-3 in the second embodiment of the present invention; Figure 10 This is a schematic diagram of the structure corresponding to step S04-4 in the second embodiment of the present invention.

[0017] Key component symbols: 10. Substrate; 11. Semiconductor layer sequence; 111. N-type semiconductor layer; 112. Active light-emitting layer; 113. P-type semiconductor layer; 114. Mesa; 12. Metal reflective layer; 13. First insulating layer; 14. First metal layer; 15. Second insulating layer; 16. Second metal layer; 17. Third insulating layer; 18. Connecting metal layer; 181. P-type connecting metal layer; 182. N-type connecting metal layer; 19. Fourth insulating layer; 20. P-type pad; 21. N-type pad.

[0018] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0019] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0020] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] Example 1 Please see Figure 1 The image shows a flip-chip light-emitting diode (LED) according to the first embodiment of the present invention, comprising: Substrate 10; Semiconductor sequence 11, located on substrate 10, has a mesa 114 exposing semiconductor sequence 11; Metal reflective layer 12 is located on semiconductor layer 11; An electric field control structure is provided in the area between the edge of the tabletop 114 and the edge of the metal reflective layer 12. The electric field control structure includes a first insulating layer 13, a first metal layer 14, a second insulating layer 15, a second metal layer 16 and a third insulating layer 17 stacked sequentially from bottom to top. The thickness of the third insulating layer 17 is greater than the thickness of the second insulating layer 15, and the thickness of the second insulating layer 15 is greater than the thickness of the first insulating layer 13. The width of the first metal layer 14 is greater than the width of the second metal layer 16, and the projection center of the second metal layer 16 on the first metal layer 14 coincides with the projection center of the first metal layer 14. The two opposite edges of the first metal layer 14 in its width direction have equal horizontal distances from the edge of the metal reflective layer 12 and the edge of the platform 114, respectively.

[0023] It is worth noting that by setting an electric field control structure in the electric field concentration region between the edge of the platform 114 and the edge of the metal reflective layer 12, and utilizing the stacked arrangement of the first insulating layer 13, the first metal layer 14, the second insulating layer 15, the second metal layer 16, and the third insulating layer 17, the electric field is distributed in multiple regions. Specifically, by making the thickness of the third insulating layer 17 greater than the thickness of the second insulating layer 15, and the thickness of the second insulating layer 15 greater than the thickness of the first insulating layer 13, the electric field intensity at each metal layer is gradually weakened by utilizing the principle that the thickness of the insulating layer is inversely proportional to the electric field strength. By making the width of the first metal layer 14 greater than the width of the second metal layer 16, and by having their projection centers coincide and be equidistant from the two side edges, a symmetrical stepped voltage distribution structure is formed. The synergistic effect of the above structures decomposes the strong electric field originally concentrated at the edge of the mesa 114 and the edge of the metal reflective layer 12 into a multi-level gradually decaying electric field distribution, effectively avoiding excessive concentration of the electric field at a single location, fundamentally suppressing local avalanche breakdown and Joule thermal damage caused by ESD high voltage, and significantly improving the chip's ESD resistance.

[0024] The substrate 10 can be made of commonly used substrate materials in the art, such as sapphire substrate, silicon carbide substrate, or silicon substrate. In this embodiment, the substrate 10 is a sapphire substrate.

[0025] Semiconductor sequence 11 is located on substrate 10 and has a mesa 114 exposing the semiconductor sequence 11. Semiconductor sequence 11 includes an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113, disposed sequentially from bottom to top. The mesa 114 penetrates the P-type semiconductor layer 113 and the active light-emitting layer 112, exposing a portion of the surface of the N-type semiconductor layer 111. The materials of the N-type semiconductor layer 111 and the P-type semiconductor layer 113 can be N-type GaN and P-type GaN, respectively, and the active light-emitting layer 112 can be an InGaN / GaN multiple quantum well structure. It is understood that the above semiconductor materials are merely illustrative, and other III-V or II-VI compound semiconductor materials may also be used.

[0026] The metal reflective layer 12 is located on the semiconductor layer sequence 11, specifically on the surface of the P-type semiconductor layer 113 that is not exposed by the mesa 114. The metal reflective layer 12 contains Ag and may further include protective metal layers, such as Ni layers or TiW layers, located on the upper and lower surfaces of the Ag layer to improve the stability and adhesion of the reflective layer. The metal reflective layer 12 is used to reflect the light emitted by the chip toward the substrate 10, thereby improving the light extraction efficiency.

[0027] An electric field modulation structure is provided in the region between the edge of the platform 114 and the edge of the metal reflective layer 12. This region is precisely the concentrated area of ​​ESD failure in the prior art. By setting an electric field modulation structure here, the present invention suppresses the electric field concentration effect at its source.

[0028] The first metal layer 14 is located on the first insulating layer 13. The first metal layer 14 and the second metal layer 16 have the same thickness and material composition, both consisting of a Ni layer, an Au layer, and a Ti layer from bottom to top. The Ni layer has a thickness of 1000-2000 angstroms, the Au layer has a thickness of 2000-5000 angstroms, and the Ti layer has a thickness of 30-50 angstroms. The Ni layer serves as an adhesion and barrier layer, the Au layer as the main conductive layer, and the Ti layer as a protective layer. Both the first metal layer 14 and the second metal layer 16 can be prepared using an electron beam evaporation process combined with a lift-off process. The width of the first metal layer 14 is 8-10 micrometers.

[0029] The second insulating layer 15 covers the exposed surfaces of the first metal layer 14 and the first insulating layer 13. The second insulating layer 15 is a SiO2 thin film deposited using a PECVD process, with a thickness of 10,000-12,000 angstroms.

[0030] The second metal layer 16 is located on the second insulating layer 15. The material and thickness of the second metal layer 16 are the same as those of the first metal layer 14. The width of the second metal layer 16 is 4-6 micrometers, which is smaller than the width of the first metal layer 14.

[0031] The third insulating layer 17 covers the exposed surfaces of the second metal layer 16 and the second insulating layer 15. The third insulating layer 17 is a SiO2 thin film deposited using a PECVD process, with a thickness of 12,000-15,000 angstroms.

[0032] Therefore, the thickness relationship of the three insulating layers in the electric field control structure is as follows: the thickness of the third insulating layer 17 is greater than the thickness of the second insulating layer 15, and the thickness of the second insulating layer 15 is greater than the thickness of the first insulating layer 13. This progressively increasing thickness design is based on the principle that "the passivation layer thickness is inversely proportional to the electric field strength," which gradually weakens the electric field strength at the first metal layer 14 and the second metal layer 16, achieving a stepped voltage division effect.

[0033] In planar layout, the projection center of the second metal layer 16 onto the first metal layer 14 coincides with the projection center of the first metal layer 14, meaning the second metal layer 16 is centrally located above the first metal layer 14. The first metal layer 14 has two opposing edges in its width direction, one edge facing the metal reflective layer 12 and the other edge facing the table surface 114. Figure 1 As shown, the horizontal distance from one edge of the first metal layer 14 facing the metal reflective layer 12 to the edge of the metal reflective layer 12 is defined as L, and the horizontal distance from one edge of the first metal layer 14 facing the mesa 114 to the edge of the mesa 114 is defined as L1. Therefore, L equals L1, and this equal horizontal distance is 2-3 micrometers. This arrangement ensures that the electric field control structure is symmetrically arranged with respect to the edges of the metal reflective layer 12 and the mesa 114, guaranteeing the balance of the electric field distribution on both sides.

[0034] The chip of this invention also includes an N-type pad 21 and a P-type pad 20. The N-type pad 21 is electrically connected to the N-type semiconductor layer 111 exposed by the mesa 114 in the semiconductor layer sequence 11. Specifically, the electric field control structure has through-holes penetrating the first insulating layer 13, the second insulating layer 15, and the third insulating layer 17, and the through-holes are filled with a connecting metal layer 18. The connecting metal layer 18 includes an N-type connecting metal layer 182 and a P-type connecting metal layer 181. The N-type connecting metal layer 182 contacts the N-type semiconductor layer 111, the first metal layer 14, and the second metal layer 16 exposed by the mesa 114 through the through-holes, respectively, to achieve electrical connection among the three, and is led out by the N-type pad 21. The P-type connecting metal layer 181 contacts the metal reflective layer 12 through the through-holes penetrating the electric field control structure, and is led out by the P-type pad 20.

[0035] The connecting metal layer 18 can adopt a multi-layer metal structure, such as a multi-layer film of Cr / Al / Ti / Pt / Ti / Pt / Ti / Au / Pt / Ti stacked in sequence, to improve conductivity, adhesion and prevent diffusion.

[0036] The chip also includes a fourth insulating layer 19. The fourth insulating layer 19 covers the surface of the bonding metal layer 18 and the areas not covered by the bonding metal layer 18. The fourth insulating layer 19 is a SiO2 thin film prepared using PECVD technology, with a thickness of 5000-10000 angstroms. Openings are formed in the fourth insulating layer 19, exposing portions of the surfaces of the N-type bonding metal layer 182 and the P-type bonding metal layer 181, respectively. P-type pads 20 and N-type pads 21 are electrically connected to the P-type bonding metal layer 181 and the N-type bonding metal layer 182 through corresponding openings. The P-type pads 20 and N-type pads 21 can be made using a multilayer metal structure such as Ti / Ni / Ti / Ni / Au, prepared using electron beam evaporation and lift-off processes.

[0037] It should be noted that the aforementioned "electrical connection between the N-type connecting metal layer 182 and the first metal layer 14 and the second metal layer 16" is the preferred method for achieving multi-stage voltage reduction and depressurization. When an ESD high-voltage pulse is applied to the chip, the high voltage is applied in reverse to the N-type semiconductor layer 111 through the N-type pad 21. At the same time, the second metal layer 16 and the first metal layer 14 in the electric field control structure, being electrically connected to the N-type pad 21, become the preferred discharge channels for electrostatic discharge. Since the second metal layer 16 is located on the top layer and is closer to the direction of the incoming ESD pulse, the electrostatic high voltage is first applied to the second metal layer 16 to complete the first stage of depressurization, and then transmitted through the connecting metal layer 182 to the first metal layer 14 for the second stage of depressurization, and finally conducted to the N-type pad 21. With the progressively thicker insulation layer design, the electric field strength is weakened layer by layer, forming a stepped smooth voltage division and decompression effect. This effectively avoids excessive concentration of the electric field at a single location on the edge of the platform 114 and the edge of the metal reflective layer 12, thus preventing avalanche breakdown and Joule thermal damage caused by ESD high voltage from the root.

[0038] Example 2 A method for fabricating a flip-chip light-emitting diode according to a second embodiment of the present invention, the method comprising steps S01-S04: S01: Provide a substrate 10, form a semiconductor sequence 11 on the substrate 10; etch the semiconductor sequence 11 to form a mesa 114 exposing the semiconductor sequence 11.

[0039] See Figure 2 As shown, in this embodiment, a substrate 10 is provided. An N-type GaN layer (i.e., N-type semiconductor layer 111), an active light-emitting layer 112, and a P-type GaN layer (i.e., P-type semiconductor layer 113) are sequentially deposited on the substrate 10 using an MOCVD process to form a semiconductor layer sequence 11. Next, photoresist is coated on the surface of the P-type GaN layer, and a portion of the photoresist is removed using an exposure and development process, exposing the P-type GaN layer beneath the area to be etched. Then, an inductively coupled plasma etching process is used to remove the exposed P-type GaN layer and the underlying active light-emitting layer 112, forming a mesa 114 and exposing the N-type GaN layer. Finally, the remaining photoresist is removed.

[0040] S02: A metal reflective layer 12 is formed on the semiconductor layer sequence 11.

[0041] See Figure 3 As shown, in this embodiment, a negative photoresist is coated, and after exposure and development, part of the photoresist is removed to expose the area where the metal reflective layer 12 is to be formed. ITO, Ag metal, Ni metal and TiW metal are sputtered sequentially using a magnetron sputtering process, and then the metal and photoresist on the photoresist are removed using a lift-off process to form the metal reflective layer 12.

[0042] S03: An electric field control structure is formed in the region between the edge of the tabletop 114 and the edge of the metal reflective layer 12. The electric field control structure includes a first insulating layer 13, a first metal layer 14, a second insulating layer 15, a second metal layer 16 and a third insulating layer 17 stacked sequentially from bottom to top. The thickness of the third insulating layer 17 is greater than the thickness of the second insulating layer 15, and the thickness of the second insulating layer 15 is greater than the thickness of the first insulating layer 13. The width of the first metal layer 14 is greater than the width of the second metal layer 16, and the projection center of the second metal layer 16 on the first metal layer 14 coincides with the projection center of the first metal layer 14. The two opposite edges of the first metal layer 14 in its width direction have equal horizontal distances from the edge of the metal reflective layer 12 and the edge of the platform 114, respectively.

[0043] This step achieves electric field modulation by forming a multilayer metal-insulator stacked structure.

[0044] Specifically, in this embodiment, S03 includes the following sub-steps: S03-1: Deposit the first insulating layer 13.

[0045] See Figure 4 As shown, firstly, an Al2O3 thin film (not shown) with a thickness of 500-1000 angstroms is deposited on the surface of the metal reflective layer 12 and its uncovered areas using atomic layer deposition (ALD). Then, a SiO2 thin film (not shown) with a thickness of 7500-9000 angstroms is deposited on the surface of the Al2O3 thin film using plasma-enhanced chemical vapor deposition (PECVD). The Al2O3 and SiO2 thin films together constitute the first insulating layer 13, with a total thickness of 8000-10000 angstroms.

[0046] S03-2: A first metal layer 14 is formed on the first insulating layer 13.

[0047] See Figure 5 As shown, a negative photoresist is coated, and after exposure and development, part of the photoresist is removed, exposing the area where the first metal layer 14 will be formed. A Ni layer, an Au layer, and a Ti layer are sequentially deposited using an electron beam evaporation process, wherein the thickness of the Ni layer is 1000-2000 angstroms, the thickness of the Au layer is 2000-5000 angstroms, and the thickness of the Ti layer is 30-50 angstroms. Then, a lift-off process is used to remove the metal and photoresist on the photoresist, forming the first metal layer 14. The width of the first metal layer 14 is 8-10 micrometers. In the width direction, the horizontal distance from one edge of the first metal layer 14 to the edge of the metal reflective layer 12 is equal to the horizontal distance from the other edge to the edge of the mesa 114, both being 2-3 micrometers.

[0048] S03-3: Deposit a second insulating layer 15 covering the first metal layer 14.

[0049] See Figure 6 As shown, a SiO2 thin film with a thickness of 10,000-12,000 angstroms is deposited using plasma-enhanced chemical vapor deposition to form a second insulating layer 15, which covers the exposed surfaces of the first metal layer 14 and the first insulating layer 13.

[0050] S03-4: A second metal layer 16 is formed on the second insulating layer 15.

[0051] See Figure 7As shown, a negative photoresist is applied, and after exposure and development, part of the photoresist is removed, exposing the area where the second metal layer 16 will be formed. A Ni layer, an Au layer, and a Ti layer are sequentially deposited using an electron beam evaporation process, with the same thickness as the first metal layer 14. Then, a lift-off process is used to remove the metal and photoresist on the photoresist, forming the second metal layer 16. The width of the second metal layer 16 is 4-6 micrometers, and the projection center of the second metal layer 16 coincides with the projection center of the first metal layer 14.

[0052] S03-5: Deposit a third insulating layer 17 covering the second metal layer 16.

[0053] See Figure 8 As shown, a SiO2 thin film with a thickness of 12,000-15,000 angstroms was deposited using plasma-enhanced chemical vapor deposition to form a third insulating layer 17.

[0054] S04: Etch the electric field control structure to form vias exposing the semiconductor sequence 11, the first metal layer 14, and the second metal layer 16 on the exposed mesa 114; fill the vias with a connecting metal layer 18 so that the first metal layer 14, the second metal layer 16, and the semiconductor sequence 11 exposed on the mesa 114 are electrically connected to the subsequently formed N-type pads 21 through the connecting metal layer 18.

[0055] This step establishes electrical connections between each metal layer and the N-type pad 21, forming a multi-stage voltage reduction and relief pathway.

[0056] Specifically, in this embodiment, S04 includes the following sub-steps: S04-1: Etching through holes.

[0057] See Figure 9 As shown, photoresist is coated on the surface of the third insulating layer 17, and after exposure and development, part of the photoresist is removed. A portion of the first insulating layer 13, the second insulating layer 15, and the third insulating layer 17 located above the mesa 114 is removed using BOE etching solution, forming mesa conductive vias that expose the N-type GaN layer (i.e., the N-type semiconductor layer 111). Simultaneously, a portion of the insulating layers located above the metal reflective layer 12 is removed, forming metal reflective layer conductive vias; and vias are formed at corresponding positions in the first metal layer 14 and the second metal layer 16. The remaining photoresist is then removed.

[0058] S04-2: Forming a connecting metal layer 18.

[0059] See Figure 9As shown, a negative photoresist is coated, and after exposure and development, part of the photoresist is removed, exposing the area where the interconnect metal layer 18 will be formed. Interconnect metal layers are sequentially deposited using electron beam evaporation, and then the metal and photoresist on the photoresist are removed using a blue film stripping process to form the interconnect metal layer 18. The interconnect metal layer 18 includes a P-type interconnect metal layer 181 and an N-type interconnect metal layer 182. The N-type interconnect metal layer 182 fills the mesa conductive vias and the vias at the first metal layer 14 and the second metal layer 16, electrically connecting the exposed N-type GaN layer (i.e., the N-type semiconductor layer 111), the first metal layer 14, and the second metal layer 16. The P-type interconnect metal layer 181 fills the conductive vias in the metal reflective layer and is electrically connected to the metal reflective layer 12.

[0060] S04-3: Deposit the fourth insulating layer 19 and create pores.

[0061] See Figure 9 As shown, a SiO2 thin film with a thickness of 5000-10000 angstroms is deposited using plasma-enhanced chemical vapor deposition (PECVD) to form a fourth insulating layer 19, covering the interconnect metal layer 18 and the exposed surface. Photoresist is then coated onto the surface of the fourth insulating layer 19. After exposure and development, part of the photoresist is removed. Inductively coupled plasma etching (ICP-EDT) is then used to remove part of the fourth insulating layer 19, forming conductive vias located above the N-type interconnect metal layer 182 and the P-type interconnect metal layer 181, respectively. The remaining photoresist is then removed.

[0062] S04-4: Form P-type pad 20 and N-type pad 21.

[0063] See Figure 10 As shown, negative photoresist is coated on the fourth insulating layer 19 and its via surfaces. After exposure and development, part of the photoresist is removed. The metal stack of the pads is deposited sequentially using an electron beam evaporation process, and then the metal and photoresist on the photoresist are removed using a stripping process to form P-type pads 20 and N-type pads 21.

[0064] This completes the fabrication of the flip-chip LED.

[0065] To verify the technical effects of this invention, based on the chip structure described in the above specific embodiments, multiple sets of flip-chip light-emitting diode (LED) chip samples (Example Groups 1 to 5, Comparative Examples) were prepared by adjusting the specific values ​​of the thickness of each insulating layer, the width of the metal layer, and the horizontal distance in the electric field control structure. A conventional flip-chip LED chip without an electric field control structure was also prepared as a comparative example. ESD capability tests were performed on each sample in Human Body Discharge (HBM) mode, and the chip size was 650 × 650 micrometers. The test results are shown in the table below.

[0066]

[0067] (Note: The comparative example does not have an electric field control structure, so the relevant parameters are represented by "—".) The data in the table shows that the ESD withstand voltage of implementation groups 1 to 5 is significantly better than that of the comparative group, with an improvement of 30% to 60%. Specifically, with the gradual increase in the thickness of the three insulating layers and the reasonable optimization of the widths of the first and second metal layers, the ESD withstand voltage of the chip shows a gradual upward trend. The ESD withstand voltage of implementation groups 3 and 5 both reach 8000V, far exceeding the 5000V of the conventional structure.

[0068] In summary, the flip-chip light-emitting diode and its fabrication method described in the above embodiments of the present invention have the following beneficial effects: An electric field modulation structure is set in the electric field concentration region between the edge of the mesa 114 and the edge of the metal reflective layer 12. Utilizing the stacked arrangement of the first insulating layer 13, the first metal layer 14, the second insulating layer 15, the second metal layer 16, and the third insulating layer 17, the strong electric field originally concentrated in a single location is dispersed to multiple regions, forming a stepped electric field distribution. Specifically, by making the thickness of the third insulating layer 17 greater than the thickness of the second insulating layer 15, and the thickness of the second insulating layer 15 greater than the thickness of the first insulating layer 13, the electric field intensity at each metal layer is gradually weakened based on the principle that the thickness of the insulating layer is inversely proportional to the electric field strength. Furthermore, by making the width of the first metal layer 14 greater than the width of the second metal layer 16, and ensuring that their projection centers coincide and are equidistant from the two edges, a symmetrical stepped voltage distribution structure is formed. The synergistic effect of these structures effectively avoids excessive concentration of the electric field at the edges of the mesa 114 and the metal reflective layer 12, fundamentally suppressing local avalanche breakdown and Joule thermal damage caused by ESD high voltage, and significantly improving the chip's ESD resistance.

[0069] Furthermore, by electrically connecting the first metal layer 14 and the second metal layer 16 to the N-type pad 21, a multi-stage voltage division and relief path is formed. When an ESD high-voltage pulse is applied, the electrostatic high voltage is first applied to the second metal layer 16 to complete the first stage of voltage relief, then transmitted to the first metal layer 14 for the second stage of voltage relief, and finally conducted to the N-type pad 21. Combined with the progressively thicker insulating layer design, a stepped smooth voltage division and relief effect is achieved, further improving the chip's resistance to ESD high voltage.

[0070] The flip-chip LED using the electric field control structure of this invention can achieve an ESD withstand voltage of 6500V to 8000V in HBM mode, which is 30% to 60% higher than the conventional structure without electric field control (approximately 5000V), demonstrating significant improvement.

[0071] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0072] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A flip-chip light-emitting diode, characterized in that, include: Substrate; A semiconductor sequence, located on the substrate, having a mesa exposing the semiconductor sequence; A metal reflective layer is located on the semiconductor sequence; An electric field control structure is provided in the region between the edge of the tabletop and the edge of the metal reflective layer. The electric field control structure includes a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer stacked sequentially from bottom to top. Wherein, the thickness of the third insulating layer is greater than the thickness of the second insulating layer, and the thickness of the second insulating layer is greater than the thickness of the first insulating layer; The width of the first metal layer is greater than the width of the second metal layer, and the projection center of the second metal layer on the first metal layer coincides with the projection center of the first metal layer; The two opposite edges of the first metal layer in its width direction have equal horizontal distances from the edge of the metal reflective layer and the edge of the platform, respectively.

2. The flip-chip LED according to claim 1, characterized in that, It also includes N-type pads, which are electrically connected to the portion of the semiconductor layer exposed by the mesa; The electric field control structure has a through hole, which is filled with a connecting metal layer. The first metal layer, the second metal layer, and the semiconductor layer sequence exposed on the mesa are electrically connected to the N-type pad through the connecting metal layer.

3. The flip-chip LED according to claim 2, characterized in that, It also includes P-type pads and a fourth insulating layer; The connecting metal layer includes a P-type connecting metal layer and an N-type connecting metal layer. The P-type connecting metal layer is connected to the metal reflective layer through a through-hole penetrating the electric field control structure. The fourth insulating layer covers the connecting metal layer and has an opening. The P-type pad is connected to the P-type connecting metal layer through the opening, and the N-type pad is connected to the N-type connecting metal layer through the opening.

4. The flip-chip LED according to claim 1, characterized in that, The equal horizontal distance is 2-3 micrometers; the width of the first metal layer is 8-10 micrometers, and the width of the second metal layer is 4-6 micrometers.

5. The flip-chip LED according to claim 1, characterized in that, The thickness of the third insulating layer is 12,000-15,000 angstroms, the thickness of the second insulating layer is 10,000-12,000 angstroms, and the thickness of the first insulating layer is 8,000-10,000 angstroms.

6. The flip-chip LED according to claim 1, characterized in that, The first metal layer and the second metal layer have the same thickness and are both composed of a Ni layer, an Au layer and a Ti layer from bottom to top, wherein the thickness of the Ni layer is 1000-2000 angstroms, the thickness of the Au layer is 2000-5000 angstroms, and the thickness of the Ti layer is 30-50 angstroms; the first insulating layer includes an Al2O3 film and a SiO2 film from bottom to top, and the second insulating layer and the third insulating layer are both SiO2 films.

7. The flip-chip LED according to claim 1, characterized in that, The semiconductor layer sequence includes, from bottom to top, an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer. The mesa penetrates the P-type semiconductor layer and the active light-emitting layer, exposing the N-type semiconductor layer. The metal reflective layer contains Ag.

8. A method for fabricating a flip-chip light-emitting diode as described in any one of claims 1-7, characterized in that, Includes the following steps: A substrate is provided on which a semiconductor sequence is formed; The semiconductor sequence is etched to form a mesa that exposes the semiconductor sequence; A metal reflective layer is formed on the semiconductor sequence; An electric field modulation structure is formed in the region between the edge of the platform and the edge of the metal reflective layer. The electric field modulation structure includes a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, and a third insulating layer stacked sequentially from bottom to top. Wherein, the thickness of the third insulating layer is greater than the thickness of the second insulating layer, and the thickness of the second insulating layer is greater than the thickness of the first insulating layer; The width of the first metal layer is greater than the width of the second metal layer, and the projection center of the second metal layer on the first metal layer coincides with the projection center of the first metal layer; The two opposite edges of the first metal layer in its width direction have equal horizontal distances from the edge of the metal reflective layer and the edge of the platform, respectively.

9. The method for fabricating a flip-chip light-emitting diode according to claim 8, characterized in that, The deposition of the first insulating layer includes: depositing an Al2O3 film with a thickness of 500-1000 angstroms using an atomic layer deposition process, and then depositing a SiO2 film with a thickness of 7500-9000 angstroms using a plasma-enhanced chemical vapor deposition process; Both the second insulating layer and the third insulating layer are formed by depositing SiO2 thin films using plasma-enhanced chemical vapor deposition.

10. The method for fabricating a flip-chip light-emitting diode according to claim 8, characterized in that, The formation of both the first metal layer and the second metal layer includes: sequentially depositing a Ni layer, an Au layer, and a Ti layer, wherein the thickness of the Ni layer is 1000-2000 angstroms, the thickness of the Au layer is 2000-5000 angstroms, and the thickness of the Ti layer is 30-50 angstroms.

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