An integrated chip and its fabrication method
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-05-28
- Publication Date
- 2026-08-14
AI Technical Summary
[0003]然而，随着集成度要求的提高，以及在一些领域芯片微缩化的要求越来越高，传统的封装设备和工艺难以达成芯片集成的精度要求
[0044]1.该集成芯片中第一芯片的第一阳极和第一阴极中的一个与所述第二芯片的第二阳极固接并电连接，另一个与所述第二芯片的第二阴极固接并电连接，也即第一芯片和第二芯片的同极性电极固接或者不同极性的电极固接，将第二芯片固定在第一芯片背离第一衬底的一侧，在芯片端实现多芯片集成，使得芯片集成的精度不再受限于封装设备和工艺，能够缩小后续的封装尺寸，进而提高芯片的集成精度，并且简化了后续的封装制程，节省封装成本。第二芯片在第一平面的正投影图形位于所述第一芯片在所述第一平面的正投影图形的范围内，使得第二芯片不会额外增加集成芯片的占用面积，能够进一步缩小后续的封装尺寸，进而提高芯片的集成精度。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of light-emitting diode technology, and more specifically, to an integrated chip and its fabrication method. Background Technology
[0002] A light-emitting diode (LED) is a semiconductor device used to convert electrical energy into light. Compared to light sources such as fluorescent lamps and incandescent lamps, LEDs have advantages such as low power consumption, long lifespan, fast response speed, and safety and environmental friendliness. They can be used in various indoor and outdoor lighting fixtures, displays, electrical signs, and other applications. In the application of LEDs, many fields require the integration of multiple LEDs, such as display devices, stage lighting, landscape lighting, and wearable devices. This integration is usually completed at the packaging or module level.
[0003] However, with increasing integration requirements and the growing demand for chip miniaturization in some fields, traditional packaging equipment and processes are struggling to meet the precision requirements of chip integration. Therefore, improving the precision of chip integration has become an urgent problem to be solved. Summary of the Invention
[0004] In view of this, the present invention provides an integrated chip and a method for manufacturing the same, which achieves multi-chip integration at the chip level, thereby reducing the package size and improving the chip integration accuracy.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:
[0006] An integrated chip comprising:
[0007] A first chip includes a first substrate, a first epitaxial stack, a first cathode, and a first anode; the first epitaxial stack is disposed on one side surface of the first substrate; the first cathode and the first anode are located above the side of the first substrate facing the first epitaxial stack.
[0008] At least one second chip is fixed to the side of the first chip facing away from the first substrate; the second chip includes a second epitaxial layer, a second cathode, and a second anode; the second cathode and the second anode are disposed facing the side of the first chip facing away from the first substrate;
[0009] One of the first anode and the first cathode of the first chip is fixedly connected to and electrically connected to the second anode of the second chip, and the other is fixedly connected to and electrically connected to the second cathode of the second chip;
[0010] The first plane is parallel to the first substrate; the orthographic projection of the second chip onto the first plane is located within the range of the orthographic projection of the first chip onto the first plane.
[0011] Optionally, the surface of the first anode has an exposed first connection area;
[0012] The surface of the first cathode has an exposed second connection area.
[0013] Optionally, the light-emitting areas of the first chip and the second chip are staggered.
[0014] Alternatively, the light-emitting areas of the first chip and the second chip may overlap, allowing the light emitted by the first chip to pass through the second chip.
[0015] Optionally, multiple second chips are provided and arranged on the outer periphery of the light-emitting area of the first chip.
[0016] Optionally, the second chip is fixed to the first chip by die bonding or wafer bonding.
[0017] Optionally, the first epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked along a direction away from the first substrate;
[0018] The first epitaxial stack has a via on the surface of the second type semiconductor layer facing the first substrate;
[0019] The first substrate is a conductive substrate;
[0020] The first chip further includes a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer, which are sequentially stacked along a direction away from the first substrate;
[0021] The second insulating layer covers the surface of the first epitaxial stack facing the first substrate and extends into the via, covering the wall of the via;
[0022] The second conductive layer is stacked on the surface of the second insulating layer facing the first substrate and embedded in the second insulating layer and electrically connected to the first type of semiconductor layer; the surface of the second conductive layer facing away from the first substrate has an exposed surface;
[0023] The first insulating layer covers the surfaces of the second insulating layer and the second conductive layer facing the first substrate and extends to the wall of the via.
[0024] The first conductive layer is stacked on the surface of the first insulating layer facing the first substrate and extends into the via to be electrically connected to the second type semiconductor layer; the surface of the first conductive layer facing away from the first substrate has an exposed surface;
[0025] One of the first anode and the first cathode is stacked on the exposed surface of the second conductive layer, and the other is stacked on the exposed surface of the first conductive layer;
[0026] The second epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked sequentially in a direction away from the first chip;
[0027] The second epitaxial stack has a groove on the surface of the exposed second type semiconductor layer facing the first chip;
[0028] One of the second anode and the second cathode is stacked on the surface of the first type semiconductor layer away from the active layer and is electrically connected to the first type semiconductor layer, while the other is stacked in the groove and is electrically connected to the second type semiconductor layer.
[0029] Optionally, one of the first insulating layer, the second insulating layer, and the first conductive layer may be a reflector;
[0030] Alternatively, two or three of the first insulating layer, the second insulating layer, and the first conductive layer may together constitute a reflector.
[0031] Optionally, the first epitaxial stack includes a second type semiconductor layer, an active layer, and a first type semiconductor layer sequentially stacked along a direction away from the first substrate;
[0032] The first epitaxial stack has a groove on the surface of the exposed second type semiconductor layer facing away from the first substrate;
[0033] One of the first anode and the first cathode is stacked on the surface of the first type semiconductor layer away from the active layer and electrically connected to the first type semiconductor layer, while the other is stacked in the groove and electrically connected to the second type semiconductor layer;
[0034] The second epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked sequentially in a direction away from the first chip; the second epitaxial stack has a groove on the surface of the second type semiconductor layer facing the first chip.
[0035] One of the second anode and the second cathode is stacked on the surface of the first type semiconductor layer away from the active layer and is electrically connected to the first type semiconductor layer, while the other is stacked in the groove and is electrically connected to the second type semiconductor layer.
[0036] Optionally, the surface of the first substrate facing away from the first epitaxial stack is provided with a reflective structure.
[0037] This invention also provides a method for manufacturing an integrated chip, comprising:
[0038] Fabricating a first chip; fabricating the first chip includes: providing a first substrate; fabricating a first epitaxial layer on one side surface of the first substrate; and fabricating a first cathode and a first anode on the side of the first substrate facing the first epitaxial layer.
[0039] Fabricating a second chip; fabricating a second chip includes: growing a second epitaxial stack, a second cathode, and a second anode;
[0040] The first chip or the second chip is moved so that the second cathode and the second anode face the side of the first chip away from the first substrate;
[0041] One of the first anode and the first cathode of the first chip is fixedly connected to the second anode of the second chip and electrically connected to it; the other is fixedly connected to the second cathode of the second chip and electrically connected to it.
[0042] The first plane is parallel to the first substrate; the orthographic projection of the second chip onto the first plane is located within the range of the orthographic projection of the first chip onto the first plane.
[0043] Compared with existing technologies, the technical solution provided by this invention has at least the following advantages:
[0044] 1. In this integrated chip, one of the first anode and the first cathode of the first chip is fixedly connected and electrically connected to the second anode of the second chip, and the other is fixedly connected and electrically connected to the second cathode of the second chip. That is, the electrodes of the first chip and the second chip are fixedly connected with the same polarity or with opposite polarities. The second chip is fixed to the side of the first chip facing away from the first substrate. This achieves multi-chip integration at the chip end, freeing the chip integration accuracy from the limitations of packaging equipment and processes. It enables the reduction of subsequent packaging dimensions, thereby improving chip integration accuracy and simplifying subsequent packaging processes, saving packaging costs. The orthographic projection pattern of the second chip on the first plane is located within the range of the orthographic projection pattern of the first chip on the first plane, ensuring that the second chip does not additionally increase the area occupied by the integrated chip, further reducing the subsequent packaging size and improving chip integration accuracy.
[0045] When the electrodes of the second and first chips of the same polarity are fixedly connected, a positive parallel structure is formed, allowing for synchronous lighting and shutdown. When the electrodes of the second and first chips of different polarities are fixedly connected, they can be asynchronously lit and switched off, achieving bidirectional conduction. In practical applications, the parallel connection method of the second and first chips can be selected according to needs. Attached Figure Description
[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0047] Figure 1A top view of one embodiment of an integrated chip;
[0048] Figure 2 A cross-sectional structural diagram of one embodiment of the first chip;
[0049] Figure 3 A cross-sectional structural diagram of one embodiment of the second chip;
[0050] Figure 4 A cross-sectional structural diagram of one embodiment of an integrated chip;
[0051] Figure 5 This is a cross-sectional structural diagram of another embodiment of an integrated chip;
[0052] Figure 6 This is a cross-sectional structural diagram of another embodiment of an integrated chip;
[0053] Figure 7 This is a cross-sectional structural diagram of another embodiment of an integrated chip;
[0054] Figure 8 This is a top view of another embodiment of an integrated chip.
[0055] Figure 9 This is a top view of another embodiment of an integrated chip.
[0056] Figure 10 This is a top view of another embodiment of an integrated chip.
[0057] Figure 11 This is a top view of another embodiment of an integrated chip.
[0058] Figure 12 A cross-sectional structural diagram of another embodiment of the first chip;
[0059] Figure 13 This is a cross-sectional structural diagram of another embodiment of an integrated chip;
[0060] Figure 14 This is a cross-sectional structural diagram of another embodiment of an integrated chip;
[0061] Figure 15 This is a cross-sectional structural diagram of another embodiment of an integrated chip;
[0062] Figure 16 This is a cross-sectional structural diagram of another embodiment of an integrated chip;
[0063] Figure 17 This is a cross-sectional structural diagram of another embodiment of an integrated chip.
[0064] Figure label:
[0065] First chip B; Second chip C; First substrate 11; Second substrate 12; First epitaxial stack W1; Second epitaxial stack W2; Through-hole K; First light-emitting region L1; Second light-emitting region L2; First type semiconductor layer 2; Active layer 4; Second type semiconductor layer 3; First insulating layer 71; Second insulating layer 72; Reflective structure 8; First conductive layer 07; Second conductive layer 08; First cathode 911; First anode 921; Second cathode 912; Second anode 922. Detailed Implementation
[0066] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0067] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0068] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included. In this application, unless specifically stated otherwise, all numerical ranges include endpoint values.
[0069] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.
[0070] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0071] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
[0072] To address the problems mentioned in the background section, this application provides an integrated chip. For example... Figure 1-6 As shown, the integrated chip includes a first chip B and at least one second chip C fixed to the side of the first chip B facing away from the first substrate 11.
[0073] refer to Figure 1-6 As shown, the first chip B includes a first substrate 11, a first epitaxial layer W1, a first cathode 911, and a first anode 921. The first epitaxial layer W1 is disposed on one side surface of the first substrate 11. The first cathode 911 and the first anode 921 are located above the side of the first substrate 11 facing the first epitaxial layer W1.
[0074] The second chip C includes a second epitaxial layer W2, a second cathode 912, and a second anode 922; the second cathode 912 and the second anode 922 are disposed on the side of the first chip B away from the first substrate 11.
[0075] One of the first anode 921 and the first cathode 911 of the first chip B is fixedly connected to and electrically connected to the second anode 922 of the second chip C, and the other is fixedly connected to and electrically connected to the second cathode 912 of the second chip C. A first plane is parallel to the first substrate 11, and the orthographic projection pattern of the second chip C onto the first plane lies within the area of the orthographic projection pattern of the first chip B onto the first plane. The first plane is also parallel to the surface of the first substrate 11 facing the first epitaxial stack W1.
[0076] In this integrated chip, the first chip B and the second chip C can be one of the following structures: upright, flip-chip, and vertical. The light emitted by the first chip B and the second chip C can be the same color or different colors. In this integrated chip, one of the first anode 921 and the first cathode 911 of the first chip B is fixedly connected to the second anode 922 of the second chip C, and the other is fixedly connected to the second cathode 912 of the second chip C. That is, the electrodes of the first chip B and the second chip C are fixed with the same polarity or with opposite polarities, fixing the second chip C to the side of the first chip B facing away from the first substrate 11. This achieves multi-chip integration at the chip level, freeing the chip integration accuracy from the limitations of packaging equipment and processes, enabling a reduction in subsequent packaging size, thereby improving chip integration accuracy, simplifying subsequent packaging processes, and saving packaging costs. The orthographic projection pattern of the second chip C on the first plane is located within the area of the orthographic projection pattern of the first chip B on the first plane, ensuring that the second chip C does not additionally increase the area occupied by the integrated chip, further reducing the subsequent packaging size and improving chip integration accuracy.
[0077] When the same polarity electrodes of the second chip C and the first chip B are fixedly connected, a positive parallel structure is formed, allowing them to be synchronously lit and turned off. (Refer to the diagram for the fixed connection of the same polarity electrodes of the second chip C and the first chip B.) Figure 5 That is, the first anode 921 and the second anode 922 are fixedly connected and electrically connected, and the first cathode 911 and the second cathode 912 are fixedly connected and electrically connected. When the electrodes of the second chip C and the first chip B of different polarities are fixedly connected, they can be asynchronously lit and turned off, achieving bidirectional conduction. (Refer to the diagram for the fixed connection of the electrodes of the second chip C and the first chip B of different polarities.) Figure 4 That is, the first anode 921 and the second cathode 912 are fixedly connected and electrically connected, and the first cathode 911 and the second anode 922 are fixedly connected and electrically connected. In actual use, the parallel connection of the second chip C and the first chip B can be selected as needed.
[0078] Based on any of the above embodiments, in an optional embodiment, the surface of the first anode 921 has an exposed first connection area; the surface of the first cathode 911 has an exposed second connection area. This configuration facilitates the connection of the integrated chip to external devices.
[0079] Optionally, refer to Figure 1 The surface of the first anode 921 facing the second chip C has an exposed first connection area. The surface of the first cathode 911 facing the second chip C has an exposed second connection area.
[0080] When the electrodes of the first chip B and the second chip C are fixed together with the same polarity or with opposite polarities, the fixing method can be bonding. The electrodes of the first chip B and the second chip C are aligned and then bonded together. After bonding, the electrodes of the second chip C and the electrodes of the first chip B are in contact with each other in pairs of the same polarity or in pairs of opposite polarities. Furthermore, the projections of the two electrodes of the first chip B onto the first plane are not completely covered by the projections of the second chip onto the first plane; the exposed portions are used for external electrical connections.
[0081] Optionally, the surfaces of the first anode 921 and the first cathode 911 of the first chip B facing away from the first substrate 11 are made of gold, which facilitates the formation of a good solder joint during subsequent wire bonding. The surfaces of the second anode 922 and the second cathode 912 of the second chip C facing the first chip B are made of materials such as tin, indium, or conductive adhesive that can bond with gold.
[0082] Based on the above embodiments, in an optional embodiment, refer to Figure 1 , 4 As shown in Figure 5, the light-emitting areas of the first chip B and the second chip C are staggered; or, refer to... Figure 7 , 8 As shown in Figure 9, the light-emitting areas of the first chip B and the second chip C overlap. This configuration allows for adaptation to different light-emitting requirements, and the appropriate chip can be selected based on actual needs. (Reference) Figure 1 The light-emitting area of the first chip B is the first light-emitting area L1. The area enclosed by the rectangular frame between the first cathode 911 and the first anode 912 in the figure is the first light-emitting area L1. Figure 1 This example only illustrates that the first light-emitting region L1 is located between the first cathode 911 and the first anode 921; the first light-emitting region L1 can also be located in other positions. The shaded area is the second chip C, which is fixedly connected to the first anode 921 and the first cathode 911 of the first chip B. The second light-emitting region L2 of the second chip C is located within the shaded area and is offset from the first light-emitting region L1.
[0083] When the light-emitting area of the first chip B and the light-emitting area of the second chip C overlap, the reference... Figure 8 It can be partially overlapping, see reference. Figure 9 Alternatively, they can completely overlap. When the light-emitting areas of the first chip B and the second chip C overlap, it is preferable that the light emitted from the first chip B can pass through the second chip C and exit. Figure 7 The diagram shows a cross-sectional structure of the integrated chip when the light-emitting regions of the first chip B and the second chip C overlap.
[0084] refer to Figure 8 ,9 The light-emitting area of the first chip B is the first light-emitting area L1. The area enclosed by the rectangular frame between the first cathode and the first anode in the figure is the first light-emitting area L1. Figure 8 , 9 This example only illustrates that the first light-emitting region L1 is located between the first cathode 911 and the first anode 921; the first light-emitting region L1 can also be located in other positions. The shaded area is the second chip C, which is fixedly connected to the first anode 921 and the first cathode 911 of the first chip B. The second light-emitting region L2 of the second chip C is located within the shaded area, and the first light-emitting region L1 and the second light-emitting region L2 partially or completely overlap.
[0085] Based on any of the above embodiments, in an optional embodiment, the second chip C has multiple components and is arranged on the outer periphery of the light-emitting area (first light-emitting area L1) of the first chip B. For example, refer to... Figure 10 Two second chips C are provided, arranged on opposite sides of the outer periphery of the light-emitting area of the first chip B. (Reference) Figure 11 Four second chips C are provided, arranged around the light-emitting area (first light-emitting area L1) of the first chip B. The first cathode 911 and the first anode 921 have a connecting arm and straight arms located at both ends of the connecting arm, forming a U-shaped structure. One of the two straight arms of the first cathode 911 is located between the two straight arms of the first anode 921; and one of the two straight arms of the first anode 921 is located between the two straight arms of the first cathode 911. The number of second chips C is not limited in this application. In other embodiments, the number of second chips C can be adjusted according to actual needs. The specific structure of the first cathode 911 and the first anode 921 can also be set to other shapes besides those shown in the figure.
[0086] With this configuration, multiple second chips C are arranged around the light-emitting area of the first chip B, resulting in more uniform light emission from the entire integrated chip. Furthermore, a recessed height difference is formed in the light-emitting area (first light-emitting area L1) of the first chip B, which can be used to fill the light-emitting area of the first chip B with fluorescent conversion material.
[0087] Based on any of the above embodiments, in an optional embodiment, the second chip C is fixed to the first chip B by die bonding or wafer bonding. Die bonding refers to the second chip C being fixed to the first chip B after it has already been divided into isolated chips. Wafer bonding refers to the second chip C being fixed to the first chip B by transfer before it is divided into isolated chips, and then being divided. Similarly, the transfer can be performed after the first chip B is divided into isolated chips, or before it is divided into isolated chips. That is, the first chip B and the second chip C can be connected by electrodes while both are in a wafer state; or both can be connected by electrodes after being cut into chips; or one can be in a wafer state and the other in a cut chip state.
[0088] Based on any of the above embodiments, in an optional embodiment, reference is made to... Figure 2 The first chip B is a vertically structured chip with electrodes on the same side. The first epitaxial stack W1 includes a first type semiconductor layer 2, an active layer 4, and a second type semiconductor layer 3, which are sequentially stacked along a direction away from the first substrate 11. The first epitaxial stack W1 has a through-hole K on the surface of the second type semiconductor layer 3 facing the first substrate 11. The first substrate 11 is a conductive substrate.
[0089] The first chip B further includes a first conductive layer 07, a first insulating layer 71, a second conductive layer 08, and a second insulating layer 72, sequentially stacked along a direction away from the first substrate 11. The second insulating layer 72 covers the surface of the first epitaxial stack W1 facing the first substrate 11 and extends into the via K, covering the wall of the via K. The second conductive layer 08 is stacked on the surface of the second insulating layer 72 facing the first substrate 11 and is embedded within the second insulating layer 72, electrically connected to the first type semiconductor layer 2; the surface of the second conductive layer 08 facing away from the first substrate 11 has an exposed surface. The first insulating layer 71 covers the surfaces of the second insulating layer 72 and the second conductive layer 08 facing the first substrate 11 and extends to the wall of the via K. The first conductive layer 07 is stacked on the surface of the first insulating layer 71 facing the first substrate 11 and extends into the via K, electrically connected to the second type semiconductor layer 3; the surface of the first conductive layer 07 facing away from the first substrate 11 has an exposed surface. One of the first anode 921 and the first cathode 911 is stacked on the exposed surface of the second conductive layer 08, and the other is stacked on the exposed surface of the first conductive layer 07.
[0090] In this design, the first type semiconductor layer 2 and the second type semiconductor layer 3 have opposite doping types. When the first type semiconductor layer 2 is an N-type semiconductor layer, the second type semiconductor layer 3 is a P-type semiconductor layer; conversely, when the first type semiconductor layer 2 is a P-type semiconductor layer, the second type semiconductor layer 3 is an N-type semiconductor layer.
[0091] In this optional embodiment, the first cathode 911 and the first anode 921 are respectively located on the exposed surfaces of the first conductive layer 07 and the second conductive layer 08 above the side of the first substrate 11 facing the first epitaxial stack W1. In the LED chip, the anode is electrically connected to the P-type semiconductor layer, and the cathode is electrically connected to the N-type semiconductor layer. Therefore, the positions of the first anode 921 and the first cathode 911 are determined according to the doping type of the first semiconductor layer 2 and the second semiconductor layer 3. That is, when the first semiconductor layer 2 is an N-type semiconductor layer and the second semiconductor layer 3 is a P-type semiconductor layer, the first anode 921 is stacked on the exposed surface of the first conductive layer 07, and the first cathode 911 is stacked on the exposed surface of the second conductive layer 08. When the first semiconductor layer 2 is a P-type semiconductor layer and the second semiconductor layer 3 is an N-type semiconductor layer, the first anode 921 is stacked on the exposed surface of the second conductive layer 08, and the first cathode 911 is stacked on the exposed surface of the first conductive layer 07. Figure 2 This example will be used to illustrate the situation.
[0092] refer to Figure 3 , 4 5. The second chip C is a flip-chip LED chip. The second epitaxial stack W2 includes a first type semiconductor layer 2, an active layer 4, and a second type semiconductor layer 3 stacked sequentially along the direction away from the first chip B. The second epitaxial stack W2 has a groove on the surface of the second type semiconductor layer 3 facing the first chip B. One of the second anode 922 and the second cathode 912 is stacked on the surface of the first type semiconductor layer 2 away from the active layer 4 and electrically connected to the first type semiconductor layer 2, while the other is stacked in the groove and electrically connected to the second semiconductor layer 3. The second epitaxial stack W2 of the second chip C is grown on one surface of the second substrate 12, and the second cathode 912 and the second anode 922 are located on the side of the second epitaxial stack W2 away from the second substrate 12. (Reference) Figure 4 , 6 In an integrated chip, the second substrate 12 can be retained or removed to reduce the size of the integrated chip. Methods for removing the second substrate 12 include, but are not limited to, laser, chemical etching, physical polishing, and plasma etching processes.
[0093] In an LED chip, the anode is electrically connected to the P-type semiconductor layer, and the cathode is electrically connected to the N-type semiconductor layer. Therefore, the positions of the second anode 922 and the second cathode 912 are determined according to the doping type of the first semiconductor layer 2 and the second semiconductor layer 3. That is, when the first semiconductor layer 2 is an N-type semiconductor layer and the second semiconductor layer 3 is a P-type semiconductor layer, the second anode 922 is stacked within a groove and electrically connected to the second semiconductor layer 3, and the second cathode 912 is stacked on the surface of the first semiconductor layer 2 away from the active layer 4 and electrically connected to the first semiconductor layer 2. When the first semiconductor layer 2 is a P-type semiconductor layer and the second semiconductor layer 3 is an N-type semiconductor layer, the second cathode 912 is stacked within a groove and electrically connected to the second semiconductor layer 3, and the second anode 922 is stacked on the surface of the first semiconductor layer 2 away from the active layer 4 and electrically connected to the first semiconductor layer 2. This situation is illustrated in the attached diagram.
[0094] More preferably, one of the first insulating layer 71, the second insulating layer 72, and the first conductive layer 07 in the first chip B is a reflector. Alternatively, two or three of the first insulating layer 71, the second insulating layer 72, and the first conductive layer 07 together constitute a reflector. This configuration allows light from the first chip B and the second chip C to be reflected to the light-emitting surface, improving the luminous efficiency of the integrated chip. For example, when the first conductive layer 07 is a reflector, the side of the first conductive layer 07 facing away from the first substrate 11 can be made of a highly reflective metal material such as silver, aluminum, rhodium, platinum, gold, palladium, or its alloy. When the first insulating layer 71 or the second insulating layer 72 is a reflector, it can be a DBR reflector, which is composed of alternating high-refractive-index layers and low-refractive-index layers; the high-refractive-index layer material includes, but is not limited to, TiO2 and SiN. x The material can be one of Ta2O5, Nb2O5, or ZrO2, and the low refractive index layer material can be one of SiO2, Al2O3, or MgF2. Alternatively, the first insulating layer 71 and / or the second insulating layer can together with the first conductive layer 07 to form an ODR reflector. The first insulating layer 71 and / or the second insulating layer 72 can be made of the aforementioned DBR reflector material, and the first conductive layer 07 can be made of the aforementioned high reflectivity metal material or its alloy.
[0095] Unlike the previous embodiment, in an optional embodiment, reference is made to... Figure 12The first chip B is a forward-mounted LED chip. The first epitaxial stack W1 includes a second type semiconductor layer 3, an active layer 4, and a first type semiconductor layer 2, which are sequentially stacked along a direction away from the first substrate 11. The first epitaxial stack W1 has a groove on the surface of the second type semiconductor layer 3 facing away from the first substrate 11, exposing the latter. One of the first anode 921 and the first cathode 911 is stacked on the surface of the first type semiconductor layer 2 facing away from the active layer 4 and electrically connected to the first type semiconductor layer 2, while the other is stacked in the groove and electrically connected to the second type semiconductor layer 3.
[0096] In this optional embodiment, the first cathode 911 and the first anode 921 are respectively located on the first epitaxial stack W1 above the side of the first substrate 11 facing the first epitaxial stack W1. In the LED chip, the anode is electrically connected to the P-type semiconductor layer, and the cathode is electrically connected to the N-type semiconductor layer. Therefore, the positions of the first anode 921 and the first cathode 911 are determined according to the doping type of the first type semiconductor layer 2 and the second type semiconductor layer 3; that is, when the first type semiconductor layer 2 is an N-type semiconductor layer and the second type semiconductor layer 3 is a P-type semiconductor layer, the first cathode 911 is stacked on the surface of the first type semiconductor layer 2 away from the active layer 4 and is electrically connected to the first type semiconductor layer 2, and the first anode 921 is stacked in the groove and is electrically connected to the second semiconductor layer 3. When the first type semiconductor layer 2 is a P-type semiconductor layer and the second type semiconductor layer 3 is an N-type semiconductor layer, the first anode 921 is stacked on the surface of the first type semiconductor layer 2 away from the active layer 4 and is electrically connected to the first type semiconductor layer 2, and the first cathode 911 is stacked in the groove and is electrically connected to the second type semiconductor layer 3. This situation is illustrated in the attached figure.
[0097] refer to Figure 13 , 14 The second chip C is a flip-chip LED chip. The second epitaxial stack W2 includes a first type semiconductor layer 2, an active layer 4, and a second type semiconductor layer 3, sequentially stacked along a direction away from the first chip B. The second epitaxial stack W2 has a groove on the surface of the second type semiconductor layer 3 facing the first chip B. One of the second anode 922 and the second cathode 912 is stacked on the surface of the first type semiconductor layer 2 away from the active layer 4 and electrically connected to the first type semiconductor layer 2, while the other is stacked in the groove and electrically connected to the second semiconductor layer 3.
[0098] Similarly, the positions of the second anode 922 and the second cathode 912 are determined according to the doping type of the first type semiconductor layer 2 and the second type semiconductor layer 3. That is, when the first type semiconductor layer 2 is an N-type semiconductor layer and the second type semiconductor layer 3 is a P-type semiconductor layer, the second cathode 912 is stacked on the surface of the first type semiconductor layer 2 away from the active layer 4 and electrically connected to the first type semiconductor layer 2, and the second anode 922 is stacked in the groove and electrically connected to the second type semiconductor layer 3. When the first type semiconductor layer 2 is a P-type semiconductor layer and the second type semiconductor layer 3 is an N-type semiconductor layer, the second cathode 912 is stacked in the groove and electrically connected to the second type semiconductor layer 3, and the second anode 922 is stacked on the surface of the first type semiconductor layer 2 away from the active layer 4 and electrically connected to the first type semiconductor layer 2. This situation is illustrated in the attached figure. (Reference) Figure 13 The integrated chip can fix and electrically connect electrodes of the same polarity; that is, the first cathode 911 and the second cathode 912 are fixed and electrically connected, and the first anode 921 and the second anode 922 are fixed and electrically connected. (Reference) Figure 15 The integrated chip can fix and electrically connect electrodes of different polarities; that is, the first cathode 911 and the second anode 922 are fixed and electrically connected, and the first anode 921 and the second cathode 912 are fixed and electrically connected. The second epitaxial layer W2 of the second chip C is grown on one side surface of the second substrate 12, and the second cathode 912 and the second anode 922 are located on the side of the second epitaxial layer W2 opposite to the second substrate 12. (Reference) Figure 14 , 16 The second substrate 12 can be retained or removed to reduce the size of the integrated chip. Methods for removing the second substrate 12 include, but are not limited to, laser, chemical etching, physical polishing, and plasma etching processes.
[0099] Preferably, refer to Figure 17 A reflective structure 8 is provided on the surface of the first substrate 11 facing away from the first epitaxial stack W1. This configuration reflects the light from the first chip and the second chip to the light-emitting surface, improving the luminous efficiency of the integrated chip. The reflective structure can be, for example, a metal reflective layer, a DBR reflective layer, or an ODR reflective layer. The metal reflective layer can be a highly reflective metal material such as silver, aluminum, rhodium, platinum, gold, palladium, or its alloy. The DBR reflective layer is composed of alternating high-refractive-index layers and low-refractive-index layers. The high-refractive-index layer material includes, but is not limited to, TiO2 and SiN. x The material of the low refractive index layer is one of Ta2O5, Nb2O5, and ZrO2, and the material of the low refractive index layer is including but not limited to one of SiO2, Al2O3, and MgF2. The ODR reflective layer can be a combination of the above-mentioned metal reflective layer materials and the DBR reflective layer materials.
[0100] This application also provides a method for manufacturing an integrated chip, comprising:
[0101] S01: Fabrication of the first chip B. Fabrication of the first chip B includes: providing a first substrate 11; fabricating a first epitaxial layer W1 on one side surface of the first substrate 11; and fabricating a first cathode 911 and a first anode 921 on the side of the first substrate 11 facing the first epitaxial layer W1.
[0102] S02: Fabrication of the second chip C. Fabrication of the second chip C includes: growing a second epitaxial stack W2, a second cathode 912, and a second anode 922. The order of steps S01 and S02 should be understood, but this application does not limit it.
[0103] Among them, the first chip B and the second chip C can be one of the following structures: upright structure, inverted structure, and vertical structure.
[0104] S03: Transfer the first chip B or the second chip C such that the second cathode 912 and the second anode 922 face the side of the first chip B away from the first substrate 11. Fix and electrically connect one of the first anode 921 and the first cathode 911 of the first chip B to the second anode 922 of the second chip C, and fix and electrically connect the other to the second cathode 912 of the second chip C.
[0105] The first plane is parallel to the first substrate 11; the orthographic projection pattern of the second chip C on the first plane is located within the area of the orthographic projection pattern of the first chip B on the first plane. The first plane is also the surface of the first substrate 11 that is parallel to the side facing the first epitaxial stack W1.
[0106] Optionally, the surface of the first anode has an exposed first connection area; the surface of the first cathode has an exposed second connection area. Specifically, refer to... Figure 1 The surface of the first anode 921 facing the second chip C has an exposed first connection area. The surface of the first cathode 911 facing the second chip C has an exposed second connection area.
[0107] Optionally, refer to Figure 1 , 4 As shown in Figure 5, the light-emitting areas of the first chip B and the second chip C are staggered; or, refer to... Figure 7 , 8 As shown in Figures 9 and 1, the light-emitting areas of the first chip B and the second chip C overlap. This configuration allows for adaptation to different light-emitting requirements, and the appropriate chip can be selected based on actual needs. More specific settings have been described in the integrated chip documentation and will not be repeated here.
[0108] Optionally, multiple second chips C are provided and arranged on the outer periphery of the light-emitting area of the first chip B. For example, refer to... Figure 10 Two second chips C are provided, arranged on opposite sides of the outer periphery of the light-emitting area of the first chip B. (Reference) Figure 11 Four second chips C are provided, arranged around the light-emitting area of the first chip B. This application does not limit the number of second chips C; in other embodiments, the number of second chips C can be adjusted according to actual needs. More specific settings have been described in the integrated chip description and will not be repeated here.
[0109] With this configuration, multiple second chips C are arranged around the light-emitting area of the first chip B, resulting in more uniform light emission from the entire integrated chip. Furthermore, a recessed height difference is created in the light-emitting area of the first chip B, which can be used to fill the light-emitting area with phosphor conversion material.
[0110] Optionally, the second chip C is fixed to the first chip B by die bonding or wafer bonding. Die bonding refers to the second chip C being fixed to the first chip B after it has already been divided into isolated cores, through transfer. Wafer bonding refers to the second chip C being fixed to the first chip B before it is divided into isolated cores, through transfer, and then divided. Similarly, the transfer can be performed after the first chip B is divided into isolated cores, or before it is divided into isolated cores. That is, the first chip B and the second chip C can be connected by electrodes while both are in a wafer state; or both can be connected by electrodes after being cut into cores; or one can be in a wafer state and the other in a cut core state when their electrodes are connected.
[0111] Based on the above, in an optional embodiment, the first chip B is a vertical structure chip with electrodes on the same side, and the second chip C is a flip-chip LED chip.
[0112] Specifically, in step S01, the fabricated first epitaxial stack W1 includes a first type semiconductor layer 2, an active layer 4, and a second type semiconductor layer 3 sequentially stacked along a direction away from the first substrate 11. The first epitaxial stack W1 has a via K on the side of the second type semiconductor layer 3 facing the first substrate 11. The first substrate 11 is a conductive substrate. The first chip B also includes a first conductive layer 07, a first insulating layer 71, a second conductive layer 08, and a second insulating layer 72 sequentially stacked along a direction away from the first substrate 11. The second insulating layer 72 covers the surface of the first epitaxial stack W1 facing the first substrate 11 and extends into the via K, covering the wall of the via K. The second conductive layer 08 is stacked on the surface of the second insulating layer 72 facing the first substrate 11 and is embedded in the second insulating layer 72 and electrically connected to the first type semiconductor layer 2; the surface of the second conductive layer 08 facing away from the first substrate 11 has an exposed surface. The first insulating layer 71 covers the surfaces of the second insulating layer 72 and the second conductive layer 08 facing the first substrate 11 and extends into the wall of the via K. The first conductive layer 07 is stacked on the surface of the first insulating layer 71 facing the first substrate 11 and extends into the via K to be electrically connected to the second type semiconductor layer 3; the surface of the first conductive layer 07 facing away from the first substrate 11 has an exposed surface. One of the first anode 921 and the first cathode 911 is stacked on the exposed surface of the second conductive layer 08, and the other is stacked on the exposed surface of the first conductive layer 07. The fabrication of the first chip B can be carried out by sequentially fabricating the second type semiconductor layer 3, the active layer 4, the first type semiconductor layer 2, the via K, the second insulating layer 72, the second conductive layer 08, and the first insulating layer 71 on one side of the temporary substrate, then forming the first conductive layer 07 by metal bonding and transferring it to the first substrate 11, then removing the temporary substrate, and then exposing the exposed surfaces of the first conductive layer 07 and the second conductive layer 08 by photolithography and etching.
[0113] The specific locations of the first anode 921 and the first cathode 911 have been detailed in the integrated chip and will not be repeated here.
[0114] Specifically, in step S02, a second substrate 12 is provided, and a second epitaxial stack W2 is grown on one side surface of the second substrate 12. The second epitaxial stack W2 includes a second type semiconductor layer 3, an active layer 4, and a first type semiconductor layer 2 sequentially stacked along a direction away from the second substrate 12. The second epitaxial stack W2 has a groove exposing a portion of the second type semiconductor layer 3 on the side surface away from the second substrate 12, wherein the groove can be fabricated using photolithography and etching processes. One of the second anode 922 and the second cathode 912 is stacked on the surface of the first type semiconductor layer 2 away from the active layer 4 and electrically connected to the first type semiconductor layer 2, while the other is stacked within the groove and electrically connected to the second semiconductor layer 3. The specific locations of the second anode 922 and the second cathode 912 have been detailed in the integrated chip description and will not be repeated here.
[0115] Then, in step S03, the second cathode and second anode of the second chip C are positioned facing the side of the first chip B away from the first substrate 11 and fixed to the first chip B. After step S03, the second substrate 12 can be retained or removed. Methods for removing the second substrate 12 include, but are not limited to, laser etching, chemical etching, physical polishing, and plasma etching.
[0116] More preferably, one of the first insulating layer 71, the second insulating layer 72, and the first conductive layer 07 is a reflector. Alternatively, two or three of the first insulating layer 71, the second insulating layer 72, and the first conductive layer 07 together constitute a reflector. This configuration allows the light from the first chip and the second chip to be reflected to the light-emitting surface, improving the luminous efficiency of the integrated chip.
[0117] Unlike the previous embodiment, in an optional embodiment, the first chip B is a conventional LED chip and the second chip C is a flip-chip LED chip.
[0118] Specifically, in step S01, the growth of the first epitaxial stack W1 includes a second type semiconductor layer 3, an active layer 4, and a first type semiconductor layer 2 grown sequentially along a direction away from the first substrate 11. The first epitaxial stack W1 has a groove on the exposed surface of the second type semiconductor layer 3 facing away from the first substrate 11, wherein the groove can be fabricated using photolithography and etching processes. One of the first anode 921 and the first cathode 911 is stacked on the surface of the first type semiconductor layer 2 facing away from the active layer 4 and electrically connected to the first type semiconductor layer 2; the other is stacked within the groove and electrically connected to the second semiconductor layer 3. The specific arrangement of the first anode 921 and the first cathode 911 has been described in detail in the integrated chip and will not be repeated here.
[0119] Specifically, in step S02, a second substrate 12 is provided, and a second epitaxial stack W2 is grown on one side surface of the second substrate 12. The second epitaxial stack W2 includes a second type semiconductor layer 3, an active layer 4, and a first type semiconductor layer 2 sequentially stacked along a direction away from the second substrate 12. The second epitaxial stack W2 has a groove exposing a portion of the second type semiconductor layer 3 on the side surface away from the second substrate 12, wherein the groove can be fabricated using photolithography and etching processes. One of the second anode 922 and the second cathode 912 is stacked on the surface of the first type semiconductor layer 2 away from the active layer 4 and electrically connected to the first type semiconductor layer 2, while the other is stacked within the groove and electrically connected to the second semiconductor layer 3. The specific locations of the second anode 922 and the second cathode 912 have been detailed in the integrated chip description and will not be repeated here.
[0120] Then, in step S03, the second cathode and second anode of the second chip C are positioned facing the side of the first chip B away from the first substrate 11 and fixed to the first chip B. After step S03, the second substrate 12 can be retained or removed. Methods for removing the second substrate 12 include, but are not limited to, laser etching, chemical etching, physical polishing, and plasma etching.
[0121] In this optional embodiment, a reflective structure 8 can also be fabricated on the surface of the first substrate 11 facing away from the first epitaxial stack W1. The reflective structure can be, for example, a metal reflective layer, a DBR reflective layer, an ODR reflective layer, etc.
[0122] The method for manufacturing this integrated chip can be used to manufacture the aforementioned integrated chip, and therefore has the beneficial effects of the aforementioned integrated chip, which will not be elaborated further here.
[0123] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.
[0124] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0125] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. An integrated chip, characterized in that, include: The first chip includes a first substrate, a first epitaxial stack, a first cathode, and a first anode; The first epitaxial layer is disposed on one side surface of the first substrate; The first cathode and the first anode are located above the side of the first substrate facing the first epitaxial stack; At least one second chip is fixed to the side of the first chip facing away from the first substrate; the second chip includes a second epitaxial layer, a second cathode, and a second anode; the second cathode and the second anode are disposed facing the side of the first chip facing away from the first substrate; One of the first anode and the first cathode of the first chip is fixedly connected to and electrically connected to the second anode of the second chip, and the other is fixedly connected to and electrically connected to the second cathode of the second chip; The first plane is parallel to the first substrate; the orthographic projection pattern of the second chip on the first plane is located within the range of the orthographic projection pattern of the first chip on the first plane.
2. An integrated chip as described in claim 1, characterized in that, The surface of the first anode has an exposed first connection area; The surface of the first cathode has an exposed second connection area.
3. An integrated chip as described in claim 1, characterized in that, The light-emitting areas of the first chip and the second chip are staggered. Alternatively, the light-emitting areas of the first chip and the second chip may overlap, allowing the light emitted by the first chip to pass through the second chip.
4. An integrated chip as described in claim 1, characterized in that, The second chip has multiple components and is arranged on the outer periphery of the light-emitting area of the first chip.
5. An integrated chip as described in claim 1, characterized in that, The second chip is fixed to the first chip by die bonding or wafer bonding.
6. An integrated chip as described in claim 1, characterized in that, The first epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer sequentially stacked along a direction away from the first substrate; The first epitaxial stack has a via on the surface of the second type semiconductor layer facing the first substrate; The first substrate is a conductive substrate; The first chip further includes a first conductive layer, a first insulating layer, a second conductive layer, and a second insulating layer, which are sequentially stacked along a direction away from the first substrate; The second insulating layer covers the surface of the first epitaxial stack facing the first substrate and extends into the via, covering the wall of the via; The second conductive layer is stacked on the surface of the second insulating layer facing the first substrate and embedded in the second insulating layer to be electrically connected to the first type of semiconductor layer; the surface of the second conductive layer facing away from the first substrate has an exposed surface; The first insulating layer covers the surfaces of the second insulating layer and the second conductive layer facing the first substrate and extends to the wall of the via. The first conductive layer is stacked on the surface of the first insulating layer facing the first substrate and extends into the via to be electrically connected to the second type semiconductor layer; the surface of the first conductive layer facing away from the first substrate has an exposed surface; One of the first anode and the first cathode is stacked on the exposed surface of the second conductive layer, and the other is stacked on the exposed surface of the first conductive layer; The second epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked sequentially in a direction away from the first chip; The second epitaxial stack has a groove on the surface of the exposed second type semiconductor layer facing the first chip; One of the second anode and the second cathode is stacked on the surface of the first type semiconductor layer away from the active layer and is electrically connected to the first type semiconductor layer, while the other is stacked in the groove and is electrically connected to the second type semiconductor layer.
7. An integrated chip as described in claim 6, characterized in that, One of the first insulating layer, the second insulating layer, and the first conductive layer is a reflector; Alternatively, two or three of the first insulating layer, the second insulating layer, and the first conductive layer may together constitute a reflector.
8. An integrated chip as described in claim 1, characterized in that, The first epitaxial stack includes a second type semiconductor layer, an active layer, and a first type semiconductor layer sequentially stacked along a direction away from the first substrate; The first epitaxial stack has a groove on the surface of the exposed second type semiconductor layer facing away from the first substrate; One of the first anode and the first cathode is stacked on the surface of the first type semiconductor layer away from the active layer and electrically connected to the first type semiconductor layer, while the other is stacked in the groove and electrically connected to the second type semiconductor layer; The second epitaxial stack includes a first type semiconductor layer, an active layer, and a second type semiconductor layer stacked sequentially in a direction away from the first chip; the second epitaxial stack has a groove on the surface of the second type semiconductor layer facing the first chip. One of the second anode and the second cathode is stacked on the surface of the first type semiconductor layer away from the active layer and is electrically connected to the first type semiconductor layer, while the other is stacked in the groove and is electrically connected to the second type semiconductor layer.
9. An integrated chip as described in claim 8, characterized in that, The surface of the first substrate facing away from the first epitaxial layer has a reflective structure.
10. A method for fabricating an integrated chip, characterized in that, include: Making the first chip; Fabricating the first chip includes: providing a first substrate; fabricating a first epitaxial layer on one side surface of the first substrate; and fabricating a first cathode and a first anode on the side of the first substrate facing the first epitaxial layer. Fabricating a second chip; fabricating a second chip includes: growing a second epitaxial stack, a second cathode, and a second anode; The first chip or the second chip is moved so that the second cathode and the second anode face the side of the first chip away from the first substrate; One of the first anode and the first cathode of the first chip is fixedly connected to the second anode of the second chip and electrically connected to it; the other is fixedly connected to the second cathode of the second chip and electrically connected to it. The first plane is parallel to the first substrate; the orthographic projection pattern of the second chip on the first plane is located within the range of the orthographic projection pattern of the first chip on the first plane.