A display panel, a method for manufacturing the same, and a display device having the same.

Abstract

This paper discloses a display panel, its manufacturing method, and a display device having the same. The display panel includes: a substrate divided into a display area and a non-display area; an encapsulation dam disposed on the non-display area and surrounding the display area, dividing the non-display area into an outer non-display area and an inner non-display area; and an outer isolation pillar disposed on the outer non-display area, surrounding the area where the encapsulation dam is located, including at least two spaced outer isolation portions and an outer encapsulation layer. The outer encapsulation layer continuously covers the outer non-display area and the outer isolation pillar, and the outer encapsulation layer is in contact with the outer non-display area in the spaced area between adjacent outer isolation portions. By setting the outer isolation pillar in the outer non-display area, a single structure can simultaneously block the water vapor erosion channel and prevent crack propagation, thereby shortening the distance between the barrier dam and the edge of the display panel, achieving the goal of reducing the bezel width of the display panel while ensuring the encapsulation effect.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, and in particular relates to a display panel, a method for manufacturing the same, and a display device having the same. Background Technology

[0002] In related technologies, conventional thin-film encapsulation structures employ a layered encapsulation structure of inorganic layer-organic layer-inorganic layer, such as... Figure 1 As shown, this encapsulation structure extends to the periphery of the encapsulation dam, achieving the encapsulation effect by forming a "sandwich" water and oxygen barrier structure with the two inorganic layers and the substrate layer. To ensure the encapsulation effect, the "sandwich" water and oxygen barrier structure formed by the two inorganic layers and the substrate layer needs to have a certain width, resulting in a relatively large bezel width for the display panel. At the same time, a crack-resistant barrier structure also needs to be set on the outside of the "sandwich" water and oxygen barrier structure, resulting in a relatively large bezel width for the display panel that is difficult to further reduce.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure aims to at least partially address the technical problem of how to reduce bezel width by optimizing the packaging structure. To this end, this disclosure provides a display panel, a method for manufacturing the same, and a display device having the same.

[0005] This disclosure provides a display panel comprising: a substrate divided into a display area and a non-display area surrounding the display area; an encapsulation dam disposed on the non-display area and circumferentially surrounding the display area, the encapsulation dam dividing the non-display area into an outer non-display area away from the display area and an inner non-display area close to the display area; an outer isolation pillar disposed on the outer non-display area, the outer isolation pillar circumferentially surrounding the area where the encapsulation dam is located, the outer isolation pillar including at least two spaced outer isolation portions; and an outer encapsulation layer continuously covering the outer non-display area and the outer isolation pillar, the outer encapsulation layer being in contact with the outer non-display area at a gap between adjacent outer isolation portions.

[0006] In some embodiments, the display panel further includes: a circuit structure layer disposed on the display area and the inner non-display area; a light-emitting device layer disposed on the side of the circuit structure layer away from the substrate, and the orthographic projection of the light-emitting device layer on the substrate is located in the display area; and an encapsulation layer continuously covering the light-emitting device layer, the circuit structure layer and the encapsulation dam, the encapsulation layer being continuously disposed with the outer encapsulation layer.

[0007] In some embodiments, the display panel further includes: an inner isolation pillar disposed on the side of the circuit structure layer away from the substrate, the orthographic projection of the inner isolation pillar on the substrate being located in the inner non-display area, the inner isolation pillar including at least two spaced-apart inner isolation portions; and an inner encapsulation layer continuously covering the inner isolation pillar, the inner encapsulation layer and the inorganic layer of the circuit structure layer closest to the substrate being in contact in the spaced area between adjacent inner isolation portions, the inner encapsulation layer area being continuously disposed with the encapsulation layer.

[0008] In some embodiments, the circuit structure layer further includes: a first passivation layer, wherein the first passivation layer is disposed at least between the outer non-display area and the outer isolation pillar, and the first passivation layer and the outer encapsulation layer are in contact with each other in the spaced area between adjacent outer isolation portions.

[0009] In some embodiments, the circuit structure layer further includes: a planarization layer disposed on the side of the circuit structure layer away from the substrate and on the side of the first passivation layer away from the substrate; wherein the outer isolation portion is formed on the planarization layer and the inner isolation portion is formed on the planarization layer.

[0010] In some embodiments, the encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked sequentially, with the first inorganic encapsulation layer located on the side closest to the substrate; the outer encapsulation layer includes a first outer inorganic encapsulation layer and a second outer inorganic encapsulation layer stacked sequentially, with the first outer inorganic encapsulation layer and the first inorganic encapsulation layer being continuously disposed together, and the second outer inorganic encapsulation layer and the second inorganic encapsulation layer being continuously disposed together.

[0011] In some embodiments, the inner encapsulation layer includes a first inner inorganic encapsulation layer, an inner organic encapsulation layer, and a second inner inorganic encapsulation layer stacked sequentially, wherein the first inner inorganic encapsulation layer is continuously disposed with the first inorganic encapsulation layer, the inner organic encapsulation layer is continuously disposed with the organic encapsulation layer, and the second inner inorganic encapsulation layer is continuously disposed with the second inorganic encapsulation layer.

[0012] In some embodiments, the circuit structure layer further includes: a second passivation layer disposed on the side of the planarization layer away from the substrate, the second passivation layer being intermittently disposed in the spacing region between adjacent outer isolation portions, and / or, the second passivation layer being intermittently disposed in the spacing region between adjacent inner isolation portions.

[0013] In some embodiments, the planarization layer has at least one outer planarization groove communicating with the first passivation layer in the outer non-display area, and the second passivation layer is continuously disposed at the outer planarization groove; and / or, the planarization layer has at least one inner planarization groove communicating with the circuit structure layer in the inner non-display area, and the second passivation layer is continuously disposed at the inner planarization groove.

[0014] In some embodiments, the inner planarization groove is located on the side of the inner isolation post closer to the encapsulation dam, and / or the inner planarization groove is located on the side of the inner isolation post away from the encapsulation dam.

[0015] In some embodiments, the edge of the outer non-display area is disposed adjacent to a gap region between at least one adjacent outer isolation portion.

[0016] The present disclosure provides a method for manufacturing the above-mentioned display panel. In the method for manufacturing the display panel, the last step before manufacturing the outer encapsulation layer on the outer non-display area is to provide an outer bottom groove communicating with the substrate on the structural layer on the outer non-display area. The outer bottom groove is the spacing area between adjacent outer isolation portions.

[0017] In some embodiments, the final step before fabricating the light-emitting device layer on the inner non-display area is to form an inner bottom-cut groove in the structural layer on the inner non-display area that communicates with the non-organic layer closest to the substrate in the circuit structure layer, the inner bottom-cut groove being the spacing region between adjacent inner isolation portions.

[0018] This disclosure provides a display device, which includes the display panel described above.

[0019] The embodiments disclosed herein have at least the following beneficial effects:

[0020] In the aforementioned display panel, the encapsulation dam can divide the non-display area of ​​the substrate into an outer non-display area and an inner non-display area. An outer isolation pillar is provided on the outer non-display area. The outer isolation pillar includes at least two spaced outer isolation portions, and a gap region can be formed between adjacent outer isolation portions, allowing the area corresponding to the gap region between the outer non-display area of ​​the substrate and the adjacent outer isolation portions to be exposed. An outer encapsulation layer continuously covers the outer non-display area and the outer isolation pillar. On the one hand, the outer encapsulation layer forms a structure in contact with the substrate in the gap region between adjacent outer isolation portions. There are no other structural layers between the outer encapsulation layer and the substrate, and no water or oxygen can pass through the cross section where the outer encapsulation layer contacts the substrate. Thus, the contact between the outer encapsulation layer and the substrate can form a blocking structure to block the channel for water and oxygen erosion. On the other hand, the gap region between adjacent outer isolation portions formed by the outer isolation pillar can make the structural layer between the outer encapsulation layer and the substrate discontinuous in the outer non-display area, thereby preventing cracks from extending from the cutting line of the display panel into the interior of the display panel, and providing the function of a crack-preventing barrier structure. In other words, by setting an external isolation pillar in the non-display area, a single structure can simultaneously block the water vapor erosion channel and prevent crack propagation, thereby shortening the distance between the barrier and the edge of the display panel. This ensures the sealing effect while reducing the width of the display panel's bezel. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A cross-sectional view of the display panel bezel in the related art is shown;

[0023] Figure 2 A cross-sectional view of the display panel border in an embodiment of this disclosure is shown;

[0024] Figure 3 It shows Figure 2 Enlarged view of the inner isolation column area;

[0025] Figure 4 It shows Figure 2 Enlarged view of the Chinese and foreign isolation column areas;

[0026] Figure 5 A cross-sectional view of the outer isolation column area in a display panel is shown in another embodiment of this disclosure;

[0027] Figure 6 A cross-sectional view of the outer isolation column area in a display panel is shown in yet another embodiment of this disclosure;

[0028] Figure 7 A cross-sectional view of the outer isolation column area in a display panel is shown in yet another embodiment of this disclosure.

[0029] Figure label:

[0030] 1. Substrate; 1a. Display area; 1b. Non-display area; 1b1. Encapsulation dam area; 1b2. Outer non-display area; 1b21. Crack prevention area; 1b22. Outer isolation pillar area; 1b3. Inner non-display area; 1b31. First circuit area; 1b32. Second circuit area; 1b33. Third circuit area; 1b34. Inner isolation pillar area; 2. Circuit structure layer; 25. Second gate metal layer; 271. First source / drain metal layer; 272. Second source / drain metal layer; 281. First passivation layer; 282. Second passivation layer; 291. First planarization layer; 292. Second planarization layer; 3. Light-emitting device layer; 31. Anode layer; 32. Pixel boundary layer; 33. Light-emitting functional layer 34. Cathode layer; 4. Encapsulation layer; 41. First inorganic encapsulation layer; 42. Organic encapsulation layer; 43. Second inorganic encapsulation layer; 5. Encapsulation dam; 51. Inner encapsulation dam; 52. Outer encapsulation dam; 6. Outer isolation pillar; 61. Outer isolation portion; 62. Spacing area between adjacent outer isolation portions; 63. Outer planarization groove; 7. Outer encapsulation layer; 71. First outer inorganic encapsulation layer; 72. Second outer inorganic encapsulation layer; 8. Inner isolation pillar; 81. Inner isolation portion; 82. Spacing area between adjacent inner isolation portions; 83. Inner planarization groove; 9. Inner encapsulation layer; 91. First inner inorganic encapsulation layer; 92. Inner organic encapsulation layer; 93. Second inner inorganic encapsulation layer; C. Cutting line. Detailed Implementation

[0031] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0032] Furthermore, reference numerals and / or reference letters may be repeated in different examples in this disclosure. Such repetition is for simplification and clarity purposes and does not in itself indicate a relationship between the various embodiments and / or settings discussed. In addition, this disclosure provides examples of various specific processes and materials, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0033] In this disclosure, unless otherwise stated, the term "co-layer arrangement" means that two layers, components, members, elements, or portions can be formed by the same manufacturing process (e.g., patterning process), and that these two layers, components, members, elements, or portions can generally be formed from the same material. For example, two or more structural layers co-layered means that these co-layered structural layers can be made of the same material and using the same manufacturing process, thereby simplifying the manufacturing process of the display panel.

[0034] In this disclosure, unless otherwise stated, a structural layer refers to any layer that makes up the display panel.

[0035] In this disclosure, unless otherwise stated, the term "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The term "one-step patterning process" refers to a process that uses a photomask to form patterned layers, components, or parts.

[0036] In this disclosure, unless otherwise stated, when a layer or element is referred to as being on another layer or substrate 1, it may mean that the layer or element is directly on the other layer or substrate 1, or that there may be an intermediate layer between the layer or element and the other layer or substrate 1. This disclosure describes exemplary embodiments with reference to cross-sectional views and / or plan views as idealized exemplary drawings. The thickness of layers or regions is enlarged in the drawings for clarity. Therefore, variations in shape relative to the drawings are contemplated due to manufacturing techniques and / or tolerances, etc. Therefore, exemplary embodiments should not be construed as being limited to the shapes shown in the drawings of this disclosure, but may include shape deviations caused by factors such as manufacturing. For example, rectangular or trapezoidal etched areas in the drawings of this disclosure typically have curved features. Therefore, the regions shown in the drawings of this disclosure are schematic in nature, and their shapes are not intended to show the actual shape of the display panel of this disclosure, nor are they intended to limit the scope of the disclosure of the embodiments of this disclosure.

[0037] This disclosure is described below with reference to the accompanying drawings and specific embodiments:

[0038] In related technologies, conventional thin-film encapsulation structures employ a layered encapsulation structure of inorganic layer-organic layer-inorganic layer, such as... Figure 1 As shown, this encapsulation structure extends to the periphery of the encapsulation dam 5, and... Figure 1On the outer non-display area 1b2 shown, two inorganic layers and substrate 1 form a "sandwich" water and oxygen barrier structure to achieve an encapsulation effect. To ensure the encapsulation effect, the "sandwich" water and oxygen barrier structure formed by the two inorganic layers and substrate 1 needs to have a certain width, resulting in a large bezel width for the display panel. At the same time, under external force, the edges of the display panel are prone to cracking. For example, when the display panel is cut at the cutting line C, a certain cutting stress will be generated. The presence of cutting stress will cause cracks to appear near the cutting line C and extend into the display panel. To prevent cracks from extending into the display panel, an anti-crack barrier structure also needs to be set on the outside of the "sandwich" water and oxygen barrier structure, that is, an anti-crack area 1b21 with a certain width is required. The simultaneous existence of the "sandwich" water and oxygen barrier structure and the anti-crack barrier structure results in a large bezel width for the display panel, making it difficult to further reduce.

[0039] To address the technical problem of large bezel widths in display panels, this disclosure provides a display panel, such as... Figures 2 to 7 As shown, the display panel includes a substrate 1, an encapsulation dam 5, an outer isolation pillar 6, and an outer encapsulation layer 7. The substrate 1 is divided into a display area 1a and a non-display area 1b surrounding the display area 1a. The encapsulation dam 5 is disposed on the non-display area 1b and surrounds the display area 1a in a ring. The encapsulation dam 5 divides the non-display area 1b into an outer non-display area 1b2 away from the display area 1a and an inner non-display area 1b3 closer to the display area 1a. The outer isolation pillar 6 is disposed on the outer non-display area 1b2, and surrounds the area where the encapsulation dam 5 is located in a ring. The outer isolation pillar 6 includes at least two spaced-apart outer isolation portions 61. The outer encapsulation layer 7 continuously covers the outer non-display area 1b2 and the outer isolation pillar 6, and the outer encapsulation layer 7 is in contact with the outer non-display area 1b2 at the interval 62 between adjacent outer isolation portions.

[0040] The display panel proposed in the embodiments of this disclosure, such as Figures 2 to 7As shown, the encapsulation dam 5 can divide the non-display area 1b of the substrate 1 into an outer non-display area 1b2 and an inner non-display area 1b3. An outer isolation pillar 6 is provided on the outer non-display area 1b2. The outer isolation pillar 6 includes at least two spaced outer isolation portions 61. A gap region 62 can be formed between adjacent outer isolation portions 61, which exposes the area corresponding to the gap region 62 between the outer non-display area 1b2 of the substrate 1 and the adjacent outer isolation portions. An outer encapsulation layer 7 continuously covers the outer non-display area 1b2 and the outer isolation pillar 6. On the one hand, the outer encapsulation layer 7 in the gap region between adjacent outer isolation portions... The outer encapsulation layer 7 forms a structure that contacts the substrate 1. There are no other structural layers between the outer encapsulation layer 7 and the substrate 1. Water and oxygen cannot pass through the cross-section where the outer encapsulation layer 7 contacts the substrate 1. Thus, the contact between the outer encapsulation layer 7 and the substrate 1 forms a blocking structure to block the path of water and oxygen erosion. On the other hand, the spacing region 62 between adjacent outer isolation portions formed by the outer isolation pillars 6 makes the structural layer between the outer encapsulation layer 7 and the substrate 1 discontinuous in the outer non-display area 1b2. This can prevent cracks from extending from the cutting line C of the display panel into the display panel, thus providing a crack-preventing barrier structure. In other words, by setting the outer isolation pillars 6 in the outer non-display area 1b2, a single structure can simultaneously block the water vapor erosion path and prevent crack extension. While ensuring the encapsulation effect, it can also shorten the distance between the barrier and the edge of the display panel, thereby achieving the goal of reducing the bezel width of the display panel.

[0041] The display panel proposed in the embodiments of this disclosure, such as Figure 2 As shown, the encapsulation dam 5 is located in the non-display area 1b. The area where the encapsulation dam 5 is located can be considered as the encapsulation dam area 1b1. The encapsulation dam 5 divides the non-display area 1b into an outer non-display area 1b2 and an inner non-display area 1b3. An outer isolation pillar 6 is set on the outer non-display area 1b2. On the one hand, the structure of the outer isolation pillar 6 has excellent water and oxygen blocking effect, so it does not need to have a large width like the "sandwich" water and oxygen blocking structure. The outer non-display area 1b2 only needs to reserve a narrower outer isolation pillar area 1b22 for setting the outer isolation pillar 6. On the other hand, the structure of the outer isolation pillar 6 can also act as a crack-prevention barrier, so there is no need to set a separate crack-prevention area in the outer non-display area 1b2, thus narrowing the width of the outer non-display area 1b2. Figure 1 Compared with the related technologies shown, the display panel of the present disclosure embodiment can significantly narrow the width of the outer non-display area 1b2, thereby effectively narrowing the bezel width of the display panel.

[0042] In some embodiments of this disclosure, the substrate 1 can be a flexible substrate 1 or a rigid substrate 1. The flexible substrate 1 can be made of materials such as polyimide (PI), polyethylene naphthalate (PEN), and thermoplastic polyester (PET). The rigid substrate 1 can be made of materials such as glass and quartz.

[0043] In some embodiments of this disclosure, optionally, such as Figure 2 As shown, two encapsulation dams 5 can be set in the non-display area 1b at the same time. The encapsulation dam 5 located on the side closer to the display area 1a can be defined as the inner encapsulation dam 51, and the encapsulation dam 5 located on the side farther from the display area 1a can be defined as the outer encapsulation dam 52. The outer encapsulation dam 52 has a structure surrounding the inner encapsulation dam 51.

[0044] In some other embodiments of this disclosure, optionally, the non-display area 1b may be provided with only one encapsulation dam 5, or the non-display area 1b may be provided with three or more encapsulation dams 5.

[0045] In some embodiments of this disclosure, such as Figure 2 , Figures 4 to 7 As shown, the outer isolation pillar 6 includes at least two spaced outer isolation portions 61, which are intended to form at least one gap region 62 between adjacent outer isolation portions, thereby enabling the outer encapsulation layer 7 to contact the substrate 1 at the gap region 62 between adjacent outer isolation portions to form a blocking structure. Optionally, the outer isolation pillar 6 may include 2, 3, 4, 5, 6, 7, 8, or other numbers of outer isolation portions 61.

[0046] In some embodiments of this disclosure, optionally, such as Figure 2 As shown, the encapsulation dam 5 (Dam) can be set on the same layer as some structural layers of the display panel.

[0047] In some embodiments of this disclosure, optionally, such as Figure 2 , Figures 4 to 7 As shown, the outer isolation part 61 in the outer isolation column 6 can be set in the same layer as some structural layers of the display panel.

[0048] In some embodiments of this disclosure, the display panel can be an Organic Light-Emitting Diode (OLED) display panel, a Micro Organic Light-Emitting Diode (Micro OLED) display panel, a Quantum Dot Light-Emitting Diode (Micro OLED) display panel, a Mini Light-Emitting Diode (Mini LED) display panel, or a Micro Light-Emitting Diode (Micro LED) display panel, etc. In the following embodiments of this disclosure, an OLED display panel will be used as an example.

[0049] As an alternative implementation method, such as Figure 2 As shown, the display panel also includes a circuit structure layer 2, a light-emitting device layer 3, and an encapsulation layer 4. The circuit structure layer 2 is disposed on the display area 1a and the inner non-display area 1b3. The light-emitting device layer 3 is disposed on the side of the circuit structure layer 2 away from the substrate 1, and the orthogonal projection of the light-emitting device layer 3 on the substrate 1 is located in the display area 1a. The encapsulation layer 4 continuously covers the light-emitting device layer 3, the circuit structure layer 2, and the encapsulation dam 5, and the encapsulation layer 4 is continuously disposed with the outer encapsulation layer 7.

[0050] In some embodiments of this disclosure, such as Figure 2 As shown, a circuit structure layer 2 and a light-emitting device layer 3 are provided on the display area 1a. Multiple sub-pixels can be formed on the display area 1a of the substrate 1 through the circuit structure layer 2 and the light-emitting device layer 3. In this disclosure, the number, shape, size, and arrangement of the sub-pixels are not limited, as long as the display requirements of the display panel can be met. For example, the multiple sub-pixels of the display panel can be arranged in an array. For example, the multiple sub-pixels of the display panel can each display a different color.

[0051] In some embodiments of this disclosure, optionally, the display panel may include a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color, the second color, and the third color may each be one of three basic colors, namely, the first color, the second color, and the third color may each be red, green, and blue, respectively. In some embodiments of this disclosure, the circuit structure layer 2 may form multiple thin-film transistors in the display area 1a. These multiple thin-film transistors can form a pixel driving circuit, meaning that each pixel circuit may include multiple thin-film transistors to drive the sub-pixels to emit light for display.

[0052] In some embodiments of this disclosure, the light-emitting device layer 3 forms a plurality of light-emitting areas in the display area 1a. Optionally, the light-emitting areas are configured in a one-to-one correspondence with the pixel driving circuit, so that the light-emitting areas are driven to emit light by the pixel driving circuit.

[0053] In some embodiments of this disclosure, such as Figure 2 As shown, the circuit structure layer 2 may include, in sequence, a semiconductor layer (not shown), a first gate insulating layer (not shown), a first gate metal layer (not shown), a second gate insulating layer (not shown), a second gate metal layer 25, an interlayer dielectric layer (not shown), and a source / drain metal layer, located away from the substrate 1. Optionally, the semiconductor layer may be made of polysilicon, or the semiconductor layer may be made of polysilicon and metal oxide. Optionally, the first gate insulating layer (GI1) and the second gate insulating layer (GI2) may each be independently made of inorganic insulating materials such as silicon dioxide, silicon nitride, and silicon oxynitride. Optionally, the first gate metal layer and the second gate metal layer 25 may be made of the same or different materials; optionally, the first gate metal layer and the second gate metal layer 25 may each be independently made of metal materials or alloy materials such as aluminum, titanium, and cobalt; the first gate metal layer and the second gate metal layer 25 may be formed by plasma-enhanced chemical vapor deposition (PECVD) or similar methods. Optionally, the material used to fabricate the interlayer dielectric layer may include inorganic insulating materials such as silicon dioxide, silicon nitride, or silicon oxynitride. Optionally, the source / drain metal layer may be a single-layer structure or a multi-layer structure, such as... Figure 2 As shown, in this embodiment of the present disclosure, the source / drain metal layer may include a first source / drain metal layer 271 (SD1) and a second source / drain metal layer 272 (SD2) stacked together.

[0054] In some embodiments of this disclosure, the semiconductor pattern, gate, source, and drain of a thin-film transistor can be formed by patterning the semiconductor layer, the first gate metal layer, the second gate metal layer 25, and the source and drain metal layers.

[0055] In some embodiments of this disclosure, optionally, the circuit structure layer 2 may also form multiple scan lines (GL) and multiple data lines (DL) in the display area 1a. Each scan line is connected to the pixel driving circuit of a row of sub-pixels to control the opening and closing of the corresponding row of sub-pixels. Each data line is connected to the pixel driving circuit of a column of sub-pixels to provide data signals to the corresponding column of sub-pixels.

[0056] In some embodiments of this disclosure, optionally, power signal lines may be formed in the non-display area 1b of the circuit structure layer 2. These power signal lines may include a negative ground line (VSS) and a power voltage line (VDD). The negative ground line (VSS) is connected to the cathode of the light-emitting device layer 3 and is used to provide a low-voltage signal to the sub-pixels during the display process of the display panel. The power voltage line is connected to the data line and is used to provide a high-level voltage to the sub-pixels during the display process of the display panel. Optionally, the power signal lines may be arranged around the display area 1a, or they may be arranged around the display area 1a according to a wiring design.

[0057] In some embodiments of this disclosure, such as Figure 2 As shown, the light-emitting device layer 3 may include an anode layer 31, a pixel defining layer 32, a light-emitting functional layer 33, and a cathode layer 34. The anode layer 31 is located between the circuit structure layer 2 and the encapsulation layer 4; the light-emitting functional layer 33 is located between the anode layer 31 and the encapsulation layer 4; the pixel defining layer 32 is located between the anode layer 31 and the encapsulation layer 4; and the cathode layer 34 is located between the light-emitting functional layer 33 / anode layer 31 and the encapsulation layer 4. The pixel defining layer 32 can divide the light-emitting functional layer 33 into multiple light-emitting areas by having multiple pixel openings. The anode layer 31 can be patterned to form multiple anode patterns, with each anode pattern corresponding to the light-emitting area of ​​a sub-pixel. Voltage can be supplied to the corresponding light-emitting area through an anode pattern and the cathode layer 34, thereby driving the corresponding light-emitting area to emit light. In other words, the anode pattern, the light-emitting area, and the cathode layer 34 together constitute the light-emitting device of the display panel.

[0058] In some embodiments of this disclosure, the anode layer 31 may optionally be a single-layer structure or a multi-layer structure. The anode layer 31 may be made of indium tin oxide (ITO).

[0059] In some embodiments of this disclosure, the light-emitting functional layer 33 may optionally include a light-emitting layer, which may be made of a light-emitting material capable of emitting a certain color, thereby allowing each light-emitting region to selectively emit a single color. Optionally, the light-emitting functional layer 33 may further include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer. Optionally, each layer in the light-emitting functional layer 33 may be formed by vapor deposition.

[0060] In some embodiments of this disclosure, optionally, the cathode layer 34 may be made of metals such as magnesium, calcium, lithium, and aluminum, or alloys of these metals. The cathode layer 34 may also be made of metal oxides such as indium tin oxide (IZO) and zinc stannate (ZTO). The cathode layer 34 may also be made of organic materials with conductive properties such as poly(3,4-ethylenedioxythiophene) (PEDOT) and polystyrene sulfonic acid (PSS).

[0061] In some embodiments of this disclosure, the display panel may optionally include a barrier layer located between the substrate 1 and the circuit structure layer 2. Optionally, the barrier layer may be formed over the entire surface of the substrate 1, and the barrier layer serves to prevent water and oxygen from entering the interior of the display panel from the bottom. Optionally, the barrier layer may be made of inorganic insulating materials such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0062] In some embodiments of this disclosure, the display panel may further include a buffer layer located between the substrate 1 and the circuit structure layer 2. Optionally, the buffer layer may be formed on the entire surface of the substrate 1. The buffer layer can improve the deposition quality of subsequent materials, thereby facilitating the formation of the circuit structure layer 2 on the substrate 1 and improving the adhesion between the circuit structure layer 2 and the substrate 1. Optionally, the buffer layer may be made of inorganic insulating materials such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0063] In some embodiments of this disclosure, when the display panel includes both a barrier layer and a buffer layer, the barrier layer is located between the substrate 1 and the buffer layer.

[0064] In the embodiments of this disclosure, the materials used to prepare each structural layer in the display panel are not limited, and the materials used to prepare each structural layer are only used for illustrative purposes and are not limited to this example.

[0065] In some embodiments of this disclosure, such as Figures 2 to 7 As shown, the encapsulation layer 4 continuously covers the light-emitting device layer 3, the circuit structure layer 2, and the encapsulation dam 5. The encapsulation layer 4 encapsulates the light-emitting device layer 3, the circuit structure layer 2, and the encapsulation dam 5, blocking water and oxygen erosion channels from the top of the display panel. Simultaneously, the encapsulation layer 4 and the outer encapsulation layer 7 are continuously arranged, meaning the encapsulation structure of the outer non-display area 1b2 and the encapsulation dam area 1b1 is continuous. This ensures that the encapsulation layer 4 and the outer encapsulation layer 7 block water and oxygen erosion channels from the top and edges of the display panel, ensuring the encapsulation effect. Optionally, the outer encapsulation layer 7 and the encapsulation layer 4 can be arranged in the same layer.

[0066] As an alternative implementation method, such as Figure 2 and Figure 3 As shown, the display panel also includes inner isolation pillars 8 and an inner encapsulation layer 9. The inner isolation pillars 8 are disposed on the side of the circuit structure layer 2 away from the substrate 1. The orthographic projection of the inner isolation pillars 8 onto the substrate 1 is located in the inner non-display area 1b3. The inner isolation pillars 8 include at least two spaced-apart inner isolation portions 81. The inner encapsulation layer 9 continuously covers the inner isolation pillars 8. The inner encapsulation layer 9 is in contact with the inorganic layer of the circuit structure layer 2 closest to the substrate 1 in the spacer region 82 between adjacent inner isolation portions. The inner encapsulation layer 9 is continuously disposed with the encapsulation layer 4.

[0067] In some embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, an inner isolation pillar 8 is provided on the inner non-display area 1b3. The inner isolation pillar 8 includes at least two spaced inner isolation portions 81, and a gap region 82 is formed between adjacent inner isolation portions 81. This allows the inorganic layer closest to the substrate 1 in the circuit structure layer 2 to be exposed in the gap region 82 between adjacent inner isolation portions. The inner encapsulation layer 9 continuously covers the inner non-display area 1b3 and the inner isolation pillar 8. The inner encapsulation layer 9 forms a structure in contact with the inorganic layer closest to the substrate 1 in the gap region 82 between adjacent inner isolation portions, thereby forming a barrier structure without an organic layer in the gap region 82 between adjacent inner isolation portions to block the channel for water and oxygen erosion, thereby further improving the encapsulation effect of the display panel. At the same time, the inner encapsulation layer 9 and the encapsulation layer 4 are continuously provided, that is, the encapsulation structure of the inner non-display area 1b3, the encapsulation dam area 1b1, and the display area 1a is in a continuous state. This ensures that the inner encapsulation layer 9 and the encapsulation layer 4 block the water and oxygen erosion channel from the upper side of the display panel, ensuring the encapsulation effect. Optionally, the inner encapsulation layer 9 and the encapsulation layer 4 can be set on the same layer.

[0068] In some embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, the non-organic layer closest to the substrate 1 in the circuit structure layer 2 can be a source / drain metal layer, and the inner packaging layer 9 forms a structure in the spacer region 82 between adjacent inner isolation portions that contacts the source / drain metal layer.

[0069] In some embodiments of this disclosure, such as Figure 2 and Figure 3As shown, the inner non-display area 1b3 can be divided into a first circuit area 1b31, a second circuit area 1b32, and a third circuit area 1b33 according to the wiring design of the circuit structure layer 2. The first circuit area 1b31 is the region near the encapsulation dam 5, and can be the region between the boundary of the cathode layer 34 / anode layer 31 and the encapsulation dam area 1b1. The third circuit area 1b33 is the region near the display area 1a, and can be the region between the boundary of the display area 1a and the boundary of the pixel defining layer 32. The second circuit area 1b32 is the region between the first circuit area 1b31 and the third circuit area 1b33, and can be the region between the boundary of the pixel defining layer 32 and the boundary of the cathode layer 34 / anode layer 31. The second circuit area 1b32 is the main wiring area for the power signal lines of the inner non-display area 1b3. Optionally, the inner isolation pillar 8 is disposed in the first circuit area 1b31, that is, the inner isolation pillar area 1b34 can overlap with the first circuit area 1b31. On the one hand, the wiring of the first circuit area 1b31 is simpler than that of the second circuit area 1b32, which can ensure that the inner encapsulation layer 9 and the circuit structure layer 2 of the first circuit area 1b31 form a relatively tight contact, thereby improving the effect of blocking the path of water and oxygen erosion. On the other hand, the first circuit area 1b31 is adjacent to the boundary of the cathode layer 34 / anode layer 31. By setting the inner isolation pillar 8 in the first circuit area 1b31, the shadow of the cathode layer 34 / anode layer 31 can be isolated by the inner isolation pillar 8, without the need to reserve an additional shadow area of ​​the cathode layer 34 / anode layer 31. This allows the width of the first circuit area 1b31 to be further reduced, thereby reducing the width of the non-display area 1b, and thus reducing the bezel of the display panel. Furthermore, the second circuit area 1b32 and the third circuit area 1b33 are not affected by the inner isolation pillar 8, and the structure and routing of the second circuit area 1b32 and the third circuit area 1b33 will not be affected by the inner isolation pillar 8.

[0070] As an alternative implementation method, such as Figure 2 and Figures 4 to 7 As shown, circuit structure layer 2 also includes:

[0071] The first passivation layer 281 (passivation SiNx, PVX1) is disposed at least between the outer non-display area 1b2 and the outer isolation pillar 6, and the first passivation layer 281 and the outer encapsulation layer 7 are in contact with each other in the spacer region 62 between adjacent outer isolation portions.

[0072] In some embodiments of this disclosure, such as Figure 2 and Figures 4 to 7As shown, a first passivation layer 281 can be provided at least between the outer non-display area 1b2 and the outer isolation pillar 6. The first passivation layer 281 can improve the encapsulation effect on the substrate 1 side. When the display panel is provided with the first passivation layer 281, the first passivation layer 281 and the outer encapsulation layer 7 can be in contact with each other in the spacer region 62 between adjacent outer isolation portions. That is, in the spacer region 62 between adjacent outer isolation portions, the outer encapsulation layer 7 and the substrate 1 layer can also include the first passivation layer 281. Since the first passivation layer 281 has a better water and oxygen barrier effect, and the first passivation layer 281 is in contact with the outer encapsulation layer 7 and the substrate 1, the contact between the outer encapsulation layer 7, the first passivation layer 281 and the substrate 1 can block the channel for water and oxygen erosion, effectively preventing water and oxygen from entering the display panel from the edge direction.

[0073] As an alternative implementation method, such as Figures 2 to 7 As shown, the circuit structure layer 2 further includes a planarization layer, which is disposed on the side of the circuit structure layer 2 away from the substrate 1 and on the side of the first passivation layer 281 away from the substrate 1; wherein, the outer isolation portion 61 is formed on the planarization layer and the inner isolation portion 81 is formed on the planarization layer.

[0074] In some embodiments of this disclosure, such as Figures 2 to 7 As shown, by setting a planarization layer on the side of the circuit structure layer 2 away from the substrate 1 and on the side of the first passivation layer 281 away from the substrate 1, on the one hand, the planarization layer can provide a surface with a certain flatness, which is convenient for the subsequent setting of the structure layer; on the other hand, the planarization layer can reduce the stress concentration inside the display panel, which can make the product more uniform and stable.

[0075] In some embodiments of this disclosure, such as Figures 2 to 7As shown, the outer isolation portion 61 is formed in the planarization layer by patterning the planarization layer, thereby forming the outer isolation portion 61 in a portion of the planarization layer. After the planarization layer is formed in the display panel, in the outer non-display area 1b2, the planarization layer contacts the substrate 1 or the first passivation layer 281. Etching or other processes can be used to pattern the planarization layer, exposing a portion of the substrate 1 or the first passivation layer 281 to form a gap region 62 between adjacent outer isolation portions. This facilitates contact with the subsequently formed encapsulation layer 4, thereby forming an outer isolation pillar 6 structure that blocks water and oxygen channels. Similarly, the inner isolation portion 81 is formed in the planarization layer by patterning the planarization layer, thereby forming the inner isolation portion 81 in a portion of the planarization layer. After the planarization layer is applied to the display panel, the planarization layer in the inner non-display area 1b3 contacts the circuit structure layer 2, for example, the second source / drain metal layer 272 of the circuit structure layer 2. Etching or other processes can be used to pattern the planarization layer, exposing a portion of the second source / drain metal layer 272 to form a gap region 82 between adjacent inner isolation portions. This facilitates contact with the subsequently formed inner encapsulation layer 9, thereby forming an inner isolation pillar 8 structure that blocks water and oxygen channels. In some embodiments of this disclosure, the planarization layer can be made of organic resin materials such as polyimide (PI) or polymethyl methacrylate (PMMA).

[0076] It should be noted that, since the planarization layer is made of organic resin, which has a certain degree of water absorption, when forming the outer isolation portion 61 and the inner isolation portion 81, if... Figure 2 and Figures 4 to 7 As shown, the planarization layer of the spacer region 62 between adjacent outer isolation portions needs to be completely removed to ensure that the outer encapsulation layer 7 is in direct contact with the substrate 1 or the first passivation layer 281; as Figure 2 and Figure 3 As shown, the planarization layer of the spacer region 82 between adjacent inner isolation sections needs to be completely removed to ensure that the inner encapsulation layer 9 is in direct contact with the circuit structure layer 2.

[0077] In some embodiments of this disclosure, optionally, such as Figures 2 to 7 As shown, the planarization layer may include a first planarization layer 291 and a second planarization layer 292, with the first planarization layer 291 located on the side close to the substrate 1.

[0078] In some embodiments of this disclosure, optionally, such as Figures 2 to 7 As shown, the outer isolation portion 61 is formed on the second planarization layer 292, and the inner isolation portion 81 is formed on the second planarization layer 292.

[0079] In other embodiments of this disclosure, optionally, such as Figures 2 to 7As shown, the outer isolation portion 61 is formed on the first planarization layer 291 and the second planarization layer 292, and the inner isolation portion 81 is formed on the first planarization layer 291 and the second planarization layer 292.

[0080] In some embodiments of this disclosure, the encapsulation dam 5 can be disposed on the same layer as any one or more of the circuit structure layer 2 and / or the light-emitting device layer 3. Optionally, as... Figure 2 As shown, the inner encapsulation dam 51 can be a multi-layer structure, with each layer being set on the same layer as any few layers in the circuit structure layer 2 and / or the light-emitting device layer 3. This same-layer setting can, to some extent, avoid increasing manufacturing costs and manufacturing difficulties. Similarly, the outer encapsulation dam 52 can be a multi-layer structure, with each layer being set on the same layer as any few layers in the circuit structure layer 2 and / or the light-emitting device layer 3. This same-layer setting can, to some extent, avoid increasing manufacturing costs and manufacturing difficulties. For example, in the encapsulation dam area 1b1, the inner encapsulation dam 51 includes a five-layer structure on the substrate 1 layer, which is disposed on the same layer as the first source / drain metal layer 271, the second source / drain metal layer 272, the second planarization layer 292, the second passivation layer 282, and the pixel defining layer 32, respectively; the outer encapsulation dam 52 includes a seven-layer structure on the substrate 1 layer, which is disposed on the same layer as the first source / drain metal layer 271, the first passivation layer 281, the first planarization layer 291, the second source / drain metal layer 272, the second planarization layer 292, the second passivation layer 282, and the pixel defining layer 32, respectively.

[0081] As an alternative implementation method, such as Figures 2 to 7 As shown, the encapsulation layer 4 includes a first inorganic encapsulation layer 41, an organic encapsulation layer 42, and a second inorganic encapsulation layer 43 stacked sequentially. The first inorganic encapsulation layer 41 is located on the side close to the substrate 1. The outer encapsulation layer 7 includes a first outer inorganic encapsulation layer 71 and a second outer inorganic encapsulation layer 72 stacked sequentially. The first outer inorganic encapsulation layer 71 is continuously disposed with the first inorganic encapsulation layer 41, and the second outer inorganic encapsulation layer 72 is continuously disposed with the second inorganic encapsulation layer 43.

[0082] In some embodiments of this disclosure, such as Figure 2 , Figures 4 to 7As shown, the encapsulation layer 4 may include a first inorganic encapsulation layer 41, an organic encapsulation layer 42, and a second inorganic encapsulation layer 43 stacked sequentially, with the first inorganic encapsulation layer 41 located on the side closest to the substrate 1. The first inorganic encapsulation layer 41 and the second inorganic encapsulation layer 43 can be used to block water and oxygen. Optionally, the first inorganic encapsulation layer 41 and the second inorganic encapsulation layer 43 can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the materials used to prepare the first inorganic encapsulation layer 41 and the second inorganic encapsulation layer 43 can be inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, and titanium oxide. The organic encapsulation layer 42 can be used for stress relief and planarization. Optionally, the organic encapsulation layer 42 can be formed by inkjet printing (IJP), screen printing, dispensing, etc., and the materials used to prepare the organic encapsulation layer 42 can be organic materials such as polyimide and epoxy resin. The composite encapsulation layer 4 is formed by stacking the first inorganic encapsulation layer 41, the organic encapsulation layer 42, and the second inorganic encapsulation layer 43, which can provide multiple protections for various functional structures of the display area 1a and the non-display area 1b, and has a good encapsulation effect.

[0083] In some embodiments of this disclosure, such as Figure 2 , Figures 4 to 7 As shown, the outer encapsulation layer 7 includes a first outer inorganic encapsulation layer 71 and a second outer inorganic encapsulation layer 72 stacked together. A structure can be formed in the interval region 62 between adjacent outer isolation portions, where the second outer inorganic encapsulation layer 72, the first outer inorganic encapsulation layer 71, and the substrate 1 / first passivation layer 281 are sequentially stacked and in contact, ensuring a water and oxygen barrier effect at this location. Simultaneously, the first outer inorganic encapsulation layer 71 is continuously disposed with the first inorganic encapsulation layer 41, and the second outer inorganic encapsulation layer 72 is continuously disposed with the second inorganic encapsulation layer 43. That is, the first outer inorganic encapsulation layer 71 and the first inorganic encapsulation layer 41 are disposed in the same layer, and the second outer inorganic encapsulation layer 72 and the second inorganic encapsulation layer 43 are disposed in the same layer. This simplifies the manufacturing process and reduces manufacturing costs, and also allows for the formation of a continuous encapsulation structure on the upper surface of the display panel.

[0084] As an alternative implementation method, such as Figure 2 and Figure 3 As shown, the inner encapsulation layer 9 includes a first inner inorganic encapsulation layer 91, an inner organic encapsulation layer 92, and a second inner inorganic encapsulation layer 93 stacked sequentially. The first inner inorganic encapsulation layer 91 is continuously arranged with the first inorganic encapsulation layer 41, the inner organic encapsulation layer 92 is continuously arranged with the organic encapsulation layer 42, and the second inner inorganic encapsulation layer 93 is continuously arranged with the second inorganic encapsulation layer 43.

[0085] In some implementations of this disclosure, such as Figure 2 and Figure 3 As shown, the inner encapsulation layer 9 includes a first inner inorganic encapsulation layer 91, an inner organic encapsulation layer 92, and a second inner inorganic encapsulation layer 93 stacked sequentially. The first inner inorganic encapsulation layer 91 can form a structure in contact with the circuit structure layer 2 in the gap region 82 between adjacent inner isolation parts, ensuring the water and oxygen barrier effect here; at the same time, the inner organic encapsulation layer 92 can fill the depression in the gap region 82 between adjacent inner isolation parts, thereby making the surface of the inner encapsulation layer 9 flat.

[0086] As an alternative implementation method, such as Figures 2 to 7 As shown, the circuit structure layer 2 further includes: a second passivation layer 282, which is disposed on the side of the planarization layer away from the substrate 1, and the second passivation layer 282 is intermittently disposed in the spacing region 62 between adjacent outer isolation portions, and / or, the second passivation layer 282 is intermittently disposed in the spacing region 82 between adjacent inner isolation portions.

[0087] In some embodiments of this disclosure, such as Figures 2 to 7 As shown, the second passivation layer 282 is disposed on the side of the planarization layer away from the substrate 1. By disposing of the second passivation layer 282 on the side of the planarization layer away from the substrate 1, the water and oxygen barrier and encapsulation effect on the side of the encapsulation layer 4 can be improved.

[0088] In some embodiments of this disclosure, such as Figure 2 , Figures 4 to 7 As shown, optionally, by discontinuously distributing the second passivation layer 282 in the interval region 62 between adjacent outer isolation portions, the interval region 62 between adjacent outer isolation portions forms an interval design in which the substrate, the first passivation layer, the first outer inorganic encapsulation layer and the second outer inorganic encapsulation layer are stacked in sequence, which can enable the interval region 62 between adjacent outer isolation portions to retain the effect of preventing cracks.

[0089] In some embodiments of this disclosure, such as Figure 2 , Figures 4 to 7 As shown, optionally, when the circuit structure layer 2 also includes a second passivation layer 282, the outer isolation portion can be patterned by etching or other processes after the second passivation layer 282 is fabricated in the display panel, and a portion of the second passivation layer 282 and the planarization layer can be removed to form a gap region 62 between adjacent outer isolation portions. When forming the gap region 62 between adjacent outer isolation portions by etching, since the second passivation layer 282 is an inorganic material and the planarization layer is an organic material, there will be a certain etching rate difference during the etching process, which will cause the cross-section of the gap region 62 between the outer isolation portions formed after etching to be an inverted trapezoid, and the first passivation layer 281 on the side of the outer isolation portion 61 away from the substrate will protrude a portion relative to the planarization layer.

[0090] In some embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, optionally, by discontinuously distributing the second passivation layer 282 in the spacer region 82 between adjacent inner isolation portions, a spacer design is formed in the spacer region 82 between adjacent inner isolation portions, in which the substrate, the first source / drain metal layer 271, the second source / drain metal layer 272, the first inner inorganic encapsulation layer 91, the inner organic encapsulation layer 92, and the second inner inorganic encapsulation layer 93 are stacked in sequence. This design can improve the encapsulation effect of the inner non-display area and also allow the spacer region 82 between adjacent inner isolation portions to retain the effect of preventing cracks.

[0091] In some embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, optionally, when the circuit structure layer 2 also includes a second passivation layer 282, the inner isolation portion can be patterned by etching or other processes after the second passivation layer 282 is fabricated in the display panel, and a portion of the second passivation layer 282 and the planarization layer can be removed to form a gap region 82 between adjacent inner isolation portions. When forming the gap region 82 between adjacent inner isolation portions by etching, since the second passivation layer 282 is an inorganic material and the planarization layer is an organic material, there will be a certain etching rate difference during the etching process, which will cause the cross-section of the gap region 82 between the inner isolation portions formed after etching to be inverted trapezoidal, and the first passivation layer 281 on the side of the inner isolation portion 81 away from the substrate will protrude a portion relative to the planarization layer.

[0092] As an alternative implementation method, such as Figure 2 , Figures 5 to 7 As shown, the planarization layer has at least one outer planarization groove 63 communicating with the first passivation layer 281 in the outer non-display area 1b2, and the second passivation layer 282 is continuously disposed at the outer planarization groove 63; and / or, the planarization layer has at least one inner planarization groove 83 communicating with the circuit structure layer 2 in the inner non-display area 1b3, and the second passivation layer 282 is continuously disposed at the inner planarization groove 83.

[0093] In some embodiments of this disclosure, such as Figures 5 to 7As shown, optionally, the planarization layer has at least one outer planarization groove 63 communicating with the first passivation layer 281 in the outer non-display area 1b2, and the second passivation layer 282 is continuously disposed in the outer planarization groove 63. On the one hand, the second passivation layer 282 can contact the first passivation layer 281, thereby forming a structure in which the outer encapsulation layer 7, the second passivation layer 282, the first passivation layer 281 and the substrate 1 are sequentially stacked and contacted in the outer planarization groove 63, which can improve the effect of preventing water and oxygen erosion in the edge direction of the display panel; on the other hand, forming a structure in which the outer encapsulation layer 7, the second passivation layer 282 and the first passivation layer 281 are sequentially stacked and contacted on the encapsulation side of the display panel can improve the effect of preventing water and oxygen erosion on the encapsulation side of the display panel.

[0094] In some embodiments of this disclosure, such as Figures 5 to 7 As shown, when the planarization layer has at least one outer planarization groove 63 communicating with the first passivation layer 281 in the outer non-display area 1b2, and the second passivation layer 282 is continuously disposed at the outer planarization groove 63, during the manufacturing process, before the second passivation layer 282 is formed on the display panel, the planarization layer can be patterned by etching or other processes to expose part of the first passivation layer 281 to form the outer planarization groove 63 communicating with the first passivation layer 281. Then, the second passivation layer 282 is formed by vapor deposition or other processes, so that the second passivation layer 282 can be continuously disposed at the outer planarization groove 63. When the outer planarization groove 63 is formed by etching, since only the planarization layer structure needs to be etched, the cross-section of the formed outer planarization groove 63 can be approximately rectangular. However, due to side etching and precision issues, it is possible that an inverted trapezoidal structure with a certain tilt angle may be formed at the bottom of the outer planarization groove 63. When the second passivation layer 282 is formed through processes such as plating, the second passivation layer 282 can be made continuous and have a relatively uniform thickness.

[0095] In some embodiments of this disclosure, such as Figure 2 and Figure 3As shown, when the planarization layer has at least one inner planarization groove 83 communicating with the circuit structure layer 2 in the inner non-display area 1b3, and the second passivation layer 282 is continuously disposed at the inner planarization groove 83, during the fabrication process, before forming the second passivation layer 282 in the display panel, the planarization layer can be patterned by etching or other processes to expose the source / drain metal layer in some areas to form the inner planarization groove 83 communicating with the circuit structure layer 2. Then, the second passivation layer 282 is formed by vapor deposition or other processes, thus allowing the second passivation layer 282 to be continuously disposed at the inner planarization groove 83. When forming the inner planarization groove 83 by etching, since only the planarization layer structure needs to be etched, the cross-section of the formed inner planarization groove 83 can be approximately rectangular. However, due to side etching and precision issues, an inverted trapezoidal structure with a certain tilt angle may be formed at the bottom of the inner planarization groove 83. When forming the second passivation layer 282 by plating or other processes, the second passivation layer 282 can be continuous and have a relatively uniform thickness.

[0096] In some embodiments of this disclosure, such as Figure 6 and Figure 7 As shown, optionally, the outer planarization groove 63 is located at least on the side of the outer isolation post 6 near the encapsulation dam 5, thereby enabling the encapsulation structure at the outer planarization groove 63 to form a continuous structure with the encapsulation structure at the encapsulation dam 5, thereby ensuring the effect of blocking water and oxygen erosion on the encapsulation side of the display panel.

[0097] In some embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, the planarization layer has at least one inner planarization groove 83 communicating with the circuit structure layer 2 in the inner non-display area 1b3. At the same time, the second passivation layer 282 is continuously disposed in the inner planarization groove 83. On the one hand, the second passivation layer 282 can contact the circuit structure layer 2, thereby forming a structure in which the inner encapsulation layer 9, the second passivation layer 282, the second source / drain metal layer 272, the first source / drain metal layer 271 and the substrate 1 are sequentially stacked and contacted in the inner planarization groove 83, which can improve the effect of preventing water and oxygen erosion in the edge direction of the display panel. On the other hand, the structure in which the inner encapsulation layer 9, the second passivation layer 282 and the circuit structure layer 2 are sequentially stacked and contacted on the encapsulation side of the display panel can improve the effect of preventing water and oxygen erosion on the encapsulation side of the display panel.

[0098] As an alternative implementation method, such as Figure 2 and Figure 3 As shown, the inner planarization groove 83 is located on the side of the inner isolation pillar 8 closer to the encapsulation dam 5, and / or the inner planarization groove 83 is located on the side of the inner isolation pillar 8 away from the encapsulation dam 5.

[0099] In some embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, the inner planarization groove 83 is located on the side of the inner isolation pillar 8 near the encapsulation dam 5, so that the encapsulation structure at the inner planarization groove 83 and the encapsulation structure of the encapsulation dam 5 form a continuous structure, thereby improving the effect of blocking water and oxygen erosion on the encapsulation side of the display panel.

[0100] In some embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, the inner planarization groove 83 is located on the side of the inner isolation pillar 8 away from the encapsulation dam 5, which can make the encapsulation structure at the inner planarization groove 83 form a continuous structure with the encapsulation mechanism of the second circuit area 1b32, so as to ensure the effect of blocking water and oxygen erosion on the encapsulation side of the display panel here.

[0101] In some embodiments of this disclosure, such as Figure 2 and Figure 3 As shown, multiple inner planarization grooves 83 can be provided, with one or more inner planarization grooves 83 located on the side of the inner isolation pillar 8 close to the encapsulation dam 5, and one or more inner planarization grooves 83 located on the side of the inner isolation pillar 8 away from the encapsulation dam 5. This forms a structure in which the inner planarization grooves 83 are located on both sides of the inner isolation pillar 8. That is, the inner planarization grooves 83 can ensure the effect of blocking water and oxygen erosion on the encapsulation side of the display panel; the inner isolation pillar 8 can also ensure the blocking of water and oxygen erosion channels from the edge of the display panel, thus ensuring the blocking of water and oxygen erosion channels on the edge side of the display panel.

[0102] As an alternative implementation method, such as Figures 5 to 7 As shown, the edge of the outer non-display area 1b2 is disposed adjacent to the gap area 62 between at least one adjacent outer isolation portion.

[0103] In some embodiments of this disclosure, such as Figures 5 to 7 As shown, the outer isolation pillar 6 includes one or more spaced outer isolation portions 61, thereby forming a gap region 62 between multiple adjacent outer isolation portions in the outer isolation area; at the same time, the planarization layer can be provided with multiple outer planarization grooves 63 communicating with the first passivation layer 281 in the outer non-display area 1b2. The edge of the outer non-display area 1b2 is the location of the cutting line C when manufacturing the display panel. By making the edge of the outer non-display area 1b2 adjacent to the gap region 62 between at least one adjacent outer isolation portion, it can be ensured that the cutting line C is adjacent to the gap region 62 between adjacent outer isolation portions. At the same time, the gap region 62 between adjacent outer isolation portions is the structure where the outer encapsulation layer 7 contacts the substrate 1 / first passivation layer 281, thereby making the gap region 62 between adjacent outer isolation portions have the function of blocking cracks, so as to reduce the risk of cracks or peeling caused when cutting at the cutting line C during the manufacturing of the display panel.

[0104] Based on the same inventive concept, this disclosure also proposes a method for manufacturing the above-mentioned display panel. In the method for manufacturing the display panel, the last step before manufacturing the outer encapsulation layer 7 on the outer non-display area 1b2 is to form an outer bottom groove communicating with the substrate 1 in the structural layer on the outer non-display area 1b2. The outer bottom groove is the spacing region 62 between adjacent outer isolation portions.

[0105] In the above-described method for preparing a display panel according to the present disclosure, by making the last step before preparing the outer encapsulation layer 7 to form an outer bottom-cut groove communicating with the substrate 1 on the structural layer on the outer non-display area 1b2, it can be ensured that the substrate 1 is exposed in the gap area 62 between adjacent outer isolation portions when preparing the outer encapsulation layer 7. This ensures that the prepared outer encapsulation layer 7 can contact the substrate 1. There are no other structural layers between the outer encapsulation layer 7 and the substrate 1 that affect the water and oxygen erosion barrier, thereby ensuring the water and oxygen barrier effect of the finally prepared outer isolation pillar 6.

[0106] As an optional implementation, in the method for manufacturing the display panel, the last step before fabricating the light-emitting device layer 3 on the inner non-display area 1b3 is to form an inner bottom-cut groove in the structural layer on the inner non-display area 1b3 that communicates with the non-organic layer closest to the substrate 1 in the circuit structure layer 2. The inner bottom-cut groove is the spacing region 82 between adjacent inner isolation portions.

[0107] In the above-mentioned method for preparing a display panel according to the embodiments of this disclosure, by making the last step before preparing the light-emitting device layer 3 on the inner non-display area 1b3 to form an inner bottom-cut groove in the structural layer on the inner non-display area 1b3 that communicates with the non-organic layer closest to the substrate 1 in the circuit structure layer 2, in the subsequent preparation step of the light-emitting device layer 3, the inner bottom-cut groove can be used to block the shadow of the anode layer 31 and / or the cathode layer 34. At the same time, the inner encapsulation layer 9 forms a structure in the spacer region 82 between adjacent inner isolation portions that contacts the non-organic layer closest to the substrate 1 in the circuit structure layer 2, thereby forming an organic-free blocking structure in the spacer region 82 between adjacent inner isolation portions to block the channel for water and oxygen erosion, thereby further improving the encapsulation effect of the display panel.

[0108] In the above-mentioned method for preparing the display panel proposed in this disclosure, except for the preparation steps of the outer bottom-cut groove and the inner bottom-cut groove, the preparation steps of other structural layers can refer to the prior disclosed technical solutions of the applicant, and will not be repeated here.

[0109] In some embodiments of this disclosure, optionally, the manufacturing steps of a display panel may be as follows:

[0110] A substrate 1 is provided, and a semiconductor layer in the circuit structure layer 2 is fabricated on the substrate 1;

[0111] A first gate insulating layer, a first gate metal layer, a second gate insulating layer, and a second gate metal layer 25 are sequentially formed on the side of the semiconductor layer away from the substrate 1.

[0112] Holes are drilled in the first gate metal layer, the second gate insulating layer, and the second gate metal layer 25 to prepare through holes for forming the source and drain.

[0113] A first source / drain metal layer 271 is formed on the side of the second gate metal layer 25 away from the substrate 1;

[0114] A first passivation layer 281 is prepared on the side of the first source / drain metal layer 271 away from the substrate 1;

[0115] A first planarization layer 291 is prepared on the side of the first passivation layer 281 away from the substrate 1;

[0116] A second source / drain metal layer 272 is prepared on the side of the first planarization layer 291 away from the substrate 1;

[0117] A second planarization layer 292 is prepared on the side of the second source / drain metal layer 272 away from the substrate 1;

[0118] A second passivation layer 282 is formed on the side of the second planarization layer 292 away from the substrate 1 on the non-display area 1b;

[0119] An outer bottom-cut groove is formed in the upper structural layer of the outer non-display area 1b2, and an inner bottom-cut groove is formed in the upper structural layer of the inner non-display area 1b3.

[0120] On the side of the second planarization layer 292 away from the substrate 1 on the display area 1a, the anode layer 31, pixel defining layer 32, light-emitting functional layer 33, and cathode layer 34 of the light-emitting device layer 3 are sequentially fabricated to obtain a semi-finished display panel; and,

[0121] A continuous encapsulation layer 4, an inner encapsulation layer 9, and an outer encapsulation layer 7 are formed on the side of the display panel semi-finished product away from the substrate 1.

[0122] In the preparation of the above structural layers, each structural layer can be patterned using a patterning process.

[0123] Based on the same inventive concept, this disclosure also proposes a display device, which includes the display panel described above.

[0124] Since the display device provided by the present invention includes the display panel of the above-mentioned technical solution, the display device provided by the present invention has all the beneficial effects of the above-mentioned foldable display panel, which will not be elaborated here.

[0125] In some embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, in-vehicle display, digital photo frame, wearable display, and navigator.

[0126] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0127] In the description of this disclosure, it should be understood that the terms “center,” “longitudinal,” “lateral,” “length,” “width,” “thickness,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” “outer,” “clockwise,” and “counterclockwise” indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0128] Furthermore, the use of terms such as "first" and "second" in this disclosure is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0129] Although embodiments of the present disclosure have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display panel, characterized in that, The display panel includes: A substrate, the substrate being divided into a display area and a non-display area surrounding the display area; An encapsulation dam is disposed on the non-display area and surrounds the display area in a ring, and the encapsulation dam divides the non-display area into an outer non-display area away from the display area and an inner non-display area close to the display area; An outer isolation pillar, disposed on the outer non-display area, the outer isolation pillar circumferentially surrounding the area where the encapsulation dam is located, the outer isolation pillar comprising at least two spaced-apart outer isolation portions; and... An outer encapsulation layer continuously covers the outer non-display area and the outer isolation pillar, and the outer encapsulation layer and the outer non-display area are in contact in the interval area between adjacent outer isolation portions.

2. The display panel as described in claim 1, characterized in that, The display panel also includes: A circuit structure layer is disposed on the display area and the inner non-display area; A light-emitting device layer, wherein the light-emitting device layer is disposed on the side of the circuit structure layer away from the substrate, and the orthographic projection of the light-emitting device layer on the substrate is located in the display area; and, An encapsulation layer continuously covers the light-emitting device layer, the circuit structure layer, and the encapsulation dam, and the encapsulation layer is continuously disposed with the outer encapsulation layer.

3. The display panel as described in claim 2, characterized in that, The display panel also includes: An inner isolation pillar is disposed on the side of the circuit structure layer away from the substrate. The orthographic projection of the inner isolation pillar on the substrate is located in the inner non-display area. The inner isolation pillar includes at least two spaced-apart inner isolation portions. An inner encapsulation layer continuously covers the inner isolation pillars. The inner encapsulation layer and the inorganic layer closest to the substrate in the circuit structure layer are in contact in the spaced area between adjacent inner isolation portions. The inner encapsulation layer area is continuously disposed with the encapsulation layer.

4. The display panel as described in claim 3, characterized in that, The circuit structure layer also includes: A first passivation layer is disposed at least between the outer non-display area and the outer isolation pillar, and the first passivation layer and the outer encapsulation layer are in contact in the spaced area between adjacent outer isolation portions.

5. The display panel as described in claim 4, characterized in that, The circuit structure layer also includes: A planarization layer is disposed on the side of the circuit structure layer away from the substrate and on the side of the first passivation layer away from the substrate; wherein the outer isolation portion is formed on the planarization layer and the inner isolation portion is formed on the planarization layer.

6. The display panel as described in claim 3, characterized in that, The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer stacked sequentially, with the first inorganic encapsulation layer located on the side closest to the substrate. The outer encapsulation layer includes a first outer inorganic encapsulation layer and a second outer inorganic encapsulation layer stacked together, wherein the first outer inorganic encapsulation layer is continuously disposed with the first inorganic encapsulation layer, and the second outer inorganic encapsulation layer is continuously disposed with the second inorganic encapsulation layer.

7. The display panel as described in claim 6, characterized in that, The inner encapsulation layer includes a first inner inorganic encapsulation layer, an inner organic encapsulation layer, and a second inner inorganic encapsulation layer stacked sequentially. The first inner inorganic encapsulation layer is continuously arranged with the first inorganic encapsulation layer, the inner organic encapsulation layer is continuously arranged with the organic encapsulation layer, and the second inner inorganic encapsulation layer is continuously arranged with the second inorganic encapsulation layer.

8. The display panel as described in claim 5, characterized in that, The circuit structure layer also includes: A second passivation layer is disposed on the side of the planarization layer away from the substrate. The second passivation layer is intermittently disposed in the spacer region between adjacent outer isolation portions, and / or, the second passivation layer is intermittently disposed in the spacer region between adjacent inner isolation portions.

9. The display panel as described in claim 8, characterized in that, The planarization layer has at least one outer planarization groove communicating with the first passivation layer in the outer non-display area, and the second passivation layer is continuously disposed at the outer planarization groove; and / or, the planarization layer has at least one inner planarization groove communicating with the circuit structure layer in the inner non-display area, and the second passivation layer is continuously disposed at the inner planarization groove.

10. The display panel as claimed in claim 9, characterized in that, The inner planarization groove is located on the side of the inner isolation post closer to the encapsulation dam, and / or the inner planarization groove is located on the side of the inner isolation post away from the encapsulation dam.

11. The display panel as claimed in claim 9, characterized in that, The edge of the outer non-display area is disposed adjacent to the gap area between at least one adjacent outer isolation portion.

12. A method for manufacturing a display panel as described in any one of claims 1 to 11, characterized in that, In the method for manufacturing the display panel, the last step before preparing the outer encapsulation layer on the outer non-display area is to form an outer bottom-cut groove in the structural layer on the outer non-display area that communicates with the substrate. The outer bottom-cut groove is the spacing area between adjacent outer isolation portions.

13. The method for manufacturing a display panel as described in claim 12, characterized in that, The final step before fabricating the light-emitting device layer on the inner non-display area is to form an inner bottom-cut groove in the structural layer on the inner non-display area that communicates with the non-organic layer closest to the substrate in the circuit structure layer. The inner bottom-cut groove is the spacing region between adjacent inner isolation portions.

14. A display device, characterized in that, The display device includes a display panel as described in any one of claims 1 to 11.

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