Display device and electronic device including the display device

Abstract

This invention discloses a display device and an electronic device including the display device. The display device includes: a substrate including a display area, with an emitting area disposed in the display area; a circuit layer disposed on the substrate; and a component layer disposed on the circuit layer. The component layer includes light-emitting elements disposed in each of the emitting areas. The circuit layer includes: light-emitting pixel drivers disposed in a first direction and a second direction, transmitting driving current to the light-emitting elements; a first power main line extending in the second direction, transmitting first power to at least some of the light-emitting pixel drivers; and a second power main line extending in the second direction, transmitting a second power, different from the first power, to some other light-emitting pixel drivers.

Description

Technical Field

[0001] This disclosure relates to display devices and electronic devices including such display devices. Background Technology

[0002] With the advancement of the information society, increasingly higher demands are being placed on display devices used to display images in various ways. For example, display devices are used in a variety of electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs.

[0003] The display device can be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of light-emitting display devices can include organic light-emitting display devices that include organic light-emitting elements, inorganic light-emitting display devices that include inorganic light-emitting elements such as inorganic semiconductors, and micron-light-emitting display devices that include micron-light-emitting elements.

[0004] Organic light-emitting display devices use light-emitting elements to display images, each of which includes a light-emitting layer containing organic light-emitting materials. As described above, organic light-emitting display devices use self-emissive elements to display images, and therefore, compared with other display devices, they can have relatively superior performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle. Summary of the Invention

[0005] When the light-emitting elements of a display device have the same structure, the brightness of some colors may be lower than that of some other colors due to differences in organic light-emitting materials.

[0006] To improve this, some color light-emitting elements may include two or more stacked light-emitting elements. In this way, the brightness of some color light-emitting elements can be increased, thereby improving the display quality of the display device.

[0007] Because some colored light-emitting elements have a different structure than some other colored light-emitting elements, the voltage-current characteristics of some colored light-emitting elements may differ from those of other colored light-emitting elements.

[0008] However, when all light-emitting elements are driven by the same power regardless of differences in voltage-current characteristics, unnecessary power consumption may occur in the display device.

[0009] The features of this disclosure provide a display device and an electronic device including the display device that can improve display quality while reducing power consumption.

[0010] However, the features of this disclosure are not limited to those set forth herein. The above and other features of this disclosure will become more apparent to those skilled in the art upon reference to the detailed description of this disclosure given below.

[0011] In embodiments of this disclosure, a display device is provided, comprising: a substrate including a display area, wherein an emitting region is disposed in the display area; a circuit layer disposed on the substrate; and a component layer disposed on the circuit layer. The component layer includes light-emitting elements disposed in each of the emitting regions. The circuit layer includes: light-emitting pixel drivers disposed in a first direction and a second direction intersecting the first direction, and transmitting driving current to the light-emitting elements; a first power main line extending in the second direction and transmitting first power to at least some of the light-emitting pixel drivers; and a second power main line extending in the second direction and transmitting second power, different from the first power, to some other light-emitting pixel drivers.

[0012] The emitting region includes a first emitting region, a second emitting region, and a third emitting region that emit light at different wavelengths. The light-emitting pixel driver includes: a first light-emitting pixel driver electrically connected to the light-emitting element in the first emitting region; a second light-emitting pixel driver electrically connected to the light-emitting element in the second emitting region; and a third light-emitting pixel driver electrically connected to the light-emitting element in the third emitting region. A first power main line is electrically connected to the first and second light-emitting pixel drivers. A second power main line is electrically connected to the third light-emitting pixel driver.

[0013] Each of the light-emitting pixel drivers includes: a first transistor that generates a drive current; a first capacitor electrically connected to the gate electrode of the first transistor; a second transistor electrically connected between a data line transmitting a data signal and the first electrode of the first transistor; a third transistor electrically connected between the gate electrode and the second electrode of the first transistor; a fourth transistor electrically connected between a gate initialization voltage line transmitting a gate initialization voltage and the gate electrode of the first transistor; a fifth transistor electrically connected to the first electrode of the first transistor; and a sixth transistor electrically connected between the second electrode of the first transistor and an output node. The output node is electrically connected to one of the light-emitting elements. The fifth transistor of the first and second light-emitting pixel drivers is electrically connected to a first power main line. The fifth transistor of the third light-emitting pixel driver is electrically connected to a second power main line.

[0014] The circuit layer further includes: a first semiconductor layer disposed on a substrate; a first interlayer insulating layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the first interlayer insulating layer; a second interlayer insulating layer disposed on the second semiconductor layer; a first source / drain conductive layer disposed on the second interlayer insulating layer; a first planarization layer covering the first source / drain conductive layer; a second source / drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source / drain conductive layer. The channel portion, first electrode, and second electrode of each of the first transistor and the fifth transistor are disposed in the first semiconductor layer. The channel portion, first electrode, and second electrode of each of the third transistor and the fourth transistor are disposed in the second semiconductor layer.

[0015] Each of the first and second power lines is disposed in the second source-drain conductive layer. Each of the first and second light-emitting pixel drivers includes a first power connection electrode disposed in the first source-drain conductive layer and electrically connected to the first power line. The first electrode of the fifth transistor of each of the first and second light-emitting pixel drivers is electrically connected to the first power line via the first power connection electrode. The third light-emitting pixel driver includes a second power connection electrode disposed in the first source-drain conductive layer and electrically connected to the second power line. The first electrode of the fifth transistor of the third light-emitting pixel driver is electrically connected to the second power line via the second power connection electrode.

[0016] The first and third light-emitting pixel drivers are arranged alternately in a second direction. Multiple second light-emitting pixel drivers may be provided in a manner where they are arranged side-by-side in the second direction. The second light-emitting pixel drivers are disposed between the first and third light-emitting pixel drivers in a first direction. A first power main line crosses the second light-emitting pixel drivers. The second power main line crosses both the first and third light-emitting pixel drivers. The first power connection electrodes of the first and second light-emitting pixel drivers, which are adjacent to each other in the first direction, are connected to each other. The first power connection electrode of the first light-emitting pixel driver is electrically connected to the first power main line through the first power connection electrode of the second light-emitting pixel driver, which is adjacent to the first light-emitting pixel driver in the first direction.

[0017] The circuit layer further includes a first power sub-line extending in a first direction and electrically connected to a first power main line. Each of the light-emitting pixel drivers intersects the first power sub-line. A first capacitor of each of the light-emitting pixel drivers is electrically connected to the first power sub-line.

[0018] The circuit layer further includes: a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; and a second gate conductive layer disposed between the second gate insulating layer and the first interlayer insulating layer. The gate electrode of the first transistor is disposed in the first gate conductive layer. A first power sub-line is disposed in the second gate conductive layer and electrically connected to the first power main line via a first power connection electrode. Each of the light-emitting pixel drivers further includes a capacitor electrode disposed in the second gate conductive layer and overlapping the gate electrode of the first transistor in a third-direction orientation. The capacitor electrode is the portion of the first power sub-line that overlaps with the gate electrode of the first transistor. The first capacitor is formed in the region where the gate electrode of the first transistor and the capacitor electrode overlap each other in a third-direction orientation.

[0019] The circuit layer further includes: a first power sub-line extending in a first direction and electrically connected to a first power main line; and a second power sub-line extending in the first direction and electrically connected to a second power main line. Between two adjacent light-emitting pixel drivers along a second direction, one light-emitting pixel driver crosses the first power sub-line, and the remaining (another) light-emitting pixel driver crosses the second power sub-line.

[0020] The first capacitor of one of the light-emitting pixel drivers is electrically connected to a first power line. The first capacitor of the remaining (other) light-emitting pixel driver is electrically connected to a second power line.

[0021] The circuit layer further includes: a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; and a second gate conductive layer disposed between the second gate insulating layer and the first interlayer insulating layer. The gate electrode of the first transistor is disposed in the first gate conductive layer. A first power sub-line and a second power sub-line are disposed in the second gate conductive layer. Each of the light-emitting pixel drivers further includes a capacitor electrode disposed in the second gate conductive layer and overlapping the gate electrode of the first transistor in a third-order upward direction. The first capacitor is formed in the region where the gate electrode of the first transistor and the capacitor electrode overlap each other. The capacitor electrode of one light-emitting pixel driver is part of the first power sub-line. The capacitor electrode of the remaining (another) light-emitting pixel driver is part of the second power sub-line.

[0022] The first capacitor of the first light-emitting pixel driver and the first capacitor of the second light-emitting pixel driver are electrically connected to the first power main line. The first capacitor of the third light-emitting pixel driver is electrically connected to the second power main line.

[0023] The circuit layer further includes: a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed between the second gate insulating layer and the first interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; and a third gate conductive layer disposed between the third gate insulating layer and the second interlayer insulating layer. The gate electrode of the first transistor is disposed in the first gate conductive layer. Each of the light-emitting pixel drivers further includes a capacitor electrode disposed in an island shape in the second gate conductive layer and overlapping the gate electrode of the first transistor in a third-direction orientation. The first capacitor is formed in the region where the gate electrode of the first transistor and the capacitor electrode overlap each other. A first power sub-line and a second power sub-line are disposed in the third gate conductive layer. The first power sub-line, the capacitor electrode of the first light-emitting pixel driver, and the capacitor electrode of the second light-emitting pixel driver are electrically connected to a first power main line via a first power connection electrode. The second power sub-line and the capacitor electrode of the third light-emitting pixel driver are electrically connected to a second power main line via a second power connection electrode.

[0024] The first emitting region emits light in a first wavelength band. The second emitting region emits light in a second wavelength band lower than the first wavelength band. The third emitting region emits light in a third wavelength band lower than the second wavelength band. Each of the light-emitting elements includes an anode electrode and a cathode electrode facing each other in a third direction perpendicular to the first and second directions, and an organic layer disposed between the anode electrode and the cathode electrode. Each of the organic layers of the light-emitting elements in the first and second emitting regions includes a light-emitting stack. The organic layer of the light-emitting element in the third emitting region includes two or more light-emitting stacks and at least one carrier generation layer disposed between the two or more light-emitting stacks. Each of the two or more light-emitting stacks and each of the light-emitting stacks includes a light-emitting layer in which electron-hole pairs are converted into light.

[0025] In embodiments of this disclosure, an electronic device is provided, comprising: a display device for displaying images; a memory for storing application programs; a processor for executing the application programs and transmitting image data signals and input control signals to the display device; and a power module for transmitting power to the display device. The display device includes: a substrate including a display area, with an emitting area disposed in the display area; a circuit layer disposed on the substrate; and a component layer disposed on the circuit layer. The component layer includes light-emitting elements disposed in each of the emitting areas. The circuit layer includes: light-emitting pixel drivers disposed in a first direction and a second direction, transmitting driving current to the light-emitting elements; a first power main line extending in the second direction, transmitting first power to at least some of the light-emitting pixel drivers; and a second power main line extending in the second direction, transmitting second power, different from the first power, to some other light-emitting pixel drivers. The emitting areas include a first emitting area, a second emitting area, and a third emitting area that emit light of different wavelengths. The light-emitting pixel drivers include: a first light-emitting pixel driver electrically connected to a light-emitting element in the first emitting area; a second light-emitting pixel driver electrically connected to a light-emitting element in the second emitting area; and a third light-emitting pixel driver electrically connected to a light-emitting element in the third emitting area. The first power main line is electrically connected to the first and second light-emitting pixel drivers. The second power main line is electrically connected to the third light-emitting pixel driver.

[0026] Each of the light-emitting pixel drivers includes: a first transistor generating a drive current; a first capacitor electrically connected to the gate electrode of the first transistor; a second transistor electrically connected between a data line transmitting a data signal and the first electrode of the first transistor; a third transistor electrically connected between the gate electrode and the second electrode of the first transistor; a fourth transistor electrically connected between a gate initialization voltage line transmitting a gate initialization voltage and the gate electrode of the first transistor; a fifth transistor electrically connected to the first electrode of the first transistor; and a sixth transistor electrically connected between the second electrode of the first transistor and an output node. The output node is electrically connected to one of the light-emitting elements. The circuit layer further includes: a first semiconductor layer disposed on a substrate; a first interlayer insulating layer disposed on the first semiconductor layer; a second semiconductor layer disposed on the first interlayer insulating layer; a second interlayer insulating layer disposed on the second semiconductor layer; a first source-drain conductive layer disposed on the second interlayer insulating layer; a first planarization layer covering the first source-drain conductive layer; a second source-drain conductive layer disposed on the first planarization layer; and a second planarization layer covering the second source-drain conductive layer. The channel portion, first electrode, and second electrode of each of the first and fifth transistors are arranged in the first semiconductor layer. A first power main line and a second power main line are disposed in a second source-drain conductive layer. Each of the first and second light-emitting pixel drivers includes a first power connection electrode disposed in the first source-drain conductive layer and electrically connected to the first power main line. The first electrode of the fifth transistor of each of the first and second light-emitting pixel drivers is electrically connected to the first power main line through the first power connection electrode. The third light-emitting pixel driver includes a second power connection electrode disposed in the first source-drain conductive layer and electrically connected to the second power main line. The first electrode of the fifth transistor of the third light-emitting pixel driver is electrically connected to the second power main line through the second power connection electrode.

[0027] The circuit layer further includes: a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed between the second gate insulating layer and the first interlayer insulating layer; and a first power sub-line extending in a first direction, disposed in the second gate conductive layer, and electrically connected to the first power main line via a first power connection electrode. Each of the light-emitting pixel drivers intersects the first power sub-line. A first capacitor of each of the light-emitting pixel drivers is electrically connected to the first power sub-line.

[0028] The circuit layer further includes: a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed between the second gate insulating layer and the first interlayer insulating layer; a first power sub-line extending in a first direction, disposed in the second gate conductive layer, and electrically connected to the first power main line via a first power connection electrode; and a second power sub-line extending in the first direction, disposed in the second gate conductive layer, and electrically connected to the second power main line via a second power connection electrode. Between two adjacent light-emitting pixel drivers along a second direction, one light-emitting pixel driver intersects the first power sub-line, and the remaining (another) light-emitting pixel driver intersects the second power sub-line. The gate electrode of the first transistor is disposed in the first gate conductive layer. Each of the light-emitting pixel drivers further includes a capacitor electrode disposed in the second gate conductive layer and overlapping the gate electrode of the first transistor in a third direction. The first capacitor is formed in the region where the gate electrode of the first transistor and the capacitor electrode overlap each other. The capacitor electrode of the light-emitting pixel driver is part of the first power sub-line. The capacitor electrode of the remaining (another) luminescent pixel driver is part of the second power sub-line.

[0029] The circuit layer further includes: a first power sub-line extending in a first direction and electrically connected to a first power main line; and a second power sub-line extending in the first direction and electrically connected to a second power main line. Between two adjacent light-emitting pixel drivers along a second direction, one light-emitting pixel driver crosses the first power sub-line, and the remaining (another) light-emitting pixel driver crosses the second power sub-line. A first capacitor of the first light-emitting pixel driver and a first capacitor of the second light-emitting pixel driver are electrically connected to the first power main line via a first power connection electrode. A first capacitor of the third light-emitting pixel driver is electrically connected to the second power main line via a second power connection electrode.

[0030] The circuit layer further includes: a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer disposed on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer disposed between the second gate insulating layer and the first interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; and a third gate conductive layer disposed between the third gate insulating layer and the second interlayer insulating layer. The gate electrode of the first transistor is disposed in the first gate conductive layer. Each of the light-emitting pixel drivers further includes a capacitor electrode disposed in an island shape in the second gate conductive layer and overlapping the gate electrode of the first transistor in a third-direction orientation. The first capacitor is formed in the region where the gate electrode of the first transistor and the capacitor electrode overlap each other. A first power sub-line and a second power sub-line are disposed in the third gate conductive layer. The first power sub-line, the capacitor electrode of the first light-emitting pixel driver, and the capacitor electrode of the second light-emitting pixel driver are electrically connected to a first power main line via a first power connection electrode. The second power sub-line and the capacitor electrode of the third light-emitting pixel driver are electrically connected to a second power main line via a second power connection electrode.

[0031] The display device in the embodiment includes a circuit layer disposed on a substrate, and the circuit layer includes a light-emitting pixel driver for transmitting driving current to a light-emitting element, a first power main line for transmitting a first power to some of the light-emitting pixel drivers, and a second power main line for transmitting a second power different from the first power to some of the other light-emitting pixel drivers.

[0032] In this way, some of the light-emitting pixel drivers in the light-emitting pixel driver can generate a drive current corresponding to the first power, while some of the other light-emitting pixel drivers in the light-emitting pixel driver can generate a drive current corresponding to the second power.

[0033] Accordingly, the light-emitting elements electrically connected to some other light-emitting pixel drivers in the light-emitting pixel driver can be driven by a driving current corresponding to the second power, thereby increasing the brightness and improving the display quality of the display device.

[0034] Furthermore, one of the first and second power supplies can be selected based on the voltage-current characteristics of the light-emitting element, so that the power consumption of the display device is not unnecessarily reduced. As a result, the power consumption of the display device and the electronic devices including the display device can be reduced.

[0035] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be apparent to those skilled in the art from the following description. Attached Figure Description

[0036] The above and other advantages and features of this disclosure will become more apparent from the detailed description of embodiments thereof with reference to the accompanying drawings, in which:

[0037] Figure 1 This is a perspective view illustrating an embodiment of the electronic device;

[0038] Figure 2 yes Figure 1 An exploded perspective view of the electronic device shown in the image;

[0039] Figure 3 It is a diagram. Figure 2 A plan view of the display device;

[0040] Figure 4 It is along Figure 3 A cross-sectional view taken from line A-A';

[0041] Figure 5 It is shown Figure 3 A schematic diagram of part B;

[0042] Figure 6 It is along Figure 5 A cross-sectional view taken from line C-C';

[0043] Figure 7 It is shown in detail Figure 6 A cross-sectional view of the first light-emitting element;

[0044] Figure 8 It is shown in detail Figure 6 A cross-sectional view of the third light-emitting element;

[0045] Figure 9 It is shown Figure 2 A block diagram of a display device;

[0046] Figure 10 It is shown Figure 5 An equivalent circuit diagram of an embodiment of the first light-emitting pixel driver;

[0047] Figure 11 It is shown Figure 5 An equivalent circuit diagram of an embodiment of the third light-emitting pixel driver;

[0048] Figure 12 It is shown Figure 5 A schematic diagram of an embodiment of the circuit layer of part D;

[0049] Figures 13 to 19 It is shown Figure 12 In the embodiments Figure 5 A plan view of an embodiment of the circuit layer of part D in the diagram;

[0050] Figure 20 It is along Figure 19 A cross-sectional view taken from line E-E';

[0051] Figure 21 It is along Figure 19 A cross-sectional view taken by line F-F';

[0052] Figure 22 It is shown Figure 5 A schematic diagram of an embodiment of the circuit layer of part D;

[0053] Figure 23 and Figure 24 It is shown Figure 5 A plan view of an embodiment of the circuit layer of part D;

[0054] Figure 25 It is along Figure 24 A cross-sectional view taken from line G-G';

[0055] Figure 26 It is along Figure 24 A cross-sectional view taken by line H-H';

[0056] Figure 27 It is shown Figure 5 A schematic diagram of an embodiment of the circuit layer of part D;

[0057] Figure 28 , Figure 29 , Figure 30 and Figure 31 It is shown Figure 5 A schematic diagram of an embodiment of the circuit layer of part D;

[0058] Figure 32 It is along Figure 31 A cross-sectional view taken from line I-I';

[0059] Figure 33 It is along Figure 31 A cross-sectional view taken from line J-J';

[0060] Figure 34 This is a block diagram of an embodiment of an electronic device; and

[0061] Figure 35 This is a schematic diagram of an embodiment of an electronic device. Detailed Implementation

[0062] In the following description, embodiments will now be described more fully with reference to the accompanying drawings. However, embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals denote the same parts. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

[0063] In order to describe embodiments of this disclosure, some parts that are not related to the description may not be provided.

[0064] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it may be directly on that other layer or substrate, or an intermediary layer may be present. In contrast, when an element is referred to as being "directly on" another element, an intermediary element may not be present.

[0065] Furthermore, the phrase "in a plan view" means when viewing a portion of the object from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting the portion of the object from the side. The terms "overlapping" or "overlapping" mean that the first object may be above, below, or to the side of the second object, and vice versa. Additionally, the term "overlapping" can include layering, stacking, facing, extending over, covering, or partially covering, or any other suitable terminology that will be understood and appreciated by one of ordinary skill in the art. The expression "non-overlapping" can include meanings such as "separated from," "set to one side," or "offset from," and any other suitable equivalent that will be understood and appreciated by one of ordinary skill in the art. The term "facing" can mean that the first object may be directly or indirectly opposite the second object. In the case where a third object is located between the first and second objects, the first and second objects can be understood as indirectly opposite each other, although still facing each other.

[0066] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” or “higher” are used herein to describe the relationship between one element or component shown in the accompanying drawings and another. It will be understood that, in addition to the orientation depicted in the drawings, spatial relative terms are intended to include different orientations of the device in use or operation. For example, in the case where the device shown in the drawings is flipped, a device located “below” or “under” another device may be located “above” another device. Accordingly, the illustrative term “below” may include both a lower and a higher position. The device may also be oriented in other directions, and therefore the spatial relative terms may be interpreted differently depending on the orientation.

[0067] When an element is referred to as being “connected” or “linked” to another element, the element may be “directly connected” or “directly linked” to the other element, or “electrically connected” or “electrically linked” to the other element, with one or more intermediary elements in between. It will be further understood that when the terms “comprising,” “having,” and / or “including” are used, they may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0068] It will be understood that although the terms “first,” “second,” or “third,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another, or for the convenience of their description and explanation. For example, when “first element” is discussed in the specification, it may be referred to as “second element” or “third element,” and “second element” and “third element” may be named in a similar manner without departing from the teachings of this document.

[0069] Given the measurements discussed and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the terms “approximately” or “about” as used herein include the stated value and mean within an acceptable range of deviation from that particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0070] In the specification and claims, the term "and / or" is intended to include any combination of the terms "and" and "or" for its meaning and interpretation. For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in combined or separate meanings and can be understood as equivalent to "and / or". In the specification and claims, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." for its meaning and interpretation. For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0071] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an ideal or overly formal sense unless explicitly defined in the specification.

[0072] In the following description, embodiments will be illustrated with reference to the accompanying drawings.

[0073] Figure 1 This is a perspective view illustrating an embodiment of an electronic device. Figure 2 yes Figure 1 An exploded perspective view of the electronic device shown in the image.

[0074] refer to Figure 1The electronic device 10 in the embodiments is a device having the function of displaying images in a display area. The electronic device 10 can provide portability. In embodiments, for example, the electronic device 10 can be a portable electronic device such as a mobile phone, smartphone, tablet PC (“PC”), smartwatch, watch phone, mobile communication terminal, e-notebook, e-book reader, portable multimedia player (“PMP”), navigation device, laptop computer, and ultra-mobile PC (“UMPC”).

[0075] The electronic device 10 in the embodiments is not limited to portable electronic devices, but can be a large device such as a television, monitor, billboard and Internet of Things (“IoT”) device.

[0076] The electronic device 10 may have a shape close to a quadrilateral (e.g., a rectangle) in a plan view. In an embodiment, the electronic device 10 may have a quadrilateral shape (e.g., a rectangle) in a plan view, the quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle or may be rounded with a selected curvature. The planar shape of the electronic device 10 is not limited to a quadrilateral shape (e.g., a rectangle), and may be formed into another polygonal shape, a circular shape, or an elliptical shape.

[0077] In this disclosure, the first direction DR1 can be a direction parallel to the short side of the electronic device 10 in a plan view, that is, the horizontal direction of the electronic device 10. The second direction DR2 can be a direction parallel to the long side of the electronic device 10 in a plan view, that is, the vertical direction of the electronic device 10. The third direction DR3 can be the thickness direction of the electronic device 10.

[0078] The electronic device 10 in the embodiments may include a display device 100 (see reference). Figure 2 ) and provided for protecting display device 100 (reference) Figure 2 The outer shell of the ) includes the cover window 11 and the lower cover 12.

[0079] refer to Figure 2 The electronic device 10 may further include a bracket 13 and a main circuit board 14 housed between the cover window 11 and the lower cover 12.

[0080] The electronic device 10 may include a display surface on which a display area DA for displaying images is disposed.

[0081] The display device 100 may include a display area DA that emits light toward the display surface of the electronic device 10.

[0082] A cover window 11 can be disposed on the display device 100 to cover the top surface of the display device 100. The cover window 11 can be used to protect the top surface of the display device 100.

[0083] The cover window 11 may include a transparent light-transmitting portion and an opaque light-blocking portion.

[0084] The light-transmitting portion of the cover window 11 can overlap with the display area DA of the display device 100 on the third-direction DR3, and the light-blocking portion of the cover window 11 can overlap with the non-display area NDA of the display device 100 on the third-direction DR3.

[0085] The cover window 11 may include a top surface portion forming the top surface of the electronic device 10, a left surface portion forming the left side surface of the electronic device 10, and a right surface portion forming the right side surface of the electronic device 10. The left surface portion of the cover window 11 may extend from the left side of the top surface portion, and the right surface portion of the cover window 11 may extend from the right side of the top surface portion.

[0086] Each of the top surface portion, left surface portion, and right surface portion of the cover window 11 may include a light-transmitting portion and a light-blocking portion.

[0087] The light-transmitting portion of the cover window 11 can be located on a large portion of each of the top surface portion, left surface portion, and right surface portion of the cover window 11.

[0088] The light-blocking portion of the cover window 11 can be provided at the upper and lower edges of the top surface portion of the cover window 11, the upper, left and lower edges of the left surface portion of the cover window 11, and the upper, right and lower edges of the right surface portion of the cover window 11.

[0089] The display device 100 may include a top surface portion facing the top surface portion of the cover window 11, a left surface portion facing the left surface portion of the cover window 11, and a right surface portion facing the right surface portion of the cover window 11. The left surface portion of the display device 100 may extend from the left side of the top surface portion of the display device 100, and the right surface portion of the display device 100 may extend from the right side of the top surface portion of the display device 100.

[0090] The display device 100 may include a display area DA for displaying images.

[0091] Each of the top surface portion, left surface portion, and right surface portion of the display device 100 may include a display area DA.

[0092] The display area DA can be disposed on a large portion of each of the top surface portion, left surface portion, and right surface portion of the display device 100.

[0093] The display device 100 may further include a display driving circuit 200, a display circuit board 300, a touch driving circuit 400, and a cable 500 extending from one side of the display circuit board 300.

[0094] The bracket 13 can be positioned below the display device 100.

[0095] The bracket 13 may be made of plastic, metal, or both. A first camera hole CMH1 into which the camera device 16 is inserted, a battery hole BH for holding the battery 18, and a cable hole CAH that serves as a channel for the cable 500 connected to the display circuit board 300 may be defined in the bracket 13.

[0096] The main circuit board 14 and the battery 18 can be disposed below the bracket 13. The main circuit board 14 can be a rigid printed circuit board or a flexible printed circuit board.

[0097] The main processor 15, camera device 16 and main connector 17 can be set (e.g., mounted) on the main circuit board 14.

[0098] The camera device 16 can be disposed on the top and bottom surfaces of the main circuit board 14, the main processor 15 can be disposed on the top surface of the main circuit board 14, and the main connector 17 can be disposed on the bottom surface of the main circuit board 14.

[0099] The main processor 15 can control all the functions of the electronic device 10.

[0100] In one embodiment, for example, the main processor 15 can output digital video data to the display driver circuit 200 via the display circuit board 300, causing the display device 100 to display an image. Additionally, the main processor 15 can receive touch data including the user's touch coordinates from the touch driver circuit 400, determine whether the user has touched or approached the device, and then execute an operation corresponding to the user's touch or proximity input. In another embodiment, for example, the main processor 15 can execute an operation or execute an application indicated by an icon touched by the user.

[0101] The main processor 15 may be an application processor, central processing unit, or system chip that includes integrated circuits.

[0102] The camera device 16 can process still images or video frames obtained by the image sensor in camera mode and output the image frames to the main processor 15.

[0103] The cable 500, having passed through the cable hole CAH in the bracket 13, can be connected to the main connector 17. Therefore, the main circuit board 14 can be electrically connected to the display circuit board 300.

[0104] Battery 18 can be spaced apart from main circuit board 14. That is, battery 18 can be mounted on third-party DR3 without overlapping with main circuit board 14. Battery 18 can be mounted on third-party DR3 in battery hole BH of bracket 13.

[0105] Additionally, the main circuit board 14 may be further equipped with a mobile communication module capable of transmitting and receiving radio signals with at least one of a base station, an external terminal, and a server in a mobile communication network. Depending on the transmission and reception of voice signals, video call signals, or text / multimedia messages, the radio signals may include various types of data.

[0106] The lower cover 12 can be disposed below the main circuit board 14 and the battery 18. The lower cover 12 can be secured by fastening it to the bracket 13. The lower cover 12 can form the upper surface, lower surface, and bottom surface of the electronic device 10. The lower cover 12 can be made of plastic, metal, or both plastic and metal.

[0107] The second camera aperture CMH2 can be confined in the lower cover 12, and the bottom surface of the camera device 16 is exposed through the second camera aperture CMH2.

[0108] However, the positions of the first camera hole CMH1 and the second camera hole CMH2 are not limited to... Figure 2 The location shown in the image.

[0109] Next, the display device 100 in the embodiments will be described.

[0110] Figure 3 It is a diagram. Figure 2 A plan view of the display device. Figure 4 It is along Figure 3 A cross-sectional view taken from line A-A'.

[0111] refer to Figure 3 and Figure 4 The display device 100 in the embodiments may be an organic light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, and a light-emitting display device using ultra-miniature light-emitting diodes (micron or nano light-emitting diodes (micron LEDs or nano LEDs)). In the following description, it is assumed that the display device 100 is an organic light-emitting display device. However, this disclosure is not limited thereto and can be applied to display devices including organic insulating materials, organic light-emitting materials, and metallic materials.

[0112] The display device 100 may be flat, but is not limited thereto. In embodiments, for example, the display device 100 may include curved portions formed at the left and right ends and having a constant or varying curvature. Additionally, the display device 100 may be flexible, allowing it to be bent, folded, or rolled.

[0113] refer to Figure 3 At least one surface of the display device 100 includes a main region MA from which light for displaying an image is emitted.

[0114] In the planar view, the display area DA can be formed as a quadrilateral shape, such as a rectangle having a short side in a first direction DR1 and a long side in a second direction DR2 that intersects the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be rounded to have a selected curvature, or they can be right angles. The planar shape of the display area DA is not limited to a quadrilateral shape (e.g., a rectangular shape), and can be formed as another polygonal shape, a circular shape, or an elliptical shape.

[0115] The display area DA can be set within most of the main area MA. Alternatively, the display area DA can be set at the center of the main area MA.

[0116] The non-display area NDA can be set around the display area DA. In other words, the display area DA can be surrounded by the non-display area NDA.

[0117] The display device 100 may include a substrate 110 comprising a main region MA and a sub-region SBA.

[0118] refer to Figure 4 The subregion SBA can protrude from at least a portion of one side of the main region MA in the second direction DR2.

[0119] Since a portion of the sub-region SBA is transformed into a bent shape, another portion of the sub-region SBA can be disposed on the rear surface of the display device 100.

[0120] In an embodiment, the display device 100 includes a substrate 110, a circuit layer 120 disposed on the substrate 110, and a component layer 130 disposed on the circuit layer 120.

[0121] The display device 100 may further include an encapsulation layer 140 disposed on the component layer 130 and a touch sensor layer 150 disposed on the encapsulation layer 140.

[0122] The display device 100 may further include a polarization layer 160 disposed on the touch sensor layer 150 to reduce the reflection of external light.

[0123] The substrate 110 may include a main region MA corresponding to the display surface and a sub-region SBA protruding from at least a portion of one side of the main region MA in the second direction DR2.

[0124] The main area MA may include the display area DA that emits light from it and the non-display area NDA that is disposed around the display area DA.

[0125] Component layer 130 may include components arranged in the emitter region EA (reference). Figure 5 The light-emitting element LE in ) (reference) Figure 6 ).

[0126] Circuit layer 120 may include a light-emitting pixel driver EPD electrically connected to the light-emitting element LE (reference). Figure 5 ).

[0127] Encapsulation layer 140 may cover component layer 130. Encapsulation layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are stacked alternately.

[0128] The touch sensor layer 150 may be disposed on the encapsulation layer 140 and may correspond to the main region MA. The touch sensor layer 150 may include touch electrodes for sensing the touch of a person or object.

[0129] The polarization layer 160 blocks external light reflected from the touch sensor layer 150, the encapsulation layer 140, the component layer 130, and the circuit layer 120 and their interfaces, and this is to prevent a reduction in image visibility due to external light reflection.

[0130] Since a portion of the sub-region SBA is transformed into a bent shape, the display driver circuit 200 disposed (e.g., mounted) in the sub-region SBA and the display circuit board 300 connected to one side of the sub-region SBA can be disposed under the substrate 110.

[0131] The display driver circuit 200 can be electrically connected to the data line DL of the circuit layer 120 (reference). Figure 9 The display driving circuit 200 can, based on control signals supplied from the display board 300, as well as power and voltage, drive the light-emitting pixel driver EPD (reference). Figure 5 and Figure 9 The data signal Vdata (reference) Figure 10 and Figure 11 Transmitted to the data line DL.

[0132] The display driving circuit 200 may be provided as an integrated circuit (“IC”) and disposed (e.g., mounted) on a sub-region SBA of the display device 100 by a chip-on-glass (“COG”) method, a chip-on-plastic (“COP”) method, or an ultrasonic method. However, this is merely an illustrative embodiment, and the present disclosure is not limited thereto. In embodiments, for example, the display driving circuit 200 may be disposed (e.g., mounted) on a display circuit board 300.

[0133] One end of the display circuit board 300 can be attached to a pad on one edge of the sub-region SBA of the display device 100 via an anisotropic conductive film.

[0134] The display circuit board 300 may be a flexible printed circuit board (“FPCB”), a rigid printed circuit board (“PCB”) that maintains a flat shape, or a composite printed circuit board that has both a rigid printed circuit board and a flexible printed circuit board.

[0135] The display board 300 can be connected to the signal pads located on one side of the sub-area SBA.

[0136] The touch driver circuit 400 can be set (e.g., mounted) on the display board 300.

[0137] The touch driver circuit 400 can be electrically connected to the touch sensor layer 150.

[0138] The touch driving circuit 400 can apply a touch driving signal to the driving line of the touch sensor layer 150 and receive a touch sensing signal from the sensing line. Furthermore, the touch driving circuit 400 can detect the amount of charge change in a capacitor based on the touch sensing signal to determine whether a user has touched or approached the device.

[0139] A user's touch means that an object such as a pen or the user's finger comes into direct contact with the top surface of the cover window located on the touch sensor layer 150. A user's proximity means that an object such as a pen or the user's finger hovers over the top surface of the cover window.

[0140] The touch driver circuit 400 can output touch data, including the user's touch coordinates, to the main processor 15 (reference). Figure 2 ).

[0141] Figure 5 It is shown Figure 3 A schematic diagram of part B. Figure 6 It is along Figure 5 The cross-sectional view taken from line C-C'.

[0142] like Figure 5 As shown, the display area DA may include the emission area EA.

[0143] The display area DA can be further included as a separation area between the emission areas EA and a non-emitting area NEA that does not emit light.

[0144] Light used for image display can be emitted through the emission zone EA.

[0145] Each of the emission regions EA can be a unit region that emits light in a wavelength band corresponding to one of two or more different colors with a brightness corresponding to the image signal.

[0146] Each of the launch areas EA can be arranged in a quadrilateral shape.

[0147] However, this is merely an illustrative embodiment, and the planar shape of the emission region EA in the embodiment is not limited to... Figure 5 The shape shown in the diagram. That is, in a planar diagram, the emission area EA can be circular, elliptical, or a polygonal shape such as a rectangle, square, hexagon, or octagon, but not a rhombus.

[0148] The emission zone EA may include a first emission zone EA1 that emits light in the first band, a second emission zone EA2 that emits light in the second band below the first band, and a third emission zone EA3 that emits light in the third band below the second band.

[0149] In an embodiment, for example, the first band may be from about 600 nanometers (nm) to about 750 nm and may correspond to red. The second band may be from about 480 nm to about 560 nm and may correspond to green. The third band may be from about 370 nm to about 460 nm and may correspond to blue.

[0150] However, this is merely an illustrative embodiment, and the first, second, and third bands in the embodiment are not limited thereto.

[0151] Since the emission area EA includes a first emission area EA1, a second emission area EA2, and a third emission area EA3, each unit pixel PX can be provided by a combination of one or more first emission areas EA1, one or more second emission areas EA2, and one or more third emission areas EA3 that are adjacent to each other in the emission areas EA.

[0152] Each of the unit pixels PX can be a unit for displaying various colors, including white. That is, the various colors of light displayed by the unit pixel PX can be implemented as a combination of light emitted from two or more emission regions EA included in each unit pixel PX.

[0153] The third transmission region EA3 may have a wider width than the first transmission region EA1, and the first transmission region EA1 may have a wider width than the second transmission region EA2. However, this is merely one embodiment, and the width of each of the transmission regions EA is not limited to this. Figure 5 The width shown in the diagram.

[0154] The first launch area EA1 and the third launch area EA3 can be arranged alternately in the first direction DR1 and the second direction DR2.

[0155] The second launch area EA2 can be set side by side with each other in the first direction DR1 and the second direction DR2.

[0156] Each of the second launch zones EA2 can be adjacent to the first launch zone EA1 or the third launch zone EA3 on the diagonal directions DR4 and DR5 that intersect the first direction DR1 and the second direction DR2.

[0157] In this configuration, each of the unit pixels PX may include a first emission region EA1 and a third emission region EA3 that are adjacent to each other in the first direction DR1, and two second emission regions EA2 that are adjacent to the first emission region EA1 and the third emission region EA3 in the diagonal directions DR4 and DR5. However, this is merely an illustrative embodiment, and the arrangement of the emission regions EA and the components of the unit pixel PX in the embodiment are not limited to those described above.

[0158] refer to Figure 6 In an embodiment, element layer 130 may include light-emitting elements LE arranged in the emission region EA.

[0159] The light-emitting element LE may include a first light-emitting element LE1 disposed in a first emission region EA1, a second light-emitting element LE2 disposed in a second emission region EA2, and a third light-emitting element LE3 disposed in a third emission region EA3.

[0160] The first light-emitting element LE1 can emit light in the first wavelength band.

[0161] The second light-emitting element LE2 can emit light in the second wavelength band.

[0162] The third light-emitting element LE3 can emit light in the third wavelength band.

[0163] like Figure 5 As shown, in this embodiment, circuit layer 120 (reference) Figure 4 It may include a light-emitting pixel driver EPD arranged on the first direction DR1 and the second direction DR2.

[0164] The light-emitting pixel driver EPD can separately drive the current Idr (reference) Figure 10 and Figure 11 Transmitted to component layer 130 (reference) Figure 4 The light-emitting element LE (reference) Figure 6 ).

[0165] The light-emitting pixel driver EPD may include a first light-emitting element LE1 (reference) Figure 6 The first light-emitting pixel driver EPD1 is electrically connected to the second light-emitting element LE2 (reference). Figure 6 The second light-emitting pixel driver EPD2 is electrically connected to the third light-emitting element LE3 (reference). Figure 6 The third luminescent pixel driver EPD3.

[0166] The first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3 can be arranged alternately on the second direction DR2.

[0167] The second light-emitting pixel driver EPD2 can be arranged side by side on the second direction DR2.

[0168] Each of the second light-emitting pixel drivers EPD2 can be positioned on the first direction DR1 between the first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3.

[0169] like Figure 6 As shown, the element layer 130 may include light-emitting elements LE respectively disposed in the emission region EA.

[0170] Each of the light-emitting elements (LE) can be an organic light-emitting diode (OLED) that includes an organic layer of organic light-emitting material.

[0171] In alternative embodiments, each of the light-emitting elements LE may be an inorganic light-emitting element having a light-emitting layer including an inorganic semiconductor, a quantum dot light-emitting element having a quantum dot light-emitting layer, and a micron-sized light-emitting diode.

[0172] In an embodiment, each of the light-emitting elements LE may include an anode electrode 131 and a cathode electrode 132 opposite to each other, and an organic layer 133 disposed between the anode electrode 131 and the cathode electrode 132.

[0173] In another embodiment, each of the light-emitting elements LE may further include a first common layer 134 disposed between the anode electrode 131 and the organic layer 133 and a second common layer 135 disposed between the organic layer 133 and the cathode electrode 132.

[0174] The first common layer 134 may include, or may be composed of, an organic material for injecting holes.

[0175] The second common layer 135 may include, or may be composed of, an organic material for electron injection.

[0176] In other words, the element layer 130 may include an anode electrode 131 disposed in the emission region EA, a pixel defining layer 136 disposed in the non-emission region NEA and covering the edge of the anode electrode 131, a first common layer 134 disposed on the anode electrode 131, an organic layer 133 disposed on the first common layer 134, a second common layer 135 disposed on the organic layer 133 and the pixel defining layer 136, and a cathode electrode 132 disposed on the second common layer 135.

[0177] Anode electrodes 131 can be disposed in the emission region EA and can be electrically connected to the light-emitting pixel driver EPD of circuit layer 120 (reference). Figure 5 The anode electrode 131 can also be referred to as the pixel electrode.

[0178] The pixel-defining layer 136 may include an organic insulating material.

[0179] Each of the organic layers 133 may include at least one light-emitting stack, ESTA (reference). Figure 7 ) or multiple light-emitting stacks ESTA1 and ESTA2 (see reference) Figure 8 At least one light-emitting stack (ESTA) (reference) Figure 7 ) and multiple light-emitting stacks ESTA1 and ESTA2 (reference) Figure 8 Each of these can include an EML (Emitting Layer) for converting electron-hole pairs into light (see reference). Figure 7 and Figure 8 ).

[0180] Cathode electrode 132 can be disposed in the emitter region EA and the non-emitter region NEA, and can be electrically connected to the third electric field line VSL (reference). Figure 10 and Figure 11 In other words, the cathode electrode 132 can be entirely disposed within the display area DA. The cathode electrode 132 can also be referred to as the common electrode.

[0181] The encapsulation layer 140 can be disposed on the circuit layer 120 and cover the component layer 130.

[0182] The encapsulation layer 140 may include a first encapsulation layer 141 that covers the element layer 130 and includes an inorganic insulating material or is composed of an inorganic insulating material, a second encapsulation layer 142 disposed on the first encapsulation layer 141 and including an organic insulating material or is composed of an organic insulating material, and a third encapsulation layer 143 that covers the second encapsulation layer 142 and includes an inorganic insulating material or is composed of an inorganic insulating material.

[0183] Figure 7 It is shown in detail Figure 6 A cross-sectional view of the first light-emitting element. Figure 8 It is shown in detail Figure 6 A cross-sectional view of the third light-emitting element.

[0184] As described above, the element layer 130 of the display device 100 in the embodiment includes a first emission region EA1 (reference). Figure 6 The first light-emitting element LE1 in ) (reference) Figure 6 ), set in the second launch area EA2 (reference) Figure 6 The second light-emitting element LE2 in ) (reference) Figure 6 ) and located in the third launch zone EA3 (reference) Figure 6 The third light-emitting element LE3 in ) (reference) Figure 6 ).

[0185] like Figure 7 and Figure 8 As shown in the embodiment, each of the first light-emitting element LE1 and the third light-emitting element LE3 may include an anode electrode 131 and a cathode electrode 132 opposite to each other on the third-direction DR3, and an organic layer 133, 133' disposed between the anode electrode 131 and the cathode electrode 132.

[0186] like Figure 7 As shown, the organic layer 133 of the first light-emitting element LE1 may include a single light-emitting stack ESTA.

[0187] A single light-emitting stack (ESTA) may include an emissive layer (EML) in which electron-hole pairs are converted into light.

[0188] A single light-emitting stack (ESTA) may further include a hole transport layer (HTL) disposed between the anode electrode 131 and the light-emitting layer (EML) and an electron transport layer (ETL) disposed between the light-emitting layer (EML) and the cathode electrode 132.

[0189] In the embodiment, the second light-emitting element LE2 (reference) Figure 6 ) can have with Figure 7 The structure of the first light-emitting element LE1 shown is the same as or similar to that shown in the figure, and therefore its redundant description will be omitted.

[0190] like Figure 8 As shown, the organic layer 133' of the third light-emitting element LE3 may include two or more light-emitting stacks ESTA1 and ESTA2 and at least one carrier generation layer CGL disposed between the two or more light-emitting stacks ESTA1 and ESTA2.

[0191] Each of the two or more light-emitting stacks ESTA1 and ESTA2 may include a light-emitting layer EML in which electron-hole pairs are converted into light.

[0192] In an embodiment, two or more light-emitting stacks ESTA1 and ESTA2 may include a first light-emitting stack ESTA1 that is adjacent to the anode electrode 131 on the third-direction DR3 and a second light-emitting stack ESTA2 that is adjacent to the cathode electrode 132 on the third-direction DR3.

[0193] In an embodiment, the organic layer 133' of the third light-emitting element LE3 may include a carrier generation layer CGL disposed between the first light-emitting stack ESTA1 and the second light-emitting stack ESTA2.

[0194] In this case, the first light-emitting stack ESTA1 may further include a hole transport layer HTL disposed between the anode electrode 131 and the light-emitting layer EML, and an electron transport layer ETL disposed between the light-emitting layer EML and the carrier generation layer CGL.

[0195] In addition, the second light-emitting stack ESTA2 may further include a hole transport layer HTL disposed between the carrier generation layer CGL and the light-emitting layer EML, and an electron transport layer ETL disposed between the light-emitting layer EML and the cathode electrode 132.

[0196] The carrier generation layer CGL may include an n-type carrier generation layer NCGL adjacent to the anode electrode 131 on the third-direction DR3 and a p-type carrier generation layer PCGL adjacent to the cathode electrode 132 on the third-direction DR3.

[0197] In an embodiment, each of the first light-emitting element LE1 and the second light-emitting element LE2 includes a single light-emitting stack ESTA (reference). Figure 7 The third light-emitting element LE3 includes two or more light-emitting stacks ESTA1 and ESTA2 (see reference). Figure 8 Accordingly, the driving voltage of the third light-emitting element LE3 can be different from the driving voltage of the first light-emitting element LE1 and the driving voltage of the second light-emitting element LE2.

[0198] Figure 9 It is shown Figure 2 A block diagram of the display device.

[0199] refer to Figure 9 The circuit layer 120 of the display device 100 in the embodiment may include a light-emitting element LE (see reference) electrically connected to the emitting region EA disposed in the display region DA. Figure 6 EPD (Emitting Pixel Driver) of light-emitting pixels.

[0200] The light-emitting pixel driver EPD may include a first light-emitting element LE1 (reference) Figure 6 The first light-emitting pixel driver EPD1 is electrically connected to the second light-emitting element LE2 (reference). Figure 6 The second light-emitting pixel driver EPD2 is electrically connected to the third light-emitting element LE3 (reference). Figure 6 The third luminescent pixel driver EPD3.

[0201] In an embodiment, circuit layer 120 may further include a gate line GL for transmitting a gate signal to the light-emitting pixel driver EPD and a data signal Vdata (reference) for transmitting a data signal to the light-emitting pixel driver EPD. Figure 10 and Figure 11 The data is transmitted to the DL line of the luminous pixel driver EPD.

[0202] The display device 100 may further include components for controlling the light-emitting element LE (see reference). Figure 6 The brightness data signal Vdata for each of the following (reference) Figure 10 and Figure 11 The display driver circuit 200 outputs data to the data line DL.

[0203] The display device 100 may further include a gate drive circuit GTDR that outputs gate signals to gate lines GL, a power supply unit 700 that supplies various powers and voltages to the light-emitting pixel driver EPD, and a timing controller 800 that controls the driving timing of each of the display drive circuit 200 and the gate drive circuit GTDR.

[0204] The timing controller 800 receives image signals supplied from outside the display device 100.

[0205] The timing controller 800 can output image data and data control signals to the display driver circuit 200.

[0206] The timing controller 800 can generate scan control signals for controlling the operating timing of the gate drive circuit GTDR.

[0207] The display driver circuit 200 can convert image data into analog data voltage (corresponding to the data signal Vdata) and output the analog data voltage to the data line DL.

[0208] The gate drive circuit GTDR can generate gate signals in response to scan control signals and output the gate signals sequentially to the gate line GL.

[0209] In an embodiment, for example, the gate line GL may include a transfer scan write signal GW (reference). Figure 10 and Figure 11The scan write line GWL and the transmission gate control signal GC (reference) Figure 10 and Figure 11 The gate control line GCL and the transmission scan initialization signal GI (reference) Figure 10 and Figure 11 The scan initialization line GIL and the transmission control signal EC (reference) are used for scanning initialization. Figure 10 and Figure 11 The transmit control line ECL and the transmit bias control signal GB (reference) Figure 10 and Figure 11 The bias control line GBL.

[0210] The gate signal can have pulses that vary to either a first gate level voltage or a second gate level voltage.

[0211] The power supply unit 700 can supply various power and voltages required to drive the light-emitting pixel driver EPD.

[0212] In this embodiment, the power supply unit 700 may supply: a first power ELVDD1 for generating a drive signal transmitted to the light-emitting element LE (reference 1). Figure 10 and Figure 11 ), Second Power ELVDD2 (Reference) Figure 11 ) and the third power ELVSS (reference) Figure 10 and Figure 11 ); Gate initialization voltage VINT used to initialize the light-emitting pixel driver EPD (reference) Figure 10 and Figure 11 ) and bias voltage VBS (reference) Figure 10 and Figure 11 ); used to initialize the first light-emitting element LE1 (reference) Figure 6 ) and the second light-emitting element LE2 (reference) Figure 6 The first anode initialization voltage VAINT1 () Figure 10 ); and for initializing the third light-emitting element LE3 (see reference). Figure 6 The second anode initialization voltage VAINT2 (reference) Figure 11 ).

[0213] Figure 10 It is shown Figure 5 An equivalent circuit diagram of an embodiment of the first light-emitting pixel driver. Figure 11 It is shown Figure 5 An equivalent circuit diagram of an embodiment of the third light-emitting pixel driver.

[0214] refer to Figure 10 and Figure 11The first light-emitting pixel driver EPD1 can be electrically connected to the first light-emitting element LE1, and the third light-emitting pixel driver EPD3 can be electrically connected to the third light-emitting element LE3.

[0215] like Figure 10 and Figure 11 As shown, each of the first light-emitting element LE1 and the third light-emitting element LE3 may include an inherent parasitic capacitance Cel.

[0216] The first light-emitting pixel driver EPD1 can be electrically connected to the first power line VDL1 used to transmit the first power ELVDD1.

[0217] Since the second light-emitting element LE2 has a structure that is substantially the same as or similar to that of the first light-emitting element LE1, the second light-emitting pixel driver EPD2 can also have a structure that is substantially the same as or similar to that of the first light-emitting pixel driver EPD1. Accordingly, redundant descriptions will be omitted.

[0218] In the embodiment, since the third light-emitting element LE3 includes two or more light-emitting stacks ESTA1 and ESTA2 (see reference) Figure 8 Therefore, the third light-emitting pixel driver EPD3 can be further electrically connected to the second power line VDL2 for transmitting a second power line ELVDD2, which is different from the first power line ELVDD1.

[0219] In an embodiment, the second power source (hereinafter also referred to as the second power source) ELVDD2 may have a lower voltage level than the first power source (hereinafter also referred to as the first power source) ELVDD1.

[0220] Each of the first light-emitting element LE1 and the third light-emitting element LE3 can be electrically connected to a third power line VSL for transmitting a third power line ELVSS that is different from the first power line ELVDD1 and the second power line ELVDD2.

[0221] The third power source (hereinafter also referred to as the third power supply) ELVSS can have a lower voltage level than the first power supply ELVDD1 and the second power supply ELVDD2.

[0222] like Figure 10 As shown, the first light-emitting pixel driver EPD1 can be electrically connected to the first power line VDL1 for transmitting the first power ELVDD1, the data line DL for transmitting the data signal Vdata, the gate initialization voltage line VIL for transmitting the gate initialization voltage VINT, the first anode initialization voltage line VAIL1 for transmitting the first anode initialization voltage VAINT1, and the bias voltage line VBSL for transmitting the bias voltage VBS.

[0223] The first light-emitting pixel driver EPD1 can be electrically connected to the scan write line GWL for transmitting the scan write signal GW, the scan initialization line GIL for transmitting the scan initialization signal GI, the gate control line GCL for transmitting the gate control signal GC, the transmit control line ECL for transmitting the transmit control signal EC, and the bias control line GBL for transmitting the bias control signal GB.

[0224] The first light-emitting pixel driver EPD1 may include a first transistor T1 that generates a drive current Idr for driving the first light-emitting element LE1, two or more transistors (i.e., second transistors T2 to eighth transistors T8) electrically connected to the first transistor T1 or the first light-emitting element LE1, and at least one capacitor (i.e., first capacitor C1).

[0225] like Figure 10 and Figure 11 As shown in the embodiment, each of the first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3 may include a first transistor T1 that generates a drive current Idr, a first capacitor C1 electrically connected to the gate electrode of the first transistor T1, a second transistor T2 electrically connected between the data line DL that transmits the data signal Vdata and the first electrode of the first transistor T1, a third transistor T3 electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1, a fourth transistor T4 electrically connected between the gate initialization voltage line VIL that transmits the gate initialization voltage VINT and the gate electrode of the first transistor T1, a fifth transistor T5 electrically connected to the first electrode of the first transistor T1, and a sixth transistor T6 electrically connected between the second electrode of the first transistor T1 and the output node N_OUT.

[0226] Circuit layer 120 (reference) Figure 4 EMP (Reference) light-emitting pixel driver Figure 9 The output node N_OUT can be electrically connected to component layer 130 (reference). Figure 4 The light-emitting element LE (reference) Figure 6 ).

[0227] In other words, the light-emitting pixel driver EPD (reference) Figure 9 One of the output nodes N_OUT can be electrically connected to the light-emitting element LE (see reference). Figure 6 )one of the.

[0228] like Figure 10 As shown, the output node N_OUT of the first light-emitting pixel driver EPD1 can be electrically connected to the first light-emitting element LE1.

[0229] like Figure 11As shown, the output node N_OUT of the third light-emitting pixel driver EPD3 can be electrically connected to the third light-emitting element LE3.

[0230] like Figure 10 As shown, in this embodiment, the fifth transistor T5 of the first light-emitting pixel driver EPD1 can be electrically connected to the first power line VDL1 that transmits the first power ELVDD1. That is, the fifth transistor T5 of the first light-emitting pixel driver EPD1 can be electrically connected between the first power line VDL1 and the first electrode of the first transistor T1.

[0231] like Figure 11 As shown, in this embodiment, the fifth transistor T5 of the third light-emitting pixel driver EPD3 can be electrically connected to a second power line VDL2 that transmits a second power line ELVDD2 different from the first power line ELVDD1. That is, the fifth transistor T5 of the third light-emitting pixel driver EPD3 can be electrically connected between the second power line VDL2 and the first electrode of the first transistor T1.

[0232] like Figure 10 and Figure 11 As shown in the embodiment, each of the first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3 may further include a seventh transistor T7 electrically connected to the output node N_OUT and an eighth transistor T8 electrically connected between the bias voltage line VBSL, which transmits the bias voltage VBS, and the first electrode of the first transistor T1.

[0233] like Figure 10 As shown, in this embodiment, the seventh transistor T7 of the first light-emitting pixel driver EPD1 can be electrically connected to the first anode initialization voltage line VAIL1, which transmits the first anode initialization voltage VAINT1. That is, the seventh transistor T7 of the first light-emitting pixel driver EPD1 can be electrically connected between the first anode initialization voltage line VAIL1 and the anode electrode of the first light-emitting element LE1.

[0234] like Figure 11 As shown, in this embodiment, the seventh transistor T7 of the third light-emitting pixel driver EPD3 can be electrically connected to the anode electrode of the third light-emitting element LE3 and transmits a voltage different from the first anode initialization voltage VAINT1 (see reference). Figure 10 The second anode initialization voltage VAINT2 is between the second anode initialization voltage line VAIL2.

[0235] like Figure 10 As shown, in an embodiment, the first capacitor C1 of the first light-emitting pixel driver EPD1 can be electrically connected to the first power line VDL1.

[0236] In other words, the first capacitor C1 of the first light-emitting pixel driver EPD1 can be electrically connected between the first power line VDL1 and the gate electrode of the first transistor T1.

[0237] Therefore, the gate electrode of the first transistor T1 can be electrically connected to the first power line VDL1 through the first capacitor C1.

[0238] The second transistor T2 can be electrically connected between the first electrode (e.g., the source electrode) of the first transistor T1 and the data line DL.

[0239] The second transistor T2 can be turned on by the scan write signal GW of the scan write line GWL.

[0240] When the second transistor T2 is turned on, the data signal Vdata of the data line DL can be transmitted to the first electrode of the first transistor T1.

[0241] The fifth transistor T5 of the first light-emitting pixel driver EPD1 can be electrically connected between the first power line VDL1 and the first electrode of the first transistor T1.

[0242] The sixth transistor T6 can be electrically connected between the second electrode (e.g., the drain electrode) of the first transistor T1 and the output node N_OUT.

[0243] The fifth transistor T5 and the sixth transistor T6 can be turned on by the emit control signal EC of the emit control line ECL.

[0244] When the data signal Vdata of data line DL is transmitted to the first electrode of first transistor T1 through the conducting second transistor T2, the voltage difference between the gate electrode of first transistor T1 and the first electrode of first transistor T1 can correspond to the voltage difference between the first power supply ELVDD1 and the data signal Vdata.

[0245] When the voltage difference between the gate electrode and the first electrode of the first transistor T1 (i.e., the gate-source voltage difference) becomes greater than or equal to the threshold voltage, the first transistor T1 is turned on, so that the drain-source current (i.e., the drive current Idr) of the first transistor T1 can be generated to have a magnitude corresponding to the data signal Vdata.

[0246] Subsequently, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 and the first light-emitting element LE1 can be connected in series between the first power line VDL1 and the third power line VSL. Accordingly, the drive current Idr corresponding to the data signal Vdata and the voltage difference between the first power supply ELVDD1 and the third power supply ELVSS can be transmitted to the first light-emitting element LE1 through the output node N_OUT.

[0247] Accordingly, the first light-emitting element LE1 can emit light with a brightness corresponding to the data signal Vdata.

[0248] The third transistor T3 can be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1.

[0249] The third transistor T3 can be turned on by the gate control signal GC of the gate control line GCL.

[0250] When the third transistor T3 is turned on, the voltage difference between the gate electrode and the second electrode of the first transistor T1 can be initialized. That is, the channel portion of the first transistor T1 can be initialized.

[0251] The fourth transistor T4 can be connected between the gate electrode of the first transistor T1 and the gate initialization voltage line VIL.

[0252] The fourth transistor T4 can be turned on by the scan initialization signal GI of the scan initialization line GIL.

[0253] When the fourth transistor T4 is turned on, the potential of the gate electrode of the first transistor T1 can be initialized to the gate initialization voltage VINT.

[0254] The seventh transistor T7 of the first light-emitting pixel driver EPD1 can be electrically connected between the output node N_OUT and the first anode initialization voltage line VAIL1.

[0255] The seventh transistor T7 can be turned on by the bias control signal GB of the bias control line GBL.

[0256] When the seventh transistor T7 of the first light-emitting pixel driver EPD1 is turned on, the potential of the anode electrode of the first light-emitting element LE1 can be initialized to the first anode initialization voltage VAINT1.

[0257] The eighth transistor T8 can be electrically connected between the first electrode of the first transistor T1 and the bias voltage line VBSL.

[0258] The eighth transistor T8 can be turned on by the bias control signal GB of the bias control line GBL.

[0259] When the eighth transistor T8 is turned on, the potential of the first electrode of the first transistor T1 can be initialized to the bias voltage VBS.

[0260] In this embodiment, since the second light-emitting element LE2 has a structure that is substantially the same as or similar to that of the first light-emitting element LE1, the second light-emitting pixel driver EPD2 can also have a structure that is substantially the same as or similar to that of the first light-emitting pixel driver EPD1. Accordingly, redundant descriptions will be omitted.

[0261] like Figure 11 As shown, in this embodiment, in addition to the third light-emitting pixel driver EPD3 being electrically connected to two or more light-emitting stacks ESTA1 and ESTA2 (see reference 1), Figure 8 The third light-emitting element LE3, the fifth transistor T5 is electrically connected to the second power line VDL2 that transmits the second power ELVDD2, and the seventh transistor T7 is electrically connected to the second anode initialization voltage line VAIL2. The third light-emitting pixel driver EPD3 is connected to... Figure 10 The first light-emitting pixel driver EPD1 is essentially the same or similar, and therefore, redundant descriptions are omitted.

[0262] Because the third light-emitting element LE3 includes two or more light-emitting stacks ESTA1 and ESTA2 (see reference) Figure 8 Therefore, the third light-emitting element LE3 can have a higher threshold voltage than the first light-emitting element LE1 and the second light-emitting element LE2.

[0263] Accordingly, in an embodiment, the fifth transistor T5 of the third light-emitting pixel driver EPD3 can be electrically connected to a second power line VDL2 that transmits a second power line ELVDD2, which is different from the first power line ELVDD1.

[0264] In other words, the fifth transistor T5 of the third light-emitting pixel driver EPD3 can be electrically connected between the first electrode of the first transistor T1 and the second power line VDL2.

[0265] Accordingly, when the fifth transistor T5 and the sixth transistor T6 in the third light-emitting pixel driver EPD3 are turned on, the first transistor T1 and the third light-emitting element LE3 can be connected in series between the second power line VDL2 and the third power line VSL. Correspondingly, the drive current Idr, corresponding to the data signal Vdata and the voltage difference between the second power supply ELVDD2 and the third power supply ELVSS, can be transmitted to the third light-emitting element LE3 through the output node N_OUT.

[0266] As described above, in this embodiment, since the first transistor T1 of the third light-emitting pixel driver EPD3 is electrically connected to the second power line VDL2 via the fifth transistor T5, the driving current Idr of the third light-emitting element LE3 can be generated using the second power supply ELVDD2, which has a voltage level lower than that of the first power supply ELVDD1. Accordingly, the power consumption of the display device 100 can be reduced while maintaining the relatively high brightness of the third light-emitting element LE3.

[0267] In an embodiment, the first capacitor C1 of the third light-emitting pixel driver EPD3 can be electrically connected to the first power line VDL1.

[0268] In other words, the light-emitting pixel driver EPD (reference) Figure 5 The first capacitor C1 of each of the following can be electrically connected to the first power line VDL1. Accordingly, this prevents the light-emitting pixel driver EPD (reference) from being affected. Figure 5 The difference in capacitance between the first capacitor C1 and the first capacitor C1 causes the light-emitting pixel driver EPD (reference) to... Figure 5 This can be advantageous in terms of the consistency of characteristics.

[0269] In an embodiment, an luminescent pixel driver EPD (reference) is included. Figure 5 Some of the transistors in the first transistor T1 to the eighth transistor T8 in the ) can be N-type MOSFETs, and the other transistors can be P-type MOSFETs.

[0270] In other words, such as Figure 10 and Figure 11 As shown, the third transistor T3 and the fourth transistor T4 can be N-type MOSFETs, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can be P-type MOSFETs.

[0271] Therefore, circuit layer 120 (reference) Figure 4 This may include a first semiconductor layer SEL1 for forming a P-type MOSFET (reference). Figure 13 ) and the second semiconductor layer SEL2 used to form the N-type MOSFET (reference) Figure 15 ).

[0272] Figure 12 It is shown Figure 5 A schematic diagram of an embodiment of the circuit layer of part D.

[0273] refer to Figure 12 The circuit layer 120 of the display device 100 in the embodiment may be arranged on the first direction DR1 and the second direction DR2 and the drive current Idr (refer to) Figure 10 and Figure 11 Transmitted to the light-emitting element LE (reference) Figure 6 The light-emitting pixel driver EPD, the first power main line VDMNL1 extending in the second direction DR2 and transmitting the first power ELVDD1 to at least some light-emitting pixel drivers (e.g., the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2) in the light-emitting pixel driver EPD, and the second power main line VDMNL2 extending in the second direction DR2 and transmitting the second power ELVDD2, which is different from the first power ELVDD1, to some other light-emitting pixel drivers (e.g., the third light-emitting pixel driver EPD3) in the light-emitting pixel driver EPD.

[0274] The light-emitting pixel driver EPD may include a first light-emitting element LE1 (reference) Figure 6 The first light-emitting pixel driver EPD1 is electrically connected to the second light-emitting element LE2 (reference). Figure 6 The second light-emitting pixel driver EPD2 is electrically connected to the third light-emitting element LE3 (reference). Figure 6 The third luminescent pixel driver EPD3.

[0275] As described above, the first light-emitting element LE1 (reference) Figure 6 It can be set in the first emission region EA1 (refer to) for emitting light in the first wavelength band. Figure 6 In ), the second light-emitting element LE2 (reference) Figure 6 A second emission region EA2 (refer to) can be set to emit light in a second band that is lower than the first band. Figure 6 In ), and the third light-emitting element LE3 (reference) Figure 6 It can be set in the third emission region EA3, which emits light in the third band below the second band (see reference). Figure 6 )middle.

[0276] In an embodiment, for example, the first light-emitting element LE1 (reference) Figure 6 The first light-emitting element (LE2) emits light in the first wavelength band. Figure 6 ) emits light in the second band, and the third light-emitting element LE3 (reference) Figure 6 It can emit light in the third band.

[0277] In an embodiment, the first light-emitting element LE1 (reference) Figure 6 ) and the second light-emitting element LE2 (reference) Figure 6 Each of these can include a light-emitting stack (ESTA) (reference). Figure 7 ), and the third light-emitting element LE3 (reference) Figure 6It may include two or more light-emitting stacks, ESTA1 and ESTA2 (see reference). Figure 8 ).

[0278] In an embodiment, the first power main line VDMNL1, which transmits the first power ELVDD1, can be electrically connected to the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0279] In other words, the fifth transistor T5 of the first light-emitting pixel driver EPD1 and the fifth transistor T5 of the second light-emitting pixel driver EPD2 can be electrically connected to the first power main line VDMNL1. Accordingly, each of the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 can generate a drive current Idr based on the first power ELVDD1.

[0280] Additionally, the second power main line VDMNL2, which transmits the second power ELVDD2, can be electrically connected to the third light-emitting pixel driver EPD3.

[0281] In other words, the fifth transistor T5 of the third light-emitting pixel driver EPD3 can be electrically connected to the second power main line VDMNL2. Accordingly, the third light-emitting pixel driver EPD3 can generate a drive current Idr based on the second power supply ELVDD2.

[0282] In this way, the brightness of the third light-emitting element LE3 can be increased and unnecessary power consumption can be reduced, thereby reducing the power consumption of the display device 100.

[0283] In an embodiment, the first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3 can be arranged alternately on the second direction DR2.

[0284] The second light-emitting pixel driver EPD2 can be arranged side by side on the second direction DR2.

[0285] Furthermore, the second light-emitting pixel driver EPD2 can be disposed between the first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3 on the first direction DR1. That is, the second light-emitting pixel driver EPD2 can be adjacent to one of the first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3 on one side of the first direction DR1, and can be adjacent to the other one of the first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3 on the opposite side of the first direction DR1.

[0286] In this embodiment, the first power main line VDMNL1 and the second power main line VDMNL2 can be arranged alternately in the first direction DR1.

[0287] Accordingly, the first power main line VDMNL1 can cross with the second light-emitting pixel driver EPD2, and the second power main line VDMNL2 can cross with the first light-emitting pixel driver EPD1 and the third light-emitting pixel driver EPD3.

[0288] In an embodiment, circuit layer 120 may further include a first power sub-line VDSBL1 extending in the first direction DR1 and electrically connected to the first power main line VDMNL1.

[0289] In other words, the first power line VDL1 used to transmit the first power ELVDD1 can have a mesh structure including the first power main line VDMNL1 and the first power secondary line VDSBL1, so that the first power ELVDD1 can be transmitted relatively evenly to the light-emitting pixel driver EPD of the display area DA.

[0290] In one embodiment, the first capacitor C1 of each of the light-emitting pixel drivers EPDs can be electrically connected to the first power sub-line VDSBL1.

[0291] Figures 13 to 19 It is shown Figure 12 In the embodiments Figure 5 A plan view of an embodiment of the circuit layer of part D in the diagram. Figure 20 It is along Figure 19 The cross-sectional view taken from line E-E'. Figure 21 It is along Figure 19 The cross-sectional view taken by line F-F'.

[0292] like Figures 13 to 21 As shown in the embodiment, the circuit layer 120 of the display device 100 may include a circuit disposed on the substrate 110 (see reference 110). Figure 20 and Figure 21 The first semiconductor layer SEL1 on the (reference) Figure 13 ), set in the first semiconductor layer SEL1 (reference) Figure 13 The first interlayer insulation layer 124 on the (reference) Figure 20 and Figure 21 ), set in the first interlayer insulation layer 124 (reference) Figure 20 and Figure 21 The second semiconductor layer SEL2 on the (reference) Figure 15 ), set in the second semiconductor layer SEL2 (reference) Figure 15 The second interlayer insulation layer 126 on the (reference) Figure 20 and Figure 21 ), set in the second interlayer insulation layer 126 (reference) Figure 20 and Figure 21 The first source / drain conductive layer SDCDL1 on the (reference) Figure 16), covering the first source / drain conductive layer SDCDL1 (reference) Figure 16 The first planarization layer 127 (reference) Figure 20 and Figure 21 ), set in the first planarization layer 127 (reference) Figure 20 and Figure 21 The second source / drain conductive layer SDCDL2 on the (reference) Figure 18 ) and covering the second source / drain conductive layer SDCDL2 (reference) Figure 18 The second planarization layer 128 (reference) Figure 20 and Figure 21 ).

[0293] In an embodiment, circuit layer 120 may further include a layer covering the first semiconductor layer SEL1 (reference 1). Figure 13 The first gate insulating layer 122 (reference) Figure 20 and Figure 21 ), and is disposed in the first gate insulating layer 122 (reference) Figure 20 and Figure 21 The first gate conductive layer GCDL1 on the ) (reference) Figure 13 ), covering the first gate conductive layer GCDL1 (reference) Figure 13 The second gate insulating layer 123 (reference) Figure 20 and Figure 21 ) and disposed in the second gate insulating layer 123 (reference) Figure 20 and Figure 21 ) and the first interlayer insulation layer 124 (reference) Figure 20 and Figure 21 The second gate conductive layer GCDL2 between (reference) Figure 14 ).

[0294] In an embodiment, circuit layer 120 may further include a second semiconductor layer SEL2 (reference 2). Figure 15 The third gate insulating layer 125 (reference) Figure 20 and Figure 21 ) and provided in the third gate insulating layer 125 (reference) Figure 20 and Figure 21 ) and the second interlayer insulation layer 126 (reference) Figure 20 and Figure 21 The third gate conductive layer GCDL3 (reference) between ) Figure 15 ).

[0295] In other words, the circuit layer 120 may include a first semiconductor layer SEL1 disposed on the substrate 110, a first gate insulating layer 122 covering the first semiconductor layer SEL1, a first gate conductive layer GCDL1 disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer GCDL1, a second gate conductive layer GCDL2 disposed on the second gate insulating layer 123, a first interlayer insulating layer 124 covering the second gate conductive layer GCDL2, a second semiconductor layer SEL2 disposed on the first interlayer insulating layer 124, a third gate insulating layer 125 covering the second semiconductor layer SEL2, a third gate conductive layer GCDL3 disposed on the third gate insulating layer 125, a second interlayer insulating layer 126 covering the third gate conductive layer GCDL3, a first source / drain conductive layer SDCDL1 disposed on the second interlayer insulating layer 126, a first planarization layer 127 covering the first source / drain conductive layer SDCDL1, a second source / drain conductive layer SDCDL2 disposed on the first planarization layer 127, and a second planarization layer 128 covering the second source / drain conductive layer SDCDL2.

[0296] In an embodiment, circuit layer 120 may further include a light-shielding layer LBL (reference) disposed on substrate 110. Figure 13 , Figure 20 and Figure 21 ) and the buffer layer 121 covering the light-shielding layer LBL (see reference) Figure 20 and Figure 21 In this case, the first semiconductor layer SEL1 (reference) Figure 13 It can be set on buffer layer 121.

[0297] Figure 13 Show Figure 5 The circuit layer of part D contains the first semiconductor layer SEL1 and the first gate conductive layer GCDL1. Figure 14 Show Figure 5 The second gate conductive layer GCDL2 of the circuit layer in part D. Figure 15 Show Figure 5 The circuit layer of part D contains the second semiconductor layer SEL2 and the third gate conductive layer GCDL3. Figure 16 Show Figure 5 The first source / drain conductive layer SDCDL1 of the circuit layer in part D. Figure 17 Show Figure 5 The circuit layer of part D consists of a first semiconductor layer SEL1, a first gate conductive layer GCDL1, a second gate conductive layer GCDL2, a second semiconductor layer SEL2, a third gate conductive layer GCDL3, and a first source / drain conductive layer SDCDL1. Figure 18 Show Figure 5 The second source / drain conductive layer SDCDL2 of the circuit layer in part D. Figure 19 Show Figure 5 The circuit layer of part D consists of a first semiconductor layer SEL1, a first gate conductive layer GCDL1, a second gate conductive layer GCDL2, a second semiconductor layer SEL2, a third gate conductive layer GCDL3, a first source / drain conductive layer SDCDL1, and a second source / drain conductive layer SDCDL2.

[0298] As described above, in each of the light-emitting pixel driver EPDs, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be formed as P-type MOSFETs. Furthermore, in each of the light-emitting pixel driver EPDs, the third transistor T3 and the fourth transistor T4 can be formed as N-type MOSFETs.

[0299] refer to Figure 13 The channel portions CH1, CH2, CH5, CH6, CH7 and CH8 of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8, the first electrodes E11, E12, E15, E16, E17 and E18 and the second electrodes E21, E22, E25, E26, E27 and E28 can be disposed in the first semiconductor layer SEL1.

[0300] The channel portion CH1 of the first transistor T1 can overlap with the light-shielding layer LBL on the third-direction DR3.

[0301] The first electrode E11 of the first transistor T1 can be connected to the channel portion CH1 of the first transistor T1, the second electrode E22 of the second transistor T2, and the second electrode E25 of the fifth transistor T5.

[0302] The second electrode E21 of the first transistor T1 can be connected to the channel portion CH1 of the first transistor T1 and the first electrode E16 of the sixth transistor T6.

[0303] The channel portion CH2 of the second transistor T2 can be connected to each of the first electrode E12 and the second electrode E22 of the second transistor T2.

[0304] The channel portion CH5 of the fifth transistor T5 can be connected to each of the first electrode E15 and the second electrode E25 of the fifth transistor T5.

[0305] The channel portion CH6 of the sixth transistor T6 can be connected to each of the first electrode E16 and the second electrode E26 of the sixth transistor T6.

[0306] The second electrode E26 of the sixth transistor T6 can be connected to the second electrode E27 of the seventh transistor T7.

[0307] The channel portion CH7 of the seventh transistor T7 can be connected to each of the first electrode E17 and the second electrode E27 of the seventh transistor T7.

[0308] The channel portion CH8 of the eighth transistor T8 can be connected to each of the first electrode E18 and the second electrode E28 of the eighth transistor T8.

[0309] The gate electrodes G1, G2, G5, G6, G7 and G8 of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can be disposed in the first gate conductive layer GCDL1.

[0310] In the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, the gate electrodes G1, G2, G5, G6, G7, and G8 can overlap with the channel portions CH1, CH2, CH5, CH6, CH7, and CH8, respectively.

[0311] Each of the scan write line GWL, emit control line ECL, bias control line GBL, and gate initialization voltage line VIL can extend in the first direction DR1 and can be located in the first gate conductive layer GCDL1.

[0312] The gate electrode G2 of the second transistor T2 can be the portion of the scan write line GWL that overlaps with the channel portion CH2 of the second transistor T2.

[0313] The gate electrode G5 of the fifth transistor T5 can be the portion of the emitter control line ECL that overlaps with the channel portion CH5 of the fifth transistor T5.

[0314] The gate electrode G6 of the sixth transistor T6 may be another part of the emitter control line ECL that overlaps with the channel portion CH6 of the sixth transistor T6.

[0315] The gate electrode G7 of the seventh transistor T7 can be the portion of the bias control line GBL that overlaps with the channel portion CH7 of the seventh transistor T7.

[0316] The gate electrode G8 of the eighth transistor T8 may be another part of the bias control line GBL that overlaps with the channel portion CH8 of the eighth transistor T8.

[0317] like Figure 14 and Figure 17As shown, each of the light-emitting pixel drivers EPDs may include a capacitor electrode CAE disposed in the second gate conductive layer GCDL2 and overlapping with the gate electrode G1 of the first transistor T1 on the third-direction DR3.

[0318] like Figure 14 As shown, the first power sub-line VDSBL1 can extend in the first direction DR1 and can be disposed in the second gate conductive layer GCDL2.

[0319] In an embodiment, the capacitor electrode CAE may be the electrode that transmits the first power ELVDD1 (reference). Figure 12 The portion of the first power sub-line VDSBL1 that overlaps with the gate electrode G1 of the first transistor T1.

[0320] like Figure 20 As shown, the first capacitor C1 can be formed in the region where the gate electrode G1 of the first transistor T1 overlaps with the capacitor electrode CAE on the third-direction DR3.

[0321] In this embodiment, since the capacitor electrode CAE of each of the light-emitting pixel drivers EPDs is electrically connected to the first power ELVDD1 (reference) for transmission... Figure 12 The first power sub-line VDSBL1, therefore the first capacitor C1 of each of the light-emitting pixel drivers EPD (reference) Figure 12 It can be electrically connected to the first power line VDL1 (reference). Figure 12 ( ) between the gate electrode G1 of the first transistor T1.

[0322] like Figure 14 As shown, circuit layer 120 may further include scan initialization auxiliary line GIAL and gate control auxiliary line GCAL disposed in the second gate conductive layer GCDL2.

[0323] Each of the scan initialization auxiliary line GIAL and the gate control auxiliary line GCAL can be extended in the first direction DR1.

[0324] like Figure 15 As shown, the channel portions CH3 and CH4 of each of the third transistor T3 and the fourth transistor T4, the first electrodes E13 and E14, and the second electrodes E23 and E24 can be disposed in the second semiconductor layer SEL2.

[0325] The channel portion CH3 of the third transistor T3 can be connected to each of the first electrode E13 and the second electrode E23 of the third transistor T3.

[0326] The channel portion CH4 of the fourth transistor T4 can be connected to each of the first electrode E14 and the second electrode E24 of the fourth transistor T4.

[0327] The second electrode E23 of the third transistor T3 can be connected to the second electrode E24 of the fourth transistor T4.

[0328] The gate electrode G3 of the third transistor T3 and the gate electrode G4 of the fourth transistor T4 can be disposed in the third gate conductive layer GCDL3.

[0329] In the third transistor T3 and the fourth transistor T4, the gate electrodes G3 and G4 can overlap with the channel portions CH3 and CH4, respectively.

[0330] Each of the scan initialization line GIL, gate control line GCL, bias voltage line VBSL, and second anode initialization voltage line VAIL2 can extend in the first direction DR1 and can be disposed in the third gate conductive layer GCDL3.

[0331] The gate electrode G3 of the third transistor T3 can be the portion of the gate control line GCL that overlaps with the channel portion CH3 of the third transistor T3.

[0332] The gate electrode G4 of the fourth transistor T4 can be the portion of the scan initialization line GIL that overlaps with the channel portion CH4 of the fourth transistor T4.

[0333] refer to Figure 16 The first anode initialization voltage line VAIL1 can extend in the first direction DR1 and can be set in the first source-drain conductive layer SDCDL1.

[0334] Each of the light-emitting pixel drivers (EPD) may include a data connection electrode (DCE), a gate connection electrode (GCE), a first anode connection electrode (ANCE1), a scan initialization connection electrode (GICE), a bias voltage connection electrode (VBSCE), a first auxiliary connection electrode (ASCE1), and a second auxiliary connection electrode (ASCE2).

[0335] Each of the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 may include a first power connection electrode VDCE1.

[0336] The third light-emitting pixel driver EPD3 may include a second power connection electrode VDCE2.

[0337] The first power connection electrode VDCE1 of the first light-emitting pixel driver EPD1 and the first power connection electrode VDCE1 of the second light-emitting pixel driver EPD2, which are adjacent to each other in the first direction DR1, can be connected to each other.

[0338] The first light-emitting pixel driver EPD1 may further include a dummy connection electrode DMCE spaced apart from the first electrical connection electrode VDCE1.

[0339] In the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2, which are adjacent to each other along the first direction DR1, the first power connection electrode VDCE1 and the dummy connection electrode DMCE of the first light-emitting pixel driver EPD1 can be symmetrical with respect to the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 and multiple portions of the first power connection electrode VDCE1 of the second light-emitting pixel driver EPD2.

[0340] Each of the data connection electrode DCE, gate connection electrode GCE, first anode connection electrode ANCE1, scan initialization connection electrode GICE, bias voltage connection electrode VBSCE, first auxiliary connection electrode ASCE1, second auxiliary connection electrode ASCE2, first power connection electrode VDCE1, second power connection electrode VDCE2, and dummy connection electrode DMCE can be arranged in an island shape in the first source-drain conductive layer SDCDL1.

[0341] like Figure 16 and Figure 17 As shown, the data connection electrode DCE can be electrically connected to the second transistor T2 (reference). Figure 13 The first electrode E12 (reference) Figure 13 ).

[0342] The first anode connection electrode ANCE1 can be electrically connected to the sixth transistor T6 (reference) through the first anode connection hole ANCH1. Figure 13 The second electrode E26 (reference) Figure 13 ) and the seventh transistor T7 (reference) Figure 13 The second electrode E27 (reference) Figure 13 ).

[0343] The scan initialization connection electrode GICE can be electrically connected to the gate initialization voltage line VIL (reference). Figure 13 ) and the fourth transistor T4 (reference) Figure 15 The first electrode E14 (reference) Figure 15 ).

[0344] The bias voltage connection electrode VBSCE can be electrically connected to the bias voltage line VBSL (reference). Figure 15 ) and the eighth transistor T8 (reference) Figure 13 The first electrode E18 (reference) Figure 13 That is to say, the eighth transistor T8 (reference) Figure 13 The first electrode E18 (reference) Figure 13 The bias voltage connection electrode VBSCE can be electrically connected to the bias voltage line VBSL (reference). Figure 15 ).

[0345] The first auxiliary connection electrode ASCE1 can be electrically connected to the first transistor T1 (reference). Figure 13 The first electrode E11 (reference) Figure 13 ), second transistor T2 (reference) Figure 13 The second electrode E22 (reference) Figure 13 ), fifth transistor T5 (reference) Figure 13 The second electrode E25 (reference) Figure 13 ) and the eighth transistor T8 (reference) Figure 13 The second electrode E28 (reference) Figure 13 That is to say, the eighth transistor T8 (reference) Figure 13 The second electrode E28 (reference) Figure 13 It can be electrically connected to the first transistor T1 (reference) via the first auxiliary connection electrode ASCE1. Figure 13 The first electrode E11 (reference) Figure 13 ) and the fifth transistor T5 (reference) Figure 13 The second electrode E25 (reference) Figure 13 ).

[0346] The second auxiliary connection electrode ASCE2 can be electrically connected to the first transistor T1 (reference). Figure 13 The second electrode E21 (reference) Figure 13 ) and the third transistor T3 (reference) Figure 15 The first electrode E13 (reference) Figure 15 In other words, the third transistor T3 (reference) Figure 15 The first electrode E13 (reference) Figure 15 It can be electrically connected to the first transistor T1 (reference) via the second auxiliary connection electrode ASCE2. Figure 13 The second electrode E21 (reference) Figure 13 ).

[0347] The gate connection electrode GCE can be electrically connected to the first transistor T1 through the first gate connection hole GCH1 (reference). Figure 13 The gate electrode G1 of the transistor can be electrically connected to the third transistor T3 (reference) through the second gate connection hole GCH2. Figure 15 The second electrode E23 (reference) Figure 15 ) and the fourth transistor T4 (reference) Figure 15 The second electrode E24 (reference) Figure 15 ).

[0348] The first power connection electrode VDCE1 can be electrically connected via the first power connection hole VDCH1 to the fifth transistor T5 of each of the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 (reference). Figure 13 The first electrode is E15.

[0349] The first power connection electrode VDCE1 can be electrically connected to the first power sub-line VDSBL1 through the second power connection hole VDCH2.

[0350] The second power connection electrode VDCE2 can be electrically connected to the fifth transistor T5 of the third light-emitting pixel driver EPD3 (reference) through the third power connection hole VDCH3. Figure 13 The first electrode is E15.

[0351] refer to Figure 18 Each of the data line DL, the first power line VDMNL1, and the second power line VDMNL2 can extend in the second direction DR2 and can be located in the second source-drain conductive layer SDCDL2.

[0352] Each of the light-emitting pixel drivers EPD may further include a second anode connection electrode ANCE2 disposed in the second source-drain conductive layer SDCDL2.

[0353] like Figure 18 and Figure 19 As shown, the first power line VDL1 may have a mesh shape including a first power sub-line VDSBL1 extending in the first direction DR1 and a first power main line VDMNL1 extending in the second direction DR2.

[0354] Accordingly, the first power ELVDD1 (reference) Figure 12 The light-emitting pixel driver EPD can transmit the light relatively evenly to the display area DA.

[0355] according to Figure 12 and Figure 19 In one embodiment, the second power line VDL2 may consist only of the second power main line VDMNL2 extending in the second direction DR2.

[0356] The data cable DL can be electrically connected to the data connection electrode DCE through the second data connection hole DCH2.

[0357] Accordingly, the second transistor T2 (reference) Figure 13 The first electrode E12 (reference) Figure 13 It can be electrically connected to the data line DL via the data connection electrode DCE.

[0358] The second anode connection electrode ANCE2 can be electrically connected to the first anode connection electrode ANCE1 through the second anode connection hole ANCH2, and can be electrically connected to the light-emitting element LE (reference) through the third anode connection hole ANCH3. Figure 6 )one of the.

[0359] Accordingly, the sixth transistor T6 (reference) Figure 13 The second electrode E26 (reference) Figure 13 ) and the seventh transistor T7 (reference) Figure 13 The second electrode E27 (reference) Figure 13 The light-emitting element LE can be electrically connected via the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2 (see reference). Figure 6 One of the anode electrodes 131 (reference) Figure 6 ).

[0360] The first power main line VDMNL1 can be electrically connected to the first power connection electrode VDCE1 through the fourth power connection hole VDCH4.

[0361] Accordingly, the fifth transistor T5 of the first light-emitting pixel driver EPD1 (reference) Figure 13 The first electrode E15, the fifth transistor T5 of the second light-emitting pixel driver EPD2 (reference) Figure 13 Each of the first electrode E15 and the first power sub-line VDSBL1 can be electrically connected to the first power mainline VDMNL1 via the first power connection electrode VDCE1.

[0362] The second power main line VDMNL2 can be electrically connected to the second power connection electrode VDCE2 through the fifth power connection hole VDCH5.

[0363] Accordingly, the fifth transistor T5 of the third light-emitting pixel driver EPD3 (reference) Figure 13 The first electrode E15 can be electrically connected to the second power main line VDMNL2 via the second power connection electrode VDCE2.

[0364] In addition, the second power main line VDMNL2 can be electrically connected to the dummy connection electrode DMCE through the dummy connection hole DMCH.

[0365] like Figure 20 As shown, the light-shielding layer LBL can be disposed on the substrate 110 and can be covered by the buffer layer 121.

[0366] First transistor T1 (reference) Figure 13 The channel portion CH1, the sixth transistor T6 (reference) Figure 13 The second electrode E26 and the seventh transistor T7 (reference) Figure 13The second electrode E27 can be disposed on the buffer layer 121 and can be covered by the first gate insulating layer 122.

[0367] First transistor T1 (reference) Figure 13 The gate electrode G1, scan write line GWL and emit control line ECL can be disposed on the first gate insulating layer 122 and can be covered by the second gate insulating layer 123.

[0368] First transistor T1 (reference) Figure 13 The channel portion CH1 can be connected to the first transistor T1 (reference) on the third-direction DR3. Figure 13 The gate electrode G1 overlaps.

[0369] First transistor T1 (reference) Figure 13 The channel portion CH1 can be disposed on the third-direction DR3 between the light-shielding layer LBL and the first transistor T1 (reference). Figure 13 Between the gate electrode G1.

[0370] The capacitor electrode CAE and the gate control auxiliary line GCAL can be disposed on the second gate insulating layer 123 and can be covered by the first interlayer insulating layer 124.

[0371] The first capacitor C1 can be formed in the first transistor T1 (reference) through the second gate insulating layer 123. Figure 13 The gate electrode G1 and the capacitor electrode CAE overlap each other in the region on the third-direction DR3.

[0372] Third transistor T3 (reference) Figure 15 The second electrode E23 and the fourth transistor T4 (reference) Figure 15 The second electrode E24 can be disposed on the first interlayer insulating layer 124 and covered by the third gate insulating layer 125.

[0373] The gate control line GCL and the second anode initialization voltage line VAIL2 can be disposed on the third gate insulating layer 125 and covered by the second interlayer insulating layer 126.

[0374] The gate control line GCL can overlap with the gate control auxiliary line GCAL on the third-direction DR3.

[0375] The gate connection electrode GCE, the first anode initialization voltage line VAIL1, and the first anode connection electrode ANCE1 can be disposed on the second interlayer insulating layer 126 and covered by the first planarization layer 127.

[0376] The gate connection electrode GCE can be electrically connected to the first transistor T1 through the first gate connection hole GCH1 (reference). Figure 13The gate electrode G1 of the transistor can be electrically connected to the third transistor T3 (reference) through the second gate connection hole GCH2. Figure 15 The second electrode E23 and the fourth transistor T4 (reference) Figure 15 The second electrode E24.

[0377] The first anode connection electrode ANCE1 can be electrically connected to the sixth transistor T6 (reference) through the first anode connection hole ANCH1. Figure 13 The second electrode E26 and the seventh transistor T7 (reference) Figure 13 The second electrode is E27.

[0378] The second power main line VDMNL2 and the second anode connection electrode ANCE2 can be disposed on the first planarization layer 127 and covered by the second planarization layer 128.

[0379] The second anode connection electrode ANCE2 can be electrically connected to the first anode connection electrode ANCE1 through the second anode connection hole ANCH2, and can be electrically connected to the light-emitting element LE (reference) through the third anode connection hole ANCH3. Figure 6 )one of the.

[0380] Accordingly, the sixth transistor T6 (reference) Figure 13 The second electrode E26 and the seventh transistor T7 (reference) Figure 13 The second electrode E27 can be electrically connected to the light-emitting element LE (reference) through the first anode connection electrode ANCE1 and the second anode connection electrode ANCE2. Figure 6 One of the anode electrodes 131 (reference) Figure 6 ).

[0381] like Figure 21 As shown, the channel portion CH5 of the fifth transistor T5, the first electrode E15 and the second electrode E25, and the first transistor T1 (reference) Figure 13 The first electrode E11 can be disposed on the buffer layer 121 and covered by the first gate insulating layer 122.

[0382] The gate electrode G5 of the fifth transistor T5 can be disposed on the first gate insulating layer 122 and covered by the second gate insulating layer 123.

[0383] The gate electrode G5 of the fifth transistor T5 can overlap with the channel portion CH5 of the fifth transistor T5 on the third-direction DR3.

[0384] The first power sub-line VDSBL1 and the gate control auxiliary line GCAL can be disposed on the second gate insulation layer 123 and covered by the first interlayer insulation layer 124.

[0385] The first power sub-line VDSBL1 can cross with the second light-emitting pixel driver EPD2 and the third light-emitting pixel driver EPD3.

[0386] The second light-emitting pixel driver EPD2 may include a first power connection electrode VDCE1.

[0387] The third light-emitting pixel driver EPD3 may include a second power connection electrode VDCE2.

[0388] The first electrical connection electrode VDCE1 and the second electrical connection electrode VDCE2 can be disposed on the second interlayer insulating layer 126 and covered by the first planarization layer 127.

[0389] The first power connection electrode VDCE1 can be electrically connected to the first electrode E15 of the fifth transistor T5 of the second light-emitting pixel driver EPD2 through the first power connection hole VDCH1, and can be electrically connected to the first power sub-line VDSBL1 through the second power connection hole VDCH2.

[0390] The second power connection electrode VDCE2 can be electrically connected to the first electrode E15 of the fifth transistor T5 of the third light-emitting pixel driver EPD3 through the third power connection hole VDCH3.

[0391] The data line DL, the first power line VDMNL1, and the second power line VDMNL2 can be disposed on the first planarization layer 127 and covered by the second planarization layer 128.

[0392] The first power main line VDMNL1 can be electrically connected to the first power connection electrode VDCE1 through the fourth power connection hole VDCH4.

[0393] Accordingly, the first electrode E15 of the fifth transistor T5 of the first power sub-line VDSBL1 and the second light-emitting pixel driver EPD2 can be electrically connected to the first power main line VDMNL1 through the first power connection electrode VDCE1.

[0394] The second power main line VDMNL2 can be electrically connected to the second power connection electrode VDCE2 through the fifth power connection hole VDCH5.

[0395] Correspondingly, the first electrode E15 of the fifth transistor T5 of the third light-emitting pixel driver EPD3 can be electrically connected to the second power main line VDMNL2 via the second power connection electrode VDCE2.

[0396] Figure 22 It is shown Figure 5 A schematic diagram of an embodiment of the circuit layer of part D.

[0397] In addition to the circuit layer 120 extending in the first direction DR1 and further including a second power sub-line VDSBL2 electrically connected to the second power main line VDMNL2, Figure 22 The display device 100 of the embodiment shown in the figure and Figure 12 The display devices 100 shown in the embodiments are substantially the same or similar, and therefore, redundant descriptions are omitted below.

[0398] like Figure 22 As shown in the embodiment, the circuit layer 120 may include a first power sub-line VDSBL1 extending in the first direction DR1 and electrically connected to the first power main line VDMNL1, and a second power sub-line VDSBL2 extending in the first direction DR1 and electrically connected to the second power main line VDMNL2.

[0399] The first power sub-line VDSBL1 and the second power sub-line VDSBL2 can be arranged alternately in the second direction DR2.

[0400] Accordingly, one of the two adjacent (closely related) light-emitting pixel drivers EPD on the second direction DR2 (e.g., Figure 22 The setting of the light-emitting pixel driver EPD in the second row can cross with the first power sub-line VDSBL1, and the remaining (another) light-emitting pixel driver EPD (e.g., Figure 22 The setting of the luminous pixel driver (EPD) in the first row can cross with the second power sub-line VDSBL2.

[0401] In the second direction DR2, one of the two adjacent light-emitting pixel drivers EPD (e.g., Figure 22 The first capacitor C1 of the luminous pixel driver (EPD) in the second row can be electrically connected to the first power sub-line VDSBL1.

[0402] Furthermore, in the second direction DR2, the remaining (other) light-emitting pixel driver EPD (e.g., Figure 22 The first capacitor C1 of the luminous pixel driver (EPD) in the first row can be electrically connected to the second power sub-line VDSBL2.

[0403] In this way, not only does the first power line VDL1 have a mesh shape, but the second power line VDL2 that transmits the second power ELVDD2 also has a mesh shape including a second power sub-line VDSBL2 extending in the first direction DR1 and a second power main line VDMNL2 extending in the second direction DR2, so that the second power ELVDD2 can be transmitted to the display area DA relatively uniformly.

[0404] Figure 23 and Figure 24 It is shown Figure 5 A plan view of an embodiment of the circuit layer of part D. Figure 25 It is along Figure 24 A cross-sectional view taken from line G-G'. Figure 26 It is along Figure 24 A cross-sectional view taken from line H-H'.

[0405] exist Figure 23 and Figure 24 In the embodiment shown, the remaining portion of circuit layer 120, except for the second gate conductive layer GCDL2 (i.e., the first semiconductor layer SEL1, the first gate conductive layer GCDL1, the second semiconductor layer SEL2, the third gate conductive layer GCDL3, the first source / drain conductive layer SDCDL1, and the second source / drain conductive layer SDCDL2), is connected to... Figure 13 , Figure 15 , Figure 16 and Figure 18 Those embodiments shown are substantially the same or similar, and therefore redundant descriptions are omitted below.

[0406] Figure 23 The diagram is based on Figure 22 of Figure 5 An embodiment of the second gate conductive layer GCDL2 of the circuit layer of part D in the diagram. Figure 25 Showing according to Figure 22 of Figure 5 An embodiment of the circuit layer of part D, comprising the first semiconductor layer SEL1, the first gate conductive layer GCDL1, the second gate conductive layer GCDL2, the second semiconductor layer SEL2, the third gate conductive layer GCDL3, the first source / drain conductive layer SDCDL1, and the second source / drain conductive layer SDCDL2.

[0407] like Figure 23 As shown in the embodiment, the first power sub-line VDSBL1 and the second power sub-line VDSBL2 can be disposed in the second gate conductive layer GCDL2 and can extend in the first direction DR1.

[0408] Each of the light-emitting pixel drivers EPDs may include a capacitor electrode CAE disposed in the second gate conductive layer GCDL2.

[0409] The capacitor electrode CAE of each of the light-emitting pixel drivers EPDs can be part of one of the first power sub-line VDSBL1 and the second power sub-line VDSBL2.

[0410] In an embodiment, between two adjacent light-emitting pixel drivers EPDs along the second direction DR2, one light-emitting pixel driver EPD (e.g., crossing the first power sub-line VDSBL1) is located... Figure 22 The capacitor electrode CAE of the light-emitting pixel driver (EPD) arranged in the second row can be part of the first power sub-line VDSBL1.

[0411] Between two adjacent light-emitting pixel drivers EPDs along the second direction DR2, the remaining (another) light-emitting pixel driver EPD (e.g., crossing the second power sub-line VDSBL2) Figure 22 The capacitor electrode CAE of the luminescent pixel driver (EPD) in the first row can be part of the second power sub-line VDSBL2.

[0412] As referenced above Figure 20 As described above, in each of the light-emitting pixel drivers EPD, the capacitor electrode CAE is connected to the first transistor T1 (reference) on the third-direction DR3. Figure 22 The gate electrode G1 overlaps with the first transistor T1, allowing the first capacitor C1 to be formed on the capacitor electrode CAE and the first transistor T1 (reference). Figure 22 The gate electrodes G1 of the third direction DR3 overlap with each other in the region.

[0413] like Figure 24 and Figure 26 As shown, in an embodiment, the first power connection electrode VDCE1 can be electrically connected to the fifth transistor T5 of the first light-emitting pixel driver EPD1 (see reference) through the first power connection hole VDCH1. Figure 22 The first electrode E15 and the fifth transistor T5 of the second light-emitting pixel driver EPD2 (reference) Figure 22 The first electrode E15 can be electrically connected to the first power sub-line VDSBL1 through the second power connection hole VDCH2.

[0414] The first power main line VDMNL1 can be electrically connected to the first power connection electrode VDCE1 through the fourth power connection hole VDCH4.

[0415] Correspondingly, the fifth transistor T5 of the first power sub-line VDSBL1 and the first light-emitting pixel driver EPD1 (reference) Figure 22 The first electrode E15 and the fifth transistor T5 of the second light-emitting pixel driver EPD2 (reference) Figure 22 The first electrode E15 can be electrically connected to the first power main line VDMNL1 via the first power connection electrode VDCE1.

[0416] The first light-emitting pixel driver EPD1 may further include a dummy connection electrode DMCE disposed in an island shape on the second interlayer insulating layer 126 and spaced apart from the first electrical connection electrode VDCE1.

[0417] like Figure 24 and Figure 25 As shown, in an embodiment, the second power connection electrode VDCE2 can be electrically connected to the fifth transistor T5 of the third light-emitting pixel driver EPD3 (see reference) via the third power connection hole VDCH3. Figure 22 The first electrode E15 can be electrically connected to the second power sub-line VDSBL2 through the sixth power connection hole VDCH6.

[0418] The second power main line VDMNL2 can be electrically connected to the second power connection electrode VDCE2 through the fifth power connection hole VDCH5.

[0419] Accordingly, the fifth transistor T5 of the second power sub-line VDSBL2 and the third light-emitting pixel driver EPD3 (reference) Figure 22 The first electrode E15 can be electrically connected to the second power main line VDMNL2 via the second power connection electrode VDCE2.

[0420] Figure 27 It is shown Figure 5 A schematic diagram of an embodiment of the circuit layer of part D.

[0421] Except for the fact that each of the light-emitting pixel drivers EPDs intersects with the first power sub-line VDSBL1 and the second power sub-line VDSBL2, the first capacitor C1 of each of the first light-emitting pixel drivers EPD1 and EPD2 is electrically connected to the first power main line VDMNL1, and the first capacitor C1 of the third light-emitting pixel driver EPD3 is electrically connected to the second power main line VDMNL2, Figure 27 The display device 100 of the embodiment shown in the figure and Figure 22 The display devices 100 shown in the embodiments are substantially the same or similar, and therefore, redundant descriptions are omitted below.

[0422] Figure 28 , Figure 29 , Figure 30 and Figure 31 It is shown Figure 5 A schematic diagram of an embodiment of the circuit layer of part D. Figure 32 It is along Figure 31 The cross-sectional view taken from line I-I'. Figure 33 It is along Figure 31 The cross-sectional view taken from line J-J'.

[0423] exist Figures 28 to 31In the embodiment shown, the remaining portion of circuit layer 120, excluding the second gate conductive layer GCDL2 and the third gate conductive layer GCDL3 (i.e., the first semiconductor layer SEL1, the first gate conductive layer GCDL1, the second semiconductor layer SEL2, the first source / drain conductive layer SDCDL1, and the second source / drain conductive layer SDCDL2), is connected to... Figure 13 , Figure 15 , Figure 16 and Figure 18 Those embodiments shown are substantially the same or similar, and therefore redundant descriptions are omitted below.

[0424] Figure 28 The diagram is based on Figure 27 of Figure 5 An embodiment of the second gate conductive layer GCDL2 of the circuit layer of part D in the diagram. Figure 29 Showing according to Figure 27 of Figure 5 An embodiment of the second semiconductor layer SEL2 and the third gate conductive layer GCDL3 of the circuit layer of part D. Figure 30 The diagram is based on Figure 27 of Figure 5 An embodiment of the circuit layer of part D, comprising the first semiconductor layer SEL1, the first gate conductive layer GCDL1, the second gate conductive layer GCDL2, the second semiconductor layer SEL2, the third gate conductive layer GCDL3, and the first source / drain conductive layer SDCDL1. Figure 31 Showing according to Figure 27 of Figure 5 An embodiment of the circuit layer of part D, comprising the first semiconductor layer SEL1, the first gate conductive layer GCDL1, the second gate conductive layer GCDL2, the second semiconductor layer SEL2, the third gate conductive layer GCDL3, the first source / drain conductive layer SDCDL1, and the second source / drain conductive layer SDCDL2.

[0425] like Figure 28 As shown, in an embodiment, each of the light-emitting pixel drivers EPD may include a capacitor electrode CAE disposed in an island-like configuration within the second gate conductive layer GCDL2.

[0426] The capacitor electrodes CAE of the two adjacent light-emitting pixel drivers EPD on the first direction DR1 can be symmetrical about the boundary between the two adjacent light-emitting pixel drivers EPD.

[0427] like Figure 29 As shown in the embodiment, the first power sub-line VDSBL1 and the second power sub-line VDSBL2 can be disposed in the third gate conductive layer GCDL3 and extend in the first direction DR1.

[0428] The first power sub-line VDSBL1 and the second power sub-line VDSBL2 can be arranged alternately in the second direction DR2.

[0429] Accordingly, one of the two adjacent (closely related) light-emitting pixel drivers EPD on the second direction DR2 (e.g., Figure 29 The setting of the light-emitting pixel driver EPD in the second row can cross with the first power sub-line VDSBL1, and the remaining (another) light-emitting pixel driver EPD (e.g., Figure 29 The setting of the luminous pixel driver (EPD) in the first row can cross with the second power sub-line VDSBL2.

[0430] like Figure 30 , Figure 32 and Figure 33 As shown, the first power connection electrode VDCE1 can be electrically connected to the fifth transistor T5 of the first light-emitting pixel driver EPD1 (reference) through the first power connection hole VDCH1. Figure 27 The first electrode E15 and the fifth transistor T5 of the second light-emitting pixel driver EPD2 (reference) Figure 27 The first electrode is E15.

[0431] In an embodiment, the first power connection electrode VDCE1 can be electrically connected to the capacitor electrode CAE of the first light-emitting pixel driver EPD1 and the capacitor electrode CAE of the second light-emitting pixel driver EPD2 through the second power connection hole VDCH2.

[0432] In an embodiment, the first power connection electrode VDCE1 can be electrically connected to the first power sub-line VDSBL1 through the seventh power connection hole VDCH7.

[0433] like Figure 31 and Figure 33 As shown, the first power main line VDMNL1 can be electrically connected to the first power connection electrode VDCE1 through the fourth power connection hole VDCH4.

[0434] Accordingly, the fifth transistor T5 (reference) of each of the first power sub-line VDSBL1 and the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 Figure 27 The first electrode E15 and the capacitor electrode CAE can be electrically connected to the first power main line VDMNL1 through the first power connection electrode VDCE1.

[0435] like Figure 30 and Figure 32As shown, the second power connection electrode VDCE2 can be electrically connected to the fifth transistor T5 of the third light-emitting pixel driver EPD3 (reference) through the third power connection hole VDCH3. Figure 27 The first electrode is E15.

[0436] In an embodiment, the second power connection electrode VDCE2 can be electrically connected to the capacitor electrode CAE of the third light-emitting pixel driver EPD3 through the sixth power connection hole VDCH6.

[0437] In this embodiment, the second power connection electrode VDCE2 can be electrically connected to the second power sub-line VDSBL2 through the eighth power connection hole VDCH8.

[0438] like Figure 31 and Figure 33 As shown, the second power main line VDMNL2 can be electrically connected to the second power connection electrode VDCE2 through the fifth power connection hole VDCH5.

[0439] Accordingly, the first electrode E15 of the fifth transistor T5 of the second power sub-line VDSBL2 and the third light-emitting pixel driver EPD3 (reference) Figure 27 The capacitor electrode CAE can be electrically connected to the second power main line VDMNL2 via the second power connection electrode VDCE2.

[0440] The display device 100 of each embodiment described above can be applied to various electronic devices 10.

[0441] The electronic device 10 in the embodiments may include the display device 100 described above.

[0442] Furthermore, the electronic device 10 in the embodiments may further include modules or devices with other additional functions besides the display device 100.

[0443] Figure 34 This is a block diagram of an embodiment of an electronic device.

[0444] refer to Figure 34 The electronic device 10 in the embodiment may include a display module 21, a processor 22, a memory 23, and a power module 24.

[0445] The display module 21 may include a display device 100 for displaying images.

[0446] Processor 22 may include at least one of a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and a controller.

[0447] The memory 23 can store the data information required for the operation of the processor 22 or the display module 21. When the processor 22 executes the application program stored in the memory 23, image data signals and / or input control signals are transmitted to the display module 21, and the display module 21 can process the received signals and output image information through the display screen.

[0448] The power module 24 may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0449] At least one of the components of the electronic device 10 described above may be included in the display device in the above embodiments. Furthermore, some individual modules that are functionally included in a single module may be included in the display device, and some other individual modules may be provided separately from the display device. In embodiments, for example, the display device may include a display module 21, and the processor 22, memory 23, and power module 24 may be provided as other devices in the electronic device 10 besides the display device.

[0450] Figure 35 This is a schematic diagram of an embodiment of an electronic device.

[0451] refer to Figure 35 The electronic device 10 in the embodiments may include not only image display electronic devices such as smartphones 10_1a, tablet personal computers (“PCs”) 10_1b, laptop computers 10_1c, televisions (“TVs”) 10_1d and desktop monitors 10_1e, but also wearable electronic devices such as smart glasses 10_2a, head-mounted (e.g., mounted) displays 10_2b and smartwatches 10_2c, and vehicle electronic devices such as interior mirror displays and central information displays (“CIDs”) for vehicle instrument panels, central dashboards and instrument clusters.

[0452] However, the effects of this disclosure are not limited to those set forth herein. The above and other effects of this disclosure will become more apparent to those skilled in the art upon reference to the claims.

Claims

1. A display device, comprising: A substrate, including a display area, wherein an emission area is disposed in the display area; A component layer is disposed on the substrate, the component layer comprising: Light-emitting elements are arranged in each of the emitting regions; and A circuit layer is disposed between the substrate and the component layer, the circuit layer comprising: A light-emitting pixel driver is arranged in a first direction and a second direction intersecting the first direction, and transmits driving current to the light-emitting element; A first power main line extends in the second direction and transmits the first power to at least some of the light-emitting pixel drivers in the light-emitting pixel drivers; and The second power main line extends in the second direction and transmits a second power, different from the first power, to some other light-emitting pixel drivers in the light-emitting pixel driver.

2. The display device according to claim 1, wherein, The emission region includes a first emission region, a second emission region, and a third emission region that emit light at different wavelengths, and The light-emitting pixel driver includes: A first light-emitting pixel driver is electrically connected to the light-emitting element of the first emitting region in the light-emitting element; A second light-emitting pixel driver is electrically connected to the light-emitting element of the second emitting region within the light-emitting element; and The third light-emitting pixel driver is electrically connected to the light-emitting element in the third emitting region of the light-emitting element. The first power main line is electrically connected to the first light-emitting pixel driver and the second light-emitting pixel driver, and The second power main is electrically connected to the third light-emitting pixel driver.

3. The display device according to claim 2, wherein, Each of the light-emitting pixel drivers includes: The first transistor generates the drive current; A first capacitor is electrically connected to the gate electrode of the first transistor; The second transistor is electrically connected between the data line transmitting the data signal and the first electrode of the first transistor. The third transistor is electrically connected between the gate electrode of the first transistor and the second electrode of the first transistor; The fourth transistor is electrically connected between the gate initialization voltage line for transmitting the gate initialization voltage and the gate electrode of the first transistor; The fifth transistor is electrically connected to the first electrode of the first transistor; and The sixth transistor is electrically connected between the second electrode of the first transistor and the output node. The output node is electrically connected to one of the light-emitting elements. The fifth transistor of the first light-emitting pixel driver and the fifth transistor of the second light-emitting pixel driver are electrically connected to the first power main line, and The fifth transistor of the third light-emitting pixel driver is electrically connected to the second power main line.

4. The display device according to claim 3, wherein, The circuit layer further includes: A first semiconductor layer is disposed on the substrate; A first interlayer insulating layer is disposed on the first semiconductor layer; The second semiconductor layer is disposed on the first interlayer insulating layer; A second interlayer insulating layer is disposed on the second semiconductor layer; The first source / drain conductive layer is disposed on the second interlayer insulating layer; A first planarization layer covers the first source / drain conductive layer; A second source / drain conductive layer is disposed on the first planarization layer; and A second planarization layer covers the second source / drain conductive layer. In this configuration, the channel portion, first electrode, and second electrode of each of the first and fifth transistors are arranged within the first semiconductor layer, and... The channel portion, first electrode, and second electrode of each of the third and fourth transistors are arranged in the second semiconductor layer.

5. The display device according to claim 4, wherein, Each of the first power main and the second power main is disposed in the second source-drain conductive layer. Each of the first and second light-emitting pixel drivers includes a first power connection electrode disposed in the first source-drain conductive layer and electrically connected to the first power mainline. The first electrode of the fifth transistor in each of the first and second light-emitting pixel drivers is electrically connected to the first power mainline via the first power connection electrode. The third light-emitting pixel driver includes a second power connection electrode disposed in the first source / drain conductive layer and electrically connected to the second power main line, and The first electrode of the fifth transistor of the third light-emitting pixel driver is electrically connected to the second power main line via the second power connection electrode.

6. The display device according to claim 5, wherein, The first light-emitting pixel driver and the third light-emitting pixel driver are arranged alternately in the second direction. The second light-emitting pixel driver is provided as a plurality of second light-emitting pixel drivers arranged side by side in the second direction. The second light-emitting pixel driver is disposed between the first light-emitting pixel driver and the third light-emitting pixel driver in the first direction. The first power main line intersects with the second light-emitting pixel driver. The second power main line intersects with the first and third light-emitting pixel drivers. The first power connection electrodes of the first light-emitting pixel driver and the first power connection electrodes of the second light-emitting pixel driver, which are adjacent to each other in the first direction, are connected to each other, and The first power connection electrode of the first light-emitting pixel driver is electrically connected to the first power main line via the first power connection electrode of the second light-emitting pixel driver that is adjacent to the first light-emitting pixel driver in the first direction.

7. The display device according to claim 6, wherein, The circuit layer further includes a first power secondary line extending in the first direction and electrically connected to the first power main line. Each of the light-emitting pixel drivers crosses the first power sub-line, and The first capacitor of each of the light-emitting pixel drivers is electrically connected to the first power line.

8. The display device according to claim 7, wherein, The circuit layer further includes: A first gate insulating layer covers the first semiconductor layer; A first gate conductive layer is disposed on the first gate insulating layer; A second gate insulating layer covers the first gate conductive layer; and A second gate conductive layer is disposed between the second gate insulating layer and the first interlayer insulating layer. The gate electrode of the first transistor is disposed in the first gate conductive layer. The first power sub-line is disposed in the second gate conductive layer and is electrically connected to the first power main line through the first power connection electrode. Each of the light-emitting pixel drivers further includes a capacitor electrode disposed in the second gate conductive layer and overlapping the gate electrode of the first transistor in a third direction perpendicular to the first and second directions. The capacitor electrode is the portion of the first power line that overlaps with the gate electrode of the first transistor, and The first capacitor is formed in the region where the gate electrode of the first transistor and the capacitor electrode overlap each other in the third direction.

9. The display device according to claim 5, wherein, The circuit layer further includes: A first power sub-line extends in the first direction and is electrically connected to the first power main line; and The second power auxiliary line extends in the first direction and is electrically connected to the second power main line. Specifically, between two adjacent light-emitting pixel drivers along the second direction, one light-emitting pixel driver crosses the first power sub-line, and the remaining light-emitting pixel drivers cross the second power sub-line.

10. The display device according to claim 9, wherein, The first capacitor of the light-emitting pixel driver is electrically connected to the first power line, and The first capacitor of the remaining light-emitting pixel driver is electrically connected to the second power line.

11. The display device according to claim 10, wherein, The circuit layer further includes: A first gate insulating layer covers the first semiconductor layer; A first gate conductive layer is disposed on the first gate insulating layer; A second gate insulating layer covers the first gate conductive layer; and A second gate conductive layer is disposed between the second gate insulating layer and the first interlayer insulating layer. The gate electrode of the first transistor is disposed in the first gate conductive layer. The first power sub-line and the second power sub-line are disposed in the second gate conductive layer. Each of the light-emitting pixel drivers further includes a capacitor electrode disposed in the second gate conductive layer and overlapping the gate electrode of the first transistor in a third direction perpendicular to the first and second directions. The first capacitor is formed in the region where the gate electrode and the capacitor electrode of the first transistor overlap. The capacitor electrode of the light-emitting pixel driver is part of the first power sub-line, and The capacitor electrodes of the remaining light-emitting pixel drivers are part of the second power sub-line.

12. The display device according to claim 9, wherein, The first capacitor of the first light-emitting pixel driver and the first capacitor of the second light-emitting pixel driver are electrically connected to the first power main line, and The first capacitor of the third light-emitting pixel driver is electrically connected to the second power main line.

13. The display device according to claim 12, wherein, The circuit layer further includes: A first gate insulating layer covers the first semiconductor layer; A first gate conductive layer is disposed on the first gate insulating layer; A second gate insulating layer covers the first gate conductive layer; A second gate conductive layer is disposed between the second gate insulating layer and the first interlayer insulating layer. A third gate insulating layer covers the second semiconductor layer; and A third gate conductive layer is disposed between the third gate insulating layer and the second interlayer insulating layer. The gate electrode of the first transistor is disposed in the first gate conductive layer. Each of the light-emitting pixel drivers further includes a capacitor electrode arranged in an island shape in the second gate conductive layer and overlapping the gate electrode of the first transistor in a third direction perpendicular to the first and second directions. The first capacitor is formed in the region where the gate electrode and the capacitor electrode of the first transistor overlap. The first and second power sub-lines are disposed in the third gate conductive layer. The first power sub-line, the capacitor electrode of the first light-emitting pixel driver, and the capacitor electrode of the second light-emitting pixel driver are electrically connected to the first power main line via the first power connection electrode, and The second power sub-line and the capacitor electrode of the third light-emitting pixel driver are electrically connected to the second power main line via the second power connection electrode.

14. The display device according to claim 2, wherein, The first emission area emits light in the first wavelength band. The second emission region emits light in a second wavelength band lower than the first wavelength band. The third emission region emits light in a third band that is lower than the second band. Each of the light-emitting elements includes an anode electrode and a cathode electrode facing each other in a third direction perpendicular to the first direction and the second direction, and an organic layer disposed between the anode electrode and the cathode electrode. Each of the organic layers of the light-emitting element in the first emitting region and the organic layers of the light-emitting element in the second emitting region includes a light-emitting stack. The organic layer of the light-emitting element in the third emission region comprises two or more light-emitting stacks and at least one carrier generating layer disposed between the two or more light-emitting stacks. Each of the two or more light-emitting stacks and the single light-emitting stack includes a light-emitting layer in which electron-hole pairs are converted into light.

15. An electronic device comprising: The display device according to any one of claims 1 to 14 displays an image; Memory, storing applications; The processor executes the application program and transmits image data signals and input control signals to the display device; as well as The power module transmits power to the display device.

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