Semiconductor devices and their manufacturing methods

Abstract

This invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate and a stack. The stack is disposed on the substrate along a first direction. The stack includes a plurality of insulating layers and a plurality of conductive layers, which are alternately stacked on the substrate along the first direction. Conductive pillars extend along the first direction and pass through at least a portion of the stack. A protective layer extends along the first direction, surrounds the conductive pillars, and is disposed between the conductive pillars and the conductive layers. The resistance of the protective layer is higher than the resistance of the conductive layers. A storage layer surrounds the protective layer and is disposed between the protective layer and the conductive layers.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same. More particularly, this invention relates to a memory device and a method for manufacturing the same. Background Technology

[0002] The demand for three-dimensional memory devices has been increasing recently. One type of three-dimensional memory device is, for example, three-dimensional bidirectional threshold-switched memory (3D OTS memory). Bidirectional threshold switches use bidirectional materials, allowing their resistance to drop significantly at a threshold voltage (Vt), forming an on state. When the voltage drops below the threshold voltage, the resistance returns to a high level, forming a blocking state. 3D bidirectional threshold-switched memory can comprise an array of vertically stacked memory cells. However, current 3D bidirectional threshold-switched memory still faces some electrical problems, such as the tendency to generate surge currents during memory cell reads. Summary of the Invention

[0003] This invention is an improvement to three-dimensional bidirectional threshold switch memory (3D OTS memory), particularly reducing inrush current to avoid component damage and increasing system stability.

[0004] According to some embodiments, the present invention provides a semiconductor device. The semiconductor device includes a substrate and a stack. The stack is disposed on the substrate along a first direction. The stack includes a plurality of insulating layers and a plurality of conductive layers, which are alternately stacked on the substrate along the first direction. Conductive pillars extend along the first direction and pass through at least a portion of the stack. A protective layer extends along the first direction, surrounds the conductive pillars, and is disposed between the conductive pillars and the conductive layers. The resistance of the protective layer is higher than the resistance of the conductive layers. A storage layer surrounds the protective layer and is disposed between the protective layer and the conductive layers.

[0005] According to some embodiments, the present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device includes the following steps: providing a substrate; forming a stack stacked on the substrate along a first direction, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers, the insulating layers and conductive layers being alternately stacked on the substrate along the first direction; forming a conductive pillar extending along the first direction and passing through at least a portion of the stack; forming a protective layer extending along the first direction, surrounding the conductive pillar and disposed between the conductive pillar and the conductive layer, wherein the resistance value of the protective layer is higher than the resistance value of the conductive layer; forming a storage layer surrounding the protective layer and disposed between the protective layer and the conductive layer.

[0006] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0007] Figure 1 A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown;

[0008] Figure 2 A cross-sectional view of a semiconductor device according to another embodiment of the present invention is shown;

[0009] Figures 3A to 3F Draw Figure 2 A flowchart of a method for fabricating a semiconductor device;

[0010] Figure 4 A cross-sectional view of a semiconductor device according to yet another embodiment of the present invention is shown; and

[0011] Figure 5 Draw Figure 4 A cross-sectional view of the method for fabricating a semiconductor device.

[0012] Explanation of reference numerals in the attached figures:

[0013] 10~30: Semiconductor devices

[0014] 100: Base Plate

[0015] 100s: Top surface

[0016] 102: Insulation layer

[0017] 104: Conductive layer

[0018] 104': Sacrificial Layer

[0019] 106,306: Storage layer

[0020] 108: Protective layer

[0021] 110: Conductive post

[0022] 110bs: Bottom surface

[0023] 112: Overlay

[0024] 114: Contact element

[0025] 116: Conductor layer

[0026] 118: External electrode layer

[0027] 118': Conductive material layer

[0028] 120: Inner electrode layer

[0029] D1: First Direction

[0030] D2: Second Direction

[0031] D3: Third direction

[0032] H11, H31: First opening

[0033] H13, H33: Holes

[0034] ST: Stacking

[0035] ST': Stacked structure Detailed Implementation

[0036] The following description, in conjunction with the accompanying drawings, details various embodiments. The descriptions and drawings are provided for illustrative purposes only and are not intended to be limiting. For clarity, some elements and / or symbols may be omitted in some drawings. Furthermore, elements in the drawings may not be drawn to scale. It is anticipated that elements and features in one embodiment can be advantageously incorporated into another embodiment without further repetition.

[0037] According to some embodiments, the semiconductor device of the present invention can be applied to three-dimensional bidirectional threshold switching (OTS) memories, such as three-dimensional OTS-only memories, but the present invention is not limited thereto. Three-dimensional OTS-only memories use only OTS elements, which serve as both storage cells and selection elements, without requiring additional transistors or other components to control data reading and writing.

[0038] Figure 1 A cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention is shown.

[0039] Please refer to Figure 1 The semiconductor device 10 includes a substrate 100, a stack ST, a conductive pillar 110, a protective layer 108, and a storage layer 106. The stack ST is stacked on the substrate 100 along a first direction D1, wherein the stack ST includes multiple insulating layers 102 and multiple conductive layers 104, which are alternately stacked on the substrate 100 along the first direction D1. In this embodiment, the first direction D1 is, for example, parallel to the normal direction of the upper surface 100s of the substrate 100, and the bottom and top layers of the stack ST are both insulating layers 102; however, the invention is not limited to this. The conductive layer 104 is made of conductive materials, such as tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), tungsten (W), aluminum (Al), copper (Cu), ruthenium (Ru), cobalt (Co), and cobalt silicide (CoSi). X ), titanium silicide (TiSi) X Nickel (Ni), nickel silicide (NiSi) XPlatinum (Pt) or any combination thereof. The material of the insulating layer 102 may include a dielectric material, such as an oxide. In some embodiments, the conductive layer 104 may be a low-resistance conductor and may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD), due to the filling of conductive material until the removal of the sacrificial layer 104' (e.g., Figure 5 As shown in the diagram (details below), atomic layer deposition (ALD) or chemical vapor deposition is a highly conformal process in the space formed by these processes.

[0040] The conductive post 110 extends along the first direction D1, passing through at least a portion of the stack ST. In this embodiment, the bottom surface 110bs of the conductive post 110 rests in the bottom conductive layer 104 of the stack ST, without completely penetrating the bottom conductive layer 104 of the stack ST, and without extending to the bottom insulating layer 102 of the stack ST. However, the invention is not limited thereto. The material of the conductive post 110 includes conductive materials, such as tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), tungsten (W), aluminum (Al), copper (Cu), ruthenium (Ru), cobalt (Co), and cobalt silicide (CoSi). X ), titanium silicide (TiSi) X Nickel (Ni), nickel silicide (NiSi) X Platinum (Pt) or any combination thereof. In some embodiments, the conductive pillar 110 may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD), which are highly conformal processes.

[0041] A protective layer 108 extends continuously along a first direction D1, surrounds the conductive post 110, and is disposed between the conductive post 110 and the conductive layer 104. It overlaps the insulating layer 102 and the conductive layer 104 in a second direction D2 and a third direction D3, wherein the first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other. Furthermore, the protective layer 108 also extends along the second direction D2 and the third direction D3, contacting the bottom surface 110bs of the conductive post 110. The resistance value of the protective layer 108 can be higher than the resistance value of the conductive layer 104 and the resistance value of the conductive post 110. Figure 1 In the cross-sectional view shown, the protective layer 108 may have a U-shaped cross-section. The material of the protective layer 108 may include a high-resistivity material, such as doped polysilicon, undoped polysilicon, or silicon-germanium alloy (SiGe). XThe protective layer 108 may be formed using materials such as germanium (Ge), gallium nitride (GaN), indium gallium zinc oxide (IGZO), indium oxide (InO), metal oxide channel material, tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), carbon, doped carbon, graphene, or others. In some embodiments, the protective layer 108 may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD), which are highly conformal processes.

[0042] The storage layer 106 extends along a first direction D1, surrounds the protective layer 108, and is disposed between the protective layer 108 and the conductive layer 104. In this embodiment, the storage layer 106 extends continuously along the first direction D1 and overlaps the insulating layer 102 and the conductive layer 104 on the second direction D2 and the third direction D3. The storage layer 106 also extends along the second direction D2 and the third direction D3, contacting the bottom surface of the protective layer 108; however, the invention is not limited thereto. Figure 1 In the cross-sectional view shown, the storage layer 106 may have a U-shaped cross-section. Multiple intersections between the storage layer 106 and the conductive layer 104 may form multiple storage cells. The storage layer 106 may include a memory material for storing 0 or 1. Furthermore, the storage layer 106 may serve as a bidirectional threshold switch, with materials such as arsenic triselenide (As₂Se₃), zinc telluride (ZnTe), or germanium selenide (GeSe). In some embodiments, the material of the storage layer 106 may include a chalcogenide, wherein the chalcogenide is combined with one or more elements selected from the group consisting of: tellurium (Te), indium (In), gallium (Ga), selenium (Se), germanium (Ge), silicon (Si), arsenic (As), titanium (Ti), sulfur (S), antimony (Sb), and phosphorus (P). In some embodiments, the storage layer 106 can be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD), which are highly conformal processes. This is achieved by filling the storage material to the first opening H11 (e.g., Figure 3B As shown in the diagram (details below), atomic layer deposition (ALD) or chemical vapor deposition is a highly conformal process. Storage layer 106 provides 0 and 1 or multilevel characteristics.

[0043] The semiconductor device 10 may also include a capping layer 112, a contact 114, and a conductor layer 116. The capping layer 112 covers the stack ST. The conductor layer 116 is disposed on the capping layer 112 and extends along a third direction D3. The contact 114 passes through the capping layer 112 and makes electrical contact with the conductive pillar 110 and the conductor layer 116. That is, the conductor layer 116 is electrically connected to the conductive pillar 110 through the contact 114.

[0044] In some embodiments, the conductive layer 104 can serve as a word line, and the conductor layer 116 can serve as a bit line.

[0045] Compared to semiconductor devices without a protective layer, the semiconductor device of the present invention includes a protective layer 108, and the resistance of the protective layer 108 is higher than that of the conductive layer 104. Therefore, the protective layer 108 can reduce surge current to avoid damage to components and increase system stability. Furthermore, since the protective layer 108 surrounds the conductive post 110 and is disposed between the conductive post 110 and the conductive layer 104, the resistance can be locally increased for each memory cell, avoiding a global increase in the resistance of the bit lines or word lines.

[0046] Figure 2 A cross-sectional view of a semiconductor device 20 according to another embodiment of the present invention is shown. The difference between semiconductor device 20 and semiconductor device 10 is that semiconductor device 20 further includes a plurality of external electrode layers 118 and an internal electrode layer 120; other identical or similar parts will not be described in detail. Elements in semiconductor device 20 that are identical or similar to those in semiconductor device 10 are indicated by the same or similar element symbols and have the same or similar structure, materials, and functions.

[0047] Please refer to Figure 2 The external electrode layer 118 of the semiconductor device 20 is disposed between the conductive layer 104 and the storage layer 106. The external electrode layer 118 surrounds the storage layer 106. Different external electrode layers 118 are separated by an insulating layer 102. The inner electrode layer 120 is disposed between the storage layer 106 and the protective layer 108, and surrounds the protective layer 108. The inner electrode layer 120 extends continuously along a first direction D1 and overlaps the insulating layer 102 and the conductive layer 104 in the second direction D2 and the third direction D3. Furthermore, the inner electrode layer 120 also extends along the second direction D2 and the third direction D3, contacting the bottom surface of the protective layer 108. Figure 2 In the cross-sectional view shown, the inner electrode layer 120 may have a U-shaped cross-section. The materials of the outer electrode layer 118 and the inner electrode layer 120 may each include a conductive material, such as tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), carbon, doped carbon, graphene, or others.

[0048] In some embodiments, the outer electrode layer 118 can be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD), due to the filling of conductive material into the pores H13 (e.g. Figure 3C As shown in the diagram (details below), atomic layer deposition (ALD) or chemical vapor deposition (CVD) is a highly conformal process. The conductive layer 104 and the storage layer 106 have good interface characteristics and stable electrical-temperature characteristics. The resistance of the outer electrode layer 118 can be less than or greater than the resistance of the conductive layer 104, but less than the resistance of the protective layer 108.

[0049] In some embodiments, the inner electrode layer 120 may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD), due to the filling of conductive material into the first opening H11 (e.g. Figure 3B As shown in the diagram (details below), atomic layer deposition (ALD) or chemical vapor deposition (CVD) is a highly conformal process. The storage layer 106 and the protective layer 108 have good interface characteristics, and the storage layer 106 and the protective layer 108 have stable electrical-temperature characteristics. The resistance of the inner electrode layer 120 can be less than or greater than the resistance of the conductive layer 104, but less than the resistance of the protective layer 108.

[0050] The inner electrode layer 120 and the conductive pillar 110 have good interface characteristics and stable electrical temperature characteristics. The resistance of the protective layer 108 can be greater than the resistance of the outer electrode layer 118, the inner electrode layer 120, and the conductive pillar 110 to reduce surge current.

[0051] The configuration of the outer electrode layer 118 and the inner electrode layer 120 is selective, depending on interface, temperature, electrical, or mechanical characteristics. However, the resistance of the protective layer 108 must be high enough to reduce inrush current. In one embodiment, the semiconductor device includes an outer electrode layer 118 but not an inner electrode layer 120. In another embodiment, the semiconductor device includes an inner electrode layer 120 but not an outer electrode layer 118.

[0052] Compared to embodiments without an outer electrode layer 118 and an inner electrode layer 120, the outer electrode layer 118 and the inner electrode layer 120 provide better interface performance between the storage layer 106 and the conductor (e.g., conductive layer 104 or conductive pillar 110), such as better electrical interface performance, mechanical interface performance, or thermal interface performance. That is, the outer electrode layer 118 and the inner electrode layer 120 can improve the electrical conductivity between the storage layer 106 and the conductor, increase the adhesion between the storage layer 106 and the conductor, or prevent metal ions in the conductor from escaping into the storage layer 106, respectively.

[0053] Figures 3A to 3F Draw Figure 2 A flowchart illustrating a method for fabricating the semiconductor device 20. Specifically, the method for fabricating the semiconductor device 20 includes, as shown below... Figures 3A to 3F The steps shown are in sequence.

[0054] Please refer to Figure 3A A base plate 100 is provided, and a stack ST is formed. The stack ST is stacked on the base plate 100 along a first direction D1, wherein the stack ST includes a plurality of insulating layers 102 and a plurality of conductive layers 104, and the insulating layers 102 and conductive layers 104 are alternately stacked on the base plate 100 along the first direction D1.

[0055] Please refer to Figure 3B A first opening H11 is formed by an etching process. The first opening H11 passes through at least a portion of the stacked ST along a first direction D1. In this embodiment, the bottom of the first opening H11 rests on the bottommost insulating layer 102 of the stacked ST.

[0056] Please refer to Figure 3C Multiple holes H13 are formed through an etching-back process, such as isotropic reactive ion etching (Isotropic RIE). The holes H13 connect to the first opening H11 and correspond to the conductive layer 104. That is, the etching-back process removes a portion of the conductive layer 104, causing the conductive layer 104 to recede and form holes H13 between two adjacent insulating layers 102.

[0057] Please refer to Figure 3DConductive material is deposited into the holes H13, the top of the stacked ST, and the first opening H11 to form a conductive material layer 118'. The conductive material layer 118' conforms to the top of the stacked ST and the first opening H11. The material of the conductive material layer 118' is the same as the material of the aforementioned outer electrode layer 118, and will not be described again here.

[0058] Please refer to Figure 3E Excess conductive material layer 118' is removed by an etching process to form an external electrode layer 118 located in the hole H13, such as isotropic reactive ion etching.

[0059] Please refer to Figure 3F A storage layer 106, an inner electrode layer 120, a protective layer 108, and a conductive pillar 110 are sequentially formed in the first opening H11 (sidewalls and bottom) through multiple deposition processes. Next, a planarization process is performed to make the tops of the topmost insulating layer 102, storage layer 106, inner electrode layer 120, protective layer 108, and conductive pillar 110 of the stacked ST layers flush. The planarization process is, for example, chemical mechanical planarization (CMP). Multiple memory cells can be formed at multiple intersections between the storage layer 106 and the conductive layer 104. Memory cells corresponding to the same storage layer 106 are stacked in the first direction D1 to form a memory array. Multiple storage layers 106 form multiple memory arrays, and multiple memory arrays form a memory array. Then, a capping layer 112 is formed to seal the memory array. The material of the capping layer 112 is, for example, an oxide.

[0060] Subsequently, a contact 114 is formed that passes through the cover layer 112 and makes electrical contact with the conductive pillar 110, and a conductor layer 116 is disposed on the cover layer 112 and the contact 114, to form such a Figure 2 The semiconductor device 20 shown.

[0061] Figure 4 A cross-sectional view of a semiconductor device 30 according to another embodiment of the present invention is shown, omitting the contact 114 and the conductor layer 116. The difference between semiconductor device 30 and semiconductor device 20 is that the shape of the storage layer 306 in semiconductor device 30 differs from that of storage layer 106; other similar or identical parts will not be described in detail. Elements in semiconductor device 30 that are the same as or similar to those in semiconductor device 20 are indicated by the same or similar element symbols and have the same or similar structure, materials, and functions.

[0062] Please refer to Figure 4The storage layer 306 extends discontinuously in the first direction D1 and overlaps the conductive layer 104 in the second direction D2 and the third direction D3. Adjacent storage layers 306 are separated by an insulating layer 102.

[0063] Because the shape of storage layer 306 differs from that of storage layer 106, the fabrication method of storage layer 306 differs slightly from that of storage layer 106. For example, in forming the first opening H31 (similar to...), Figure 3B After forming the first opening H11 (and having the same method of forming the first opening H11), the hole H33 (similar to) is formed. Figure 3C A hole H13 is formed using the same method as hole H13. A first opening H31 extends along a first direction D1 through at least a portion of the stack ST. The width of the first opening H31 in the second direction D2 may be less than the width of the first opening H11 in the second direction D2. A hole H33 connects to the first opening H31 and corresponds to the conductive layer 104. The width of the hole H33 in the second direction D2 may be greater than the width of the hole H13 in the second direction D2. For example, the hole H33 is formed by an isotropic etching process that etches the conductive layer 104 to form a deeper recessed profile than the hole H11. The isotropic etching process has very high selectivity for the conductive layer 104. The insulating layer 102 remains almost intact. Subsequently, conductive material is filled into the hole H33 by a deposition method (e.g., ALD or CVD). Next, an isotropic etching process is performed to pull back the conductive material, forming a shallow recess that is shallower than the hole H33. In other words, a portion of the conductive material is removed to re-expose a portion of the hole H33, and the remaining portion of the conductive material forms the outer electrode layer 118. The isotropic etching process has very high selectivity for the conductive material forming the conductive layer 104. The insulating layer 102 remains almost intact. Then, storage material is filled into the portion (shallow recess) of the hole H33, onto the stack ST, and into the first opening 31, forming a storage material layer (not shown) conformally to the stack ST and the first opening 31. Excess storage material layer (not shown) is then removed by an isotropic etching process to form the storage layer 306 in the hole H33. The isotropic etching process has very high selectivity for the storage material layer (not shown). The insulating layer 102 remains almost intact. That is, the hole H33 can accommodate the outer electrode layer 118 and the storage layer 306. After the storage layer 306 is formed, the inner electrode layer 120, the protective layer 108 and the conductive pillar 110 are sequentially formed in the first opening H31 by the same method as described above for the fabrication of the inner electrode layer 120, the protective layer 108 and the conductive pillar 110.

[0064] In one embodiment, the method for forming the stacked STs of semiconductor device 30 is the same as the method for forming the stacked STs of semiconductor device 20 described above; however, the present invention is not limited thereto. In another embodiment, the method for forming the stacked STs of semiconductor device 30 differs from the method for forming the stacked STs of semiconductor device 20 described above, such as... Figure 5 As shown.

[0065] Figure 5 Draw Figure 4 A cross-sectional view of a method for fabricating another embodiment of the semiconductor device 30.

[0066] The steps for forming the stacked ST of the semiconductor device 30 may include the steps described below. First, forming as... Figure 5 The layered structure ST' shown is an insulating layer 102 and a plurality of sacrificial layers 104' alternately stacked along a first direction D1, wherein the material of the insulating layer 102 may be the same as that described above. Figure 2 The insulating layer 102 is made of the same material as the sacrificial layer 104', and the material of the sacrificial layer 104' may include nitrides, such as silicon nitride. After forming the conductive pillars 110 and the capping layer 112, the sacrificial layer 104' is removed by an etching process, and conductive material is filled in the location where the sacrificial layer 104' is removed to form the conductive layer 104, wherein the material of the conductive layer 104 may be the same as that described above. Figure 2 The conductive layer 104 is made of the same material.

[0067] It should be understood that, Figure 1 and Figure 2 The formation steps of the stacked STs of the semiconductor devices 10~20 can also be replaced with the steps regarding... Figure 5 The aforementioned manufacturing method.

[0068] In summary, the present invention provides a semiconductor device and a method for manufacturing the same. Because the semiconductor device of the present invention includes a protective layer, which can locally increase the resistance value of each memory cell, surge current can be reduced, components can be protected from damage by surge current, and the stability of the system can be increased.

[0069] While the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art will be able to make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor device, comprising: One base plate; A stack is disposed on the base plate along a first direction, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers, the insulating layers and the conductive layers being alternately stacked on the base plate along the first direction; A conductive post extends along the first direction and passes through at least a portion of the stack; A protective layer extending along the first direction, surrounding the conductive post and disposed between the conductive post and the conductive layers, wherein the resistance of the protective layer is higher than the resistance of the conductive layers; and A storage layer surrounds the protective layer and is disposed between the protective layer and the conductive layers.

2. The semiconductor device of claim 1, wherein the storage layer extends continuously along the first direction and overlaps the insulating layer and the conductive layer in a second direction and a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other.

3. The semiconductor device of claim 1, wherein the storage layer extends discontinuously in the first direction and overlaps the conductive layers in a second direction and a third direction, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

4. The semiconductor device of claim 1 further includes a plurality of external electrode layers disposed between the conductive layers and the storage layer.

5. The semiconductor device of claim 4, wherein the external electrode layers surround the memory layer.

6. The semiconductor device according to claim 1, further comprising an internal electrode layer disposed between the storage layer and the protective layer.

7. The semiconductor device of claim 6, wherein the inner electrode layer surrounds the protective layer.

8. The semiconductor device of claim 1, further comprising a conductor layer disposed on the stack and electrically connected to the conductive pillar.

9. The semiconductor device of claim 1, wherein the protective layer extends continuously along the first direction and overlaps the insulating layers and the conductive layers in a second direction and a third direction, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

10. The semiconductor device of claim 1, wherein the storage layer serves as a bidirectional threshold switch.

11. A method for manufacturing a semiconductor device, comprising: Provide a base plate; A stack is formed on the base plate along a first direction, wherein the stack includes a plurality of insulating layers and a plurality of conductive layers, which are alternately stacked on the base plate along the first direction; A conductive pillar is formed, which extends along the first direction and passes through at least a portion of the stack; A protective layer is formed, extending along the first direction, surrounding the conductive post and disposed between the conductive post and the conductive layers, wherein the resistance value of the protective layer is higher than the resistance value of the conductive layers; and A storage layer is formed, which surrounds the protective layer and is disposed between the protective layer and the conductive layers.

12. The method for manufacturing a semiconductor device according to claim 11, further comprising: A first opening is formed, the first opening passing through at least a portion of the stack along the first direction; as well as The storage layer and the protective layer are formed sequentially in the first opening.

13. The method of manufacturing a semiconductor device according to claim 12, wherein the storage layer extends continuously along the first direction and overlaps the insulating layer and the conductive layer in a second direction and a third direction, wherein the first direction, the second direction and the third direction are perpendicular to each other.

14. The method for manufacturing a semiconductor device according to claim 12, further comprising: Multiple holes are formed, which are connected to the first opening and correspond to the conductive layers; as well as Conductive material is filled into these pores to form multiple outer electrode layers.

15. The method of fabricating a semiconductor device according to claim 12, further comprising forming an internal electrode layer between the storage layer and the protective layer.

16. The method for manufacturing a semiconductor device according to claim 11, further comprising: A first opening is formed, the first opening passing through at least a portion of the stack along the first direction; Multiple holes are formed, which are connected to the first opening and correspond to the conductive layers; Fill these pores with conductive material; A portion of the conductive material is removed to expose a portion of these pores, and the remaining portion of the conductive material forms multiple outer electrode layers; The storage material is filled into this portion of the pores to form the storage layer; as well as The protective layer is formed in the first opening.

17. The method of manufacturing a semiconductor device according to claim 16, wherein the storage layer extends discontinuously in the first direction and overlaps the conductive layers in a second direction and a third direction, wherein the first direction, the second direction, and the third direction are perpendicular to each other.

18. The method for manufacturing a semiconductor device according to claim 16, further comprising: Conductive material is filled into these pores to form multiple outer electrode layers.

19. The method of fabricating a semiconductor device according to claim 16, further comprising forming an internal electrode layer between the storage layer and the protective layer.

20. The method of fabricating a semiconductor device according to claim 11, wherein the step of forming the stack comprises: A stacked structure is formed, the stacked structure comprising insulating layers and a plurality of sacrificial layers stacked alternately along the first direction; as well as These sacrificial layers are removed, and conductive material is filled in the locations where the sacrificial layers were removed to form these conductive layers.

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