An electrochemical vertical memristor transistor and its fabrication method

Abstract

This invention belongs to the field of microelectronic device technology, specifically an electrochemical vertical memristor transistor and its fabrication method. It comprises a substrate, gate, electrolyte layer, semiconductor layer, source, insulating layer, and drain stacked together. Part of the electrolyte layer is disposed on the gate, and part on the substrate, forming a step through the height difference between the two sides. The semiconductor layer is disposed on the electrolyte layer. The source is disposed on the semiconductor layer in a portion that does not overlap with the gate in the vertical projection direction. The insulating layer is disposed on the source to prevent direct electrical contact between the source and drain. The drain is disposed on both the semiconductor layer and the insulating layer. This invention employs a stepped structure, placing the gate and source on opposite sides of the step, concentrating the gate electric field in the vertical channel region. By effectively constraining the gate electric field region, device power consumption can be reduced, and more precise resistive state control can be achieved.

Description

Technical Field

[0001] This invention belongs to the field of microelectronic device technology, specifically relating to an electrochemical vertical memristor transistor and its fabrication method. Background Technology

[0002] With the rapid development of artificial intelligence and edge computing, traditional von Neumann architectures are facing challenges. The von Neumann architecture, due to its separation of storage and computation, faces bottlenecks of high energy consumption and high latency, making it difficult to meet the demands of real-time, low-power intelligent sensing and computing. Biosynapses, through their "sensing-computing-storage integrated" parallel processing mechanism, achieve complex cognitive functions with ultra-low power consumption, providing a core inspiration for hardware solutions.

[0003] Memristors, as typical two-terminal in-memory computing devices, achieve resistive state switching through electric field-induced ion or electron migration. They possess advantages such as volatile / non-volatile characteristics, low power consumption, and high integration density, and are widely used to simulate biological synapses. However, the inherent limitations of the two-terminal structure, such as shared read / write paths, crosstalk and creeping currents, and insufficient degrees of freedom in state control, limit their application in high-precision, large-scale neuromorphic systems. Memristor transistors, improved in-memory computing devices based on traditional field-effect transistors, have a three-terminal architecture. The presence of their gate is crucial for synaptic weight adjustment and is key to improving the accuracy and uniformity of in-memory computing devices. However, memristor transistors still face drawbacks such as complex structure, low integration density, and high power consumption. Therefore, how to improve the accuracy and integration density of in-memory computing devices while reducing power consumption is an urgent technical problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide an electrochemical vertical memristor transistor and its fabrication method, so as to reduce power consumption and improve accuracy.

[0005] To achieve the above objectives, the present invention provides an electrochemical vertical memristor transistor, comprising: a substrate, a gate, an electrolyte layer, a semiconductor layer, a source, and a drain; wherein, the gate is disposed on the substrate, a portion of the electrolyte layer is disposed on the gate, and a portion is disposed on the substrate adjacent to the gate, forming a step through the height difference between the two sides; the semiconductor layer is disposed on the electrolyte layer, also forming a step through the height difference between the two sides; the source is disposed on one side of the step in the vertical projection direction of the semiconductor layer and the gate, which does not overlap; the drain is disposed on the other side of the step in the semiconductor layer, and the semiconductor layer forms a vertical channel between the drain and the source.

[0006] Furthermore, the thickness of the gate electrode is 1-500 nm, and the thickness of the source electrode is less than the thickness of the gate electrode.

[0007] Furthermore, the thickness of the electrolyte layer is greater than or equal to half the thickness of the gate.

[0008] Furthermore, the lateral spacing between the source and the gate in the vertical projection direction is 5 nm-10 μm, preferably 10 nm-2 μm.

[0009] Furthermore, it also includes an insulating layer disposed above the source electrode, the insulating layer at least covering the upper surface of the source electrode, for preventing direct electrical contact between the source electrode and the drain electrode.

[0010] Furthermore, the drain electrode at least covers the corner region of the step on the other side of the semiconductor layer.

[0011] Furthermore, the electrolyte layer is made of Li. x SiO y Li x AlO y Li x TaO y LiPON, Li x M y One or more of PS3, wherein M is Mg, Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Cd, In, Sn or Hg, and x and y are numbers greater than 0 used to represent stoichiometry, and its thickness is 1-500 nm; The semiconductor layer is made of oxide semiconductor or two-dimensional semiconductor material, and its thickness is 1-100 nm.

[0012] Furthermore, the source electrode is made of metal or graphene with a thickness of 1-100 nm, and the drain electrode is made of metal with a thickness of 1-300 nm. The insulating layer is made of SiO2, Si3N4, Al2O3, HfO2, Sb2O3 or BN, and its thickness is 1-500 nm.

[0013] The present invention also provides a method for fabricating the electrochemical vertical memristor transistor according to any one of the above claims, comprising the following steps: S1. A gate electrode is fabricated on a portion of the substrate; S2. An electrolyte layer is prepared on the gate electrode. Part of the electrolyte layer is stacked on the gate electrode, and another part is stacked on the substrate adjacent to the gate electrode to form a stepped structure. S3. Prepare a semiconductor layer on the electrolyte layer to form a stacked stepped structure as a vertical channel; S4. The source electrode is prepared by stepping on the side of the semiconductor layer that does not overlap with the gate in the direction perpendicular to the projection direction. S5. Prepare a drain on the step on the other side of the semiconductor layer.

[0014] Furthermore, before fabricating the drain in step S5, an insulating layer is fabricated on the source, and then the drain is fabricated on the other side step and the insulating layer.

[0015] In summary, compared with the prior art, the above-described technical solutions conceived by this invention mainly possess the following technical advantages: 1. The electrochemical vertical memristor transistor structure provided by this invention adopts a vertical structure design. The electrolyte layer covers the junction of the substrate and the gate, forming a step, which in turn forms a vertical channel region on the semiconductor layer. The channel length can be adjusted by the step height. This structural design effectively constrains the gate electric field, concentrating it in the vertical channel region, which helps reduce gate leakage current and thus power consumption. At the same time, the "corner" at the vertical channel region increases the contact area between the electrolyte layer and the semiconductor layer, which is beneficial for controlling lithium-ion migration at low gate voltages and achieving precise modulation of channel conductance through low gate voltage programming.

[0016] 2. In this invention, a lithium-ion-doped solid electrolyte layer is used instead of a conventional gate dielectric layer. Under a positive gate bias, lithium ions are embedded from the electrolyte layer into the channel layer, increasing the channel conductivity. Under a negative gate bias, lithium ions are extracted from the channel, decreasing the channel conductivity. The hysteresis window based on ion migration enables the device to exhibit memristor characteristics.

[0017] 3. The present invention adopts a vertical structure design, which can significantly reduce the device area and achieve high-density integration. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure obtained in the first step of the preparation process of Example 1 of the present invention; Figure 2 This is a schematic diagram of the structure obtained in the second step of the preparation process in Example 1 of the present invention; Figure 3 This is a schematic diagram of the structure obtained in the third step of the preparation process in Example 1 of the present invention; Figure 4 This is a schematic diagram of the structure obtained in the fourth step of the preparation process in Example 1 of the present invention; Figure 5 This is a schematic diagram of the structure obtained in the fifth step of the preparation process in Example 1 of the present invention; Figure 6 This is a schematic diagram of the structure obtained in the sixth step of the preparation process in Example 1 of the present invention; Figure 7 This is a schematic diagram of the structure obtained in the seventh step of the preparation process in Example 1 of the present invention; Figure 8 This is a schematic diagram of the structure obtained in the sixth step of the preparation process in Example 2 of the present invention; Figure 9This is a schematic diagram of the structure obtained in the seventh step of the preparation process in Example 2; Figure 10 This is a schematic diagram of the structure obtained in the fifth step of the preparation process in Example 3; Figure 11 This is a schematic diagram of the structure obtained in the sixth step of the preparation process in Example 3 of the present invention; Figure 12 This is a schematic diagram of the structure obtained in the seventh step of the preparation process in Example 3 of the present invention.

[0019] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein: 100 - Substrate, 200 - Gate, 300 - Electrolyte layer, 400 - Semiconductor layer, 500 - Source, 600 - Insulating layer, 700 - Drain. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0021] This invention provides an electrochemical vertical memristor transistor, comprising: a substrate 100, a gate 200, an electrolyte layer 300, a semiconductor layer 400, a source 500, an insulating layer 600, and a drain 700, which are sequentially stacked. A portion of the electrolyte layer 300 is disposed on the gate 200, and a portion is disposed on the substrate 100 adjacent to the gate 200, forming a step through a height difference between its two sides. The semiconductor layer 400 is disposed on the electrolyte layer 300, also forming a step through a height difference between its two sides. The source 500 is disposed on one step on which the vertical projections of the semiconductor layer 400 and the gate 200 do not overlap. The drain 700 is disposed on the other step of the semiconductor layer 400, and at least covers the corner region of the other step. The semiconductor layer 400 forms a vertical channel between the drain 700 and the source 500.

[0022] To reduce leakage current and optimize gate control, this invention employs a stepped structure, placing the gate and source on opposite sides of a step. This cleverly combines the local constraint of the gate electric field with the vertical channel, overcoming the problems of high leakage current and high power consumption inherent in conventional planar lithium-ion gate electrochemical transistors. This structure can precisely control the transistor at low gate voltage by optimizing the gate electric field distribution, thereby reducing device power consumption. Furthermore, it also offers the advantage of increased integration density.

[0023] The substrate 100 is a rigid substrate or a flexible substrate with an insulating layer.

[0024] The thickness of the gate 200 is 1-200 nm, preferably 5-50 nm, and the thickness of the source 500 is less than or equal to the thickness of the gate 200. The thickness of the source 500 is also preferably less than or equal to the thickness of the semiconductor layer 400. The gate 200 is made of metal.

[0025] The height of the step is determined by the thickness of the gate 200, and is 1–200 nm, preferably 5–50 nm. The vertical channel region is formed along the sidewall of the step, and its channel length is determined by the height of the step. In particular, the thickness of the electrolyte layer 300 is greater than or equal to half the thickness of the gate 200, so as to ensure that the sidewall at the step of the gate 200 can be completely shielded by the electrolyte layer 300.

[0026] The lateral spacing between the source 500 and the gate 200 in the vertical projection direction is 5 nm-10 μm, preferably 10 nm-2 μm. By adjusting this spacing, the integration density can be controlled, and the electric field distribution can be optimized, thereby better confining the gate electric field locally to the vertical channel.

[0027] Specifically, when the drain 700 and the source 500 do not overlap in their vertical downward projections, an insulating layer may not be required. Preferably, the insulating layer 600 is disposed above the source 500 and at least covers the upper surface of the source 500 to prevent direct electrical contact between the source 500 and the drain 700. In this case, the drain 700 may cover the semiconductor layer 400 and the insulating layer 600.

[0028] In some embodiments, the drain 700 covers the entire area of ​​the step on the other side of the semiconductor layer 400 and the area above the insulating layer 600, such as... Figure 7 Or 9. The drain 700 can also cover only a localized area adjacent to the corner (above the vertical channel) on the other side of the step (left side of the diagram), such as... Figure 12 .

[0029] In some embodiments, the source 500 can cover the entire area of ​​the right-side step (i.e., the side step that does not overlap with the gate 200 in the direction perpendicular to its projection), such as... Figure 5 Alternatively, it can cover only a portion of the step, such as... Figure 10 .

[0030] The electrolyte layer 300 is made of lithium-ion electrolyte, such as Li. x SiO y Li x AlO y Li x TaOy LiPON, Li x M y PS3, etc., wherein M is Mg, Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Cd, In, Sn or Hg, and x and y are numbers greater than 0 used to represent stoichiometry, and its thickness is 1-500 nm, preferably 5-50 nm.

[0031] The semiconductor layer 400 is made of oxide semiconductor or two-dimensional semiconductor material, and its thickness is 1-100 nm, preferably 5-30 nm.

[0032] The source electrode 500 is made of metal or graphene, with a thickness of 1-100 nm, preferably 1-20 nm; the drain electrode 700 is made of metal, with a thickness of 1-300 nm, preferably 10-50 nm. The insulating layer 600 is made of SiO2, Si3N4, Al2O3, HfO2, Sb2O3 or BN, and its thickness is 1-500 nm, preferably 5-30 nm.

[0033] This invention uses a lithium-ion electrolyte as the electrolyte layer to achieve electrochemical doping. When a gate voltage is applied, lithium ions gather at the interface between the electrolyte and the semiconductor and are embedded in the semiconductor layer. When the gate voltage is removed, the lithium ions separate from the semiconductor layer. Channel resistance switching is achieved based on the lithium ion embedding and separation process.

[0034] It should be noted that the accompanying drawings for the following embodiments are only schematic diagrams, and their dimensions may not completely correspond to those of the embodiments. However, those skilled in the art should understand that the actual structure obtained will vary depending on the process. For example, during the deposition of each layer, the edges are usually not right-angled structures, but rather rounded or chamfered structures. Therefore, a gentle transition structure can usually be formed at the steps.

[0035] Example 1 This embodiment describes an electrochemical vertical memristor transistor and its fabrication method, the final structure of which is as follows: Figure 7As shown, the electrochemical vertical transistor is formed by stacking a substrate 100, a gate 200, an electrolyte layer 300, a semiconductor layer 400, a source 500, an insulating layer 600, and a drain 700. Part of the electrolyte layer 300 is disposed on the gate 200 and part is disposed on the substrate 100, forming a step. The semiconductor layer 400 is disposed on the electrolyte layer 300, also forming a step structure. The source 500 is disposed on the portion of the semiconductor layer 400 that does not overlap with the gate 200 in the vertical projection direction. The insulating layer 600 is disposed on the source 500 and at least covers the upper surface of the source 500, blocking direct electrical contact between the source 500 and the drain 700. The drain 700 covers the entire area of ​​the step on the other side of the semiconductor layer 400 and the area above the insulating layer 600.

[0036] The fabrication method of an electrochemical vertical memristor transistor specifically includes the following steps: (1) Using a silicon wafer with 300 nm SiO2 as the substrate, cut it into 1 cm × 1 cm pieces, and then ultrasonically clean it for 15 min each in acetone, isopropanol, and deionized water. After rinsing it with deionized water, dry it with a nitrogen gas gun. Figure 1 .

[0037] (2) Gate patterns were fabricated on silicon wafers using electron beam lithography. PMMA photoresist was used, and after spin coating, the sample was baked at 150°C for 5 min. After exposure, the sample was immersed in the developer for 5-10 s, then in the fixer for 10 s and dried with a nitrogen gas gun. 40 nm W was deposited as the gate using thermal evaporation deposition. The process conditions were: W particles as the evaporation source, an evaporation rate of 0.1 Å / s, and a chamber pressure less than 8 × 10⁻⁶. -4 Pa. After coating, the prepared sample is placed in acetone, which is heated to 60-70℃, and soaked for 20 minutes to complete the removal of the adhesive. Figure 2 .

[0038] (3) An electrolyte layer pattern is fabricated on a silicon wafer using electron beam lithography, exposing part of it on the gate and the other part on the substrate, under the same process conditions as in step (2). 30 nm Li is deposited using radio frequency magnetron sputtering. 1 / 3AlO 5 / 3 As a solid electrolyte, the process conditions are: using Li 1 / 3 AlO 5 / 3 The sputtering target is used as the sputtering target, with argon as the working gas. The process parameters are 80 W, 35 sccm Ar, such as... Figure 3 .

[0039] (4) After depositing 30 nm Li 1 / 3 AlO 5 / 3Subsequently, 20 nm indium gallium zinc oxide (IGZO) was deposited using radio frequency magnetron sputtering as the semiconductor channel. The process conditions were as follows: IGZO target was used as the sputtering target, argon and oxygen were used as the working gases, and the process parameters were 60 W, 35 sccm Ar, and 5 sccm O2. After deposition, the prepared sample was placed in acetone, which was heated to 60-70℃, and immersed for 20 min to complete the resist removal. Figure 4 .

[0040] (5) A source layer pattern is fabricated on the semiconductor layer using electron beam lithography, ensuring it is located on the entire area of ​​the other side of the stepped structure and does not overlap with the gate in the vertical projection direction. The process conditions are the same as in step (2). 20 nm Au is prepared as the source using thermal evaporation deposition. The process conditions are: Au particles as the evaporation source, evaporation rate of 0.1 Å / s, and chamber pressure less than 8 × 10⁻⁶. -4 Pa. After coating, the prepared sample is placed in acetone, which is heated to 60-70℃, and soaked for 20 minutes to complete the removal of the adhesive. Figure 5 .

[0041] (6) An insulating layer pattern was fabricated on the source electrode using electron beam lithography, making it slightly larger than the source electrode layer. The process conditions were the same as in step (2). A 20 nm Sb₂O₃ insulating layer was prepared by thermal evaporation deposition. The process conditions were: Sb₂O₃ powder was used as the evaporation source, the evaporation rate was 0.1 Å / s, and the chamber pressure was less than 8 × 10⁻⁶. -4 Pa. After coating, the prepared sample is placed in acetone, which is heated to 60-70℃, and soaked for 20 minutes to complete the removal of the adhesive. Figure 6 .

[0042] (7) A drain pattern is fabricated on the insulating layer using electron beam lithography, simultaneously covering both the semiconductor and insulating layers. The process conditions are the same as in step (2). 50 nm Au is prepared as the drain using thermal evaporation deposition. The process conditions are: Au particles as the evaporation source, an evaporation rate of 0.1 Å / s, and a chamber pressure less than 8 × 10⁻⁶. -4 Pa. After coating, the prepared sample was placed in acetone, which was heated to 60-70℃ and immersed for 20 minutes to remove the adhesive. The final structure is as follows. Figure 7 .

[0043] Example 2 The difference from Example 1 is that in step (6), the insulating layer not only covers the source electrode but also a small portion of the semiconductor layer to the left of the step. By extending the insulating layer to cover a local area of ​​the semiconductor layer to the left of the step, the risk of direct contact between the source and drain electrode during subsequent drain deposition can be further reduced, improving the reliability of source-drain isolation. Figure 8-9 .

[0044] Example 3 The difference from Example 1 is that in step (5), the source electrode only covers a portion of the right-side step, while its left side is separated from the step sidewall, such as... Figure 10 In step (6), the insulating layer covers the source electrode and the gap between its left side and the step sidewall to avoid direct electrical contact between the source electrode and the subsequent drain electrode deposition, such as... Figure 11 In step (7), the drain only covers a local area above the vertical channel in the left step, that is, the part adjacent to the sidewall of the step, such as... Figure 12 .

[0045] In summary, this invention uses a lithium-ion electrolyte as the electrolyte layer to achieve electrochemical doping. When a gate voltage is applied, lithium ions accumulate at the electrolyte-semiconductor interface and embed into the semiconductor layer. When the gate voltage is removed, the lithium ions separate from the semiconductor layer. Channel resistance switching is achieved based on the lithium ion embedding and separation process. To reduce leakage current and optimize gate control, a stepped structure is adopted, with the gate and source respectively positioned on opposite sides of the step, concentrating the gate electric field in the vertical channel region. This invention employs a vertical structure design, which significantly reduces device area and achieves high-density integration. By effectively constraining the gate electric field region, device power consumption can be reduced, and more precise resistance control can be achieved, demonstrating extremely high application value in artificial neurons and neuromorphic computing applications.

[0046] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An electrochemical vertical memristor transistor, characterized in that, include: The device comprises a substrate (100), a gate (200), an electrolyte layer (300), a semiconductor layer (400), a source (500), and a drain (700). The gate (200) is disposed on the substrate (100). A portion of the electrolyte layer (300) is disposed on the gate (200), and a portion is disposed on the substrate (100) adjacent to the gate (200), forming a step through the height difference between the two sides. The semiconductor layer (400) is disposed on the electrolyte layer (300), also forming a step through the height difference between the two sides. The source (500) is disposed on the step on one side of the semiconductor layer (400) that does not overlap with the gate (200) in the vertical projection direction. The drain (700) is disposed on the step on the other side of the semiconductor layer (400), and the semiconductor layer (400) forms a vertical channel between the drain (700) and the source (500).

2. The electrochemical vertical memristor transistor according to claim 1, characterized in that, The thickness of the gate (200) is 1-200 nm, and the thickness of the source (500) is less than or equal to the thickness of the gate (200).

3. The electrochemical vertical memristor transistor according to claim 2, characterized in that, The thickness of the electrolyte layer (300) is greater than or equal to half the thickness of the gate (200).

4. The electrochemical vertical memristor transistor according to any one of claims 1-3, characterized in that, The lateral spacing between the source (500) and the gate (200) in the vertical projection direction is 5 nm-10 μm, preferably 10 nm-2 μm.

5. The electrochemical vertical memristor transistor according to claim 4, characterized in that, It also includes an insulating layer (600) disposed above the source electrode (500), the insulating layer (600) covering at least the upper surface of the source electrode (500) to prevent direct electrical contact between the source electrode (500) and the drain electrode (700).

6. The electrochemical vertical memristor transistor according to claim 5, characterized in that, The drain (700) at least covers the corner region of the step on the other side of the semiconductor layer (400).

7. The electrochemical vertical memristor transistor according to claim 1, characterized in that, The electrolyte layer (300) is made of Li x SiO y Li x AlO y Li x TaO y LiPON, Li x M y One or more of PS3, wherein M is Mg, Al, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Cd, In, Sn or Hg, x and y are numbers greater than 0 used to represent stoichiometry, and the thickness of the electrolyte layer (300) is 1-500 nm; The semiconductor layer (400) is made of oxide semiconductor or two-dimensional semiconductor material, and its thickness is 1-100 nm.

8. The electrochemical vertical memristor transistor according to claim 1, characterized in that, The source electrode (500) is made of metal or graphene and has a thickness of 1-100 nm; the drain electrode (700) is made of metal and has a thickness of 1-300 nm. The insulating layer (600) is made of SiO2, Si3N4, Al2O3, HfO2, Sb2O3 or BN, and its thickness is 1-500 nm.

9. A method for fabricating an electrochemical vertical memristor transistor according to any one of claims 1-8, characterized in that, Includes the following steps: S1. A gate (200) is fabricated on a portion of the substrate (100). S2. An electrolyte layer (300) is prepared on the gate (200). Part of the electrolyte layer (300) is stacked on the gate (200), and another part is stacked on the substrate (100) adjacent to the gate (200) to form a stepped structure. S3. A semiconductor layer (400) is prepared on the electrolyte layer (300) to form a stacked stepped structure as a vertical channel; S4. A source electrode (500) is prepared on a step on the side of the semiconductor layer (400) that does not overlap with the gate (200) in the perpendicular projection direction. S5. A drain (700) is fabricated on the step on the other side of the semiconductor layer (400).

10. The method for fabricating an electrochemical vertical memristor transistor according to claim 9, characterized in that, Before fabricating the drain (700) in step S5, the process further includes: fabricating an insulating layer (600) on the source (500), and then fabricating the drain (700) on the other side step and the insulating layer (600).

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