A method for preparing gallium zinc oxide thin films, and gallium zinc oxide thin films, MOS devices, and semiconductor devices.

CN122579898APending Publication Date: 2026-08-14张江国家实验室
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-12-05
Publication Date
2026-08-14

AI Technical Summary

Technical Problem

然而,其本征载流子浓度较高(主要由氧空位等施主缺陷导致),导致击穿电场受限(理论值虽达8 MV/cm,但实际器件中常低于3MV/cm),难以满足更高性能器件的需求

Benefits of technology

[0024]根据本发明,能够提供一种镓锌氧薄膜的制备方法及镓锌氧薄膜、MOS器件、半导体器件,其能够通过三维堆叠结构与热退火协同优化器件击穿电场,来解决现有技术中受主掺杂效率低、退火工艺缺陷修复不充分的问题,同时提升材料的电学性能与器件可靠性。

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Abstract

The purpose of this invention is to provide a method for preparing gallium zinc oxide thin films, as well as gallium zinc oxide thin films, MOS devices, and semiconductor devices, to solve the problems of low acceptor doping efficiency and insufficient defect repair in the annealing process in the prior art, while improving the electrical performance of the materials and the reliability of the devices. The method for preparing gallium zinc oxide thin films of this invention includes: step S1, alternating deposition of Ga2O3 and ZnO on a substrate using atomic layer deposition; and step S2, thermal annealing treatment under an inert atmosphere.
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Description

Technical Field

[0001] This invention relates to the field of semiconductor materials technology, and in particular to a method for preparing gallium zinc oxide thin films, as well as gallium zinc oxide thin films, MOS devices, and semiconductor devices. Background Technology

[0002] Gallium oxide (Ga2O3), as an ultrawide bandgap semiconductor (bandgap of approximately 4.8-4.9 eV), has significant potential in high-voltage, high-temperature, and high-power electronic devices. However, its intrinsic carrier concentration is relatively high (mainly due to donor defects such as oxygen vacancies), which limits the breakdown electric field (theoretically reaching 8 MV / cm, but often below 3 MV / cm in practical devices), making it difficult to meet the requirements of higher-performance devices.

[0003] In existing technologies, doping processes (such as Mg and N doping) and annealing have been attempted to modulate the electrical properties of Ga2O3, but these methods suffer from the following problems: 1) Traditional acceptor doping (such as Mg) has low activation efficiency, making it difficult to effectively compensate for donor defects; 2) High-temperature annealing easily introduces secondary defects, resulting in insignificant improvements in material resistivity and breakdown electric field; 3) Poor process compatibility makes it difficult to integrate with device manufacturing processes. Therefore, there is an urgent need for an efficient and stable method to synergistically enhance the breakdown electric field of Ga2O3. Summary of the Invention

[0004] The technical problem that the invention aims to solve

[0005] In some existing technologies, Ga2O3 thin films are deposited only on SiO2 / Si and then heat-treated at 800 °C to fabricate MOS devices.

[0006] In some existing technologies, Mg doping is performed on Ga2O3 to fabricate MOS devices, and its breakdown electric field is verified to be 3MV / cm. This preparation method uses the Czeklauski method to grow Mg-doped β-Ga2O3 single crystals and obtains large-size Mg-doped single crystal ingots by rotating and pulling the molten raw materials. The preparation cost is high, a high temperature environment (1800 ℃) is required, the success rate is low, large-size preparation is not possible, and the Mg doping ratio cannot be precisely controlled.

[0007] In addition, some existing technologies use MOCVD to dope Zn in Ga2O3 (gallium oxide) and fabricate MOS devices. This existing technology employs metal-organic chemical vapor deposition, which involves complex organic chemical reactions, numerous influencing factors, and difficulty in linearly and precisely controlling the zinc-gallium material ratio, thus failing to meet the demands of large-scale mass production.

[0008] In addition, some existing technologies prepare amorphous Ga2O3 thin films by magnetron sputtering, and fabricate MOS devices solely from amorphous Ga2O3, verifying that their breakdown field strength is approximately 0.28 MV / cm.

[0009] In addition, some existing technologies employ ink application or printing to deposit sol-gel layers or sol-gels on a substrate to prepare inorganic films. These films are then chemically treated to prevent nanoparticle loss during subsequent layer deposition. This deposition and treatment process is repeated, and finally, annealing yields an inorganic nanofilm. Because the nanoparticles formed by ink application or printing in this inorganic film preparation method may be rod-shaped or spherical, and because fillers, dopants, ligands, or one or more mixtures are subsequently introduced, it is easy to encounter problems with the difficulty in precisely controlling the thickness, composition, and surface roughness.

[0010] To address the aforementioned technical problems, the present invention aims to provide a method for preparing gallium zinc oxide thin films, as well as gallium zinc oxide thin films, MOS devices, and semiconductor devices. This method optimizes the breakdown electric field of Ga2O3 through a three-dimensional stacked structure and thermal annealing, thereby solving the problems of low acceptor doping efficiency and insufficient repair of defects in the annealing process in the prior art, while improving the electrical properties of the material and the reliability of the device.

[0011] Technical solutions to solve technical problems

[0012] According to one aspect of the present invention, a method for preparing a gallium zinc oxide thin film is provided, comprising:

[0013] Step S1: Alternately deposit Ga2O3 and ZnO on the substrate using atomic layer deposition; and Step S2: Perform thermal annealing under an inert atmosphere.

[0014] Furthermore, the deposition of Ga2O3 depends on a saturated and irreversible gas-solid reaction of trimethylgallium or triethylgallium as a precursor and O2 as a reactant, and the deposition of ZnO depends on a saturated and irreversible gas-solid reaction of diethylzinc or dimethylzinc as a precursor and H2O as a reactant.

[0015] Further, in step S1, the cycle ratio of the alternating deposition of gallium oxide and zinc oxide is set to 1:0 to 7:1.

[0016] Further, in step S2, the inert atmosphere is one of nitrogen, argon, and a mixed gas obtained by mixing nitrogen and argon, with a gas purity ≥ 99.999%.

[0017] Furthermore, in step S2, the temperature of the thermal annealing treatment is 600–1000 °C, the time is 10–60 s, and the heating rate is 5–20 °C / s.

[0018] Further, in step S2, the thermal annealing process is performed by introducing Zn atoms from the ZnO into the Ga2O3 lattice, which serves as an intrinsic donor, to replace Ga atom sites and form acceptor centers, thereby compensating for the intrinsic donor defects.

[0019] According to another aspect of the present invention, a gallium zinc oxide thin film is provided, which is prepared by the gallium zinc oxide thin film preparation method described above.

[0020] According to another aspect of the present invention, a MOS device is provided, comprising: a substrate; a gallium zinc oxide thin film as described above; and a metal electrode.

[0021] Furthermore, in the MOS device described above, the substrate is at least one of SiO2 / Si, Al2O3 / Si, HfO2 / Si, and ZrO2 / Si; and / or, the metal electrode is at least one of Au / Cr, Au / Ti, and Au / Ni / Al / Ti.

[0022] According to another aspect of the present invention, a semiconductor device is provided, comprising the MOS device as described above.

[0023] Invention Effects

[0024] According to the present invention, a method for preparing gallium zinc oxide thin films, as well as gallium zinc oxide thin films, MOS devices, and semiconductor devices, can be provided. This method can solve the problems of low acceptor doping efficiency and insufficient repair of defects in the annealing process in the prior art by optimizing the breakdown electric field of the device through a three-dimensional stacked structure and thermal annealing, while improving the electrical performance of the material and the reliability of the device. Attached Figure Description

[0025] This disclosure can be better understood by describing exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, in which:

[0026] Label Explanation:

[0027] Figure 1 This is a schematic diagram illustrating the film structure (three-dimensional GZO film structure) prepared by the gallium zinc oxide thin film preparation method according to the embodiments of the present invention, in which Ga2O3 and ZnO are alternately deposited in a cyclic manner.

[0028] Figure 2 This is a flowchart illustrating the gallium zinc oxide thin film preparation method according to an embodiment of the present invention.

[0029] Figure 3 This is a graph showing the experimental and stacking deposition rates of Ga2O3, ZnO, and gallium zinc oxide thin films according to one embodiment of the present invention.

[0030] Figure 4This diagram illustrates the formation mechanism of ALD-GZO according to one embodiment of the present invention.

[0031] Figure 5 This shows the X-ray diffraction (XRD) patterns of the gallium zinc oxide thin film before and after annealing according to the embodiment.

[0032] Figure 6 This indicates the density of Ga2O3, ZnO, and gallium zinc oxide thin films before and after annealing according to one embodiment of the present invention.

[0033] Figure 7 This is a schematic diagram illustrating the structure of a gallium zinc oxide thin film-based MOS device according to another embodiment of the present invention.

[0034] Figure 8 This is a comparison graph showing the breakdown electric fields of the MOS device according to another embodiment of the present invention. Detailed Implementation

[0035] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0036] In the description of this disclosure, it should be noted that, unless otherwise stated, "a plurality of" means two or more; the terms "upper," "lower," "left," "right," etc., indicating orientation or positional relationship are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. "Vertical" is not vertical in the strict sense, but within the allowable tolerance range. "Parallel" is not parallel in the strict sense, but within the allowable tolerance range.

[0037] The directional terms used in the following description refer to the directions shown in the figures and are not intended to limit the specific structure of this disclosure. It should also be noted that, unless otherwise explicitly specified and limited, the terms "assembly," "connected," "linked," "relative," "interlocking," and "connected" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0038] In this document, the term "implementation" means that a particular feature, structure, or characteristic described in connection with an implementation may be included in at least one implementation of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same implementation, nor is it a separate or alternative implementation mutually exclusive with other implementations. It will be explicitly and implicitly understood by those skilled in the art that the implementations described herein can be combined with other implementations.

[0039] In one embodiment of the present invention, a method for preparing gallium zinc oxide thin films is described, such as... Figure 2 As shown, the main steps include:

[0040] Step S1: Alternately deposit Ga2O3 and ZnO on the substrate using atomic layer deposition; and

[0041] Step S2: Perform heat annealing under an inert atmosphere.

[0042] The following uses appendix Figures 1 to 6 The embodiments of the present invention will be described in detail below. Figure 1 This is a schematic diagram illustrating the film structure (three-dimensional GZO film structure) prepared by the gallium zinc oxide thin film preparation method according to the embodiments of the present invention, in which Ga2O3 and ZnO are alternately deposited in a cyclic manner. Figure 2 This is a flowchart illustrating the gallium zinc oxide thin film preparation method according to an embodiment of the present invention. Figure 3 This is a graph showing the experimental and stacked deposition rates of Ga2O3, ZnO, and gallium zinc oxide thin films according to one embodiment of the present invention. Here, the deposition rate is expressed as growth per cycle (GPC), defined as the slope of the function relationship between thickness and cycle. Figure 4 This diagram illustrates the formation mechanism of ALD-GZO according to one embodiment of the present invention. Figure 5 This shows the X-ray diffraction (XRD) patterns of a gallium zinc oxide thin film before and after annealing according to one embodiment of the present invention. Figure 6 This indicates the density of Ga2O3, ZnO, and gallium zinc oxide thin films before and after annealing according to one embodiment of the present invention.

[0043] Preparation of gallium zinc oxide thin films (hereinafter referred to as GZO thin films)

[0044] First, a three-dimensional stacked thin film deposition process was performed. Ga2O3 and ZnO were prepared on a cleaned SiO2 / Si substrate using atomic layer deposition. Figure 1 As shown, a GZO supercycle consists of 7 Ga2O3 cycles and 1 ZnO cycle. Repeating this supercycle forms a three-dimensional GZO stacked film of a certain thickness.

[0045] More specifically, in a GZO supercycle, the alternating deposition ratio of Ga₂O₃ and ZnO is set to 7:1, meaning 7 layers of Ga₂O₃ are stacked followed by 1 layer of ZnO. As an example, assuming each Ga₂O₃ layer is 0.06 nm and each ZnO layer is 0.2 nm, repeating this GZO supercycle 30 times will form a GZO stacked film of a certain thickness. Theoretically, the total thickness of the stacked GZO film would be 18.6 nm, including a 6 nm thick ZnO layer and a 12.6 nm thick Ga₂O₃ layer. However, the actual measured total thickness of the GZO film is 24.0 nm. In this case, if... Figure 3 As shown, the deposition rate (GPC, 0.80 nm / cycle) is significantly higher than the theoretical stacking rate of ZnO and Ga2O3 films under the same cycling conditions (GPC, 0.62 nm / cycle). This is mainly due to the self-adsorption reaction of functional groups on the Ga2O3 interface during ZnO deposition, which provides active sites for further growth of the GZO film and crystallization after annealing. The alternating atomic layer deposition method of the three-dimensional stacked films significantly improves the deposition rate, laying the foundation for the high-speed and highly uniform preparation of composite functional films. The number of supercycles mentioned above is 30, but it is not limited to this; the number can be set to 1–100.

[0046] Furthermore, by precisely controlling the alternating deposition ratio of Ga2O3 and ZnO during atomic layer deposition—that is, by precisely controlling the cycling ratio of Ga2O3 and ZnO—precise linear adjustment of the Zn atom concentration can be achieved, thereby enabling control of the Zn concentration content. Specifically, when the alternating deposition ratio of Ga2O3 and ZnO varies from 7:1, 5:1 to 3:1, the Zn atom concentration is 1×10⁻⁶. 17 cm -3 ~ 1×10 19 cm -3 More specifically, for example, when the alternating deposition ratio of Ga2O3 to ZnO is 7:1, the Zn atom concentration is 1×10⁻⁶. 17 cm -3 When the alternating deposition ratio of Ga2O3 and ZnO is 5:1, the Zn atom concentration is 5 × 10⁻⁶. 18cm -3 When the alternating deposition ratio of Ga2O3 and ZnO is 3:1, the Zn atom concentration is 1×10⁻⁶. 19 cm -3 Preferred size: 1×10 17 cm -3 .

[0047] The main principle of atomic layer deposition of three-dimensional stacked GZO thin films is explained below, which is mainly based on the layer-by-layer growth principle of self-limited adsorption interface chemical reaction. First, as shown in reaction formulas (1) and (2) below, the deposition of Ga2O3 depends on the saturated adsorption and irreversible gas-solid reaction of the precursor trimethylgallium ((CH3)3Ga, TMGa) and O2. Second, as shown in reaction formulas (3) and (4) below, the deposition of ZnO depends on the saturated adsorption and irreversible gas-solid reaction of the precursor diethylzinc ((C2H5)2Zn, DEZn) and H2O, thereby obtaining a GZO thin film of three-dimensional monolayer Ga2O3 and three-dimensional monolayer ZnO stacked together.

[0048]

[0049] Figure 4 The diagram shows the formation mechanism of ALD-GZO, including the reaction process of ALD-Ga2O3 with TMGa and O2 as precursors and reactants, and the reaction process of ALD-ZnO with DEZn and H2O as precursors and reactants.

[0050] In the ALD-Ga2O3 reaction process, firstly, in process (1), a TMGa pulse is introduced into the reaction chamber to induce a self-limited adsorption interface chemical reaction with the substrate surface, forming a uniform monolayer. Then, an inert gas is used to purge unreacted excess TMGa precursor and any potential reaction byproducts from the reaction chamber (this purging process is omitted in the figure). Next, in process (2), reactant O2 is introduced. The highly reactive particles obtained by ionizing the reactant O2 react strongly with the monolayer formed in process (1), thereby generating a PE ALD-Ga2O3 film (PE ALD: Plasma-Enhanced Atomic Layer Deposition). Afterward, an inert gas is used again to thoroughly remove reaction byproducts from the reaction chamber. By repeating processes (1) and (2), the desired number or thickness of Ga2O3 film layers can be obtained.

[0051] Next, in the ALD-ZnO reaction process, in process (3), following process (2) above, a DEZn pulse is introduced into the reaction chamber to induce a self-limited adsorption interface chemical reaction between the DEZn precursor and the active sites on the Ga2O3 surface. Then, an inert gas is used to purge the unreacted excess DEZn precursor and any potential reaction byproducts from the reaction chamber (this purging illustration is omitted in the figure). Next, in process (4), a reactant H2O pulse is introduced, which reacts with the DEZn precursor adsorbed on the substrate surface in process (3), thereby generating a TH ALD-ZnO thin film (TH ALD: Thermal Atomic Layer Deposition). By repeating processes (1) to (4) above and controlling the ratio of Ga2O3 to ZnO cycle numbers, a GZO thin film with precisely controllable film thickness and Zn concentration can be obtained. The aforementioned precursors for Ga2O3 deposition include trimethylgallium ((CH3)3Ga, TMGa), but are not limited to this; other gallium-containing precursors such as triethylgallium ((C2H5)3Ga, TEGa) can also be used. Furthermore, the aforementioned precursors for ZnO deposition include diethylzinc ((C2H5)2Zn, DEZn), but are not limited to this; other zinc-containing precursors such as dimethylzinc ((CH3)2Zn, DMZ) can also be used.

[0052] rapid annealing

[0053] In rapid annealing, an inert atmosphere needs to be introduced into the rapid annealing furnace for hot annealing. Specifically, for example, high-purity nitrogen needs to be introduced into the rapid annealing furnace for rapid high-temperature hot annealing. The inert atmosphere can be selected from nitrogen, argon, or a mixture thereof, with a purity ≥99.999%.

[0054] Furthermore, the rapid high-temperature thermal annealing treatment is set at a temperature of 600~1000 ℃, a time of 10~60 s, and a heating rate of 5~20 ℃ / s. Among these, the preferred temperatures, times, and heating rates are 800 ℃, 30 s, and 20 ℃ / s, respectively.

[0055] Because insufficient Zn concentration leads to inadequate defect compensation, while excessive concentration easily results in the formation of Zn clusters, Zn atoms are introduced into the Ga₂O₃ lattice as intrinsic donors to replace Ga sites and form acceptor centers (Zn). 2+ This allows for the compensation of intrinsic donor defects (such as oxygen vacancy V), thereby enabling the compensation of intrinsic donor defects (such as oxygen vacancy V). O + Specifically, rapid thermal annealing is used to activate Zn acceptors, promoting their occupancy of Ga sites, such as... Figure 5As shown, the XRD peaks of the GZO film after annealing indicate the formation of crystalline Ga2O3 and GaZnO. This is used to repair lattice damage caused by ion implantation, such as... Figure 6 As shown, the density of the GZO film decreased significantly after annealing, indicating that the internal stress of the film decreased compared to before annealing. To suppress the concentration gradient caused by Zn atom diffusion, as mentioned above, some Zn atoms substituted for Ga sites, thus weakening the effect of diffusion.

[0056] In another embodiment of the present invention, a gallium zinc oxide thin film (GZO thin film) is provided, which is prepared by the above-described method for preparing gallium zinc oxide thin films. Specifically, the thickness of the GZO thin film obtained by the above method is 5 to 100 nm, preferably 24.0 nm.

[0057] Therefore, the GZO thin film in this invention is a three-dimensional stacked structure of ZnO and Ga2O3 uniformly distributed in a certain ratio. The crystal structure in the three-dimensional stacked structure is mainly hexagonal wurtzite ZnO and β-Ga2O3. Atomic layer deposition is used to stack the Ga2O3 and ZnO thin films. The reaction process based on the self-adsorption principle is simple and controllable. The zinc-gallium ratio can be precisely controlled by controlling the number of cycles, meeting the requirements for large-area, high-uniformity mass production. This enables the large-area, high-uniformity, and high-density controllable preparation of GZO thin films.

[0058] Below, refer to Figure 7 and Figure 8 Another embodiment of the present invention will be described. Figure 7 This is a schematic diagram illustrating the structure of a gallium zinc oxide thin film-based MOS device according to another embodiment of the present invention. Figure 8 This is a comparison graph showing the breakdown electric fields of the MOS device according to another embodiment of the present invention.

[0059] like Figure 7 As shown, a MOS device 1000 is provided, including: a substrate 200, a GZO thin film 100 as described above, and a metal electrode 300. Cr / Au electrodes of different sizes are grown on the GZO thin film 100 using physical vapor deposition (PVD) through a hard mask. The resulting MOS device structure is as follows. Figure 6 As shown. The substrate 200 can be at least one of SiO2 / Si, Al2O3 / Si, HfO2 / Si, and ZrO2 / Si, wherein the base substrate of the substrate 200 is Si. The metal electrode 300 can be at least one of Au / Cr, Au / Ti, and Au / Ni / Al / Ti.

[0060] The performance test results of the MOS device 1000 are described below. In this invention, the breakdown electric field of the MOS device 1000 based on the three-dimensional stacked GZO thin film 100 after the above annealing is tested in the vertical direction.

[0061] As shown in Table 1 below and Figure 8 The electric field test results are shown. Five control groups were set up. One group did not undergo thermal annealing, while the other four groups were annealed at 400 ℃, 600 ℃, 800 ℃ and 1000 ℃ for 30 s, respectively, with a heating rate of 20 ℃ / s.

[0062] From Table 1 and Figure 8 It is evident that heat treatment significantly enhances the breakdown electric field of MOS devices compared to no heat treatment. Compared to untreated GZO films, the breakdown electric field of MOS devices 1000 based on GZO films 100 heat-treated at 400-1000 ℃ was correspondingly improved, with 800 ℃ heat treatment enabling the breakdown electric field of the MOS device to reach 17.3 MV / cm.

[0063] After annealing, the breakdown electric field of the MOS device 1000 based on the three-dimensional stacked GZO thin film 100 is ≥5.5 MV / cm. The uniform stacking of Zn atoms reduces the carrier concentration (n-type → semi-insulator), and annealing further optimizes the lattice quality. The two work together to increase the breakdown electric field of the MOS device 1000 to 17.3 MV / cm (more than 2 times higher than the untreated sample).

[0064] Table 1. Breakdown electric field test results for the five control groups in the implementation method.

[0065]

[0066] As described above, the present invention has the following beneficial effects:

[0067] 1) Significantly improved performance: This invention, through the stacking of three-dimensional atomic layers of GZO and the synergistic thermal annealing process, enables the breakdown electric field of MOS devices to break through 5.5 MV / cm and increase it to as high as 17.3 MV / cm, which is significantly better than existing doping technologies (such as Mg doping ~3 MV / cm);

[0068] 2) Strong process compatibility: It can be integrated with existing semiconductor manufacturing processes (such as thin film deposition and annealing furnaces);

[0069] 3) Low cost: No special equipment or complex process steps are required; the reaction process is simple and controllable.

[0070] 4) It can be applied to high-voltage power devices: Ga2O3-based field-effect transistors (FETs), Schottky barrier diodes (SBDs), deep ultraviolet photodetectors, etc., and has a variety of application scenarios;

[0071] 5) By controlling the number of atomic layer deposition cycles, the zinc-gallium ratio can be precisely controlled to meet the requirements of large-area, high-uniformity mass production. This enables the large-area, high-uniformity, and high-density controllable preparation of GZO thin films to meet their mass production application requirements in advanced logic and memory.

[0072] Furthermore, in another embodiment of the present invention, a semiconductor device is provided, including the MOS device described above.

[0073] It should be understood that the above description is illustrative and not restrictive. For example, the above embodiments (and / or aspects thereof) can be used in combination with each other. Furthermore, many modifications can be made to adapt particular conditions or materials to the teachings of the various embodiments of the invention without departing from the scope of the invention. While the dimensions and types of materials described herein are used to define parameters of the various embodiments of the invention, the embodiments are not intended to be restrictive but are exemplary. Many other embodiments will become apparent to those skilled in the art upon reading the above description. Therefore, the scope of the various embodiments of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A method for preparing gallium zinc oxide thin films, characterized in that, include: Step S1: Alternately deposit Ga2O3 and ZnO on the substrate using atomic layer deposition; and Step S2: Perform heat annealing under an inert atmosphere.

2. The method for preparing gallium zinc oxide thin films as described in claim 1, characterized in that, The deposition of Ga2O3 depends on a saturated and irreversible gas-solid reaction of trimethylgallium or triethylgallium as a precursor and O2 as a reactant. The deposition of ZnO depends on the saturated adsorption and irreversible gas-solid reaction of diethylzinc or dimethylzinc as precursors and H2O as reactants.

3. The method for preparing gallium zinc oxide thin films as described in claim 1 or 2, characterized in that, In step S1, the cycle ratio of alternating deposition of gallium oxide and zinc oxide is set to 1:0 to 7:

1.

4. The method for preparing gallium zinc oxide thin films as described in claim 1 or 2, characterized in that, In step S2, the inert atmosphere is one of nitrogen, argon, and a mixed gas obtained by mixing nitrogen and argon, with a gas purity ≥ 99.999%.

5. The method for preparing gallium zinc oxide thin films as described in claim 1 or 2, characterized in that, In step S2, the temperature of the heat annealing treatment is 600-1000 ℃, the time is 10-60 s, and the heating rate is 5-20 ℃ / s.

6. The method for preparing gallium zinc oxide thin films as described in claim 1 or 2, characterized in that, In step S2, the thermal annealing process is performed by introducing Zn atoms from the ZnO into the Ga2O3 lattice, which serves as an intrinsic donor, to replace Ga atom sites and form acceptor centers, thereby compensating for the intrinsic donor defects.

7. A gallium zinc oxide thin film, characterized in that, It is prepared by the gallium zinc oxide thin film preparation method according to any one of claims 1-6.

8. A MOS device, characterized in that, include: Substrate; The gallium zinc oxide thin film as described in claim 7; and Metal electrode.

9. The MOS device as described in claim 8, characterized in that, The substrate is at least one selected from SiO2 / Si, Al2O3 / Si, HfO2 / Si, and ZrO2 / Si; and / or, The metal electrode is at least one of Au / Cr, Au / Ti, and Au / Ni / Al / Ti.

10. A semiconductor device, characterized in that, Including the MOS device as described in claim 8 or 9.