A physical etching method for chip circuits

Abstract

This invention discloses a physical etching method for chip circuits, belonging to the field of semiconductor chip processing. It comprises three steps: tooling assembly, vacuum sealing, and electric field physical etching. A positively charged energy storage device covered with an insulating film is placed at the bottom of a vacuum chamber. Chips and a limiting mask with circuit traces are then stacked sequentially. After the chamber is evacuated, negatively charged particles are injected from top to bottom. The electrostatic field formed by the positive and negative charges breaks down the insulating layer and ablates the chip along the preset trajectory, completing the circuit etching. This invention abandons traditional chemical etching processes, produces no pollutants, uses simple and low-cost equipment, and can process various types of chips by changing the limiting mask. It can be widely used in mass production etching of various semiconductor chips.

Description

Technical Field

[0001] This invention relates to the field of chip processing technology, specifically to a physical etching method for chip circuits, which can be widely applied to the circuit etching processing of industrial control chips, agricultural environmental sensing chips, and commercial consumer electronics chips. Background Technology

[0002] Currently, chip circuit etching generally uses photolithography combined with chemical etching processes. Production requires photoresist and various etching chemical reagents, and the processing generates waste liquid and waste gas, causing environmental pollution. The supporting production equipment is expensive, and the processing process is complicated, making it difficult to meet the processing needs of small and medium batches of chips for various industrial, agricultural, and commercial applications. Summary of the Invention

[0003] To address the shortcomings of existing chemical etching methods, such as high pollution, high cost, and cumbersome processes, a physical etching method for chip circuits is provided. This method relies on the physical interaction of positive and negative charges to complete the etching process and is suitable for chip production across all industries, including manufacturing, agriculture, and commerce. Technical solution

[0004] A physical etching method for chip circuits, comprising the following steps: S1. Tooling assembly: Select a sealed vacuum chamber as the working base, and arrange the positive charge energy storage device with an insulating film on the outside of the vacuum chamber at the bottom. Stack the chip to be processed and the limiting mask baffle on the positive charge energy storage device in sequence. The limiting mask baffle has a pre-set etching line cutout trajectory. S2. Vacuum sealing treatment: The vacuum chamber is sealed and closed, and the gas inside the chamber is extracted by the pumping equipment to maintain the vacuum sealing condition of the chamber, which is isolated from the normal pressure. S3. Electric field physical etching: Negative charged particles are injected directionally from the top of the cavity toward the inside of the cavity, and positive and negative charges couple to form a directional electrostatic field; the electrostatic field breaks down the corresponding insulating film along the preset line area of ​​the limiting baffle, the positive charge energy storage device releases the charge outward, and the negative charge penetrates the limiting baffle along the preset line trajectory and ablates the chip substrate, realizing the physical forming etching of the chip circuit.

[0005] Working principle The insulating film on the outside of the positive charge energy storage device isolates the initial external static electricity, and the vacuum environment isolates the external stray air charge from interfering with the etching path; after the negative charge particles are introduced, they form an electric field that automatically breaks down and ablates the local insulating layer, and physical etching is completed by directional charge penetration, without the need for any chemical raw materials. Detailed Implementation

[0006] A rigid, sealed enclosure is used as the fixed vacuum chamber. An ultra-thin PE insulating film is thermally bonded to the surface of the positive charge storage device to form an integrated insulating component, which is placed at the bottom of the chamber. A silicon-based chip is placed flat on the storage device, and a limiting mask baffle is pressed against the top surface of the chip. The baffle has the target circuit pattern pre-etched on it. The chamber is then closed and sealed, and an external vacuum pump is used to evacuate the internal air to create a vacuum environment. A beam of negative electron particles is introduced from the top of the chamber downwards. The electric field breaks down and erodes the insulating layer directly below the baffle's circuitry, causing the positive charge storage device to release its charge. The negative electrons then penetrate the chip substrate along the pattern, resulting in an etched chip. Different limiting mask baffles can be replaced to process industrial control chips, agricultural soil sensor chips, and commercial consumer chips such as those for mobile phones. Beneficial effects

[0007] 1. Physical etching consumes no chemical reagents, produces zero waste liquid pollution, and is green and environmentally friendly; 2. The equipment has a simple structure, requiring only a vacuum chamber and a charge supply device, which significantly reduces production input costs; 3. By changing the limit mask baffle, the chip type can be switched, which is suitable for chip processing in multiple fields such as industry, agriculture, commerce and special industries. Attached Figure Description

[0008] Appendix Figure 1 This is a schematic diagram of the overall cross-sectional structure of the present invention; Label Explanation: 1-Positive charge energy storage device; 2-Chip to be etched; 3-Limiting mask baffle; 4-Vacuum cavity; The vertical arrow in the diagram indicates the downward movement direction of the negatively charged particles; additional explanation: the surface of the positively charged energy storage device is covered with an insulating film, which is attached to the surface of the energy storage device and is not shown separately.

Claims

1. A method for physical etching of chip circuits, characterized in that, The process includes the following steps: S1. Tooling assembly: Select a sealed vacuum chamber as the working base, and arrange the positive charge energy storage device with an insulating film on the outside of the vacuum chamber at the bottom. Stack the chip to be processed and the limiting mask baffle on the positive charge energy storage device in sequence. The limiting mask baffle has a pre-set etching line cutout trajectory. S2. Vacuum sealing treatment: The vacuum chamber is sealed and closed, and the gas inside the chamber is extracted by the pumping equipment to maintain the vacuum sealing condition of the chamber, which is isolated from the normal pressure. S3. Electric field physical etching: Negative charged particles are injected directionally from the top of the cavity toward the inside of the cavity, and positive and negative charges couple to form a directional electrostatic field; the electrostatic field breaks down the corresponding insulating film along the preset line area of ​​the limiting baffle, the positive charge energy storage device releases the charge outward, and the negative charge penetrates the limiting baffle along the preset line trajectory and ablates the chip substrate, realizing the physical forming etching of the chip circuit.

2. The chip circuit physical etching method according to claim 1, characterized in that: The positive charge energy storage device and the outer insulating film are integrally bonded together. The insulating film has no independent separate structure and is attached to and covers the outer surface of the positive charge energy storage device.

3. The chip circuit physical etching method according to claim 1, characterized in that: The physical etching method described above is applicable to the circuit etching of semiconductor chips, sensor chips, consumer electronics chips, industrial control chips, and special function chips.

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