Wafer charge release method

Abstract

This application discloses a wafer charge release method, comprising: performing a preset fabrication process on the wafer, adsorbing the wafer onto an electrostatic chuck, and maintaining the reaction chamber in a plasma-excited state after the preset fabrication process; performing a first-stage voltage reduction on the electrostatic chuck, gradually decreasing the voltage from a first voltage to a second voltage; performing a second-stage voltage reduction on the electrostatic chuck, decreasing the voltage from the second voltage to a third voltage; and separating the wafer from the electrostatic chuck after the second-stage voltage reduction. This method facilitates the full release of accumulated charge on the wafer, reduces residual charge on the wafer, and thus improves product yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a wafer charge release method. Background Technology

[0002] In the semiconductor manufacturing field, electrostatic chuck (ESC) technology has become the mainstream method for fixing wafers in etching, deposition, and other processes due to its advantages such as high wafer thickness compatibility and good temperature control precision. Almost all types of wafer processing rely on this technology to achieve wafer fixation during the process. However, the electrostatic discharge problem after the above processes has always been one of the factors affecting production yield.

[0003] In related technologies, a rapid voltage reduction method is often used after etching, deposition, and other processes. This involves directly switching the ESC voltage from the process voltage to a safe value to release the charge on the wafer surface, thereby releasing the electrostatic chuck's adhesion to the wafer and allowing it to detach from the chuck and be lifted by the ejector pins. However, this method cannot completely release the charge accumulated on the wafer, leaving a large amount of residual charge on the unloaded wafer. Taking silicon-on-insulator (SOI) wafers as an example, although SOI wafers can effectively isolate devices, reduce parasitic effects, and significantly improve the performance of integrated circuits by introducing a buried oxide layer between the top silicon layer and the silicon substrate, the presence of the buried oxide layer will prevent the movement of charge within the wafer, making the residual charge problem more serious. This will cause electrostatic damage to the precision structures in the device, leading to increased leakage current, decreased reliability, and ultimately seriously affecting the product yield. Summary of the Invention

[0004] This application provides a wafer charge release method, which is beneficial for fully releasing the charge accumulated on the wafer, reducing residual charge on the wafer, and thus improving product yield.

[0005] In view of this, this application provides a wafer charge release method, comprising:

[0006] A preset preparation process is performed on the wafer, which is adsorbed onto an electrostatic chuck. After the preset preparation process, the reaction chamber is kept in a plasma-excited state.

[0007] The electrostatic chuck is subjected to a first-stage voltage reduction, with the voltage of the electrostatic chuck gradually decreasing from the first voltage to the second voltage.

[0008] The electrostatic chuck undergoes a second-stage voltage reduction, decreasing its voltage from the second voltage to the third voltage. After this second-stage voltage reduction, the wafer separates from the electrostatic chuck.

[0009] Optionally, during the first-stage voltage reduction process, the voltage reduction range for each step is 50V-150V.

[0010] Optionally, the first voltage is -600V to -800V.

[0011] Optionally, the second voltage is -50V to -150V.

[0012] Optionally, the third voltage is 0V.

[0013] Optionally, after the second-stage voltage reduction, the electrostatic chuck voltage is maintained at the third voltage, and the plasma excitation state of the reaction chamber is maintained until the wafer is unloaded.

[0014] Optionally, the wafer is a silicon-on-insulator wafer.

[0015] Optionally, the process parameters for maintaining the plasma excitation state in the reaction chamber include: argon flow rate of 800 sccm-1200 sccm, chamber pressure of 100 mTorr-200 mTorr, and high-frequency power of 30 W-70 W.

[0016] Optionally, the preset preparation process includes an etching process.

[0017] Optionally, the preset preparation process includes a deposition process.

[0018] The technical solution of this application has at least the following advantages:

[0019] This application employs a gradient voltage reduction method for the first stage of voltage reduction in the electrostatic chuck, gradually decreasing the voltage from a first voltage to a second voltage while maintaining the plasma excitation state in the reaction chamber during the voltage reduction process. This facilitates the full release of accumulated charge on the wafer, reducing residual charge and thus improving product yield. Specifically, the gradient voltage reduction provides sufficient time for the charge accumulated on the wafer, especially within the wafer, to be released, which helps reduce residual charge. Simultaneously, the gradient voltage reduction allows for a slow change in the electric field on the wafer surface, improving the uniformity of the electric field and charge distribution. Furthermore, the charged particles in the plasma synergize with the gradient voltage reduction, continuously neutralizing the charge on the wafer surface, further promoting a more thorough release of charge and reducing residual charge. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 This is a process flow diagram of a wafer charge release method provided in an exemplary embodiment of this application;

[0022] Figure 2 This is a wafer charge distribution diagram after the wafer is unloaded in a wafer charge release method provided in an exemplary embodiment of this application;

[0023] Figure 3 This is a wafer charge distribution diagram after the wafer is unloaded in a wafer charge release method provided in an exemplary comparative example of this application;

[0024] Figure 4 This is a failure distribution diagram of the wafer probe test (CP) of SOI wafer after chip manufacturing is completed in related technologies;

[0025] Figure 5 This is a failure distribution diagram of the SOI wafer after unloading in the wafer charge release method provided in an exemplary embodiment of this application, after the chip manufacturing is completed, during wafer probe testing. Detailed Implementation

[0026] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0029] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0030] The following is combined with Figures 1 to 5 This describes an embodiment of the present application.

[0031] refer to Figure 1 The illustration shows an embodiment of this application, providing a wafer charge release method, comprising:

[0032] S1, a preset preparation process is performed on the wafer. The wafer is adsorbed onto an electrostatic chuck. After the preset preparation process, the reaction chamber is kept in a plasma excited state.

[0033] For example, the wafer can be a bulk silicon wafer, a silicon-on-insulator wafer, a strained silicon wafer, or other types of wafers used to fabricate semiconductor devices. The preset fabrication process can be an etching process, a deposition process, or other wafer processing processes with electrostatic discharge problems. The electrostatic chuck can be an electrostatic chuck installed in the corresponding preset fabrication process equipment.

[0034] In some embodiments, after a preset preparation process, the reaction chamber is kept in a plasma-excited state by controlling the argon flow rate to 800 standard milliliters per minute (sccm) - 1200 sccm, the chamber pressure to 100 millitors (mTorr) - 200 mTorr, and the high-frequency power to 30 watts (W) - 70 W.

[0035] For example, the argon flow rate can be 800 sccm, 900 sccm, 1000 sccm, 1100 sccm, 1200 sccm, etc., the chamber pressure can be 100 Torr, 130 mTorr, 150 mTorr, 170 mTorr, 200 Torr, etc., and the high-frequency power can be 30W, 40W, 50W, 60W, 70W, etc.

[0036] It should be noted that keeping the reaction chamber in a plasma-excited state after the preset preparation process means that the plasma-excited state of the reaction chamber will continue to be maintained in the subsequent first-stage depressurization process and the second-stage depressurization process.

[0037] S2, the electrostatic chuck is subjected to the first stage of voltage reduction, and the voltage of the electrostatic chuck is gradually reduced from the first voltage to the second voltage.

[0038] In some embodiments, during the first-stage voltage reduction process, the voltage reduction range is 50V-150V per step.

[0039] For example, the voltage reduction step can be 50V, 100V, 150V, etc.

[0040] In some embodiments, during the first-stage pressure reduction process, each pressure reduction step takes 1-2 seconds.

[0041] For example, the time for each step of pressure reduction is 1s, 1.5s, 2s, etc.

[0042] In some embodiments, the first voltage is -600V to -800V.

[0043] For example, the first voltage can be -600V, -700V, -800V, etc.

[0044] In some embodiments, the second voltage is -50V to -150V.

[0045] For example, the second voltage can be -50V, 100V, -150V, etc.

[0046] It should be noted that the negative signs in the first voltage and the second voltage indicate the polarity of the voltage.

[0047] S3, the electrostatic chuck is subjected to a second stage of voltage reduction. The voltage of the electrostatic chuck is reduced from the second voltage to the third voltage. After the second stage of voltage reduction, the wafer is separated from the electrostatic chuck.

[0048] In some embodiments, the third voltage is 0V.

[0049] In some embodiments, the second-stage pressure reduction time is 1-2 seconds. For example, the pressure reduction time for each step is 1 second, 1.5 seconds, 2 seconds, etc.

[0050] In some embodiments, after the second-stage voltage reduction, the electrostatic chuck voltage is maintained at the third voltage and the plasma-excited state of the reaction chamber is maintained until the wafer is unloaded.

[0051] For example, after the second stage of voltage reduction, the voltage of the electrostatic chuck is kept at 0V and the plasma excitation state of the reaction chamber is maintained until the wafer is unloaded. This method can ensure that the wafer is not re-adsorbed onto the electrostatic chuck and can also prolong the desorption time, which is beneficial to the full release of charge in the wafer.

[0052] It should be noted that wafer separation from electrostatic chuck means that there is no longer any adhesion between the wafer and the surface of the electrostatic chuck, and the wafer can be lifted by the ejector pin. Wafer unloading means that the wafer is taken away by the robotic arm.

[0053] In related technologies, a rapid voltage reduction method is often used after etching, deposition, and other processes, that is, directly jumping the ESC voltage from the process voltage to -100V to release the charge on the wafer surface. This rapid voltage reduction can lead to the inability to release the charge accumulated on the wafer, especially inside the wafer, resulting in a large amount of residual charge on the wafer, and also causing uneven charge distribution on the wafer surface. Taking silicon-on-insulator (SOI) wafers as an example, although SOI wafers can effectively isolate devices, reduce parasitic effects, and significantly improve the performance of integrated circuits by introducing a buried oxide layer between the top silicon layer and the silicon substrate, the presence of the buried oxide layer will prevent the movement of charge within the wafer, making the problem of residual charge more serious. This will cause electrostatic damage to precision structures such as the gate oxide layer in the device, leading to increased leakage current, decreased reliability, and ultimately seriously affecting the product yield. In related technologies, after the SOI wafer chip is manufactured, wafer probe testing (Circuit Probe, CP) is performed. The failure distribution diagram is shown in [reference needed]. Figure 4 .

[0054] This application employs a gradient voltage reduction method for the first stage of electrostatic discharge (ESD) on the electrostatic chuck. The voltage of the ESD chuck is gradually reduced from a first voltage to a second voltage, while maintaining the plasma excitation state of the reaction chamber during the voltage reduction process. This facilitates the full release of accumulated charge on the wafer, reducing residual charge and thus improving product yield. The gradient voltage reduction provides sufficient time for the charge accumulated on the wafer, especially within the wafer, reducing residual charge. Simultaneously, the gradient voltage reduction allows for a slow change in the electric field on the wafer surface, improving the uniformity of the electric field and charge distribution. Furthermore, charged particles in the plasma synergize with the gradient voltage reduction, continuously neutralizing the charge on the wafer surface, further promoting a more thorough release of charge and reducing residual charge. This method is beneficial for ESD discharge of various types of wafers, particularly SOI wafers. Using this method to improve the charge discharge problem of SOI wafers, after SOI wafer chip manufacturing, wafer probe testing is performed, and the failure distribution diagram is shown below. Figure 5 .

[0055] To verify the technical effect of this application, the inventors used the methods provided in Example 1 and Comparative Example 1 to release charge from the wafer, and tested the unloaded wafer using a non-contact electrostatic voltmeter (Trek 541A) and a wafer surface potential scanning system. The test results are shown in Table 1 and Table 2, respectively. Figure 1-2 .

[0056] Example 1:

[0057] This embodiment provides a wafer charge release method, including:

[0058] S1, a preset preparation process is performed on the wafer. The wafer is adsorbed onto an electrostatic chuck. After the preset preparation process, the reaction chamber is kept in a plasma excited state.

[0059] In this embodiment, the wafer is a silicon-on-insulator wafer, the preset fabrication process is an etching process, and the electrostatic chuck is an electrostatic chuck installed in the etching equipment.

[0060] In this embodiment, after the etching process, the reaction chamber is kept in a plasma-excited state by controlling the argon flow rate to 1000 sccm, the chamber pressure to 150 mTorr, and the high-frequency power to 50 W.

[0061] S2, the electrostatic chuck is subjected to the first stage of voltage reduction, and the voltage of the electrostatic chuck is gradually reduced from the first voltage to the second voltage.

[0062] In this embodiment, the first voltage is -700V.

[0063] In this embodiment, the second voltage is -100V.

[0064] In this embodiment, during the first stage of voltage reduction, the voltage reduction increment is 100V per step. That is, the electrostatic chuck voltage is reduced in 5 steps, from -700V to -600V, -600V to -500V, -500V to -400V, -400V to -300V, -300V to -200V, and -200V to -100V.

[0065] In this embodiment, during the first stage of pressure reduction, the pressure reduction time for each step is 1 second.

[0066] In this embodiment, during the first stage of depressurization, the plasma excitation state of the reaction chamber is maintained by controlling the argon flow rate to 1000 sccm, the chamber pressure to 150 mTorr, and the high-frequency power to 50 W.

[0067] S3, the electrostatic chuck is subjected to a second stage of voltage reduction. The voltage of the electrostatic chuck is reduced from the second voltage to the third voltage. After the second stage of voltage reduction, the wafer is separated from the electrostatic chuck.

[0068] In this embodiment, the third voltage is 0V. That is, the voltage of the electrostatic chuck in S3 decreases from -100V to 0V.

[0069] In this embodiment, the second-stage pressure reduction time is 1 second.

[0070] In this embodiment, during the second stage of depressurization, the argon flow rate is controlled at 1000 sccm, the chamber pressure at 150 mTorr, and the high-frequency power at 50 W to maintain the plasma excitation state of the reaction chamber. After the second stage of depressurization, the electrostatic chuck voltage is maintained at 0V, and the plasma excitation state of the reaction chamber is maintained until the wafer is unloaded.

[0071] Comparative Example 1:

[0072] The only difference between this comparative example and Example 1 is that step S2 is replaced by: reducing the voltage of the electrostatic chuck, with the electrostatic chuck voltage switching directly from -700V to -100V.

[0073] Table 1

[0074] residual charge -60V -120V

[0075] From Table 1 and Figure 1-2 As can be seen, compared with Comparative Example 1, the wafer treated by the method of Example 1 has a significantly reduced residual charge, a more uniform charge distribution on its surface, and a significant reduction in residual charge in the edge region.

[0076] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A wafer charge release method, characterized in that, include: A preset preparation process is performed on the wafer, which is adsorbed onto an electrostatic chuck. After the preset preparation process, the reaction chamber is kept in a plasma-excited state. The electrostatic chuck is subjected to a first-stage voltage reduction, with the voltage of the electrostatic chuck gradually decreasing from the first voltage to the second voltage. The electrostatic chuck undergoes a second-stage voltage reduction, decreasing its voltage from the second voltage to the third voltage. After this second-stage voltage reduction, the wafer separates from the electrostatic chuck.

2. The method according to claim 1, characterized in that, In the first stage of voltage reduction, the voltage reduction range is 50V-150V per step.

3. The method according to claim 1, characterized in that, The first voltage is -600V to -800V.

4. The method according to claim 1, characterized in that, The second voltage is -50V to -150V.

5. The method according to claim 1, characterized in that, The third voltage is 0V.

6. The method according to claim 1, characterized in that, After the second stage of voltage reduction, the electrostatic chuck voltage is maintained at the third voltage, and the plasma excitation state of the reaction chamber is maintained until the wafer is unloaded.

7. The method according to claim 1, characterized in that, The wafer is a silicon-on-insulator wafer.

8. The method according to any one of claims 1-7, characterized in that, The process parameters for maintaining the plasma excitation state in the reaction chamber include: argon flow rate of 800 sccm-1200 sccm, chamber pressure of 100 mTorr-200 mTorr, and high-frequency power of 30 W-70 W.

9. The method according to any one of claims 1-7, characterized in that, The preset preparation process includes an etching process.

10. The method according to any one of claims 1-7, characterized in that, The preset preparation process includes a deposition process.

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