A semiconductor device and its manufacturing method

Abstract

A semiconductor device and a method for manufacturing the same are disclosed. The method includes: providing a semiconductor substrate; forming a polishing stop layer on the semiconductor substrate; sequentially etching the polishing stop layer and the semiconductor substrate to form a plurality of first shallow trenches and a plurality of second shallow trenches; depositing a first isolation material to fill the first and second shallow trenches and cover the polishing stop layer; performing a chemical mechanical polishing (CMP) process to remove the first isolation material above the polishing stop layer; etching away a portion of the semiconductor substrate between adjacent second shallow trenches in a second region to form a third shallow trench; and filling the third shallow trench with a second isolation material such that the second isolation material filled in the third shallow trench is connected to the first isolation material filled in the second shallow trenches on both sides thereof. This invention effectively avoids active region exposure at the edge of the surface-mounted tumbler (STI).

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor device and its manufacturing method. Background Technology

[0002] In semiconductor manufacturing processes, shallow trench isolation (STI) technology is widely used for electrical isolation between active regions. A typical STI process flow includes: forming a hard mask (including pad oxide and pad silicon nitride layers) on a silicon substrate, etching to form trenches, depositing isolation material, and then performing chemical mechanical polishing (CMP) to planarize the surface.

[0003] As process nodes advance to 40nm and below, STI CMP (Silicon Tire Injection) processes face challenges. Due to the characteristics of the polishing slurry, severe dishing occurs during CMP in areas with low active area density or high STI density. Furthermore, the silicon nitride layer in these areas, lacking support on both sides, is over-polished during CMP, resulting in very low residual silicon nitride after CMP. During subsequent wet etching to adjust the step height, if the loss of STI oxide thickness in these areas exceeds the remaining thickness of the polishing stop layer, active area silicon exposure occurs. Exposed silicon reacts with the ambient gas during subsequent annealing after ion implantation, forming silicon damage defects that severely impact device yield.

[0004] In the prior art, one solution is to reduce the overpolishing time of STI CMP to ensure the amount of silicon nitride residue. However, this method will narrow the CMP process window, which can easily lead to silicon oxide residue defects, making it impossible to completely remove silicon nitride in the subsequent process. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: A semiconductor substrate is provided, the semiconductor substrate comprising a first region and a second region; A polishing stop layer is formed on the semiconductor substrate; The polishing stop layer and the semiconductor substrate are etched sequentially to form a plurality of first shallow trenches in the first region and a plurality of second shallow trenches in the second region; A first insulating material is deposited to fill the first shallow trench and the second shallow trench, and to cover the polishing stop layer; Perform a chemical mechanical polishing process to remove the first isolation material above the polishing stop layer; Etching removes a portion of the semiconductor substrate between adjacent second shallow trenches in the second region to form a third shallow trench; A second insulating material is filled into the third shallow trench, such that the second insulating material filled in the third shallow trench is connected to the first insulating material filled in the second shallow trench on both sides thereof.

[0007] In one embodiment, in the second region, the semiconductor substrate on only one side of each second shallow trench is removed to form the third shallow trench; Alternatively, in the second region, at least one of the semiconductor substrates on both sides of the second shallow trench is removed to form two third shallow trenches.

[0008] In one embodiment, the etching process removes a portion of the semiconductor substrate between adjacent second shallow trenches in the second region to form a third shallow trench, comprising: A patterned photoresist layer is formed on the polishing stop layer, and a window is formed in the photoresist layer, the window exposing at least the area above the semiconductor substrate between two adjacent second shallow trenches; Using the photoresist layer as a mask, the polishing stop layer and the semiconductor substrate exposed by the window are etched sequentially to form the third shallow trench.

[0009] In one embodiment, filling the third shallow trench with a second isolation material includes: filling the third shallow trench with the second isolation material using a selective liquid phase deposition process, wherein the photoresist layer is not removed during the selective liquid phase deposition process, so that the second isolation material is selectively filled only inside the third shallow trench.

[0010] In one embodiment, the width of the window is greater than or equal to the maximum distance between two adjacent second shallow trenches; the window also exposes portions of the second shallow trenches on both sides of the third shallow trench, and during the etching process using the first photoresist layer as a mask, a portion of the first isolation material filling the second shallow trenches on both sides of the third shallow trench is also removed.

[0011] In one embodiment, the first shallow trench and the second shallow trench are of equal size.

[0012] In one embodiment, the polishing stop layer comprises a silicon oxide layer and a silicon nitride layer formed sequentially.

[0013] In one embodiment, the chemical mechanical polishing process also removes a portion of the thickness of the silicon nitride layer.

[0014] In one embodiment, the chemical mechanical polishing process uses a polishing slurry containing cerium dioxide particles.

[0015] Another embodiment of the present invention provides a semiconductor device, comprising: a semiconductor substrate, the semiconductor substrate including a first region and a second region; Multiple first shallow trench isolation structures are located in the first region, and the first shallow trench isolation structures are filled with a first isolation material; Multiple second shallow trench isolation structures are located in the second region, and the width of the second shallow trench isolation structure is greater than the width of the first shallow trench isolation structure; the second shallow trench isolation structure is filled with the first isolation material and the second isolation material, the first isolation material is located on both sides of the second isolation material, and the second isolation material is connected to the first isolation material on both sides.

[0016] In one embodiment, the semiconductor device is manufactured using the method described above.

[0017] According to the semiconductor device manufacturing method of the present invention, narrow trenches are formed in both the first and second regions to avoid STI depression during CMP process and to avoid over-polishing of the polishing stop layer; then, by removing part of the semiconductor substrate between adjacent second shallow trenches and filling it again, the newly filled second isolation material is connected to the original first isolation material on both sides to form the required wide STI structure, thereby effectively preventing active region silicon exposure and subsequent silicon damage defects. Attached Figure Description

[0018] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0019] In the attached image: Figures 1A-1F A cross-sectional view of a semiconductor device obtained by sequentially performing the steps of a semiconductor device manufacturing method in the related art is shown. Figure 2 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown; Figures 3A-3FA cross-sectional view of a semiconductor device obtained by sequentially performing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown. Detailed Implementation

[0020] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0021] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0023] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0026] like Figures 1A-1F As shown, in related technologies, firstly as Figure 1A As shown, a semiconductor substrate 100 is provided, on which a silicon oxide layer 101, a silicon nitride layer 102, and a photoresist layer 103 are sequentially formed. Using the photoresist layer 103 as a mask, the silicon nitride layer 102, the silicon oxide layer 101, and the semiconductor substrate are sequentially etched to form multiple shallow trenches. A first shallow trench 104 with a smaller width is formed in regions with a higher active area density, while a second shallow trench 105 with a larger width is formed in regions with a lower active area density. Then, as... Figure 1B As shown, the first shallow trench 104 and the second shallow trench 105 are filled with insulating material 106; then as... Figure 1CAs shown, chemical mechanical polishing (CMP) is performed using silicon nitride layer 102 as a stop layer to remove excess isolation material 106. During the CMP process, due to the characteristics of the polishing slurry, and because the active region density is low and the STI density is high in the area where the second shallow trench 105 is located, severe dishing occurs. Furthermore, because the silicon nitride layer 102 in this area lacks support on both sides, it is over-polished during the CMP process, resulting in a very low residual amount of silicon nitride layer 102 in this area after CMP.

[0027] Next, as Figure 1D As shown, wet etching is used to adjust the step height of the isolation material 106. During this process, if the loss thickness H3 of the isolation material 106 on both sides of the second shallow trench 105 exceeds the remaining thickness H2 of the silicon nitride layer 102 and the thickness H1 of the silicon oxide layer 101, it will lead to silicon exposure in the active region. In subsequent steps... Figure 1E The ion implantation shown and as Figure 1F As shown in the annealing process, the exposed silicon reacts with the ambient gas during the subsequent annealing process after ion implantation, forming silicon damage defects, which seriously affect the device yield.

[0028] To address the above problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. The following refers to... Figure 2 and Figures 3A-3F A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail. For example... Figure 2 As shown, the manufacturing method mainly includes the following steps: In step S201, a semiconductor substrate is provided, the semiconductor substrate including a first region and a second region.

[0029] like Figure 3A As shown, the semiconductor substrate 300 is made of at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors; or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). As an example, in this embodiment, the semiconductor substrate 300 is made of single-crystal silicon.

[0030] The semiconductor substrate 300 includes a first region 300A and a second region 300B. The first region 300A is a region with a high active region density and a small STI design width; the second region 300B is a region with a low active region density and a large STI design width.

[0031] Next, in step S202, a polishing stop layer is formed on the semiconductor substrate 300.

[0032] For example, the polishing stop layer includes a silicon oxide layer 301 and a silicon nitride layer 302 formed sequentially. The silicon oxide layer 301 is used to alleviate stress between the silicon nitride layer 302 and the semiconductor substrate 300, effectively preventing dislocation generation; the silicon nitride layer 302 is used as the polishing endpoint in subsequent CMP processes. The silicon oxide layer 301 can be obtained by thermal oxidation or by deposition; the silicon nitride layer 302 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. As an example, the thickness of the silicon oxide layer 301 is approximately 10 nm-20 nm, and the thickness of the silicon nitride layer 302 is not less than 100 nm.

[0033] Next, in step S203, the polishing stop layer and the semiconductor substrate are etched sequentially to form a plurality of first shallow trenches in the first region and a plurality of second shallow trenches in the second region.

[0034] Specifically, a patterned first photoresist layer 303 can be formed on the polishing stop layer. Using the first photoresist layer 303 as a mask, the polishing stop layer and the semiconductor substrate 300 are etched to form a first shallow trench 304 and a second shallow trench 305. Anisotropic dry etching methods such as plasma etching and reactive ion etching can be used, with an etching depth of approximately 300 nanometers.

[0035] In this embodiment of the invention, the width of the first shallow trench 304 formed in the first region 300A is the designed width of the shallow trench isolation structure in that region. The second shallow trench 305 in the second region 300B is not the ultimately required wider shallow trench, but rather a narrower trench with the same or approximately the same size as the first shallow trench 304 in the first region 300A. In this embodiment, the width of both the first shallow trench 304 and the second shallow trench 305 is approximately 150 nanometers. Furthermore, the width, depth, and spacing of the first shallow trench 304 and the second shallow trench 305 are all equal.

[0036] After the first shallow trench 304 and the second shallow trench 305 are formed, the first photoresist layer 303 can be removed by ashing or chemical reagent removal process.

[0037] Next, in step S204, a first isolation material is deposited, which covers the upper surface of the polishing stop layer.

[0038] Exemplarily, a padding layer is first formed covering the bottom and sidewalls of the first shallow trench 304 and the second shallow trench 305. The padding layer is used to avoid problems that may occur when directly filling the shallow trenches with insulating material, such as poor adhesion between the insulating material and the semiconductor substrate 300 exposed on the trench sidewalls, voids during filling, and large stresses caused by mismatch between the insulating material and the semiconductor material on the trench sidewalls. Simultaneously, the padding layer can repair damage to the trench sidewalls caused during the etching process. The padding layer can be formed using thermal oxidation methods, such as dry oxidation, moisture oxidation, wet oxidation, or other suitable methods. Exemplarily, the padding layer is a thin silicon oxide layer formed using an in-situ moisture oxidation (ISSG) process. Subsequently, a rapid thermal annealing process is performed to eliminate the stress generated during the growth of the padding layer.

[0039] Next, as Figure 3B As shown, a first insulating material 306 is filled in the first shallow trench 304 and the second shallow trench 305 using high-density plasma chemical vapor deposition (HDP CVD) or high aspect ratio process (HARP). The first insulating material 306 can be one or more of silicon dioxide, fluorosilicone glass, undoped silicate glass (USG), or tetraethyl orthosilicate (TEOS). The first insulating material 306 completely fills the first shallow trench 304 and the second shallow trench 305 and covers the upper surface of the polishing stop layer.

[0040] Next, in step S205, a chemical mechanical polishing process is performed to remove the first isolation material above the polishing stop layer.

[0041] Specifically, such as Figure 3C As shown, the first isolation material 306 is subjected to chemical mechanical polishing (CMP) to remove the isolation material outside the shallow trench until the polishing stop layer is exposed, thereby forming a preliminary shallow trench isolation structure. The CMP process uses the silicon nitride layer 302 as the stop layer. When the endpoint detection system of the CMP equipment detects the silicon nitride signal, the main polishing is stopped, and overpolishing can be performed for a period of time.

[0042] For example, the polishing slurry uses an alkaline slurry containing cerium dioxide particles. This polishing slurry has a high removal rate for silicon oxide but a low removal rate for silicon nitride. Therefore, when polishing reaches the surface of the silicon nitride layer 302, the polishing rate drops significantly, thereby achieving the effect of using the silicon nitride layer 302 as a stop layer. Since both the first shallow trench 304 and the second shallow trench 305 are narrow trenches with consistent size and density, the polishing rate is uniform across the entire wafer surface. Neither the first region 300A nor the second region 300B has large areas of silicon oxide, therefore, severe dishing does not occur during the CMP process.

[0043] The CMP process in this embodiment of the invention allows for a certain degree of over-polishing. That is, after polishing to the surface of the silicon nitride layer 302, polishing continues for a period of time to remove a portion of the silicon nitride layer 302, thereby ensuring that the first isolation material 306 above the silicon nitride layer 302 is completely removed and providing a flat surface for subsequent processes. Since the first shallow trench 304 and the second shallow trench 305 of this invention are both narrow trenches with equal dimensions, and the polishing behavior of the first region 300A and the second region 300B is consistent during the CMP process, the remaining thickness of the silicon nitride layer 302 in the two regions remains essentially equal after over-polishing. This avoids the problem of excessive silicon nitride loss in the wide STI region of the prior art, and also avoids the risk of active silicon exposure in the second region 300B.

[0044] Next, in step S206, the semiconductor substrate between some adjacent second shallow trenches in the second region is etched away to form a third shallow trench.

[0045] Specifically, such as Figure 3D As shown, a patterned photoresist layer, namely the second photoresist layer 307, is first formed on the polishing stop layer. This second photoresist layer 307 has windows that expose at least the area above the semiconductor substrate 300 between two adjacent second shallow trenches 305. Then, using the second photoresist layer 307 as a mask, the polishing stop layer and the semiconductor substrate 300 exposed by the windows are sequentially etched to form the third shallow trench 308. Anisotropic dry etching methods such as plasma etching or reactive ion etching can be used, with an etching depth of approximately 300 nanometers, comparable to the depths of the first shallow trench 304 and the second shallow trench 305.

[0046] In one embodiment, to ensure good communication between the subsequently filled second isolation material and the first isolation materials on both sides, the width of the window in the second photoresist layer 307 is designed to be greater than or equal to the maximum width of the active region between two adjacent second shallow trenches 305. Specifically, the second shallow trench 305 has an inverted trapezoidal cross-section that is wider at the top and narrower at the bottom, while the active region between adjacent second shallow trenches 305 has a regular trapezoidal cross-section that is narrower at the top and wider at the bottom. The width of the window is not less than the bottom width of the regular trapezoidal cross-section to avoid the formation of silicon bumps at the bottom of the subsequently formed second shallow trench 305 isolation structure.

[0047] Since the width of the window is not less than the width of the bottom of the active region but greater than the width of the top of the active region, during the etching process, in addition to the complete removal of the semiconductor substrate 300 between the two second shallow trenches 305, part of the first isolation material in the second shallow trenches 305 on both sides of the semiconductor substrate 300 is also removed. Finally, a third shallow trench 308 with a rectangular cross-section is formed between the two second shallow trenches 305. The left and right sidewalls of the third shallow trench 308 are both composed of the first isolation material 306.

[0048] In one embodiment, such as Figure 3D As shown, in the second region 300B, only one side of the semiconductor substrate 300 of each second shallow trench 305 is removed to form the third shallow trench 308. For example, assuming that shallow trenches A, B, C, and D are formed in the second region 300B, the semiconductor substrate 300 between shallow trench A and shallow trench B is removed, the semiconductor substrate 300 between shallow trench B and shallow trench C is not removed, and the semiconductor substrate between shallow trench C and shallow trench D is removed. That is, each third shallow trench 308 at most forms a wide trench together with the second shallow trenches 305 on its left and right sides, without connecting more second shallow trenches 305.

[0049] In another embodiment, in the second region 300B, the semiconductor substrates on both sides of at least one second shallow trench 305 are removed to form two third shallow trenches 308. For example, if a wider shallow trench is required, the semiconductor substrates 300 on both sides of shallow trench B can be removed together, thereby connecting shallow trenches A, B, and C into a wider shallow trench. Specifically, the semiconductor substrates 300 to be removed can be selected according to the design width of the shallow trench isolation structure.

[0050] Next, in step S207, a second insulating material is filled into the third shallow trench, such that the second insulating material filled in the third shallow trench is connected to the first insulating material filled in the second shallow trenches on both sides, together forming the STI structure of the second region.

[0051] like Figure 3E As shown, in this embodiment, a second insulating material 309 is filled into the third shallow trench 308 using a selective liquid phase deposition (S-LPD) process. S-LPD is a wet chemical deposition process that uses a supersaturated aqueous hexafluorosilicic acid solution as the deposition solution, and silicon dioxide is selectively deposited on the exposed silicon or silicon oxide surface under low temperature conditions.

[0052] In the step of depositing the second isolation material 309 using the S-LPD process, the second photoresist layer 307 is not removed, covering the area outside the third shallow trench 308. The LPD process selectively grows silicon dioxide only inside the exposed third shallow trench 308, without depositing it on the surface of the second photoresist layer 307. Therefore, CMP is not required after deposition. Furthermore, due to the low deposition temperature of the LPD process, the second photoresist layer 307 is not damaged. The second isolation material 309 grown in the third shallow trench 308 is interconnected with the first isolation material 306 filled in the second shallow trenches 305 on both sides, forming a continuous and complete STI structure. After deposition, as shown... Figure 3F As shown, the second photoresist layer 307 is removed using an ashing or wet cleaning process.

[0053] Subsequently, the first isolation material 306 and the second isolation material 309 can be etched back to adjust the step height of the STI structure. Since the silicon nitride layer 302 in the second region 300B is not over-polished, the semiconductor substrate 300 on both sides of the silicon nitride layer 302 will not be exposed after the etch back, thus preventing silicon damage defects in the future. Finally, the silicon nitride layer 302 is removed, and subsequent device manufacturing processes such as ion implantation and annealing are performed.

[0054] In summary, the semiconductor device manufacturing method of this invention forms a wide STI structure by forming narrow trenches in both the first region 300A and the second region 300B, and then selectively removing a portion of the semiconductor substrate between the second trenches in the second region 300B and performing secondary filling. This avoids the problems of depression or over-polishing in the CMP process and effectively prevents active region silicon exposure and silicon damage defects.

[0055] The present invention also provides a semiconductor device that can be manufactured using the above-described process.

[0056] like Figure 3F As shown, the semiconductor device includes a semiconductor substrate 300, which includes a first region 300A and a second region 300B. The first region 300A is a region with a high active region density and a narrow STI design width, and the second region 300B is a region with a low active region density and a wide STI design width. Multiple first shallow trench isolation structures are located in the first region 300A, and the first shallow trench isolation structures are filled with a first isolation material 306; Multiple second shallow trench isolation structures are located in the second region 300B, and the width of the second shallow trench isolation structure is greater than the width of the first shallow trench isolation structure. The second shallow trench isolation structure is filled with a first isolation material 306 and a second isolation material 309, with the first isolation material 306 located on both sides of the second isolation material 309, and the second isolation material 309 connected to the first isolation material 306 on both sides.

[0057] For example, both the first insulating material 306 and the second insulating material 309 are silicon dioxide.

[0058] In another embodiment of the present invention, an electronic device is also provided, including the aforementioned semiconductor device, which is prepared according to the aforementioned method.

[0059] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned semiconductor devices, has better performance.

[0060] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate comprising a first region and a second region; A polishing stop layer is formed on the semiconductor substrate; The polishing stop layer and the semiconductor substrate are etched sequentially to form a plurality of first shallow trenches in the first region and a plurality of second shallow trenches in the second region; A first insulating material is deposited to fill the first shallow trench and the second shallow trench, and to cover the polishing stop layer; Perform a chemical mechanical polishing process to remove the first isolation material above the polishing stop layer; Etching removes a portion of the semiconductor substrate between adjacent second shallow trenches in the second region to form a third shallow trench; A second insulating material is filled into the third shallow trench, such that the second insulating material filled in the third shallow trench is connected to the first insulating material filled in the second shallow trench on both sides thereof.

2. The method according to claim 1, characterized in that, In the second region, the semiconductor substrate on only one side of each second shallow trench is removed to form the third shallow trench; Alternatively, in the second region, at least one of the semiconductor substrates on both sides of the second shallow trench is removed to form two third shallow trenches.

3. The method according to claim 1, characterized in that, The etching process removes a portion of the semiconductor substrate between adjacent second shallow trenches in the second region to form a third shallow trench, including: A patterned photoresist layer is formed on the polishing stop layer, and a window is formed in the photoresist layer, the window exposing at least the area above the semiconductor substrate between two adjacent second shallow trenches; Using the photoresist layer as a mask, the polishing stop layer and the semiconductor substrate exposed by the window are etched sequentially to form the third shallow trench.

4. The method according to claim 3, characterized in that, The step of filling the third shallow trench with a second isolation material includes: filling the third shallow trench with the second isolation material using a selective liquid phase deposition process, wherein the photoresist layer is not removed during the selective liquid phase deposition process, so that the second isolation material is selectively filled only inside the third shallow trench.

5. The method according to claim 3, characterized in that, The width of the window is greater than or equal to the maximum distance between two adjacent second shallow trenches; the window also exposes a portion of the second shallow trenches on both sides of the third shallow trench, and during the etching process using the first photoresist layer as a mask, a portion of the first isolation material filling the second shallow trenches on both sides of the third shallow trench is also removed.

6. The method according to claim 1, characterized in that, The first shallow trench has the same dimensions as the second shallow trench.

7. The method according to claim 1, characterized in that, The polishing stop layer comprises a silicon oxide layer and a silicon nitride layer formed sequentially.

8. The method according to claim 7, characterized in that, The chemical mechanical polishing process also removes a portion of the thickness of the silicon nitride layer.

9. The method according to claim 7, characterized in that, The chemical mechanical polishing process uses a polishing slurry containing cerium dioxide particles.

10. A semiconductor device, characterized in that, The semiconductor device includes: A semiconductor substrate, the semiconductor substrate comprising a first region and a second region; Multiple first shallow trench isolation structures are located in the first region, and the first shallow trench isolation structures are filled with a first isolation material; Multiple second shallow trench isolation structures are located in the second region, and the width of the second shallow trench isolation structure is greater than the width of the first shallow trench isolation structure; the second shallow trench isolation structure is filled with the first isolation material and the second isolation material, the first isolation material is located on both sides of the second isolation material, and the second isolation material is connected to the first isolation material on both sides.

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