A straight-hole silicon through-hole packaging structure and method

Abstract

This invention discloses a through-silicon via (TSV) packaging structure and method, comprising a silicon substrate having a TSV structure with an arc-shaped bottom. The invention divides the etching process into a main etching stage and a bottom-forming stage. In the main etching stage, a higher SF6 / C4F8 flow ratio, higher electrode power, and higher pressure are used to increase the etching rate and quickly form a TSV structure with a preset depth and diameter. When the etching depth reaches 90%-95% of the target value, the bottom-forming stage begins. At this stage, the SF6 gas flow rate is gradually reduced while the C4F8 gas flow rate is increased, and the etching rate is reduced. Through the deposition of the C4F8 polymer film in the corner region of the bottom of the hole and the gentle etching effect of the SF6 etching particles, the sharp structure at the corner of the bottom of the hole is gradually etched into an arc-shaped transition structure. The radius of the arc can be controlled by adjusting the gas ratio and etching time in this stage, ultimately forming a TSV structure with an arc-shaped bottom.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor chip packaging technology, specifically relating to a through-silicon via (TSV) packaging structure and method. Background Technology

[0002] In the field of semiconductor packaging technology, through-silicon vias (TSVs), as the core interconnect structure for achieving three-dimensional chip integration, are widely used in advanced microelectronic devices such as image sensors and high-performance computing chips. In existing technologies, the etching process for straight-hole TSVs is mainly based on inductively coupled plasma etching (ICP-C). Its basic structure is a columnar via that vertically penetrates the silicon substrate. The etching principle utilizes SF6 plasma to provide fluorine-based active particles to physically bombard and chemically etch the silicon material. Simultaneously, a polymer film generated by C4F8 gas protects the hole walls, achieving a high aspect ratio hole structure. However, in existing processes, the flow ratio of SF6 and C4F8 and the etching rate control are relatively fixed. During the etching process, sharp right-angle or near-right-angle corner structures are formed at the junction of the hole bottom and the hole wall. In subsequent chip packaging processes (such as bonding and dicing) and during long-term device operation, these sharp corner structures become stress concentration areas. When subjected to thermal cycling stress, mechanical vibration, or external impact, they are very likely to cause microcracks in the silicon substrate at the corner of the hole bottom. In severe cases, this can lead to the breakage of the through-hole structure and interconnect failure, significantly reducing the reliability and lifespan of the device. This problem is particularly prominent in applications with high aspect ratio straight through-hole silicon vias. Summary of the Invention

[0003] To address the problems in the prior art, the present invention aims to provide a straight-hole through-silicon via (TSV) packaging structure and method, which achieves the formation of an arc-shaped hole bottom structure for TSVs by controlling the etching gas flow rate and speed without increasing additional process steps and equipment costs.

[0004] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows: A through-silicon via (TSV) packaging structure includes a silicon substrate having a TSV structure with an arc-shaped bottom.

[0005] This invention also discloses a method for packaging through-silicon vias with straight holes, comprising the following steps: Step 1: Pre-treat, clean, and dry the silicon substrate, and then form a patterned mask corresponding to the target via on the surface of the silicon substrate using photolithography, ensuring that the mask opening size is consistent with the target via diameter; Step 2: Place the silicon substrate into the reaction chamber of the etching equipment, close the reaction chamber and evacuate it, then introduce argon gas for plasma cleaning; Step 3: Complete the main etching; Step 4: Complete the hole bottom forming; Step 5: Remove the silicon substrate and remove the surface photoresist to obtain a straight-hole silicon through-hole structure with an arc-shaped hole bottom.

[0006] Furthermore, in step one, the drying temperature is 110-130℃ and the drying time is 30-40 minutes.

[0007] Furthermore, in step three, the main etching stage begins, and SF6 and C4F8 gases are introduced, with the SF6 gas flow rate being greater than the C4F8 gas flow rate, and the flow rate ratio between the two being 3:1-5:1.

[0008] Furthermore, in step four, during the bottom forming stage, the SF6 gas flow rate is reduced and the C4F8 gas flow rate is increased, so that the SF6 gas flow rate is slightly greater than the C4F8 gas flow rate, and the flow rate ratio between the two is 1:1-2:1.

[0009] Furthermore, in step four, an arc-shaped transition structure is formed by forming the bottom of the hole, with an arc radius of 0.5-5μm.

[0010] Furthermore, in step five, after etching is completed, the SF6 and C4F8 gases are turned off, and argon gas is continuously introduced to purge the reaction chamber for 5-10 minutes. Then, the silicon substrate is removed, and the surface photoresist is removed by stripping with an organic solvent, finally obtaining a straight-hole silicon through-hole structure with an arc-shaped hole bottom.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention achieves the formation of an arc-shaped bottom structure for straight through-hole silicon vias by controlling the flow rate and velocity of etching gas, without adding extra process steps or equipment costs. The arc-shaped bottom formed by this invention is equivalent to constructing a natural chamfer structure at the corner of the hole bottom, which can effectively disperse the stress distribution in the hole bottom area, improve the fracture resistance and mechanical stability of the through-hole structure, and at the same time, the arc-shaped bottom structure avoids charge accumulation at sharp corners, reduces the occurrence of electromigration during subsequent metallization, optimizes the electrical performance of the through-hole, and has good process compatibility and industrial application prospects. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of step three of the present invention; Figure 2 This is a schematic diagram of step four of the present invention. Detailed Implementation

[0013] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0014] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0015] like Figure 1-2 As shown, the present invention discloses a straight-hole through-silicon via (TSV) packaging structure, including a silicon substrate 1, wherein the silicon substrate 1 has a straight-hole TSV structure with an arc-shaped hole bottom.

[0016] This invention also discloses a method for packaging through-silicon vias (TSVs) with straight holes. During the etching process of TSVs with straight holes, the etching process is divided into a main etching stage and a hole bottom forming stage. By real-time control of the gas flow ratio of SF6 and C4F8 and the etching rate, the controllable forming of the arc-shaped hole bottom is achieved. In the main etching stage, a higher SF6 / C4F8 flow ratio, larger electrode power, and higher pressure are used to increase the etching rate and quickly form a straight hole structure with a preset depth and diameter. When the etching depth reaches 90%-95% of the target value, the hole bottom forming stage begins. At this stage, the SF6 gas flow rate is gradually reduced while the C4F8 gas flow rate is increased, while the etching rate is reduced. Through the deposition of the C4F8 polymer film in the corner area of ​​the hole bottom and the gentle etching effect of the SF6 etching particles, the sharp structure at the corner of the hole bottom is gradually etched into an arc-shaped transition structure. The arc radius can be controlled by adjusting the gas ratio and etching time in this stage, ultimately forming a straight TSV structure with an arc-shaped hole bottom. Throughout the etching process, the consistency and accuracy of the arc-shaped hole bottom structure are ensured by real-time monitoring of plasma density and active particle concentration, and by adjusting gas flow rate and radio frequency power accordingly. This method specifically includes the following steps: Step 1: First, the silicon substrate undergoes pre-treatment by grinding to reach the target thickness. Then, it is cleaned with conventional organic materials and rinsed with deionized water to remove surface grease and other contaminants. After cleaning, it is dried in an oven at 110-130℃ for 30-40 minutes to remove surface oil and impurities. Subsequently, a patterned mask corresponding to the target via is formed on the surface of the silicon substrate using photolithography, ensuring that the mask opening size matches the target via diameter. Step 2: Place the silicon substrate into the reaction chamber of the etching equipment, close the reaction chamber and evacuate it, and introduce argon gas for plasma cleaning to remove residual trace contaminants and natural oxide layer on the surface of the silicon substrate, ensuring the uniformity and consistency of the etching process. Step 3: Enter the main etching stage. Set a high reaction chamber pressure, a large inductive coupling power (600-3500W), and a high RF bias power (0-500W). Introduce SF6 and C4F8 gases, with the SF6 gas flow rate greater than the C4F8 gas flow rate. For example, set the initial ratio to 3:1 to 5:1. Maintain a high etching rate (1.77-50μm / min) to achieve a via depth of 90-95%, completing the main etching stage. Figure 1 As shown; The optical emission spectroscopy (OES) monitoring system integrated into the etching equipment collects plasma spectral signals through the optical window reserved in the reaction chamber. At this stage, two characteristic wavelengths are detected: the 703.7 nm characteristic emission line of F atoms and the 287.4 nm characteristic emission line of CF2 groups. The spectral intensity is converted into relative particle concentration. When the monitored value deviates from the range of ±10%, the gas flow rate ratio is automatically adjusted to ensure the dynamic balance between the etching rate and the hole wall protection during the main etching process. Through OES monitoring, when the intensity of the characteristic spectral line of SiF4 shows a phased decay and remains stable for 10-20 seconds, it is determined that the depth has reached the target and the hole bottom forming stage is triggered. Step 4: Enter the bottom hole forming stage, gradually adjust the gas flow rate: reduce the SF6 gas flow rate and increase the C4F8 gas flow rate, making the SF6 gas flow rate slightly greater than the C4F8 gas flow rate, such as adjusting the SF6 / C4F8 flow rate ratio to 1:1 to 2:1; simultaneously, reduce the etching rate by feedback adjustment of the reduced RF bias power; during this process, the polymer film generated by the C4F8 gas forms selective protection on the bottom and sidewalls of the hole, and the gentle etching effect of the SF6 plasma gradually removes the sharp parts at the corners, forming an arc-shaped transition structure. The radius of the arc can be controlled within the range of 0.5-5μm by adjusting the gas ratio and etching time in this stage. When the via depth reaches 100μm, stop etching. Figure 2 As shown; During the etching process, the characteristic emission intensity of F atoms and CFx groups in the plasma is monitored in real time using OES to ensure that the gas ratio remains stable within the set range. When the etching depth approaches the target value, the amount of silicon material remaining at the bottom of the via decreases, the reaction rate of Si and F slows down, the production of SiF4 decreases accordingly, and the spectral intensity of F atoms monitored by OES shows a significant phased decay, indicating the end of etching. Step 5: After etching is complete, turn off SF6 and C4F8 gases, continue to purge the reaction chamber with argon gas for 5-10 minutes, then remove the silicon substrate and remove the surface photoresist by peeling with an organic solvent (acetone, etc.) to finally obtain a straight-hole silicon through-hole structure with an arc-shaped hole bottom.

[0017] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0018] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A straight-hole through-silicon via (TSV) packaging structure, characterized in that, Includes a silicon substrate having a through-hole silicon structure with an arc-shaped bottom.

2. A method for encapsulating through-silicon vias with straight holes, characterized in that, Includes the following steps: Step 1: Pre-treat, clean, and dry the silicon substrate, and then form a patterned mask corresponding to the target via on the surface of the silicon substrate using photolithography, ensuring that the mask opening size is consistent with the target via diameter; Step 2: Place the silicon substrate into the reaction chamber of the etching equipment, close the reaction chamber and evacuate it, then introduce argon gas for plasma cleaning; Step 3: Complete the main etching; Step 4: Complete the hole bottom forming; Step 5: Remove the silicon substrate and remove the surface photoresist to obtain a straight-hole silicon through-hole structure with an arc-shaped hole bottom.

3. The method for packaging through-silicon vias with straight holes according to claim 1, characterized in that, In step one, the drying temperature is 110-130℃ and the drying time is 30-40 minutes.

4. The method for packaging through-silicon vias with straight holes according to claim 1, characterized in that, In step three, the main etching stage begins, and SF6 and C4F8 gases are introduced, with the SF6 gas flow rate being greater than the C4F8 gas flow rate, and the flow rate ratio between the two being 3:1-5:

1.

5. A method for packaging through-silicon vias with straight holes according to claim 1, characterized in that, In step four, the bottom forming stage begins. The flow rate of SF6 gas is reduced, while the flow rate of C4F8 gas is increased, so that the flow rate of SF6 gas is slightly greater than that of C4F8 gas, with a flow rate ratio of 1:1 to 2:

1.

6. The method for packaging through-silicon vias with straight holes according to claim 1, characterized in that, In step four, an arc-shaped transition structure is formed by forming the bottom of the hole, with an arc radius of 0.5-5μm.

7. The method for packaging through-silicon vias with straight holes according to claim 1, characterized in that, In step five, after etching is completed, the SF6 and C4F8 gases are turned off, and argon gas is continuously introduced to purge the reaction chamber for 5-10 minutes. Then, the silicon substrate is removed, and the surface photoresist is removed by stripping with an organic solvent, finally obtaining a straight-hole silicon through-hole structure with an arc-shaped hole bottom.

Images