A chip DFN packaging process

Abstract

This invention relates to the field of chip packaging technology, and in particular to a chip DFN packaging process, comprising the following steps: S1: wafer thinning; S2: dicing; S3: die mounting; S4: bonding; S5: molding; S6: post-curing; S7: electroplating; S8: dicing; S9: reflow soldering; S10: testing and marking; S11: finished product inspection and packaging. This invention does not focus on improving a single process, but rather, starting from wafer thinning, dicing, die mounting, bonding, molding, post-curing, electroplating, dicing, reflow soldering, and finally testing, it meticulously matches and coordinates the equipment selection, material application, and process parameters for each key process. This systematic approach solves the bottleneck problem of mutual influence between processes, thereby achieving a leap in overall product yield and long-term reliability.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a chip DFN packaging process. Background Technology

[0002] As a core type of leadless packaging technology, DFN packaging has become the mainstream packaging solution in consumer electronics, automotive electronics, industrial control, and the Internet of Things due to its outstanding advantages such as small package size, low parasitic parameters, excellent heat dissipation performance, and controllable cost. With the rapid iteration of semiconductor technology towards miniaturization, high density, high reliability, and low power consumption, the market has placed higher demands on DFN packaging processes: on the one hand, package size needs to continue to shrink, and pin pitch needs to be further reduced to meet the integration requirements of portable electronic devices; on the other hand, high-end applications such as automotive electronics and industrial control have placed more stringent standards on the reliability and pin density of packaged products; in addition, the demand for large-scale mass production also requires packaging processes to have higher production efficiency and yield.

[0003] In existing DFN packaging processes, excessively thin wafers are prone to warping, cracks, and micro-defects during wafer thinning and dicing. The mechanical stress and debris generated during dicing can cause edge damage and micro-cracks in the chip, severely affecting its mechanical strength and long-term reliability. Therefore, a new DFN packaging process for chips needs to be designed. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a chip DFN packaging process.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a chip DFN packaging process, comprising the following steps: S1: Wafer thinning, the wafer is polished using polishing equipment, and the thickness of the thinned wafer is controlled to be ≥80μm, the thickness tolerance is ±10μm, the total thickness change (TTV) is ≤5μm, and the surface roughness is ≤15nm; S2: Dicing. The thinned wafer is diced into individual chips using a dicing machine. The dicing width is controlled to be ≥40μm, and the dicing accuracy is ≤5μm. Diamond-coated blades are used during the dicing process, and the chip edge burr height is controlled to be ≤3μm. The blade thickness is 15-30μm. Before dicing, a UV-cured protective film with a thickness of 50-80μm is attached to the front side of the wafer. The dicing speed is controlled in segments at 10-20mm / s. After dicing, the protective film is removed by UV irradiation with a wavelength of 365nm and an energy of 1000-1500mJ / cm². S3: Chip mounting. Using a dispensing and mounting device, the chip is fixed to the lead frame with conductive adhesive. The thickness of the conductive adhesive is controlled at 7-15μm, the positioning accuracy of the chip mounting is ±20μm, and the chip push force CPK>1.67. S4: Pressure bonding, using pressure bonding equipment, the pads of the chip are electrically connected to the pins of the lead frame through metal wires. The diameter of the metal wires ranges from 0.5 to 2.0 mil, the bonding speed is ≥24 wires / sec, the opening of the bonding pads is ≥42μm, and the spacing between the bonding pads is ≥40μm. S5: Molding. Molding equipment is used, which has a vacuum adsorption function for the lower mold. Epoxy resin molding compound is used to mold the semi-finished product after pressure welding. The molding temperature is 175-180℃, the pressure is 10-12MPa, and the time is 90-120 seconds. The lead wire offset is controlled to be <2%. S6: Post-curing. The encapsulated semi-finished product is placed in a constant temperature curing oven and cured at 175±5℃ for 4-8 hours. The heating rate is 3-5℃ / min and the cooling rate is 2-3℃ / min. This is used to eliminate internal stress in the encapsulated body. S7: Electroplating. The semi-finished product after post-curing is tin-plated using electroplating equipment. The electroplating solution is an acidic tin plating solution, with a current density of 2.0-2.2A / dm², an electroplating time of 30-35 seconds, a plating thickness of 7-13μm, and a plating uniformity error of ≤±1μm. S8: Cutting. The electroplated lead frame is cut and separated using cutting equipment at a cutting speed of 25-30mm / s. Water cooling is used during the cutting process to control the cutting accuracy to ≤5μm and the finished package size tolerance to within ±20μm. S9: Reflow soldering, the semi-finished product after cutting is reflow soldered. The reflow soldering parameters are: heating rate 3-5℃ / sec, peak temperature 260±5℃, peak temperature holding time 10-15 seconds, cooling rate 2-3℃ / sec. S10: Testing and printing. The electrical performance of the finished product after reflow soldering is tested using an electrical performance testing platform. The appearance is inspected using an AOI six-sided inspection device. After passing the inspection, the printing is completed by a laser printing device with a printing depth of 5-10μm. S11: Finished product re-inspection and packaging. Sampling reliability tests are conducted on printed products, and qualified products are packaged and put into storage.

[0006] As a further description of the above technical solution: In step S1, the grinding process controls the grinding speed at 3000-4000 rpm, the grinding pressure at 0.1-0.15 MPa, and the grinding wheel grit size at 10000-15000 mesh. After thinning, the wafer surface is cleaned using a plasma cleaning device for 3-5 minutes with a plasma power of 100-150W.

[0007] As a further description of the above technical solution: In step S3, a reinforcing rib structure is preset at the cutting edge of the lead frame, and the width of the reinforcing rib is 10-20μm, the thickness is the same as that of the lead frame, and the reinforcing rib is integrally formed with the lead frame.

[0008] As a further description of the above technical solution: In step S4, the metal wire is one or more of Au wire, Ag wire, PdCu wire, and Cu wire.

[0009] As a further description of the above technical solution: In step S5, the vacuum adsorption time before sealing is 3-5 seconds, and the vacuum pressure is 8-10 MPa.

[0010] As a further description of the above technical solution: In step S7, the acidic tin plating solution consists of SnSO4, H2SO4, brightener and leveling agent, and is pickled with 5% H2SO4 solution for 10-15 seconds before electroplating to remove the oxide layer on the lead frame surface.

[0011] As a further description of the above technical solution: The electrical performance test items in step S10 include breakdown voltage, leakage current, on-resistance, output voltage, and quiescent current; the AOI inspection items include identifiable scratches, excess adhesive, pin deformation, and plating defects.

[0012] As a further description of the above technical solution: The reliability test in step S11 includes high and low temperature cycling test, damp heat test, salt spray test and mechanical shock test.

[0013] The present invention has the following beneficial effects: 1. Compared with existing technologies, this invention does not focus on improving a single process, but rather starts from wafer thinning, encompassing dicing, die mounting, bonding, molding, post-curing, electroplating, cutting, reflow soldering, and testing. It meticulously matches and coordinates the equipment selection, material application, and process parameters for each key process. This systematic approach solves the bottleneck problems of mutual influence between processes (such as thinning stress affecting dicing, bonding quality affecting molding, etc.), thereby achieving a leap in overall product yield and long-term reliability. Furthermore, through high-precision thinning, ultra-narrow dicing technology, ±20μm chip mounting accuracy, and stable bonding processes for micro-pads, this invention successfully achieves stable mass production of ultra-small packages and ultra-fine pin pitch packages, driving further product miniaturization.

[0014] 2. Compared with the prior art, the present invention uses a vacuum adsorption molding equipment during molding, which makes the molded body free of delamination and bubbles. After high and low temperature cycle testing, the cracking rate of the molded body is effectively reduced. Attached Figure Description

[0015] Figure 1 This is a process flow diagram of the present invention. Detailed Implementation

[0016] Reference Figure 1 The present invention provides a chip DFN packaging process, comprising the following steps: S1: Wafer thinning Equipment Selection: Grinding equipment is precisely matched according to wafer size. The DFG8761 grinding machine is selected for 12-inch wafers, while the DFG8540 grinding machine is selected for 4-inch, 5-inch, 6-inch, and 8-inch wafers. Both types of equipment are equipped with high-precision grinding control modules, which can achieve precise control of both thickness and roughness, adapting to the thinning requirements of wafers of different sizes.

[0017] Process parameter optimization: Grinding speed 3000-4000rpm (the larger the wafer size, the higher the grinding speed; 4000rpm for 12-inch wafers and 3000rpm for 4-inch wafers); Grinding pressure 0.1-0.15MPa (adjusted according to the initial thickness of the wafer; 0.15MPa when the initial thickness is >600μm, and 0.1MPa when the initial thickness is <500μm); Grinding wheel grit 10000-15000 mesh (10000 mesh for the rough grinding stage and 15000 mesh for the fine grinding stage). The thickness is quickly reduced through rough grinding, and the surface precision is improved through fine grinding.

[0018] Quality control indicators: after thinning, the wafer thickness is ≥80μm (minimum can be 80μm to adapt to ultra-thin wafer devices), the thickness tolerance is ±10μm, the total thickness variation (TTV) is ≤5μm (to ensure uniform thickness in all areas of the wafer), and the surface roughness is ≤15nm (preferably ≤12nm to reduce contact defects between the adhesive layer and the wafer surface during subsequent die bonding).

[0019] Auxiliary processing: After thinning, the wafer surface is cleaned using plasma cleaning equipment to remove dust and impurities generated during the grinding process. The cleaning time is 3-5 minutes, and the plasma power is 100-150W to ensure that the wafer surface cleanliness is ≤50ppm, providing a good foundation for subsequent dicing and die-attaching processes.

[0020] S2: School district The core of the dicing process is to precisely cut the wafer into individual chips while avoiding contamination of the chip surface and edge damage.

[0021] Equipment selection: Select the Disco series dicing equipment according to the wafer size. For 12-inch wafers, select DFD6361 / DFD6362 / DFD6363 (dicing accuracy ±2μm). For 8-inch and smaller wafers, select DFD6240 / DFD6340 / DFD6341 / 6450 (dicing accuracy ±1μm). Blade selection: Diamond-coated blades are used, with a blade thickness of 15-30μm (adjusted according to the width of the cutting track), diamond particle size of 3-5μm, and hardness ≥HV10000, to ensure cutting sharpness and durability; Protective film technology: Before dicing, a UV-cured protective film with a thickness of 50-80μm is attached to the front side of the wafer. The adhesiveness of the protective film is 10-20g / in, which can effectively protect the chip surface. After dicing, the adhesiveness of the protective film is reduced to 1-3g / in by UV irradiation (wavelength 365nm, energy 1000-1500mJ / cm²), which facilitates the removal of the film and avoids scratches on the chip surface.

[0022] Cutting parameter control: Cutting speed: segmented control at 10-20 mm / s, with a 20%-30% reduction in speed at the wafer edge region (radius ≥ 90% of wafer radius) to reduce edge stress concentration; Cutting depth: Full cut and micro-overcut modes are adopted, with an overcutting depth ≤5μm, to ensure complete chip separation without damaging the cutting stage; Dust removal and cooling: High-pressure nitrogen (0.3-0.5MPa) is used to blow away cutting debris during the cutting process, and coolant (with the same composition as polishing fluid) is sprayed at the same time to control the temperature of the cutting area to ≤30℃, so as to avoid damage to the chip due to high temperature.

[0023] S3: Core Equipment Selection: The ASMAD832i intelligent dispensing and core loading equipment is adopted. This equipment has the following core advantages: ① Position accuracy of ±20μm, meeting the positioning requirements of ultra-small chips; ② Minimum dispensing area of ​​0.04mm², suitable for ultra-small chips below 150μm; ③ Intelligent silver paste control system, which can adjust the dispensing amount in real time to ensure uniform adhesive thickness.

[0024] Material selection and parameter control: Adhesive material: EPO-TEKH70E conductive adhesive (thermal conductivity ≥1.2W / (m・K)) is selected.

[0025] Adhesive thickness control: Conductive adhesive thickness 7-15μm (adjusted according to chip size; 7-10μm for chip size <200μm, 12-15μm for chip size >1mm), insulating adhesive thickness 13-23μm (uniformity error ±2μm).

[0026] Leadframe parameters: The leadframe thickness is selected from 0.127mm, 0.152mm, 0.203mm, or 0.1mm, with a flatness ≤5μm / m, ensuring core positioning accuracy and bonding reliability. Leadframe reinforcing rib design: Rib width 10-20μm (adjusted according to the kerf width; 10μm for 40μm kerf, 20μm for 50μm kerf), thickness consistent with the leadframe (0.127mm, 0.152mm, 0.203mm, or 0.1mm), material Cu, integrally molded with the leadframe. Arrangement: Reinforcing ribs are evenly arranged on both sides of the kerf of the leadframe, with a spacing of 500-1000μm, ensuring the stability of the frame during the packaging process and preventing carrier exposure.

[0027] Process parameter optimization: core loading temperature 80℃-100℃ (initial curing temperature of conductive adhesive), core loading pressure 0.05-0.1MPa, core loading time 1-2 seconds / piece.

[0028] Quality control indicators: chip thrust CPK>1.67, no bubbles or excess adhesive in the adhesive layer, and positioning deviation of the chip being mounted ≤±20μm.

[0029] S4: Pressure welding Equipment selection: The ASMI Hawk Aero wire bonding equipment is adopted. This equipment supports multi-wire compatibility, has a fast welding speed, and high stability. Key parameters: welding speed 24 wires / sec, positioning accuracy ≤1μm, supports three wire bonding methods: forward bonding, reverse bonding, and BSOB, which can meet the welding needs of high pin density devices.

[0030] Wire selection and parameter design: Wire type: Select Au wire, Ag wire, PdCu wire, or Cu wire based on cost and reliability requirements. Wire parameters are shown in Table 1. Table 1 shows the wire parameters.

[0031] Welding parameter control: EFO (Electronic Flame Extinguishing) parameters: ignition current 2-5A, ignition time 0.1-0.3ms, burning ball diameter is 1.8-2.2 times the wire diameter.

[0032] First solder joint (chip pad): soldering pressure 0.1-0.2MPa, soldering temperature 200℃-220℃, soldering time 15-25ms, to ensure a tight bond between the solder joint and the pad.

[0033] Second solder joint (lead frame pin): soldering pressure 0.15-0.25MPa, soldering temperature 220℃-240℃, soldering time 20-30ms, to improve the bonding strength between the solder joint and the pin.

[0034] WireLoop control: Arc height is adjusted according to package thickness (50-70μm when package thickness is 0.375mm, 100-120μm when package thickness is 0.75mm), with a safe arc height ≥20μm (to avoid wire breakage due to friction with the molded body).

[0035] Quality control indicators: Wirepull CPK > 1.67, Ballshear CPK > 1.67, X-ray inspection shows no solder joint peeling, and WireLoop deformation rate ≤ 1%.

[0036] S5: Plastic sealing Equipment Selection: The IDEALmold3G120Ton fully automatic molding and sealing equipment is adopted. This equipment has a vacuum adsorption function for the lower mold (vacuum degree ≤ -95kPa), which can effectively remove air from the mold and avoid the formation of air bubbles in the molded body; the output per unit time (UPH) is ≥132 pieces / H, and it is compatible with LF of various thicknesses of 0.102mm, 0.127mm, 0.152mm and 0.203mm, with high production efficiency.

[0037] EMC Material Selection: Epoxy resin molding compound (EMC) is selected, with the following core parameters: glass transition temperature (Tg) ≥150℃, coefficient of thermal expansion (CTE) ≤20ppm / ℃ (25℃-125℃), flexural strength ≥150MPa, water absorption ≤0.2% (85℃ / 85%RH, 24H), and flame retardant rating V-0, ensuring the high temperature and humidity resistance of the molded body.

[0038] Process parameter optimization: Molding temperature: 175℃-180℃ (EMC curing temperature, to ensure full curing).

[0039] Encapsulation pressure: 10-12MPa (adjusted according to lead frame thickness; 10MPa for lead frame thickness of 0.102mm and 12MPa for lead frame thickness of 0.203mm).

[0040] Imaging time: 90-120 seconds (adjusted according to the encapsulation thickness; 90 seconds for 0.375mm thickness and 120 seconds for 0.75mm thickness).

[0041] Vacuum adsorption time: Vacuum adsorption for 3-5 seconds before molding to remove air from the mold and prevent bubbles and delamination from forming in the molded body.

[0042] Quality control indicators: Wiresweep <2% (lead offset ≤2% of wire length), no delamination or bubbles in the encapsulation (inspected by X-Ray and SAT scanning acoustic microscopy, bubble diameter ≤50μm, bubble number ≤3 / bubble), encapsulation dimensional tolerance ±10μm, surface roughness ≤5μm.

[0043] S6: Post-curing Equipment selection: A precision constant temperature curing oven is adopted, with a temperature control accuracy of ±2℃ and a hot air circulation function (wind speed 0.5-1m / s) to ensure uniform temperature inside the oven and avoid local overheating that could cause the molded body to crack.

[0044] Process parameter design: curing temperature 175℃±5℃, curing time 4-8 hours (adjusted according to the thickness of the molding compound; 4-6 hours for a thickness of 0.375-0.5mm, and 6-8 hours for a thickness of 0.75mm); heating rate 3-5℃ / min (to avoid sudden temperature rise that could cause the molding compound to crack), cooling rate 2-3℃ / min (natural cooling to room temperature).

[0045] Quality control indicators: internal stress of the molded body ≤50MPa (tested by a stress meter), EMC curing degree ≥95% (detected by differential scanning calorimetry DSC), Shore hardness of the molded body ≥85D.

[0046] Auxiliary treatment: After post-curing, use plasma cleaning equipment to clean the surface of the molded body to remove residual EMC dust. The cleaning time is 2-3 minutes, and the plasma power is 80-100W to ensure that the surface of the molded body is clean.

[0047] S7: Electroplating Equipment Selection: The fully automatic loading and unloading electroplating equipment is adopted. This equipment has the following advantages: ① Automatic padding paper placement function to avoid scratches on the plating layer; ② Compatible with frames with a width of 50-100mm, with strong compatibility; ③ Electroplating solution circulation filtration system with filtration accuracy ≤1μm to ensure uniform plating layer.

[0048] Electroplating process design: Electroplating solution: Acidic tin plating solution, the main components of which include SnSO4 (concentration of 40-60g / L), H2SO4 (concentration of 100-150g / L), brightener (sodium methanesulfonate concentration of 5-10mL / L), leveling agent (polyethyleneimine concentration of 3-5mL / L), pH value of 1.0-1.5, temperature of 25-30℃, to ensure the density and uniformity of the plating layer.

[0049] Electroplating parameters: current density 2.0-2.2A / dm² (adjust according to the coating thickness; use 2.0A / dm² for a thickness of 7-10μm and 2.2A / dm² for a thickness of 10-13μm), electroplating time 30-35 seconds, electroplating solution circulation speed 5-8L / min to ensure uniform coating thickness.

[0050] Pretreatment: Before electroplating, pickling (5% H2SO4 solution, temperature 25℃, time 10-15 seconds) is used to remove the oxide layer on the surface of the lead frame, and then rinsed with deionized water (rinsing time 3-5 seconds) to avoid the oxide layer affecting the adhesion of the plating.

[0051] Quality control indicators: coating thickness 7-13μm (uniformity error ≤±1μm), coating adhesion ≥1.5N / mm (tape test, ASTM D3359), coating gloss ≥80GU (measured at 60° angle), no missed coating or incomplete coating.

[0052] S8: Cutting Equipment selection: The DiscoDFD3350 high-precision cutting equipment is adopted. This equipment has a cutting accuracy of ≤5μm, a repeatability of ≤2μm, and excellent stability. It is equipped with a water-cooling system, which can effectively prevent the die from being damaged by high temperature during the cutting process.

[0053] Process parameter optimization: Cutting speed: 25-30mm / s (adjusted according to the package size; 25mm / s for sizes <1mm×1mm, and 30mm / s for sizes >2mm×2mm).

[0054] Cutting tool: Diamond cutting blade, thickness 20-30μm, hardness HRC≥70, cutting edge roughness ≤0.1μm, ensuring a smooth cutting surface without chipping.

[0055] Water cooling parameters: cooling water temperature 20℃-25℃, water flow rate 1-2L / min, water pressure 0.1-0.2MPa, directly rinsing the cutting area to reduce the cutting temperature.

[0056] Quality control indicators: cutting accuracy ≤5μm, finished product packaging size tolerance ±20μm, cutting surface perpendicularity ≥90°±0.5°, no chipping or cracking.

[0057] S9: Reflow soldering Equipment selection: High-precision reflow oven with multi-temperature zone control (≥8 temperature zones) and temperature control accuracy of ±1℃ is adopted, which can accurately simulate the reflow soldering environment of PCB assembly.

[0058] Process parameter design: Heating zone: The temperature rises from room temperature to 150℃-180℃ at a rate of 3-5℃ / sec to ensure uniform heating of the plating and solder joints and avoid thermal shock.

[0059] Constant temperature zone: The temperature is maintained at 180℃-200℃ for 60-90 seconds to fully activate the flux and remove the oxide layer on the pin surface.

[0060] Reflow zone: Peak temperature 260℃±5℃, peak temperature held for 10-15 seconds, to ensure full melting of the solder joint and improve welding reliability.

[0061] Cooling zone: Cools from peak temperature to room temperature at a rate of 2-3°C / sec to avoid rapid cooling that could cause internal stress in the package.

[0062] Quality control indicators: No cracking of the encapsulation, deformation of the leads, or peeling of the plating after reflow soldering; the solder joints are fully melted.

[0063] S10: Testing and Printing Electrical performance testing: Equipment selection: The Accotest STS8200, QT-6000 or QT-4000 electrical performance testing platform is adopted, and the test sorting machine is selected from ASM Ftmini and Shenkeda equipment, which supports the testing of various device types such as analog devices, discrete devices and power MOS.

[0064] Test parameters: Test items are set according to the device SPEC, including breakdown voltage (Vbr), leakage current (Ileak), on-resistance (Rds(on)), output voltage (Vout), quiescent current (Iq), etc., with test accuracy ≤ ±0.1%.

[0065] Testing process: A 100% full inspection mode is adopted, with each product undergoing at least 3 testing stations to ensure reliable test results; products that fail the test are automatically sorted into the waste box, and the pass rate is statistically analyzed in real time.

[0066] AOI six-sided inspection: Equipment selection: AOI six-sided inspection equipment with an inspection accuracy of ≤2μm and image recognition algorithm, which can automatically identify appearance defects.

[0067] Inspection items include: plastic package scratches (length ≤ 0.5 mm, width ≤ 0.1 mm), excess glue (excess glue amount ≤ 0.1 mm), pin deformation (deformation amount ≤ 0.05 mm), plating defects (corrosion, peeling), chip misalignment (misalignment amount ≤ 0.1 mm), solder joint defects (cold solder joint, desoldering), etc.

[0068] Inspection process: The product is conveyed through a conveyor mechanism to acquire images of six sides: top, bottom, front, back, left, and right. The images are compared with a standard template, and defective products are automatically marked and sorted.

[0069] Laser printing: Equipment selection: Fiber laser printer, output power 10-20W, printing speed ≥1000 characters / second, printing accuracy ≤5μm.

[0070] Printed content includes product model, production batch, and traceability code (QR code or barcode). The printing depth is 5-10μm, the character width is ≥50μm, and the character height is ≥100μm.

[0071] Quality control: Print clarity ≥ 95% (no blurring, no broken strokes).

[0072] S11: Finished Product Re-inspection and Packaging Final visual inspection: Manual visual inspection and magnifying glass inspection are used, with a sampling rate of 10%. The focus is on checking the clarity of the printed text, the integrity of the plastic package, the condition of the pins, and the quality of the solder joints to ensure that no defects are missed.

[0073] Reliability testing: Reliability testing is conducted on a sample basis, with a sampling rate of 0.1%. Test items include high and low temperature cycling test, damp heat test, salt spray test, and mechanical shock test.

[0074] Packaging and warehousing: Qualified products are sealed in anti-static packaging bags, 500-1000 pieces per bag. A desiccant is placed inside the packaging bag, and the outer box is labeled with the product model, production batch, quantity, and production date.

[0075] Example S1: Wafer thinning Equipment: DFG8540 grinding mill; Process parameters: grinding speed 3500rpm, grinding pressure 0.12MPa, grinding wheel grit size 12000 mesh; Auxiliary treatment: Plasma cleaning time 4 minutes, power 120W; Quality indicators: wafer thickness after thinning is 100μm, thickness tolerance is ±8μm, TTV=3μm, surface roughness is 10nm.

[0076] S2: School district Equipment: DFD6340 dicing machine; Process parameters: diamond-coated blade thickness 20μm, 60μm thick UV-cured protective film (adhesive 15g / in) attached to the front side of the wafer, dicing speed segmented control (15mm / s in the middle area and 10mm / s in the edge area), UV stripping parameters (wavelength 365nm, energy 1200mJ / cm²). Quality indicators: cutting accuracy ±3μm, chip edge burr height 2μm.

[0077] S3: Core Equipment: ASMAD832i dispensing and core-mounting equipment; Leadframe: A leadframe with reinforcing ribs of 15μm width is selected; Process parameters: conductive adhesive thickness 10μm, core loading temperature 90℃, core loading pressure 0.08MPa, core loading time 1.5 seconds / core; Quality indicators: Chip positioning accuracy ±15μm, chip thrust CPK=1.82.

[0078] S4: Pressure welding Equipment: ASMI Hawk Aero type pressure welding equipment; Process parameters: EFO ignition current 3A, time 0.2ms, first solder joint temperature 210℃, pressure 0.15MPa, time 20ms, second solder joint temperature 230℃, pressure 0.2MPa, time 25ms, WireLoop arc height 60μm; Quality indicators: Welding speed 26 wires / sec, Wirepull CPK=1.75, Ballshear CPK=1.80.

[0079] S5: Plastic sealing Equipment: IDEALmold3G120Ton type molding machine; Process parameters: molding temperature 178℃, pressure 11MPa, time 100 seconds, vacuum adsorption for 4 seconds before molding (vacuum degree -96kPa). Quality indicators: lead offset 1.2%, encapsulation size 1.2mm×1.2mm×0.375mm, no bubbles or delamination.

[0080] S6: Post-curing Equipment: Precision constant temperature curing oven; Process parameters: curing temperature 175℃, curing time 6 hours, heating rate 4℃ / min, cooling rate 2.5℃ / min; Quality indicators: internal stress of the encapsulated body 42MPa, EMC curing degree 97%.

[0081] S7: Electroplating Equipment: Fully automatic loading and unloading electroplating equipment; Process parameters: pickling (5% H2SO4 solution, 25℃, 12 seconds), current density 2.1A / dm², electroplating time 32 seconds, electroplating solution circulation rate 6L / min; Quality indicators: coating thickness 10μm, uniformity error ±0.8μm, coating adhesion 1.8N / mm.

[0082] S8: Cutting Equipment: DiscoDFD3350 cutting machine; Process parameters: cutting speed 28mm / s, diamond blade thickness 25μm, water cooling parameters (water temperature 22℃, water flow rate 1.5L / min, water pressure 0.15MPa). Quality indicators: cutting accuracy ±4μm, finished product packaging size tolerance ±15μm, cutting surface perpendicularity 90°±0.3°.

[0083] S9: Reflow soldering Equipment: High-precision 8-zone reflow oven; Process parameters: heating rate 4℃ / sec (room temperature → 170℃), isothermal zone (180℃, 75 seconds), reflux zone peak temperature 260℃, holding time 12 seconds, cooling rate 2.5℃ / sec; Quality indicators: No plastic encapsulation cracks or lead deformation.

[0084] S10: Testing and Printing Electrical performance testing: Accotest STS8200 platform, testing parameters such as breakdown voltage (Vbr) and leakage current (Ileak); AOI inspection: Six-sided inspection equipment (accuracy ±2μm) to identify defects such as scratches and excess glue; Laser printing: 15W power, 8μm printing depth, content includes model number, batch number, and QR code.

[0085] S11: Finished Product Re-inspection and Packaging Reliability testing: Sampling rate 0.1% (10 units / 10,000 units), high and low temperature cycling, damp heat and other tests are carried out; Packaging: Sealed in anti-static bags, 500 pieces per bag, with desiccant inside.

[0086] Test methods (a) Experimental grouping Experimental group: 1000 DFN packaged chips were prepared using the process of the present invention in the above embodiments; Control group: 1000 DFN packaged chips were prepared using existing conventional DFN packaging technology (without plasma cleaning, without UV protective film dicing, without plastic sealing vacuum adsorption, and without lead frame reinforcing ribs), with other basic materials being the same.

[0087] (II) Test items and equipment are shown in Table 2

[0088] (III) Testing Process Production stage: Simultaneously record the number of defects in each process of the two sets of processes (such as chip cracks, lead wire misalignment, plating defects, etc.). Finished product stage: 100% electrical performance testing + AOI inspection, yield rate statistics; randomly select 50 pieces / group to test packaging accuracy; Reliability phase: 10 units / group are randomly selected and four reliability tests are completed, including high and low temperature cycling and damp heat tests, and failure situations are recorded; Data processing: Compare the yield, accuracy, electrical performance parameters, reliability, and failure probability of the two groups.

[0089] The experimental data are shown in Table 3.

[0090] The experimental results above are analyzed in conjunction with Table 3. (I) Analysis of the reasons for the improvement in yield The yield rate in the experimental group (98.5%) was 6.2 percentage points higher than that in the control group (92.3%). The core reason for this is: After wafer thinning, a plasma cleaning process is added to remove surface dust and impurities, reducing contact defects of the adhesive layer during wafer mounting. In the control group, which lacks this process, the defect rate of poor bonding between the chip and the conductive adhesive reaches 3.1%. During the dicing stage, a UV-cured protective film and segmented speed control were used, resulting in a chip edge burr height of ≤2μm and a crack defect rate of only 0.1%. In contrast, the control group, which had no protective film, experienced a chip edge damage defect rate of 2.8% due to dicing debris. The lead frame has a pre-set reinforcing rib structure, which effectively avoids frame deformation during the packaging process. In the control group, the defect rate of core offset and lead offset caused by frame deformation reached 2.5%.

[0091] (II) Packaging accuracy and electrical performance optimization analysis Packaging accuracy: The package size tolerance of the experimental group was ±15μm and the cutting accuracy was ±4μm, which was significantly better than the control group (±30μm, ±8μm). This was due to the ±15μm positioning accuracy of the chip loading equipment, the water cooling during the cutting process, and the synergy of high-precision equipment, which reduced the size deviation caused by mechanical stress. Electrical performance: The average on-resistance of the test group was 42mΩ (lower than the control group's 48mΩ), and the average leakage current was 0.3μA (lower than the control group's 0.7μA). This is because the precise parameter control of the pressure welding process (such as the matching of solder joint temperature and pressure) ensured the tight connection between the metal wire and the Pad and pin, reducing the contact resistance. At the same time, the plastic encapsulation was free of bubbles and delamination, reducing the drift of electrical performance.

[0092] (III) Reliability Improvement Mechanism Analysis The molding process uses vacuum adsorption (4 seconds) to remove air from the mold, resulting in a bubble rate of only 0.2% in the molded body (compared to 3.8% in the control group). The cracking rate after high and low temperature cycling is 0.3% (compared to 3.5% in the control group), thus avoiding the rupture of the molded body caused by thermal expansion and contraction during temperature cycling. The post-curing process (175℃×6 hours) effectively eliminates the internal stress (42MPa) of the molding compound, improving the bonding stability between the molding compound and the chip and lead frame. No failures were observed after the damp heat test (compared to 2.1% failure rate in the control group). Pickling before electroplating removes the oxide layer on the lead frame surface, resulting in a plating adhesion of 1.8 N / mm. After salt spray testing, the corrosion rate is only 0.1%, far lower than the 1.8% of the control group, thus enhancing the product's service life in harsh environments.

[0093] This invention achieves three core advantages through the coordinated optimization of equipment selection, material parameters, and process parameters in 11 key processes: production yield is increased from 92.3% to 98.5%, reducing cost losses caused by process defects; packaging accuracy reaches ±15μm, adapting to the needs of ultra-small, high-density DFN packaging; and reliability is significantly improved, with the failure probability after high and low temperature cycling and damp heat tests being much lower than that of conventional processes, meeting the stringent requirements of high-end scenarios such as automotive electronics and industrial control.

[0094] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A chip DFN packaging process, characterized in that, Includes the following steps: S1: Wafer thinning, the wafer is polished using polishing equipment, and the thickness of the thinned wafer is controlled to be ≥80μm, the thickness tolerance is ±10μm, the total thickness change (TTV) is ≤5μm, and the surface roughness is ≤15nm; S2: Dicing. The thinned wafer is diced into individual chips using a dicing machine. The dicing width is controlled to be ≥40μm, and the dicing accuracy is ≤5μm. Diamond-coated blades are used during the dicing process, and the chip edge burr height is controlled to be ≤3μm. The blade thickness is 15-30μm. Before dicing, a UV-cured protective film with a thickness of 50-80μm is attached to the front side of the wafer. The dicing speed is controlled in segments at 10-20mm / s. After dicing, the protective film is removed by UV irradiation with a wavelength of 365nm and an energy of 1000-1500mJ / cm². S3: Chip mounting. Using a dispensing and mounting device, the chip is fixed to the lead frame with conductive adhesive. The thickness of the conductive adhesive is controlled at 7-15μm, the positioning accuracy of the chip mounting is ±20μm, and the chip push force CPK>1.

67. S4: Pressure bonding, using pressure bonding equipment, the pads of the chip are electrically connected to the pins of the lead frame through metal wires. The diameter of the metal wires ranges from 0.5 to 2.0 mil, the bonding speed is ≥24 wires / sec, the opening of the bonding pads is ≥42μm, and the spacing between the bonding pads is ≥40μm. S5: Molding. Molding equipment is used, which has a vacuum adsorption function for the lower mold. Epoxy resin molding compound is used to mold the semi-finished product after pressure welding. The molding temperature is 175-180℃, the pressure is 10-12MPa, and the time is 90-120 seconds. The lead wire offset is controlled to be <2%. S6: Post-curing. The encapsulated semi-finished product is placed in a constant temperature curing oven and cured at 175±5℃ for 4-8 hours. The heating rate is 3-5℃ / min and the cooling rate is 2-3℃ / min. This is used to eliminate internal stress in the encapsulated body. S7: Electroplating. The semi-finished product after post-curing is tin-plated using electroplating equipment. The electroplating solution is an acidic tin plating solution, with a current density of 2.0-2.2A / dm², an electroplating time of 30-35 seconds, a plating thickness of 7-13μm, and a plating uniformity error of ≤±1μm. S8: Cutting. The electroplated lead frame is cut and separated using cutting equipment at a cutting speed of 25-30mm / s. Water cooling is used during the cutting process to control the cutting accuracy to ≤5μm and the finished package size tolerance to within ±20μm. S9: Reflow soldering, the semi-finished product after cutting is reflow soldered. The reflow soldering parameters are: heating rate 3-5℃ / sec, peak temperature 260±5℃, peak temperature holding time 10-15 seconds, cooling rate 2-3℃ / sec. S10: Testing and printing. The electrical performance of the finished product after reflow soldering is tested using an electrical performance testing platform. The appearance is inspected using an AOI six-sided inspection device. After passing the inspection, the printing is completed by a laser printing device with a printing depth of 5-10μm. S11: Finished product re-inspection and packaging. Sampling reliability tests are conducted on printed products, and qualified products are packaged and put into storage.

2. The chip DFN packaging process according to claim 1, characterized in that: In step S1, the grinding process controls the grinding speed at 3000-4000 rpm, the grinding pressure at 0.1-0.15 MPa, and the grinding wheel grit size at 10000-15000 mesh. After thinning, the wafer surface is cleaned using a plasma cleaning device for 3-5 minutes with a plasma power of 100-150W.

3. The chip DFN packaging process according to claim 1, characterized in that: In step S3, a reinforcing rib structure is preset at the cutting edge of the lead frame, and the width of the reinforcing rib is 10-20μm, the thickness is the same as that of the lead frame, and the reinforcing rib is integrally formed with the lead frame.

4. The chip DFN packaging process according to claim 1, characterized in that: In step S4, the metal wire is one or more of Au wire, Ag wire, PdCu wire, and Cu wire.

5. The chip DFN packaging process according to claim 1, characterized in that: In step S5, the vacuum adsorption time before sealing is 3-5 seconds, and the vacuum pressure is 8-10 MPa.

6. The chip DFN packaging process according to claim 1, characterized in that: In step S7, the acidic tin plating solution consists of SnSO4, H2SO4, brightener and leveling agent, and is pickled with 5% H2SO4 solution for 10-15 seconds before electroplating to remove the oxide layer on the lead frame surface.

7. The chip DFN packaging process according to claim 1, characterized in that: The electrical performance test items in step S10 include breakdown voltage, leakage current, on-resistance, output voltage, and quiescent current; the AOI inspection items include identifiable scratches, excess adhesive, pin deformation, and plating defects.

8. The chip DFN packaging process according to claim 1, characterized in that: The reliability test in step S11 includes high and low temperature cycling test, damp heat test, salt spray test and mechanical shock test.

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