Device stacking double-sided fan-out embedded packaging method and substrate

Abstract

This invention discloses a method and substrate for double-sided fan-out embedded packaging of stacked devices, relating to the field of packaging substrate technology. The method includes: providing a first substrate; fabricating conductive barriers on the surface of a second circuit; laminating a first dielectric layer onto the side of the first substrate where the second circuit is located; creating a first blind via in the first dielectric layer; filling the first blind via with conductive material; placing a second device on the side of the first dielectric layer away from the first substrate; laminating a second dielectric layer onto the side of the first dielectric layer away from the first substrate; creating a second blind via in the second dielectric layer, communicating with the second circuit and the second device; performing via-filling electroplating on the second blind via; and fabricating a third circuit communicating with the second blind via at the bottom of the second dielectric layer, thereby obtaining the packaging substrate. According to the method of this invention, the packaging area can be reduced, while achieving double-sided fan-out of stacked devices, increasing interconnect density, reducing interconnect distance, and improving product performance.

Description

Technical Field

[0001] This invention relates to the field of packaging substrate technology, and in particular to a device stacking double-sided fan-out embedded packaging method and substrate. Background Technology

[0002] In traditional packaging technologies, passive components such as resistors, capacitors, and inductors, as well as active devices such as chips, are typically mounted on the substrate surface. This approach not only occupies a significant amount of space but also severely limits the miniaturization and high performance of devices. To overcome this bottleneck, embedded technology has emerged. By embedding passive components and active devices inside the substrate, embedded technology significantly improves integration density and drastically reduces device size. However, existing embedded substrate technologies still face many challenges, such as thermal expansion coefficient mismatch, flatness control, and internal defects.

[0003] With the ever-increasing demand for high-performance integrated circuits in consumer electronics, communication equipment, automotive electronics, and other fields, the importance of embedded substrate technology is becoming increasingly prominent. In order to meet the demand for higher performance, embedded substrate technology urgently needs continuous innovation in materials and processes to break through existing bottlenecks and drive electronic devices towards smaller, stronger, and more reliable designs.

[0004] Currently, when embedding multiple devices in a packaging substrate, the common practice is to create multiple horizontal cavities on the frame and arrange the devices horizontally inside the cavities. However, this method of horizontally placing embedded devices occupies a large packaging area, which is not conducive to package miniaturization. There are also methods that vertically stack and embed multiple devices, but existing vertical stacking embedding methods can only achieve single-sided fan-out of the devices, not double-sided fan-out, further increasing interconnect density and reducing interconnect distance, and also cannot provide heat dissipation on one side of the devices. Furthermore, the devices need to be bumped to interconnect after vertical stacking, which is costly. Summary of the Invention

[0005] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a device stacking double-sided fan-out embedded packaging method and substrate, which can reduce the packaging area, while realizing double-sided fan-out of stacked devices, increasing interconnect density, reducing interconnect distance, and improving product performance.

[0006] In a first aspect, a device stacking double-sided fan-out embedded packaging method according to an embodiment of the present invention includes the following steps: A first substrate is provided, wherein a conductive post and a first device are disposed therein, and a first line and a second line are disposed on both sides of the first substrate and connected through the conductive post, wherein the first line is connected to one side of the first device and the second line is connected to the other side of the first device. A conductive barrier is fabricated on the surface of the second circuit; A first dielectric layer is laminated on the side of the first substrate where the second circuit is disposed, and the first dielectric layer covers the second circuit and the conductive barrier; An opening is made in the first dielectric layer to form a first blind hole, the first blind hole being located within the conductive enclosure and connected to the second line; The first blind hole is filled with conductive material; A second device is placed on the side of the first dielectric layer away from the first substrate, and the second device is in contact with the conductive material; A second dielectric layer is laminated onto the side of the first dielectric layer away from the first substrate, and the second dielectric layer covers the second device; An opening is made in the second dielectric layer to form a second blind via that communicates with the second circuit and the second device; The second blind via is filled by electroplating, and a third line connected to the second blind via is formed at the bottom of the second dielectric layer to obtain a packaging substrate.

[0007] According to some embodiments of the present invention, the provision of the first substrate includes: A support plate is provided, wherein the support plate is provided with the guide post and the cavity; The first device is placed inside the cavity; A third dielectric layer is pressed onto the first surface of the carrier plate to encapsulate the first device. The third dielectric layer covers the first surface of the carrier plate and fills the cavity. An opening is made in the third dielectric layer to form a first blind via that communicates with one end of the conductive post and one side of the first device; The first blind via is filled by electroplating, and the first line that is connected to the first blind via is formed on the surface of the third dielectric layer. The second circuit is formed on the second surface of the carrier plate, and the second circuit is connected to the other end of the conductive post and the other side of the first device.

[0008] According to some embodiments of the present invention, a first metal surface is provided on one side of the first device, and a first signal terminal is provided on the other side of the first device; placing the first device in the cavity includes: A temporary bonding film is disposed on the second surface of the carrier plate; The first device is placed inside the cavity, and the temporary bonding film fixes the side of the first device that is provided with the first signal terminal. After the step of creating an opening in the third dielectric layer to form a first blind via communicating with one end of the conductive post and one side of the first device, the temporary bonding film is removed.

[0009] According to some embodiments of the present invention, the step of fabricating a conductive barrier on the surface of the second line includes: A protective dry film is attached to the surface of the first substrate; The protective dry film is exposed and developed to form a pattern corresponding to the conductive barrier. Electroplating is performed according to the described pattern to form the conductive enclosure; Remove the protective dry film.

[0010] According to some embodiments of the present invention, the conductive enclosure is in the form of a ring.

[0011] According to some embodiments of the present invention, filling the first blind hole with conductive material includes: Conductive material is filled into the first blind hole by 3D printing, dispensing, or printing.

[0012] According to some embodiments of the present invention, a second metal surface is provided on one side of the second device, and a second signal terminal is provided on the other side of the second device; placing the second device on the side of the first dielectric layer away from the first substrate includes: A second device is placed on the side of the first dielectric layer away from the first substrate, and the second device is bonded through the first dielectric layer. The second signal terminal of the second device is connected to the conductive material. The first dielectric layer and the conductive material are thermally cured.

[0013] In a second aspect, the device stacking double-sided fan-out embedded packaging substrate according to embodiments of the present invention includes: A first substrate has a conductive post and a first device disposed therein. A first line and a second line are disposed on both sides of the first substrate and are connected through the conductive post. The first line is connected to one side of the first device and the second line is connected to the other side of the first device. A conductive barrier is installed on the surface of the second circuit; A first dielectric layer is disposed on the side of the first substrate where the second circuit is disposed. The first dielectric layer covers the second circuit and the conductive barrier. The first dielectric layer has a first blind via located inside the conductive barrier and is connected to the second circuit. Conductive material is used to fill the first blind hole; The second device is located on the side of the first dielectric layer away from the first substrate, and the second device is in contact with the conductive material; A second dielectric layer is disposed on the side of the first dielectric layer away from the first substrate. The second dielectric layer covers the second device. The second dielectric layer has a second blind via. The second blind via is connected to the second circuit and the second device. The second blind via is filled by via plating. The third line is disposed at the bottom of the second dielectric layer, and the third line is connected to the second blind via after the via filling electroplating.

[0014] According to some embodiments of the present invention, a first metal surface is provided on one side of the first device, and a first signal terminal is provided on the other side of the first device.

[0015] According to some embodiments of the present invention, a second metal surface is provided on one side of the second device, and a second signal terminal is provided on the other side of the second device.

[0016] The device stacking double-sided fan-out embedded packaging method and substrate according to embodiments of the present invention have at least the following beneficial effects: vertical stacking of devices can be achieved without the need for solder bumping, thereby reducing the packaging area; at the same time, double-sided fan-out of stacked devices can be achieved, increasing interconnect density, reducing interconnect distance, and improving product performance.

[0017] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a flowchart illustrating the steps of the device stacking double-sided fan-out embedded packaging method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of the support plate according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after a temporary bonding film is provided on the carrier plate according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure after the first device is placed in the cavity according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure after the third medium layer is pressed onto the bearing plate according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure after opening holes in the third dielectric layer according to an embodiment of the present invention; Figure 7This is a schematic diagram of the structure after removing the temporary bonding film in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure after a conductive barrier is fabricated on the surface of the second circuit according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the structure after the first dielectric layer is laminated onto the first substrate, according to an embodiment of the present invention. Figure 10 This is a schematic diagram of the structure after a first blind via is formed by opening a hole in the first dielectric layer according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure after the first blind hole is filled with conductive material according to an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure after placing the second device in the first dielectric layer according to an embodiment of the present invention; Figure 13 This is a schematic diagram of the structure after the second dielectric layer is laminated onto the first dielectric layer according to an embodiment of the present invention; Figure 14 This is a schematic diagram of the structure after a second blind via is formed by opening a hole in the second dielectric layer according to an embodiment of the present invention; Figure 15 This is a schematic diagram of the packaging substrate according to an embodiment of the present invention. Detailed Implementation

[0019] The embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0020] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0021] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0022] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0023] Currently, when embedding multiple devices in a packaging substrate, the common practice is to create multiple horizontal cavities on the frame and arrange the devices horizontally inside the cavities. However, this method of horizontally placing embedded devices occupies a large packaging area, which is not conducive to package miniaturization. There are also methods that vertically stack and embed multiple devices, but existing vertical stacking embedding methods can only achieve single-sided fan-out of the devices, not double-sided fan-out, further increasing interconnect density and reducing interconnect distance, and also cannot provide heat dissipation on one side of the devices. Furthermore, the devices need to be bumped to interconnect after vertical stacking, which is costly.

[0024] To address the aforementioned issues, this invention proposes a device stacking double-sided fan-out embedded packaging method. This method eliminates the need for solder bumping and enables vertical stacking of devices, thereby reducing the package area. Simultaneously, it allows for double-sided fan-out of stacked devices, increasing interconnect density, reducing interconnect distance, and improving product performance.

[0025] The following description, in conjunction with the accompanying drawings, details the wettable side-wing packaging substrate structure, its fabrication method, equipment, and medium according to embodiments of the present invention.

[0026] On the one hand, such as Figure 1 As shown, the device stacking double-sided fan-out embedded packaging method according to an embodiment of the present invention includes, but is not limited to, steps S100-S900: Step S100: Provide the first substrate 700; Specifically, such as Figure 8As shown, in this example, a conductive post 120 and a first device 300 are disposed within the first substrate 700. A first line 500 and a second line 600, which are connected through the conductive post 120, are disposed on both sides of the first substrate 700. The first line 500 is connected to one side of the first device 300, and the second line 600 is connected to the other side of the first device 300. By providing the first line 500 on one side of the first substrate 700 and making the first line 500 connected to the first device 300, one side of the first device 300 can be fanned out; by providing the second line 600 on the other side of the first substrate 700 and making the second line 600 connected to the first device 300, the other side of the first device 300 can be fanned out.

[0027] Step S200: Create a conductive barrier 610 on the surface of the second line 600; The conductive wall 610 can be a copper pillar wall. The conductive wall 610 can limit the pressing depth of the subsequent second device 1000 in terms of height, so as to avoid short circuits between dense terminals due to the second device 1000 pressing too deeply and squeezing the conductive material 900 horizontally. At the same time, the conductive wall 610 can confine the conductive material 900 inside the conductive wall 610, so as to avoid the problem of ion migration of conductive ions in the conductive material 900 during subsequent use.

[0028] Step S300: Press the first dielectric layer 800 onto the side of the first substrate 700 where the second line 600 is disposed; like Figure 9 As shown, the first dielectric layer 800 covers the second line 600 and the conductive barrier 610. By setting the first dielectric layer 800, the second line 600 and the conductive barrier 610 are insulated and protected.

[0029] Step S400: Open a hole in the first dielectric layer 800 to form a first blind via 810; like Figure 10 As shown, the first blind hole 810 is located within the conductive enclosure 610 and is connected to the second circuit 600. By opening the first blind hole 810, the second circuit 600 is exposed, facilitating conductivity between the second circuit 600 and the conductive material 900. Since the first blind hole 810 is located within the conductive enclosure 610, the conductive material 900 can be confined within the conductive enclosure 610, preventing ion migration of conductive ions during subsequent use. The size of the first blind hole 810 can be the same as or smaller than the inner diameter of the conductive enclosure 610.

[0030] Step S500: Fill the first blind hole 810 with conductive material 900; like Figure 11As shown, by filling the first blind hole 810 with conductive material 900, it is convenient to lead out the second line 600 and connect it to the subsequent second device 1000.

[0031] Step S600: Place the second device 1000 on the side of the first dielectric layer 800 away from the first substrate 700, and make the second device 1000 conductive with the conductive material 900. like Figure 12 As shown, since the second device 1000 is connected to the conductive material 900, and the conductive material 900 is connected to the second line 600, the first line 500, the first device 300, the second line 600, the conductive material 900, and the second device 1000 are all interconnected.

[0032] Step S700: Press the second dielectric layer 1100 onto the side of the first dielectric layer 800 away from the first substrate 700; like Figure 13 As shown, the second dielectric layer 1100 covers the second device 1000, and the second dielectric layer 1100 serves to insulate and protect the second device 1000.

[0033] Step S800: Open a hole in the second dielectric layer 1100 to form a second blind via 1110 that communicates with the second line 600 and the second device 1000; like Figure 14 As shown, by setting a second blind hole 1110, the second line 600 and the second device 1000 are exposed, which facilitates the connection between the second line 600 and the second device 1000 and the subsequent third line 1200.

[0034] Step S900: Fill the second blind via 1110 with electroplating, and fabricate a third line 1200 that is connected to the second blind via 1110 at the bottom of the second dielectric layer 1100 to obtain the packaging substrate.

[0035] like Figure 15 As shown, by performing a hole-filling electroplating on the second blind hole 1110 to form a through hole, a third circuit 1200 is then fabricated at the bottom of the second dielectric layer 1100, enabling the third circuit 1200 to conduct through the through hole to the second circuit 1200 and the second device 1000. In this way, the first device 300 and the second device 1000 can be fanned out on both sides.

[0036] The device stacking double-sided fan-out embedded packaging method according to the embodiments of this application can achieve vertical stacking of devices without the need for soldering bumping, thereby reducing the packaging area. At the same time, it can achieve double-sided fan-out of stacked devices, increase interconnect density, reduce interconnect distance, and improve product performance.

[0037] Furthermore, in some embodiments of this application, the first substrate 700 is obtained through the following steps: Step S110: Provide a support plate 110, which is provided with a guide post 120 and a cavity 130; Step S120: Place the first device 300 inside the cavity 130; Step S130: Press the third dielectric layer 400 onto the first surface of the carrier plate 110, so that the third dielectric layer 400 encapsulates the first device 300, the third dielectric layer 400 covers the first surface of the carrier plate 110, and the third dielectric layer 400 fills the cavity 130. Step S140: Open a hole in the third dielectric layer 400 to form a first blind hole 410 that communicates with one end of the conductive post 120 and one side of the first device 300; Step S150: Fill the first blind hole 410 with electroplating, and fabricate a first line 500 that is connected to the first blind hole 410 on the surface of the third dielectric layer 400. Step S160: A second line 600 is fabricated on the second surface of the carrier plate 110, and the second line 600 is connected to the other end of the conductive post 120 and the other side of the first device 300.

[0038] Specifically, such as Figure 2 As shown, a support plate 110 is first provided. This support plate 110 has multiple through posts 120 extending through it. Simultaneously, the support plate 110 also has a cavity 130 to facilitate the placement of the first device 300. For example... Figure 4 As shown, a first metal surface 310 is provided on one side of the first device 300, and a first signal terminal 320 is provided on the other side of the first device 300. The first metal surface 310 can be used for both electrical connection and heat dissipation. When placing the first device 300 in the cavity 130, in order to initially fix the first device 300, as follows... Figure 3 As shown, a temporary bonding film 200 is first set on the second surface of the carrier plate 110, and then, as Figure 4 As shown, a first device 300 is placed inside the cavity 130, and a temporary bonding film 200 fixes the side of the first device 300 where the first signal terminal 320 is located; then, as... Figure 5 As shown, a third dielectric layer 400 is pressed onto the first surface of the carrier plate 110, thereby encapsulating the first device 300. The third dielectric layer 400 covers the first surface of the carrier plate 110 and fills the cavity 130; then, as... Figure 6 As shown, an opening is made in the third dielectric layer 400 to form a first blind via 410 communicating with one end of the conductive post 120 and one side of the first device 300. The first blind via 410 can be formed by laser drilling. Figure 7As shown, after the fabrication of the first blind via 410 is completed, the temporary bonding film 200 can be removed. Figure 8 As shown, the first blind via 410 is filled with electroplating, and a first line 500 communicating with the first blind via 410 is formed on the surface of the third dielectric layer 400, so that the first line 500 can communicate with the conductive post 120 and the first metal surface 310 of the first device 300 through the filled and electroplated first blind via 410; as shown Figure 8 As shown, a second circuit 600 is formed on the second surface of the carrier plate 110. The second circuit 600 is connected to the other end of the conductive post 120 and the other side of the first device 300. Thus, the first circuit 500 can be connected to the second circuit 600 through the first blind via 410 (after hole filling and plating) and the conductive post 120. The first metal surface 310 of the first device 300 can be brought out through the first circuit 500, and the first signal terminal 320 of the first device 300 can be brought out through the second circuit 600.

[0039] Furthermore, in some embodiments of this application, in order to create a conductive barrier 610 on the surface of the second line 600, the following four steps are included: Step S210: Apply a protective dry film to the surface of the first substrate 700; Step S220: Expose and develop the protective dry film to form a pattern corresponding to the conductive barrier 610; Step S230: Electroplating is performed according to the pattern to form a conductive barrier 610; Step S220: Remove the protective dry film.

[0040] Protective dry films are attached to both sides of the first substrate 700 to protect the first line 500 and the second line 600. Then, the protective dry films are exposed and developed to create openings at locations where conductive barriers 610 need to be electroplated, while the remaining areas are protected by the protective dry film. Next, conductive barriers 610 are formed at the opened locations by electroplating. Finally, the protective dry film is removed by etching or other methods. Figure 8 As shown, the conductive barrier 610 can be circular or other shapes. The position of the conductive barrier 610 corresponds to the position of the first signal terminal 610, and the number of conductive barriers 610 is the same as the number of the first signal terminals 610.

[0041] like Figure 12 As shown, in some embodiments of this application, a second metal surface 1010 is provided on one side of the second device 1000, and a second signal terminal 1020 is provided on the other side of the second device 1000; when the second device 1000 is placed on the side of the first dielectric layer 800 away from the first substrate 700, the following steps are included: Step S610: Place the second device 1000 on the side of the first dielectric layer 800 away from the first substrate 700, and bond the second device 1000 through the first dielectric layer 800. The second signal terminal 1020 of the second device 1000 is connected to the conductive material 900. Step S620: The first dielectric layer 800 and the conductive material 900 are thermo-cured.

[0042] like Figure 12 As shown, the second signal terminal 1020 of the active surface of the second device 1000 is aligned with the conductive material 900 and flip-chip bonded onto the first dielectric layer 800. Then, the first dielectric layer 800 and the conductive material 900 are cured, allowing the conductive material 900 to directly conduct electricity between the second device 1000 and the second circuit 600. The first dielectric layer 800 simultaneously performs three functions: as a permanent insulating layer on the packaging substrate to insulate the circuit; as an adhesive material to bond the second device 1000; and as an underfill to fill the gap between the bottom of the second device 1000 and the package.

[0043] After completing the installation of the second device 1000, as follows Figure 13 As shown, a second dielectric layer 1100 is pressed onto the side of the first dielectric layer 800 away from the first substrate 700, so that the second dielectric layer 1100 covers the second device 1000, and the second dielectric layer 1100 is cured. The second dielectric layer 1100 serves a protective and insulating function. Figure 14 As shown, a second blind via 1110 is formed by laser drilling into the second dielectric layer 1100. It should be noted that when the second blind via 1110 needs to connect to the second circuit 600, it passes through both the first dielectric layer 800 and the second dielectric layer 1100. When the second blind via 1110 needs to connect to the second device 1000, it only needs to pass through a portion of the second dielectric layer 1100. Figure 15 As shown, the second blind via 1110 is filled by electroplating, and a third line 1200 connected to the second blind via 1110 is formed at the bottom of the second dielectric layer 1100 to obtain the packaging substrate. Thus, the second metal surface 1020 of the second device 1000 and the first signal terminal 320 of the first device 300 can be fanned out through the second line 600 and the third line 1200, and the first metal surface 310 of the first device 300 and the second signal terminal 10250 of the second device 1000 can be fanned out through the first line 500 and the second line 600, thereby achieving double-sided fan-out of the device.

[0044] The device stacking double-sided fan-out embedded packaging method according to the embodiments of this application can achieve vertical stacking of devices without the need for soldering bumping, thereby reducing the packaging area. At the same time, it can achieve double-sided fan-out of stacked devices, increase interconnect density, reduce interconnect distance, and improve product performance.

[0045] Secondly, embodiments of this application also propose a device stacking double-sided fan-out embedded packaging substrate, including: a first substrate 700, a conductive barrier 610, a first dielectric layer 800, a conductive material 900, a second device 1000, a second dielectric layer 1100, and a third circuit 1200, such as Figure 8 As shown, a conductive post 120 and a first device 300 are disposed within a first substrate 700. A first line 500 and a second line 600, which are connected through the conductive post 120, are disposed on both sides of the first substrate 700. The first line 500 is connected to one side of the first device 300, and the second line 600 is connected to the other side of the first device 300. By providing the first line 500 on one side of the first substrate 700 and making the first line 500 connected to the first device 300, one side of the first device 300 can be fanned out; by providing the second line 600 on the other side of the first substrate 700 and making the second line 600 connected to the first device 300, the other side of the first device 300 can be fanned out. A conductive barrier 610 is disposed on the surface of the second circuit 600. The conductive barrier 610 can be a copper pillar barrier. The conductive barrier 610 can limit the downward pressing depth of the subsequent second device 1000 in terms of height, preventing short circuits between densely packed terminals due to excessive pressing of the second device 1000 causing horizontal expansion of the conductive material 900. Simultaneously, the conductive barrier 610 can confine the conductive material 900 within the conductive barrier 610, preventing ion migration of conductive ions during subsequent use. For example... Figure 10As shown, the first blind via 810 is located within the conductive enclosure 610 and is connected to the second circuit 600. By opening the first blind via 810, the second circuit 600 is exposed, facilitating communication between the second circuit 600 and the conductive material 900. Since the first blind via 810 is located within the conductive enclosure 610, the conductive material 900 can be confined within the conductive enclosure 610, preventing ion migration of conductive ions during subsequent use. The size of the first blind via 810 can be the same as or smaller than the inner diameter of the conductive enclosure 610. A first dielectric layer 800 is disposed on the side of the first substrate 700 where the second circuit 600 is located. The first dielectric layer 800 covers the second circuit 600 and the conductive enclosure 610. The first dielectric layer 800 has a first blind via 810, which is located within the conductive enclosure 610 and is connected to the second circuit 600. By setting the first dielectric layer 800, insulation and protection are achieved for the second circuit 600 and the conductive wall 610. The second circuit 600 is exposed by opening the first blind hole 810, facilitating communication between the second circuit 600 and the conductive material 900. Since the first blind hole 810 is located within the conductive wall 610, the conductive material 900 can be confined within the conductive wall 610, preventing ion migration during subsequent use. The size of the first blind hole 810 can be the same as or smaller than the inner diameter of the conductive wall 610. The conductive material 900 fills the first blind hole 810, such as... Figure 11 As shown, by filling the first blind hole 810 with conductive material 900, it is convenient to lead out the second line 600 and connect it to the subsequent second device 1000. Figure 12 As shown, the second device 1000 is located on the side of the first dielectric layer 800 away from the first substrate 700. The second device 1000 is conductive to the conductive material 900. Since the second device 1000 is conductive to the conductive material 900, and the conductive material 900 is conductive to the second line 600, the first line 500, the first device 300, the second line 600, the conductive material 900, and the second device 1000 are all interconnected. Figure 13 As shown, the second dielectric layer 1100 is disposed on the side of the first dielectric layer 800 away from the first substrate 700. The second dielectric layer 1100 covers the second device 1000. The second dielectric layer 1100 has a second blind via 1110, which communicates with the second circuit 600 and the second device 1000. The second blind via 1110 is filled by electroplating. The second dielectric layer 1100 covers the second device 1000 and serves to insulate and protect the second device 1000. Figure 14As shown, by providing a second blind via 1110, the second line 600 and the second device 1000 are exposed, facilitating the connection between the second line 600 and the second device 1000 and the subsequent third line 1200. Figure 15 As shown, by performing a hole-filling electroplating on the second blind hole 1110 to form a through hole, a third circuit 1200 is then fabricated at the bottom of the second dielectric layer 1100, enabling the third circuit 1200 to conduct through the through hole to the second circuit 1200 and the second device 1000. In this way, the first device 300 and the second device 1000 can be fanned out on both sides.

[0046] like Figure 4 As shown, a first metal surface 310 is provided on one side of the first device 300, and a first signal terminal 320 is provided on the other side of the first device 300. The first metal surface 310 can be used for both electrical connection and heat dissipation. When placing the first device 300 in the cavity 130, in order to initially fix the first device 300, as follows... Figure 3 As shown, a temporary bonding film 200 is first set on the second surface of the carrier plate 110, and then, as Figure 4 As shown, a first device 300 is placed inside the cavity 130, and a temporary bonding film 200 fixes the side of the first device 300 where the first signal terminal 320 is located; then, as... Figure 5 As shown, a third dielectric layer 400 is pressed onto the first surface of the carrier plate 110, thereby encapsulating the first device 300. The third dielectric layer 400 covers the first surface of the carrier plate 110 and fills the cavity 130; then, as... Figure 6 As shown, an opening is made in the third dielectric layer 400 to form a first blind via 410 communicating with one end of the conductive post 120 and one side of the first device 300. The first blind via 410 can be formed by laser drilling. Figure 7 As shown, after the fabrication of the first blind via 410 is completed, the temporary bonding film 200 can be removed. Figure 8 As shown, the first blind via 410 is filled with electroplating, and a first line 500 communicating with the first blind via 410 is formed on the surface of the third dielectric layer 400, so that the first line 500 can communicate with the conductive post 120 and the first metal surface 310 of the first device 300 through the filled and electroplated first blind via 410; as shown Figure 8As shown, a second circuit 600 is formed on the second surface of the carrier plate 110. The second circuit 600 is connected to the other end of the conductive post 120 and the other side of the first device 300. Thus, the first circuit 500 can be connected to the second circuit 600 through the first blind via 410 (after hole filling and plating) and the conductive post 120. The first metal surface 310 of the first device 300 can be brought out through the first circuit 500, and the first signal terminal 320 of the first device 300 can be brought out through the second circuit 600.

[0047] like Figure 12 As shown, in some embodiments of this application, a second metal surface 1010 is provided on one side of the second device 1000, and a second signal terminal 1020 is provided on the other side of the second device 1000. The second signal terminal 1020 of the active surface of the second device 1000 is aligned with the conductive material 900 and flip-chip bonded onto the first dielectric layer 800. Then, the first dielectric layer 800 and the conductive material 900 are cured, so that the conductive material 900 directly conducts electrically between the second device 1000 and the second circuit 600. The first dielectric layer 800 simultaneously plays three roles: as a permanent insulating layer of the packaging substrate to insulate the circuit, as an adhesive material for bonding the second device 1000, and as an underfill to fill the gap between the bottom of the second device 1000 and the package.

[0048] According to the embodiments of this application, the device stacking double-sided fan-out embedded packaging substrate can achieve vertical stacking of devices without the need for soldering bumping, thereby reducing the packaging area. At the same time, it can achieve double-sided fan-out of stacked devices, increase interconnect density, reduce interconnect distance, and improve product performance.

[0049] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method for double-sided fan-out embedded packaging of stacked devices, characterized in that, Includes the following steps: A first substrate is provided, wherein a conductive post and a first device are disposed therein, and a first line and a second line are disposed on both sides of the first substrate and connected through the conductive post, wherein the first line is connected to one side of the first device and the second line is connected to the other side of the first device. A conductive barrier is fabricated on the surface of the second circuit; A first dielectric layer is laminated on the side of the first substrate where the second circuit is disposed, and the first dielectric layer covers the second circuit and the conductive barrier; An opening is made in the first dielectric layer to form a first blind hole, the first blind hole being located within the conductive enclosure and connected to the second line; The first blind hole is filled with conductive material; A second device is placed on the side of the first dielectric layer away from the first substrate, and the second device is in contact with the conductive material; A second dielectric layer is laminated onto the side of the first dielectric layer away from the first substrate, and the second dielectric layer covers the second device; An opening is made in the second dielectric layer to form a second blind via that communicates with the second circuit and the second device; The second blind via is filled by electroplating, and a third line connected to the second blind via is formed at the bottom of the second dielectric layer to obtain a packaging substrate.

2. The device stacking double-sided fan-out embedded packaging method according to claim 1, characterized in that, The provision of the first substrate includes: A support plate is provided, wherein the support plate is provided with the guide post and the cavity; The first device is placed inside the cavity; A third dielectric layer is pressed onto the first surface of the carrier plate to encapsulate the first device. The third dielectric layer covers the first surface of the carrier plate and fills the cavity. An opening is made in the third dielectric layer to form a first blind via that communicates with one end of the conductive post and one side of the first device; The first blind via is filled by electroplating, and the first line that is connected to the first blind via is formed on the surface of the third dielectric layer. The second circuit is formed on the second surface of the carrier plate, and the second circuit is connected to the other end of the conductive post and the other side of the first device.

3. The device stacking double-sided fan-out embedded packaging method according to claim 2, characterized in that, The first device has a first metal surface on one side and a first signal terminal on the other side. Placing the first device within the cavity includes: A temporary bonding film is disposed on the second surface of the carrier plate; The first device is placed inside the cavity, and the temporary bonding film fixes the side of the first device that is provided with the first signal terminal. After the step of creating an opening in the third dielectric layer to form a first blind via communicating with one end of the conductive post and one side of the first device, the temporary bonding film is removed.

4. The device stacking double-sided fan-out embedded packaging method according to claim 2, characterized in that, The step of creating a conductive barrier on the surface of the second line includes: A protective dry film is attached to the surface of the first substrate; The protective dry film is exposed and developed to form a pattern corresponding to the conductive barrier. Electroplating is performed according to the described pattern to form the conductive enclosure; Remove the protective dry film.

5. The device stacking double-sided fan-out embedded packaging method according to claim 2, characterized in that, The conductive enclosure is circular in shape.

6. The device stacking double-sided fan-out embedded packaging method according to claim 2, characterized in that, The step of filling the first blind hole with conductive material includes: Conductive material is filled into the first blind hole by 3D printing, dispensing, or printing.

7. The device stacking double-sided fan-out embedded packaging method according to claim 1, characterized in that, The second device has a second metal surface on one side and a second signal terminal on the other side. Placing the second device on the side of the first dielectric layer away from the first substrate includes: A second device is placed on the side of the first dielectric layer away from the first substrate, and the second device is bonded through the first dielectric layer. The second signal terminal of the second device is connected to the conductive material. The first dielectric layer and the conductive material are thermally cured.

8. A device stacking double-sided fan-out embedded packaging substrate, characterized in that, include: A first substrate has a conductive post and a first device disposed therein. A first line and a second line are disposed on both sides of the first substrate and are connected through the conductive post. The first line is connected to one side of the first device and the second line is connected to the other side of the first device. A conductive barrier is installed on the surface of the second circuit; A first dielectric layer is disposed on the side of the first substrate where the second circuit is disposed. The first dielectric layer covers the second circuit and the conductive barrier. The first dielectric layer has a first blind via located inside the conductive barrier and is connected to the second circuit. Conductive material is used to fill the first blind hole; The second device is located on the side of the first dielectric layer away from the first substrate, and the second device is in contact with the conductive material; A second dielectric layer is disposed on the side of the first dielectric layer away from the first substrate. The second dielectric layer covers the second device. The second dielectric layer has a second blind via. The second blind via is connected to the second circuit and the second device. The second blind via is filled by via plating. The third line is disposed at the bottom of the second dielectric layer, and the third line is connected to the second blind via after the via filling electroplating.

9. The device stacking double-sided fan-out embedded packaging substrate according to claim 8, characterized in that, The first device has a first metal surface on one side and a first signal terminal on the other side.

10. The device stacking double-sided fan-out embedded packaging substrate according to claim 8, characterized in that, The second device has a second metal surface on one side and a second signal terminal on the other side.

Images