Semiconductor packaging

Abstract

This invention provides a semiconductor package comprising a first die, a first interconnect layer, and a packaging layer. The first die includes a first portion and a second portion, the first portion having a first surface and the second portion having a second surface. The first interconnect layer is disposed on the second surface. The packaging layer surrounds the first die and the first interconnect layer. In a cross-sectional view, the first portion has a first width at the first surface, and the second portion has a second width at the junction between the first portion and the second portion, and the second width is greater than the first width.

Description

Technical Field

[0001] This invention relates to electronic devices, and more particularly to electronic devices having semiconductor packages. Background Technology

[0002] Packaging technology can increase the integration density of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) in a given area, and has been widely used in the production of electronic devices in recent years. As semiconductor package sizes become smaller and smaller, the reliability requirements for chip manufacturing and packaging technologies are also becoming increasingly stringent.

[0003] Advanced 2.5D or 3D packaging technologies, employing stereolithography, can stack chips (dies) and then encapsulate them on a substrate, thereby reducing the area occupied by the chip, lowering costs, and reducing the power consumption of the driver chip. Semiconductor packaging has many interface integration structures (e.g., the interface between the die and the package layer, the interface between the insulating layer and the package layer, etc.). During the bonding process, dissimilar materials or flat interface structures are prone to stress concentration, leading to problems such as delamination, peeling, or cracking, which can affect the performance and reliability of semiconductor packaging.

[0004] As mentioned above, developing structural designs that can improve the reliability of semiconductor packaging (e.g., improve the stability or strength of the packaging structure) remains one of the topics that the industry is currently focusing on researching. Summary of the Invention

[0005] According to some embodiments of the present invention, a semiconductor package is provided, comprising a first die, a first interconnect layer, and a packaging layer. The first die includes a first portion and a second portion, the first portion having a first surface and the second portion having a second surface. The first interconnect layer is disposed on the second surface. The packaging layer surrounds the first die and the first interconnect layer. In a cross-sectional view, the first portion has a first width at the first surface, and the second portion has a second width at the junction between the first portion and the second portion, and the second width is greater than the first width. Attached Figure Description

[0006] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0007] Figure 1 This diagram shows a cross-sectional view of a semiconductor package according to some embodiments of the present invention.

[0008] Figure 2A This is illustrated in some embodiments of the present invention. Figure 1 A magnified structural diagram of region A1 in the diagram;

[0009] Figure 2B This is illustrated in some embodiments of the present invention. Figure 1 A magnified structural diagram of region A2 in the diagram;

[0010] Figure 2C This is illustrated in some embodiments of the present invention. Figure 1 A magnified structural diagram of region A3 in the diagram;

[0011] Figure 2D This is illustrated in some embodiments of the present invention. Figure 1 An enlarged structural diagram of region A4 in the diagram;

[0012] Figure 3 This diagram shows a cross-sectional view of a semiconductor package according to some embodiments of the present invention.

[0013] Figure 4 The diagram shows a cross-sectional structure of a semiconductor package according to some embodiments of the present invention.

[0014] Figure label:

[0015] 1: Semiconductor Packaging

[0016] 2: Semiconductor Packaging

[0017] 10: Semiconductor Packaging

[0018] 100: First die

[0019] 100D1: First side surface

[0020] 100D2: Second side surface

[0021] 100P1: Part 1

[0022] 100P2: Part Two

[0023] 100S1: First Surface

[0024] 100S2: Second Surface

[0025] 102: First Intranet Layer

[0026] 104: Insulation layer

[0027] 200: Second die

[0028] 200D: Side surface

[0029] 200S1: Surface

[0030] 200S2: Surface

[0031] 200V: Guide hole

[0032] 202: Second Intra-Connection Layer

[0033] 204: Circuit Layer

[0034] 206: Dielectric layer

[0035] 208: Conductive components

[0036] 210: Connecting components

[0037] 300: Structural core

[0038] 304: Insulation layer

[0039] 304D: Side surface

[0040] 400: Encapsulation layer

[0041] 400a: First sublayer

[0042] 400b: Second Sublayer

[0043] 402: Dummy contact pad

[0044] 404: First bonding layer

[0045] 406: Second bonding layer

[0046] 410: Composite structure

[0047] 410a: First silicon nitride layer

[0048] 410b: Silicon oxide layer

[0049] 410c: Second silicon nitride layer

[0050] 500: Third die

[0051] 510: Connecting components

[0052] 512: Insulation layer

[0053] 520: Encapsulation layer

[0054] 520V: Guide hole

[0055] 522: Connecting components

[0056] 600:Substrate

[0057] 600V: Guide hole

[0058] 602: Circuit Layer

[0059] 604: Contact pad

[0060] 606: Conductive Components

[0061] 612: Insulation layer

[0062] 700:Substrate

[0063] 700V: Guide hole

[0064] 702: Circuit Layer

[0065] 704: Contact pad

[0066] 706: Circuit Layer

[0067] 708: Connecting Components

[0068] 800: Fourth die

[0069] 802: Third Intranet Layer

[0070] 804: Circuit Layer

[0071] A1: Area

[0072] A2: Area

[0073] A3: Area

[0074] A4: Area

[0075] CF: Chamfer

[0076] DP1: Part 1

[0077] DP2: Part Two

[0078] Dx: Gap

[0079] E1: First end

[0080] E2: Second end

[0081] E3: Third end

[0082] E4: Fourth end

[0083] FP: Border

[0084] L1: Length

[0085] L2: Length

[0086] PT: Extended Profile

[0087] T104: Thickness

[0088] T304: Thickness

[0089] Ta: Thickness

[0090] Tb: Thickness

[0091] Tc: Thickness

[0092] W1: First width

[0093] W2: Second width

[0094] θ1: Angle Detailed Implementation

[0095] The following provides a detailed description of semiconductor packaging according to embodiments of the present invention. It should be understood that the following description provides many different embodiments for implementing various forms of some embodiments of the present invention. The specific components and arrangements described below are merely for simple and clear description of some embodiments of the present invention. Of course, these are merely examples and not limitations of the present invention. Furthermore, similar and / or corresponding reference numerals may be used in different embodiments to identify similar and / or corresponding components for clear description of the present invention. However, the use of these similar and / or corresponding reference numerals is only for simple and clear description of some embodiments of the present invention and does not imply any correlation between the different embodiments and / or structures discussed.

[0096] It should be understood that relative terms, such as "lower," "bottom," "higher," or "top," may be used in the embodiments to describe the relative relationship of one component of the figures to another. It is understood that if the apparatus in the figures is flipped upside down, the component described as being on the "lower" side will become the component on the "higher" side. Embodiments of the present invention may be used in conjunction with the accompanying drawings. Figure 1 It should be understood that the accompanying drawings of this invention are also considered part of the description of the invention. It should be understood that the drawings of this invention are not drawn to scale; in fact, the dimensions of components may be arbitrarily enlarged or reduced to clearly illustrate the features of the invention.

[0097] Furthermore, when it is mentioned that a first material layer is located on or above a second material layer, it may include situations where the first material layer and the second material layer are in direct contact, or situations where the first material layer and the second material layer are not in direct contact, that is, situations where there may be one or more other material layers between the first material layer and the second material layer. However, if the first material layer is located directly on the second material layer, it indicates that the first material layer and the second material layer are in direct contact.

[0098] Furthermore, it should be understood that the ordinal numbers used in the specification and claims, such as "first," "second," etc., to modify components, do not in themselves imply any prior ordinal number for that (or the plurality of) components, nor do they represent the order of one component with another, or the order of manufacturing methods. The use of these ordinal numbers is solely to clearly distinguish one component with a certain name from another component with the same name. The claims and specification may not use the same terminology; for example, the first component in the specification may be the second component in the claims.

[0099] In some embodiments of the present invention, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding joining and connecting may also include cases where both structures are movable or both structures are fixed. In addition, the terms "electrical connection" or "coupling" include any direct and indirect electrical connection means.

[0100] In this text, the terms "approximately," "substantially," and "roughly" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The phrase "the range is between the first and second values" indicates that the range includes the first value, the second value, and other values ​​in between. Furthermore, any two values ​​or directions used for comparison may have a certain degree of error. If the first value equals the second value, it implies an approximately 10% error between them; if the first direction is perpendicular to the second direction, the angle between them may be between 80 and 100 degrees; if the first direction is parallel to the second direction, the angle may be between 0 and 10 degrees.

[0101] According to embodiments of the present invention, the width, thickness, or height of each component, and the spacing or distance between components, can be measured using a scanning electron microscope (SEM), an optical microscope (OM), an alpha-step thickness gauge, an ellipsometry, or other suitable methods. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional image containing the components to be measured, and the width, thickness, or height of each component, and the spacing or distance between components, can be measured.

[0102] It should be understood that the features described below can be replaced, reorganized, or combined in several different embodiments to complete other embodiments without departing from the spirit of the invention. Features between embodiments can be arbitrarily combined and used as long as they do not violate the spirit of the invention or conflict with it.

[0103] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this invention.

[0104] According to embodiments of the present invention, a semiconductor package is provided, which includes a specific structural design that can mitigate excessive stress concentration at the interface between different layers during bonding processes (e.g., during reflow soldering), reduce problems such as delamination, peeling, or component breakage at the interface, thereby improving the structural strength or reliability of the semiconductor package.

[0105] According to embodiments of the present invention, the provided semiconductor package can be applied, for example, to wafer-level package (WLP) or panel-level package (PLP) processes, and can employ a chip-first process or a chip-last / RDL-first process. Furthermore, according to embodiments of the present invention, the semiconductor package may include a system-on-chip (SoC), a system-in-package (SiP), a chip-on-wafer-on-substrate (CoWoS) package, a system-on-integrated-chip (SoIC), an antenna-in-package (AiP), a co-packaged optical component (CPO), a microelectromechanical system (MEMS), or a combination thereof, but is not limited thereto.

[0106] Please refer to Figure 1 , Figure 1 The figures show a cross-sectional view of a semiconductor package 10 according to some embodiments of the present invention. It should be understood that, for clarity, some components of the semiconductor package 10 may be omitted from the figures, and only some components are schematically shown. According to some embodiments, additional features may be added to the semiconductor package 10 described below. According to other embodiments, some features of the semiconductor package 10 described below may be replaced or omitted.

[0107] like Figure 1 As shown, the semiconductor package 10 may include a first die 100, a first interconnect layer 102, and a package layer 400. The first die 100 may be disposed on the first interconnect layer 102, and the package layer 400 may surround the first die 100 and the first interconnect layer 102.

[0108] The first die 100 may include a first portion 100P1 and a second portion 100P2, the first portion 100P1 having a first surface 100S1 and the second portion 100P2 having a second surface 100S2. The first surface 100S1 may be relative to the second surface 100S2. According to some embodiments, the second surface 100S2 is closer to the first inline layer 102 than the first surface 100S1. Furthermore, the second surface 100S2 may be the active surface of the first die 100, which may include a plurality of active components.

[0109] For more details, please refer to the following: Figure 1 as well as Figure 2A , Figure 2A This is illustrated in some embodiments of the present invention. Figure 1 An enlarged structural schematic diagram of region A1 is shown. In a cross-sectional view, the first portion 100P1 has a first width W1 at the first surface 100S1, and the second portion 100P2 has a second width W2 at the junction FP between the first portion 100P1 and the second portion 100P2, and the second width W2 is greater than the first width W1. Further, according to some embodiments, the difference DX between the first width W1 and the second width W2 of the first die 100 can be between 0.1 μm and 1 μm (i.e., 0.1 μm ≤ difference DX ≤ 1 μm), for example, it can be 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, or 0.9 μm. Moreover, according to some embodiments, the thickness T1 of the first portion 100P1 of the first die 100 is greater than the thickness T2 of the second portion 100P2. The aforementioned thickness T1 refers to the maximum thickness of the first portion 100P1 in the normal direction of the first die 100 (e.g., the Z direction in the figure); the thickness T2 refers to the maximum thickness of the second portion 100P2 in the normal direction of the first die 100 (e.g., the Z direction in the figure).

[0110] It is worth noting that, with the aforementioned configuration, the interface between the first die 100 and the encapsulation layer 400 can be located away from the body of the first die 100 in the direction toward the first inline layer 102, which can guide stress away from the first inline layer 102 and reduce the risk of interface delamination, peeling or cracking extending to the first inline layer 102.

[0111] In addition, such as Figure 2AAs shown, according to some embodiments, a first portion 100P1 of the first die 100 has a first side surface 100D1, and a second portion 100P2 of the first die 100 has a second side surface 100D2, with the first side surface 100D1 and the second side surface 100D2 disposed between the first surface 100S1 and the second surface 100S2. According to some embodiments, the roughness of the first side surface 100D1 is greater than the roughness of the second side surface 100D2. According to embodiments of the present invention, roughness can be determined using a scanning electron microscope (SEM) or a transmission electron microscope (TEM) to observe the surface undulations at an appropriate magnification. The surface undulations are compared per unit length (e.g., 1 μm). Here, "appropriate magnification" means that at least one surface can have at least five undulation peaks and valleys observed at this magnification.

[0112] Furthermore, according to some embodiments, in a thickness direction (or in the normal direction of the first die 100, such as the Z direction in the figures), the length L1 of the first side surface 100D1 is greater than the length L2 of the second side surface 100D2. According to some embodiments, the length L1 of the first side surface 100D1 may be between 3 micrometers and 100 micrometers (i.e., 3 μm ≤ length L1 ≤ 100 μm), or between 3 micrometers and 50 micrometers, for example, 6 micrometers, 10 micrometers, 15 micrometers, 20 micrometers, 25 micrometers, 30 micrometers, 35 micrometers, 40 micrometers, or 45 micrometers. According to some embodiments, the length L2 of the second side surface 100D2 may be between 0.1 micrometers and 1 micrometer (i.e., 0.1 μm ≤ length L2 ≤ 1 μm), for example, 0.2 micrometers, 0.3 micrometers, 0.4 micrometers, 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, or 0.9 micrometers. According to some embodiments, in a cross-sectional view, the first side surface 100D1 has a first end E1 located at the first surface 100S1 and a second end E2 located at the junction FP between the first side surface 100D1 and the second side surface 100D2, and the first end E1 is recessed inward relative to the second end E2.

[0113] As mentioned above, the interface between the first die 100 and the encapsulation layer 400 (e.g., the first side surface 100D1) is located away from the body of the first die 100 in the direction toward the first inline layer 102, thereby directing stress away from the first inline layer 102 and thus reducing the risk of interface delamination, peeling or cracking extending to the first inline layer 102.

[0114] According to some embodiments, the first die 100 may include a known-good die (KGD), an integrated circuit chip (IC), or other suitable electronic components, but is not limited thereto. According to some embodiments, the first die 100 may be an auxiliary chip. Specifically, according to some embodiments, the first die 100 may include a system-on-a-chip (SoC), dynamic random access memory (DRAM), high-bandwidth memory, photonic integrated circuit, application-specific integrated circuit (ASIC), active component, passive component, power management system chip, or other logic integrated circuit, but is not limited thereto.

[0115] Please continue to refer to Figure 1 as well as Figure 2A The first interconnect layer 102 may be disposed on the second surface 100S2 of the second portion 100P2 of the first die 100. The first interconnect layer 102 may be electrically connected to the first die 100. According to some embodiments, the first interconnect layer 102 may include the relevant circuit lines and signal lines required by the first die 100.

[0116] The first interconnect layer 102 may have one or more dielectric layers and patterned conductive layers. According to some embodiments, the dielectric layer of the first interconnect layer 102 may comprise a polymer dielectric insulating material, such as polystyrene-butadiene polymer (PSP). Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), other suitable polymeric dielectric materials, or combinations thereof, but not limited thereto, may be used. According to other embodiments, the dielectric layer of the first inline layer 102 may comprise silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), other suitable dielectric materials, or combinations thereof, but not limited thereto. According to some embodiments, the material of the patterned conductive layer of the first inline layer 102 may comprise copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), gold (Au), tin (Sn), molybdenum (Mo), chromium (Cr), nickel (Ni), platinum (Pt), palladium (Pd), alloys of the aforementioned metals, other suitable conductive materials, or combinations thereof, but not limited thereto.

[0117] As described above, the encapsulation layer 400 may surround the first die 100 and the first interconnect layer 102. According to some embodiments, the encapsulation layer 400 may have a multi-layer structure, for example, it may include a first sub-layer 400a and a second sub-layer 400b, the second sub-layer 400b being disposed between the first die 100 and the first sub-layer 400a, and between the first interconnect layer 102 and the first sub-layer 400a. According to some embodiments, the encapsulation layer 400 may contact the first die 100 and the first interconnect layer 102, for example, the second sub-layer 400b may contact the first die 100 and the first interconnect layer 102. The encapsulation layer 400 may reduce the impact of water and oxygen from the external environment on the first die 100 and the first interconnect layer 102, reduce impact damage to the first die 100 and the first interconnect layer 102, improve the mechanical stability of the structure, or provide a heat dissipation path.

[0118] According to some embodiments, the materials of the first sublayer 400a and the second sublayer 400b of the encapsulation layer 400 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicon glass (USG), and polybenzo[a]bis(hydroxyl) silicate glass. Polybenzoxazole (PBO), benzocyclobutene (BCB), other suitable encapsulation materials, or combinations thereof, but not limited thereto, may be used. The first sublayer 400a and the second sublayer 400b of the encapsulation layer 400 may be formed of different materials. According to some embodiments, the first sublayer 400a may comprise silicon oxide, and the second sublayer 400b may comprise silicon nitride.

[0119] Please continue to refer to Figure 1The semiconductor package 10 may further include a second die 200 and a structural die 300. A first die 100 may be disposed on the second die 200, and the structural die 300 may be disposed on the second die 200 and adjacent to the first die 100. The first die 100 and the second die 200 are electrically connected, and the structural die 300 is electrically insulated from the second die 200. According to some embodiments, a package layer 400 may surround the second die 200 and the structural die 300. According to some embodiments, the package layer 400 may be disposed between the second die 200 and the structural die 300, or between the second die 200 and the first die 100. According to some embodiments, the package layer 400 may contact the first die 100, the second die 200, and the structural die 300.

[0120] According to some embodiments, the size of the second die 200 may be larger than the size of the first die 100 and the structural die 300. According to some embodiments, the second die 200 may overlap with the first die 100 and the structural die 300 in the normal direction (e.g., the Z direction in the figures). For example, one second die 200 may overlap with one first die 100 and two structural dies 300, but is not limited thereto. It should be understood that the number of the first die 100, the second die 200, and the structural die 300 is not limited to those shown in the figures. According to other embodiments, the semiconductor package 10 may have other suitable configurations of the first die 100, the second die 200, and the structural die 300.

[0121] According to some embodiments, the second die 200 may include a known-good die (KGD), an integrated circuit chip (IC), or other suitable electronic components, but is not limited thereto. According to some embodiments, the second die 200 may be an arithmetic chip, such as a central processing unit (CPU), a graphics processing unit (GPU), or other digital logic circuits, but is not limited thereto.

[0122] According to some embodiments, the structural die 300 may serve as a dummy die, not electrically connected to other components, but rather providing structural support and a heat dissipation path. According to some embodiments, the structural die 300 may be disposed on both sides of the first die 100. According to some embodiments, the structural die 300 may comprise bulk semiconductor, glass, sapphire, ceramic, or other suitable materials, but is not limited thereto.

[0123] Please refer to Figure 1 as well as Figure 2B , Figure 2B This is illustrated in some embodiments of the present invention. Figure 1 An enlarged structural schematic diagram of region A2 is shown. According to some embodiments, the semiconductor package 10 may further include an insulating layer 304, which may be disposed between the structural die 300 and the second die 200, and the package layer 400 contacts the side surface 304D of the insulating layer 304. According to some embodiments, the package layer 400 may surround the structural die 300 and the insulating layer 304. Specifically, the second sublayer 400b of the package layer 400 may contact the side surface 304D of the insulating layer 304. According to some embodiments, in a cross-sectional view, the side surface 304D of the insulating layer 304 includes a third end E3 in contact with the structural die 300 and a fourth end E4 away from the third end E3, and the fourth end E4 is recessed inward relative to the third end E3. Furthermore, according to some embodiments, the side surface 304D of the insulating layer 304 includes a first portion DP1 connected to the third end E3 and a second portion DP2 connected to the fourth end E4, and the second portion DP2 forms an angle θ1 relative to the first portion DP1. According to some embodiments, the angle θ1 may be between 1 degree and 45 degrees, for example, 5 degrees, 10 degrees, 15 degrees, 20 degrees, 25 degrees, 30 degrees, 35 degrees or 40 degrees.

[0124] In other words, the side surface 304D of the insulating layer 304 has at least one inwardly curved profile. It is worth noting that the interface (e.g., side surface 304D) between the insulating layer 304 and the encapsulation layer 400 is recessed inward and has a curved profile, which can reduce excessive stress concentration at the interface and thus reduce the risk of interface delamination, peeling or cracking.

[0125] According to some embodiments, the material of the insulating layer 304 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, other suitable insulating materials, or combinations thereof, but is not limited thereto.

[0126] Please refer to this again. Figure 1 According to some embodiments, the semiconductor package 10 may further include a second interconnect layer 202, which may be electrically connected to the second die 200. According to some embodiments, the second interconnect layer 202 may include the necessary circuitry and signal lines required by the second die 200. The second die 200 may have a surface 200S1 adjacent to the first die 100 and a surface 200S2 away from the first die 100. Surface 200S2 may be the active surface of the second die 200, which may include multiple active components. The second interconnect layer 202 may be disposed on the surface 200S2 of the second die 200 away from the first die 100, and the first interconnect layer 102 may be electrically connected to the second interconnect layer 202 via a via 200V in the second die 200. Furthermore, according to some embodiments, the package layer 400 may surround the second die 200 and the second interconnect layer 202.

[0127] The second interconnect layer 202 may have one or more dielectric layers and patterned conductive layers. According to some embodiments, the dielectric layer of the second interconnect layer 202 may comprise a polymer dielectric insulating material, such as polystyrene-butadiene polymer (PSP). Polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), other suitable polymeric dielectric materials, or combinations thereof, but not limited thereto, may be used. According to other embodiments, the dielectric layer of the second inline layer 202 may comprise silicon nitride, silicon oxide, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), other suitable dielectric materials, or combinations thereof, but not limited thereto. According to some embodiments, the material of the patterned conductive layer of the second inline layer 202 may comprise copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), gold (Au), tin (Sn), molybdenum (Mo), chromium (Cr), nickel (Ni), platinum (Pt), palladium (Pd), alloys of the aforementioned metals, other suitable conductive materials, or combinations thereof, but not limited thereto.

[0128] According to some embodiments, the semiconductor package 10 may further include a first bonding layer 404 and a second bonding layer 406. The first bonding layer 404 may be disposed on the first interconnect layer 102, and the second bonding layer 406 may be disposed on the surface 200S1 of the second die 200 adjacent to the first die 100, with the first bonding layer 404 directly bonded to the second bonding layer 406. According to some embodiments, the first interconnect layer 102 may be electrically connected to a via 200V in the second die 200 via the first bonding layer 404 and the second bonding layer 406, thereby being electrically connected to the second interconnect layer 202. According to some embodiments, the first die 100 and the second die 200 may be bonded via the first bonding layer 404 and the second bonding layer 406, for example, via a hybrid bonding process.

[0129] The first bonding layer 404 and the second bonding layer 406 may comprise a metallic material. According to some embodiments, the metallic material may comprise copper (Cu), gold (Au), nickel (Ni), silver (Ag), titanium (Ti), aluminum (Al), alloys of the aforementioned metals, other suitable metallic materials, or combinations thereof, but is not limited thereto.

[0130] Furthermore, according to some embodiments, the semiconductor package 10 may further include an insulating layer 104, which may be disposed between the first die 100 and the second die 200, and the first bonding layer 404 may penetrate the insulating layer 104. According to some embodiments, the package layer 400 may surround the insulating layer 104, and the insulating layer 104 may contact the package layer 400, for example, the insulating layer 104 may contact the second sublayer 400b of the package layer 400. According to some embodiments, the thickness T104 of the insulating layer 104 may be less than the thickness T304 of the insulating layer 304. The aforementioned thickness T104 refers to the maximum thickness of the insulating layer 104 in the normal direction of the first die 100 (e.g., the Z direction in the figures); the thickness T304 refers to the maximum thickness of the insulating layer 304 in the normal direction of the structural die 300 (e.g., the Z direction in the figures).

[0131] According to some embodiments, the material of the insulating layer 104 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, other suitable insulating materials, or combinations thereof, but is not limited thereto.

[0132] Next, please refer to Figure 1 as well as Figure 2C , Figure 2C This is illustrated in some embodiments of the present invention. Figure 1 An enlarged structural schematic diagram of region A3 is shown. According to some embodiments, the second die 200 includes a surface 200S1 and a side surface 200D adjacent to the first die 100, and a chamfer CF is formed between the surface 200S1 and the side surface 200D. According to some embodiments, in a cross-sectional view, the chamfer CF includes an arcuate edge. According to some embodiments, the second sub-layer 400b of the encapsulation layer 400 may contact the surface 200S1, the side surface 200D, and the chamfer CF of the second die 200. According to some embodiments, the thickness of the encapsulation layer 400 (second sub-layer 400b) in contact with the chamfer CF is different from the thickness of the encapsulation layer 400 (second sub-layer 400b) in contact with the surface 200S1, and the thickness of the encapsulation layer 400 (second sub-layer 400b) in contact with the chamfer CF is also different from the thickness of the encapsulation layer 400 (second sub-layer 400b) in contact with the side surface 200D. According to some embodiments, the thickness of the second sublayer 400b in contact with the chamfer CF is less than the thickness of the second sublayer 400b in contact with the surface 200S1. According to some embodiments, the thickness of the second sublayer 400b in contact with the chamfer CF is less than the thickness of the second sublayer 400b in contact with the side surface 200D. Furthermore, according to some embodiments, the second sublayer 400b adjacent to the chamfer CF but not in contact with the second die 200 has an extended profile PT, which comprises silicon nitride to enhance protection for the second die 200, such as blocking moisture.

[0133] It is worth noting that, thanks to the aforementioned chamfered CF configuration, the interface between the second die 200 and the encapsulation layer 400 has an arc-shaped chamfer, which can reduce excessive stress concentration at this location and thus reduce the risk of interface delamination, peeling, or cracking.

[0134] Next, please refer to Figure 1 as well as Figure 2D , Figure 2D This is illustrated in some embodiments of the present invention. Figure 1 An enlarged structural schematic diagram of region A4 is shown. According to some embodiments, the semiconductor package 10 may further include a composite structure 410, which may be disposed between the second die 200 and the combination of the first die 100 and the structural die 300. That is, the composite structure 410 may be disposed between the second die 200 and the first die 100, and the composite structure 410 may also be disposed between the second die 200 and the structural die 300. According to some embodiments, the composite structure 410 may include a first silicon nitride layer 410a, a silicon oxide layer 410b, and a second silicon nitride layer 410c, with the second silicon nitride layer 410c being closer to the second die 200 than the first silicon nitride layer 410a. The silicon oxide layer 410b may be sandwiched between the first silicon nitride layer 410a and the second silicon nitride layer 410c. According to some embodiments, the first silicon nitride layer 410a may contact the second sublayer 400b of the encapsulation layer 400, and the first silicon nitride layer 410a may also contact the insulating layer 104 and the insulating layer 304.

[0135] It is worth noting that the silicon oxide layer 410b can be a compressive stress layer, while the first silicon nitride layer 410a and the second silicon nitride layer 410c can be tensile stress layers. Therefore, the composite structure 410 can balance the tensile and compressive stresses and reduce the risk of interface delamination, peeling, or warpage.

[0136] According to some embodiments, the thickness Tb of the silicon oxide layer 410b is greater than the thickness Ta of the first silicon nitride layer 410a and greater than the thickness Tc of the second silicon nitride layer 410c. According to some embodiments, the thickness Ta of the first silicon nitride layer 410a is greater than the thickness Tc of the second silicon nitride layer 410c. More specifically, according to some embodiments, the thickness Ta of the first silicon nitride layer 410a may be between 0.1 μm and 0.5 μm (i.e., 0.1 μm ≤ thickness Ta ≤ 0.5 μm), for example, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, or 0.45 μm. According to some embodiments, the thickness Tb of the silicon oxide layer 410b can be between 0.4 μm and 1 μm (i.e., 0.4 μm ≤ thickness Tb ≤ 1 μm), for example, 0.45 μm, 0.5 μm, 0.55 μm, 0.6 μm, 0.65 μm, 0.7 μm, 0.75 μm, 0.8 μm, 0.85 μm, 0.9 μm, or 0.95 μm. According to some embodiments, the thickness Tc of the second silicon nitride layer 410c can be between 0.02 μm and 0.15 μm (i.e., 0.02 μm ≤ thickness Tc ≤ 0.15 μm), for example, 0.03 μm, 0.04 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.11 μm, 0.12 μm, 0.13 μm, or 0.14 μm.

[0137] The aforementioned thickness Ta refers to the maximum thickness of the first silicon nitride layer 410a in the normal direction of the first die 100 (e.g., the Z direction in the figure); the thickness Tb refers to the maximum thickness of the silicon oxide layer 410b in the normal direction of the first die 100 (e.g., the Z direction in the figure); and the thickness Tc refers to the maximum thickness of the second silicon nitride layer 410c in the normal direction of the first die 100 (e.g., the Z direction in the figure).

[0138] In addition, such as Figure 1 as well as Figure 2DAs shown, according to some embodiments, the semiconductor package 10 may further include a dummy contact pad 402, which may be disposed between the package layer 400 and the second die 200, and the package layer 400 may be disposed between the first die 100 and the structural die 300. According to some embodiments, the dummy contact pad 402 may overlap with the package layer 400 and the second die 200 in the normal direction of the second die 200 (e.g., the Z direction in the figures). According to some embodiments, the dummy contact pad 402 may contact the second sublayer 400b of the package layer 400, the first silicon nitride layer 410a of the composite structure 410, and the silicon oxide layer 410b. According to some embodiments, the dummy contact pad 402 may penetrate the first silicon nitride layer 410a and extend into the silicon oxide layer 410b, but does not contact the second silicon nitride layer 410c.

[0139] It is worth noting that when the first die 100 and the second die 200 are pressed against each other during the packaging process, or when the structural die 300 and the second die 200 are pressed against each other, the configuration of the dummy contact pad 402 can balance the pressure in areas without dies, reducing the risk of damage or destruction to the structure caused by the packaging process.

[0140] According to some embodiments, the material of the dummy contact pad 402 may include a conductive material, such as a metallic conductive material. According to some embodiments, the dummy contact pad 402 may include copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), gold (Au), tin (Sn), molybdenum (Mo), chromium (Cr), nickel (Ni), platinum (Pt), palladium (Pd), alloys of the aforementioned metals, other suitable conductive materials, or combinations thereof, but is not limited thereto.

[0141] Please refer to this again. Figure 1 According to some embodiments, the semiconductor package 10 may further include a circuit layer 204, a dielectric layer 206, a conductive component 208, and a connection component 210. The circuit layer 204 may be disposed on the second interconnect layer 202 and between the dielectric layer 206 and the second interconnect layer 202. The conductive component 208 may be disposed on the circuit layer 204 and electrically connected to conductive components (not shown) in the circuit layer 204. Furthermore, the conductive component 208 may penetrate the dielectric layer 206 and be electrically connected to the connection component 210. The connection component 210 may be disposed corresponding to the conductive component 208. That is, in the normal direction of the second die 200 (e.g., the Z direction in the figures), the connection component 210 may overlap with the conductive component 208. According to some embodiments, the connection component 210 may be further electrically connected to other external electronic components.

[0142] According to some embodiments, circuit layer 204 may have one or more layers and may include one or more dielectric layers and patterned conductive layers. According to some embodiments, circuit layer 204 may serve as a redistribution layer (RDL). According to some embodiments, the dielectric layer of circuit layer 204 may be made of an organic dielectric material, such as polystyrene-bismuth substructure. Polybenzoxazole (PBO), perfluoroalkoxy alkane (PFA), polytetrafluoroethylene (PTFE), fluorinated ethylenepropylene (FEP), Ajinomoto build-up film (ABF), flame-retardant glass fiber (FR4), glass fiber resin composites, polyimide, benzocyclobutene (BCB), epoxy resin, other suitable dielectric materials, or combinations thereof, but not limited thereto. According to some embodiments, the material of the patterned conductive layer of circuit layer 204 may include copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), gold (Au), tin (Sn), molybdenum (Mo), chromium (Cr), nickel (Ni), platinum (Pt), palladium (Pd), alloys of the aforementioned metals, other suitable conductive materials, or combinations thereof, but not limited thereto.

[0143] According to some embodiments, the material of dielectric layer 206 may comprise inorganic materials, organic materials, or combinations thereof, but is not limited thereto. According to some embodiments, the inorganic material may comprise silicon nitride, silicon oxide, silicon oxynitride, other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the organic material may comprise polyimide (PI), photosensitive polyimide (PSPI), polybenzo[a]bis(2,3-di ... Polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, ABF (Ajinomoto Build-up Film) build-up material, other suitable materials, or combinations thereof, but not limited thereto.

[0144] According to some embodiments, the conductive material of the conductive component 208 may include copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), gold (Au), tin (Sn), molybdenum (Mo), chromium (Cr), nickel (Ni), platinum (Pt), tantalum (Ta), ruthenium (Ru), alloys of the aforementioned metals, other suitable conductive materials, or combinations thereof, but is not limited thereto.

[0145] According to some embodiments, the material of the connection component 210 may include tin, silver, lead-free tin, copper, nickel, gold, other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the connection component 210 may be bonded to various substrates by means of reflow soldering, fusion bonding, hybrid bonding, metal-to-metal bonding, other suitable methods, or combinations thereof.

[0146] Next, please refer to Figure 3 , Figure 3 The accompanying drawings show a cross-sectional view of the semiconductor package 1 according to other embodiments of the present invention. It should be understood that, for clarity, some components of the semiconductor package 1 may be omitted from the drawings, and only some components are schematically shown. According to some embodiments, additional features may be added to the semiconductor package 1 described below. Furthermore, components that are the same as or similar to those described above will be indicated by the same or similar reference numerals, and their materials and functions are the same as or similar to those described above; therefore, this part will not be repeated hereafter.

[0147] Specifically, semiconductor package 1 can be formed based on the structure of the aforementioned semiconductor package 10 and combined with a suitable package combination. For example, semiconductor package 1 can be applied to a package structure similar to chip on wafer on substrate (CoWoS).

[0148] like Figure 3 As shown, the semiconductor package 1 has the structure of the semiconductor package 10, and may further include a third die 500. The third die 500 may be disposed adjacent to the semiconductor package 10, and may be disposed together with the semiconductor package 10 on the substrate 600. In detail, the semiconductor package 1 may further include a connection component 510 and an insulating layer 512. The third die 500 may be electrically connected to a conductive component (not shown) on the substrate 600 via the connection component 510. The insulating layer 512 may surround the third die 500 and the semiconductor package 10, and the insulating layer 512 may be disposed between the third die 500 and the substrate 600 and between the semiconductor package 10 and the substrate 600.

[0149] The third die 500 may include, but is not limited to, a known-good die (KGD), an integrated circuit chip (IC), or other suitable electronic components. According to some embodiments, the third die 500 may be an auxiliary chip or a control chip. Specifically, according to some embodiments, the third die 500 may include a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), dynamic random access memory, high-bandwidth memory, photonic integrated circuits, active components, passive components, a power management system chip, or other logic integrated circuits, but is not limited to these. Furthermore, the type of the third die 500 may be the same as or different from the first die 100.

[0150] According to some embodiments, the material of the connection component 510 may include tin, silver, lead-free tin, copper, nickel, gold, other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the connection component 510 may be bonded to the substrate 600 by means of a reflow process, a fusion bonding process, a hybrid bonding process, a metal-to-metal bonding process, other suitable methods, or combinations thereof.

[0151] According to some embodiments, the insulating layer 512 may be an encapsulation material or an underfill, but is not limited thereto. According to some embodiments, the insulating layer 512 may comprise a molding compound, epoxy resin, other suitable encapsulation materials, or combinations thereof, but is not limited thereto. Furthermore, the insulating layer 512 may comprise filler particles, such as silicon oxide, aluminum oxide, titanium oxide, zirconium oxide, silicon carbide, graphene, carbon nanotubes, combinations thereof, or other suitable materials, but is not limited thereto.

[0152] Furthermore, the semiconductor package 1 may further include a substrate 600, a circuit layer 602, a contact pad 604, a conductive component 606, and an insulating layer 612. The circuit layer 602 may be disposed on the substrate 600, and the substrate 600 may be disposed between the semiconductor package 10 and the circuit layer 602, or between the third die 500 and the circuit layer 602. The contact pad 604 may be disposed between the circuit layer 602 and the conductive component 606. The conductive component 606 may be disposed corresponding to the contact pad 604. That is, in the normal direction of the substrate 600 (e.g., the Z direction in the figures), the conductive component 606 may overlap with the contact pad 604.

[0153] The third die 500 can be electrically connected to a conductive component (not shown) on the substrate 600 via the connection component 510. The first die 100 and the second die 200 in the semiconductor package 1 can also be electrically connected to a conductive component (not shown) on the substrate 600 via the connection component 210. Furthermore, the substrate 600 has a via 600V, through which the third die 500 and the first die 100 and the second die 200 in the semiconductor package 1 can be further electrically connected to the circuit layer 602, and the contact pad 604 and the conductive component 606 can be electrically connected to the circuit layer 602.

[0154] The substrate 600 can serve as an interposer. According to some embodiments, the substrate 600 may comprise silicon wafers, quartz, glass, sapphire, ceramic, but is not limited thereto. According to some embodiments, the substrate 600 may be glass and have a via 600V, i.e., a through-glass via (TGV) structure.

[0155] According to some embodiments, circuit layer 602 may have one or more layers and may include one or more dielectric layers and patterned conductive layers. According to some embodiments, circuit layer 602 may serve as a redistribution layer (RDL). The materials of the dielectric layer and patterned conductive layer of circuit layer 602 may be the same as or similar to those of the aforementioned circuit layer 204, and will not be repeated here.

[0156] According to some embodiments, contact pad 604 may comprise a conductive material, such as a metallic conductive material. According to some embodiments, contact pad 604 may comprise copper (Cu), titanium (Ti), aluminum (Al), tungsten (W), silver (Ag), gold (Au), tin (Sn), molybdenum (Mo), chromium (Cr), nickel (Ni), platinum (Pt), palladium (Pd), alloys of the aforementioned metals, other suitable conductive materials, or combinations thereof, but is not limited thereto.

[0157] According to some embodiments, the material of the conductive component 606 may include tin, silver, lead-free tin, copper, nickel, gold, other suitable materials, or combinations thereof, but is not limited thereto.

[0158] According to some embodiments, the material of the insulating layer 612 may be the same as or similar to that of the aforementioned insulating layer 512, and will not be repeated here.

[0159] In addition, such as Figure 3As shown, the semiconductor package 1 may further include a substrate 700, a circuit layer 702, a contact pad 704, a circuit layer 706, and a connection component 708. The substrate 700 and substrate 600 may be disposed on opposite sides of the conductive component 606. The circuit layer 702 may be disposed between the conductive component 606 and the substrate 600, and the circuit layer 702 may be electrically connected to the conductive component 606 via the contact pad 704. The conductive component 606 may be disposed corresponding to the contact pad 704. That is, in the normal direction of the substrate 600 (e.g., the Z direction in the figure), the conductive component 606 may overlap with the contact pad 704. The circuit layers 702 and 706 may be disposed on opposite sides of the substrate 700, and the circuit layer 702 may be electrically connected to the circuit layer 706 via a via 700V in the substrate 700. The connection component 708 may be disposed on the circuit layer 706, the circuit layer 706 may be electrically connected to the connection component 708, and the connection component 708 may be further electrically connected to other external electronic components.

[0160] According to some embodiments, the material of substrate 700 may include silicon wafer, quartz, glass, sapphire, ceramic, but is not limited thereto. According to some embodiments, substrate 700 may be glass and have a via 700V, that is, it has a through-glass via (TGV) structure.

[0161] Circuit layers 702 and 706 may have one or more layers and may include one or more dielectric layers and patterned conductive layers. According to some embodiments, circuit layers 702 and 706 may serve as redistribution layers (RDLs). The materials of the dielectric layers and patterned conductive layers of circuit layers 702 and 706 may be the same as or similar to those of the aforementioned circuit layer 204, and will not be repeated here.

[0162] According to some embodiments, the material of contact pad 704 may be the same as or similar to that of the aforementioned contact pad 604, and will not be repeated here.

[0163] According to some embodiments, the material of the connection component 708 may include tin, silver, lead-free tin, copper, nickel, gold, other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the connection component 708 may be further bonded to other external electronic components by means of reflow soldering processes, fusion bonding processes, hybrid bonding processes, metal-to-metal bonding processes, other suitable methods, or combinations thereof. For example, the connection component 708 may be further electrically connected to a printed circuit board (PCB), a chip, a control component, or other electronic components (not shown), but the invention is not limited thereto.

[0164] Next, please refer to Figure 4 , Figure 4The figures show a cross-sectional view of the semiconductor package 2 according to other embodiments of the present invention. It should be understood that, for clarity, some components of the semiconductor package 2 may be omitted from the figures, and only some components are schematically shown. According to some embodiments, additional features may be added to the semiconductor package 2 described below. Furthermore, components that are the same as or similar to those described above will be indicated by the same or similar reference numerals, and their materials and functions are the same as or similar to those described above; therefore, this part will not be repeated hereafter.

[0165] Specifically, semiconductor package 2 can be formed based on the structure of the aforementioned semiconductor package 10 and combined with a suitable package combination. For example, semiconductor package 2 can be applied to a package structure similar to integrated fan-out package on package (InFO-PoP).

[0166] like Figure 4 As shown, the semiconductor package 2 may further include a fourth die 800, a third interconnect layer 802, and a circuit layer 804. The fourth die 800 may be disposed on the semiconductor package 10, and the third interconnect layer 802 and the circuit layer 804 may be disposed between the fourth die 800 and the semiconductor package 10. Furthermore, the semiconductor package 2 may further include a package layer 520 and a connection component 522. The package layer 520 may surround the semiconductor package 10, and the semiconductor package 10 may be electrically connected to the third interconnect layer 802 and the circuit layer 804 via vias 520 in the package layer 520 and the connection component 522, thereby being electrically connected to the fourth die 800. Moreover, an insulating layer 512 may surround the fourth die 800, and the insulating layer 512 may be disposed between the fourth die 800 and the semiconductor package 10, and between the fourth die 800 and the package layer 520.

[0167] The fourth die 800 may include, but is not limited to, a known-good die (KGD), an integrated circuit chip (IC), or other suitable electronic components. According to some embodiments, the fourth die 800 may include a system-on-a-chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), an application-specific integrated circuit (ASIC), dynamic random access memory, high-bandwidth memory, photonic integrated circuits, active components, passive components, a power management system chip, or other logic integrated circuits, but is not limited to these. Furthermore, the type of the fourth die 800 may be the same as or different from that of the first die 100 and the second die 200.

[0168] The third interconnect layer 802 may have one or more dielectric layers and patterned conductive layers. The materials of the dielectric layer and patterned conductive layer of the third interconnect layer 802 may be the same as or similar to those of the first interconnect layer 102, and will not be repeated here.

[0169] Circuit layer 804 may have one or more layers and may include one or more dielectric layers and patterned conductive layers. According to some embodiments, circuit layer 804 may serve as a redistribution layer (RDL). The materials of the dielectric layer and patterned conductive layer of circuit layer 804 may be the same as or similar to those of the aforementioned circuit layer 204, and will not be repeated here.

[0170] Encapsulation layer 520 can reduce the impact of water and oxygen in the external environment on the semiconductor package 1, reduce impact damage to the die and interconnect layers, improve the mechanical stability of the structure, or provide a heat dissipation path. According to some embodiments, encapsulation layer 520 may comprise molding compound, epoxy resin, other suitable encapsulation materials, or combinations thereof, but is not limited thereto.

[0171] According to some embodiments, the material of the connection component 522 may include tin, silver, lead-free tin, copper, nickel, gold, other suitable materials, or combinations thereof, but is not limited thereto. According to some embodiments, the connection component 522 may be bonded to the circuit layer 804 by means of a reflow process, a fusion bonding process, a hybrid bonding process, a metal-to-metal bonding process, other suitable methods, or combinations thereof, thereby bonding the fourth die 800 to the semiconductor package 10.

[0172] In addition, semiconductor package 2 may also include, for example Figure 3 The structural configuration of the semiconductor package 1 shown, including contact pad 604, conductive component 606, substrate 700, circuit layer 702, contact pad 704, circuit layer 706, and connection component 708, will not be repeated here.

[0173] In summary, according to embodiments of the present invention, the provided semiconductor package includes a specific structural design that can mitigate excessive stress concentration at the interfaces of different layers during bonding processes (e.g., reflow soldering or hybrid bonding), reducing problems such as delamination, peeling, or component breakage at the interfaces, thereby improving the structural strength or reliability of the semiconductor package.

[0174] While the embodiments and advantages of the present invention have been disclosed above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the invention. Features between embodiments of the present invention can be freely combined and used as long as they do not violate the spirit of the invention or conflict with it. Furthermore, the scope of protection of the present invention is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of the specification. Anyone skilled in the art can understand from the disclosure of the present invention that current or future developed processes, machines, manufacturing, material composition, apparatus, methods, and steps can be used according to the present invention as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of the present invention includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. The scope of protection of the present invention shall be determined by the appended claims. No embodiment or claim of the present invention is required to achieve all the objects, advantages, and features disclosed in the present invention.

Claims

1. A semiconductor package, characterized in that, include: A first die includes a first portion and a second portion, wherein the first portion has a first surface and the second portion has a second surface; A first interconnect layer is disposed on the second surface; as well as A packaging layer surrounds the first die and the first interconnect layer. In a cross-sectional view, the first part has a first width at the first surface, and the second part has a second width at the junction between the first part and the second part, and the second width is greater than the first width.

2. The semiconductor package as described in claim 1, characterized in that, The thickness of the first part is greater than the thickness of the second part.

3. The semiconductor package as described in claim 1, characterized in that, The difference between the first width and the second width is between 0.1 micrometers and 1 micrometer.

4. The semiconductor package as described in claim 1, characterized in that, The first part has a first side surface, the second part has a second side surface, and the first side surface and the second side surface are disposed between the first surface and the second surface.

5. The semiconductor package as described in claim 4, characterized in that, The roughness of the first side surface is greater than the roughness of the second side surface.

6. The semiconductor package as described in claim 4, characterized in that, In a thickness direction, a length of the first side surface is greater than a length of the second side surface.

7. The semiconductor package as described in claim 6, characterized in that, The length of the second side surface is between 0.1 micrometers and 1 micrometer.

8. The semiconductor package as described in claim 4, characterized in that, In the cross-sectional view, the first side surface has a first end located at the first surface and a second end located at the junction between the first side surface and the second side surface, and the first end is recessed inward relative to the second end.

9. The semiconductor package as described in claim 1, characterized in that, Including: A second die, wherein the first die is disposed on the second die; and A structural core is disposed on the second core and adjacent to the first core. The first core is electrically connected to the second core, and the structural core is electrically insulated from the second core.

10. The semiconductor package as claimed in claim 9, characterized in that, Including: A second inline layer is disposed on a surface of the second die away from the first die, and the first inline layer is electrically connected to the second inline layer through a guide hole in the second die.

11. The semiconductor package as claimed in claim 9, characterized in that, Including: A first bonding layer is disposed on the first interconnect layer; as well as A second bonding layer is disposed on a surface of the second die adjacent to the first die, wherein the first bonding layer is directly bonded to the second bonding layer.

12. The semiconductor package as described in claim 9, characterized in that, The second die includes a surface adjacent to the first die and a side surface, and a chamfer is formed between the surface and the side surface.

13. The semiconductor package as described in claim 12, characterized in that, In this cross-sectional view, the chamfer includes an arc-shaped edge.

14. The semiconductor package as claimed in claim 9, characterized in that, Including: An insulating layer is disposed between the structure die and the second die, and the encapsulation layer is in contact with one side surface of the insulating layer.

15. The semiconductor package as described in claim 14, characterized in that, In the cross-sectional view, the side surface of the insulating layer includes a first end that contacts the core of the structure and a second end that is away from the first end, and the second end is recessed inward relative to the first end.

16. The semiconductor package as claimed in claim 15, characterized in that, The side surface of the insulating layer includes a first portion connected to the first end and a second portion connected to the second end, and the second portion forms an angle relative to the first portion.

17. The semiconductor package as claimed in claim 9, characterized in that, Including: A composite structure is disposed between the second die and the combination of the first die and the structural die, wherein the composite structure includes a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer, and the second silicon nitride layer is closer to the second die than the first silicon nitride layer.

18. The semiconductor package as claimed in claim 17, characterized in that, The thickness of the silicon oxide layer is greater than the thickness of the first silicon nitride layer and also greater than the thickness of the second silicon nitride layer.

19. The semiconductor package as claimed in claim 17, characterized in that, The thickness of the first silicon nitride layer is greater than the thickness of the second silicon nitride layer.

20. The semiconductor package as claimed in claim 9, characterized in that, Including: A dummy contact pad is disposed between the encapsulation layer and the second die, wherein the encapsulation layer is disposed between the first die and the structural die.

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