A packaging method and packaging structure for co-packaging discrete devices and resistors

Abstract

This invention relates to the field of advanced integrated circuit packaging technology, specifically to a packaging method for encapsulating discrete devices and resistors. The method includes the following steps: fabricating a chip base island and external resistor terminals on a separable copper foil; mounting the discrete devices; laminating a molding compound; manufacturing printed resistors and series circuits; laminating the molding compound; patterning the separable copper foil to form external solder pads; and cutting to obtain the packaged product. This method introduces resistor fabrication into the packaging process, allowing for flexible configuration of the resistor's shape, size, number, electrode distribution, and connection method with the discrete devices. The resulting packaged product has a small size and high integration density.

Description

Technical Field

[0001] This invention relates to the field of advanced packaging technology for integrated circuits, and more specifically to a packaging method for encapsulating discrete devices and resistors together. Background Technology

[0002] The development trend of electronic products is towards high-density integration and miniaturization. Single-device packaging no longer meets the needs, and functional modularization is now the norm. In electronic circuits, discrete components (such as diodes, transistors, MOSFETs, thyristors, etc.) are often used in combination with resistor-capacitor (RC) series networks (RC circuits composed of resistors R and C in series). This allows the filtering / delay / coupling characteristics of the RC network to complement the switching / control characteristics of the discrete components, achieving more precise and stable functions. When discrete components are connected in series with resistors, current limiting protection, damped oscillation suppression, and signal limiting can be achieved. This is widely used in power supplies, amplification, control, and communication fields, and is a key method for designing stable and reliable circuits.

[0003] Figure 1 The diagram shows the traditional method of connecting discrete components and resistors in series. The discrete components are connected to the resistor chip in sequence through bonding wires, leads, PCB traces, and resistor leads, which results in extremely high parasitic inductance and occupies a large area of ​​the PCB. Figure 2 The diagram shows a packaging method that combines discrete components with resistors, simplifying PCB routing to direct metal connections within the package. This reduces parasitic inductance and PCB area usage to some extent, but the package size is still relatively large.

[0004] The package shapes of conventional discrete devices are usually standardized by industry. For example, the package shapes of diode devices are DFN1006, DFN1208, DFN1610, and DFN2510. How to package high-performance resistors in a smaller size has become a challenge in the packaging process of discrete devices and resistors. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the first aspect of this invention provides a packaging method for encapsulating discrete devices and resistors, achieving miniaturized packaging of discrete devices and resistors. The specific technical solution is as follows: A packaging method for combining discrete components and resistors includes the following steps: S10 fabricates a chip base island and external resistor terminals on a separable copper foil, mounts discrete devices on the chip base island, and electrically connects the lower surface electrodes of the discrete devices to the chip base island. S20 encapsulates discrete components and external resistor terminals to form a plastic encapsulation layer. Interlayer vias are drilled through the plastic encapsulation layer, and resistor paste is injected into the interlayer vias. The resistor paste is then subjected to UV curing and heat curing to form a vertically placed printed resistor. The lower end face of the printed resistor is electrically connected to the external resistor terminals.

[0006] S30 drills blind holes and metallizes them in the molding layer to form interconnect vias that communicate with the upper surface electrodes of the discrete device. A redistribution layer process is used to fabricate chip resistor connection lines on the surface of the molding layer. One end of the chip resistor connection line is connected to the upper surface electrodes of the discrete device through the interconnect vias, and the other end is electrically connected to the printed resistor contact. Chip base island, discrete devices, interconnect vias, chip resistor connection lines, printed resistors and external resistor terminals form a series circuit; The connection lines between S40 molded printed resistors and chip resistors are formed by patterning and etching separable copper foil to create external pads, which are then cut to obtain the packaged product. The height of the printed resistor is no more than 200μm.

[0007] Optionally, drilling interlayer through holes further includes: machining a slurry flow channel along the inner wall of the interlayer through hole, with the end of the slurry flow channel extending to the bottom of the interlayer through hole.

[0008] Optionally, the slurry flow channel has multiple branches, with the ends of the branches extending to the bottom surface of the interlayer through-hole.

[0009] Optionally, before pouring the quantitative resistance slurry, the interlayer vias may be treated using one or more of the following methods: a. The inner wall of the interlayer via is bombarded with oxygen plasma. b. Use ultraviolet ozone to clean the inner wall of the interlayer through-hole; c. A hydrophilic molecular coating is formed on the inner wall of the interlayer via by vacuum-assisted impregnation or vapor deposition. The hydrophilic molecular coating is a silane coupling agent self-assembled monolayer or a hydrophilic polymer coating.

[0010] Optionally, after step S20 and before step S30, the method further includes: laser etching the upper surface of the printed resistor to reduce the height of the printed resistor and thus reduce its resistance.

[0011] Optionally, the size of the interlayer via is determined according to the following steps: Obtain the target resistance value of the printed resistor and the resistivity of the resistive paste. Height of the sealing layer Upper aperture With lower aperture The ratio; Calculate the design resistance value of printed resistors Design resistance value The ratio of the resistance to the target resistance is not less than 1.05:1; According to the resistance formula Calculate the upper diameter of the interlayer through-hole.

[0012] Optionally, the grouting of resistance slurry is carried out under a vacuum of ≤-0.1MPa, and pressure is maintained for 3-10 minutes after grouting.

[0013] Optionally, in step S30, before fabricating the chip resistor connection lines on the surface of the molding compound using the redistribution layer process, a copper seed layer of 50 nm to 200 nm thickness is sputtered onto the surface of the printed resistor.

[0014] Optionally, step S10 further includes fabricating a first sub-circuit on a separable copper foil; Step S20 further includes: drilling multiple interlayer vias in the molding layer, wherein the bottom surface of the multiple interlayer vias is the upper surface of the first sub-circuit or the upper surface of the external resistor terminal; injecting resistor paste into the multiple interlayer vias respectively; and performing UV curing and heat curing treatment on the resistor paste to form multiple vertically placed printed resistors. The first sub-circuit is used to connect the lower ends of two adjacent printed resistors; Step S30 further includes fabricating a second sub-circuit on the surface of the molding layer using a redistribution layer process. The second sub-circuit includes chip resistor connection lines and resistor upper end face connection lines. The resistor upper end face connection lines are used to connect the upper end faces of two adjacent printed resistors. The chip base island, discrete devices, interconnect vias, first sub-circuit, second sub-circuit, printed resistors, and external resistor terminals form a series circuit.

[0015] A second aspect of the present invention provides a packaging structure manufactured using any of the aforementioned packaging methods.

[0016] In summary, this invention discloses a packaging method and packaging structure for co-encapsulating discrete devices and resistors. The beneficial effects of this invention using the above solution are as follows: 1. By introducing resistor fabrication into the packaging process, printed resistors are manufactured during the packaging process instead of directly packaging finished resistors. This significantly reduces the space occupied by the finished resistors due to factors such as fixed size, fixed electrode position, and the presence of a protective layer. The package size is small and the integration is high. 2. By using interlayer through-holes to accommodate the fluid state of the resistive slurry, the morphology of the resistive slurry can remain basically unchanged before and after curing, which greatly reduces the resistance fluctuation caused by overflow and collapse during the resistance drop curing process. 3. Laser drilling can form high-precision interlayer vias according to the design dimensions, which are used to accommodate and form printed resistors of the corresponding shape, avoiding resistance fluctuations caused by the dimensional tolerances of interlayer vias, and ensuring good batch consistency. 4. The cured printed resistor is embedded in the molding layer, which does not occupy vertical space and does not require re-molding protection, further reducing the space occupied by the package. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of existing PCB traces in series; Figure 2 This is a schematic diagram of wire bonding and encapsulation in existing technology packaging; Figure 3 This is a schematic diagram of the board-level fan-out planar sealing process; Figure 4 This is a schematic diagram of the vertical stacking and sealing process of finished resistors; Figure 5-14 This is a schematic diagram of a packaging method for encapsulating discrete devices and resistors according to an embodiment of the present invention; Figure 15-16 This is a schematic diagram of the slurry guiding channel in Embodiment 1 of the present invention; Figure 17-31 This is a schematic diagram of a packaging method for encapsulating discrete devices and resistors according to Embodiment 2 of the present invention;

[0018] In the picture: 1-Separable copper foil; 11-Chip base island; 12-External resistor terminal; 2-Discrete device; 3-Encapsulation layer; 31-Interlayer via; 311-Paste flow channel; 4-Printed resistor; 41-Resistor paste; 5-Series circuit; 501-Chip resistor connection circuit; 502-Resistor upper surface connection circuit; 51-First sub-circuit; 52-Second sub-circuit. Detailed Implementation

[0019] The following description, in conjunction with the accompanying drawings, further illustrates a packaging method for combining discrete devices and resistors according to the present invention.

[0020] Taking the co-packaging of diode chips and resistors as an example, the package dimensions of conventional diode devices have industry standards: such as DFN1006, DFN1208, DFN1610, and DFN2510. When packaging a resistor element, the overall package size increases depending on the component's dimensions, and the increase percentage varies depending on the packaging process.

[0021] If the diode chip size is The single-chip package specification is DFN1006 ( It is necessary to encapsulate a 10000Ω resistor with a specification of 0603. ) is a resistive element.

[0022] like Figure 2 The diagram shows a wire bonding and encapsulation scheme. Considering the space required for wire bonding and pins, the minimum planar dimension is [missing information]. This size can only be increased to match DFN1610 ( The use of this specification results in significant space waste.

[0023] In some implementations, board-level packaging processes can eliminate the need for wire bonding, such as... Figure 3 The board-level fan-out planar encapsulation process shown can reduce the planar dimensions of the resulting package structure to [size missing]. This size can match DFN1208 ( This reduces the space occupied by one size.

[0024] In some implementations, discrete components are stacked and packaged with finished resistors in the vertical direction, eliminating wire bonding, thereby further reducing the planar dimensions, such as... Figure 4 The stacked packaging process shown can reduce the planar dimensions of the resulting package structure to DFN1006 ( The planar dimensions are the same as those of a single-chip package. In the vertical direction, due to the stacking of diode chips and resistors, the height of the package structure exceeds the standard height of DFN1006. This can be addressed by thinning the chip substrate layer or using flattened resistor elements to meet the thickness of the standard package size.

[0025] In some implementations, resistors are integrated into the packaging process to achieve more flexible series-to-package configurations, as detailed below: Example 1: Figure 5-14 The diagram illustrates a packaging method for combining discrete components and resistors according to an embodiment of the present invention, comprising the following steps: S10 A chip base island 11 and an external resistor terminal 12 are fabricated on a separable copper foil 1. Discrete device 2 is mounted on the chip base island 11, and the lower surface electrode of the discrete device 2 is electrically connected to the chip base island 11. S20 The discrete device 2 and the external resistor terminal 12 are encapsulated to form a molding layer 3, the thickness of which is 100μm to 200μm; A laser drilling device is used to drill an interlayer through-hole 31 through the plastic seal layer 3, and a resistor paste 41 is injected into the interlayer through-hole 31. The resistor paste 41 is subjected to ultraviolet curing and heat curing treatment to form a vertically placed printed resistor 4. The lower end face of the printed resistor 4 is electrically connected to the external terminal of the resistor.

[0026] S30 Drills blind holes and metallizes them in the molding layer 3 to form interconnect vias that communicate with the upper surface electrodes of the discrete device 2. A chip resistor connection line 501 is fabricated on the surface of the molding layer 3 using a redistribution layer process. One end of the chip resistor connection line 501 is connected to the upper surface electrodes of the discrete device through the interconnect vias, and the other end is electrically connected to the printed resistor 4. The chip base island 11, discrete device 2, interconnect via, chip resistor connection line 501, printed resistor 4 and resistor external terminal 12 form a series line 5. S40 plastic-encapsulated printed resistor 4 and chip resistor connection line 501, the separable copper foil 1 is patterned and etched to form external solder pads, and then cut to obtain the packaged finished product; Separable copper foil 1 is separably pressed onto a carrier plate, which is a copper-clad laminate or an organic carrier plate, used to provide support during processing. An insulating dielectric layer is pressed onto the separable copper foil 1. Holes are drilled and metallized in the insulating dielectric layer to form interconnecting vias. Chip base island 11 and external resistor terminals 12 are formed on the surface of the insulating dielectric layer by patterned electroplating. Discrete device 2 is mounted on chip base island 11 and fixed by reflow soldering. At this time, the back electrode of discrete device 2 is connected to chip base island 11.

[0027] The insulating dielectric layer and the encapsulating layer can be laminated using vacuum lamination or molding processes. Laser drilling is used for drilling holes in both the insulating dielectric layer and the encapsulating layer.

[0028] The thickness of discrete devices is typically between 50-150 μm. Setting the thickness of molding layer 3 to 100 μm to 200 μm can cover the molding protection requirements and interlayer via size requirements of most discrete devices. Effective protection of discrete devices cannot be achieved below 100μm, while above 200μm, the diameter of the interlayer vias is too deep, increasing the difficulty of drilling, slurry filling and UV curing processes. In addition, the printed resistance increases, requiring a larger cross-sectional area and occupying more planar space for the same resistance value.

[0029] The resistive paste 41 can be injected by screen printing, vacuum potting or vacuum printing, with vacuum potting being the preferred method.

[0030] As an optional implementation method of this embodiment, the injection of quantitative resistance slurry 41 is carried out under a vacuum degree ≤ -0.1MPa. After injection, the pressure is maintained for 3-10 minutes. Under vacuum, most of the air in the micro-blind hole is extracted to avoid air bubble residue and ensure dense filling. Maintaining pressure under vacuum for 3-10 minutes allows the slurry to fully penetrate to the bottom of the hole.

[0031] As an optional implementation method in this embodiment, such as Figure 15 As shown, drilling the interlayer through hole 31 also includes: A slurry guiding channel 311 is machined along the inner wall of the interlayer through hole 31, and the end of the slurry guiding channel 311 extends to the bottom of the interlayer through hole 31.

[0032] The slurry guiding channel 311 can guide and accelerate the resistance slurry 41 to flow along a specific path to the bottom of the interlayer through hole 31 through capillary action, overcome viscous resistance, and avoid blockage at the orifice or middle of the hole, which would lead to bottom voids.

[0033] As an optional implementation method in this embodiment, such as Figure 16 As shown, the slurry guiding channel 311 has multiple branches, with the ends of the branches extending to the bottom surface of the interlayer through-hole 31. The multiple branches can extend to all directions and corners of the interlayer through-hole 31, uniformly distributing and diffusing the resistive slurry to the entire bottom surface of the interlayer through-hole.

[0034] The slurry guiding channel 311 can be formed by using high-precision laser processing equipment, with an extremely fine spot (diameter ≤5μm) moving along the inner wall of the guiding channel from the top to the bottom of the inner wall to ablate. As the processing area gradually moves downward, the laser power gradually increases to compensate for the energy attenuation when the laser moves away from the focal point.

[0035] As an optional implementation of this embodiment, before pouring the quantitative resistance slurry 41, the interlayer via 31 is treated by one or more of the following methods: a. The inner wall of the interlayer via is bombarded with oxygen plasma. b. Use ultraviolet ozone to clean the inner wall of the interlayer through-hole; c. A hydrophilic molecular coating is formed on the inner wall of the interlayer via by vacuum-assisted impregnation or vapor deposition. The hydrophilic molecular coating is a silane coupling agent self-assembled monolayer or a hydrophilic polymer coating.

[0036] The inner wall of the activated interlayer through-hole 31 is cleaned with oxygen plasma or ultraviolet ozone. While decomposing the organic matter on the surface, a large number of polar hydrophilic groups such as hydroxyl (-OH) and carboxyl (-COOH) are introduced through oxidation reaction, so that the contact angle of the inner wall is reduced to below 10°. The resistive slurry can be quickly wetted and flow rapidly along the inner wall surface under the drive of surface tension.

[0037] The self-assembled monolayer of silane coupling agent can be formed by immersing the cleaned and activated interlayer vias 31 in a diluted silane coupling agent solution under vacuum conditions, followed by rinsing and curing, or by vapor deposition. The hydrophilic polymer coating can be made from PVP (polyvinylpyrrolidone), PAA (polyacrylic acid), PEG (polyethylene glycol), or PVA (polyvinyl alcohol) film using a vacuum impregnation method.

[0038] The hydrophilic molecular coating can significantly reduce the contact angle between the inner surface of the interlayer via 31 and the resistive paste, bringing it close to 0°, which facilitates the complete spreading and smooth filling of the resistive paste. In addition, the selection of silanes (such as epoxy silanes and amino silanes) that are compatible with the resistive paste resin system can react with the resin in the resistive paste to form chemical bonds, providing stronger bonding.

[0039] As an optional implementation of this embodiment, in step S30, before fabricating the chip resistor connection lines on the surface of the molding compound using the redistribution layer process, a copper seed layer with a thickness of 50nm to 200nm is sputtered on the surface of the printed resistor.

[0040] The printed resistor formed by the resistive paste consists of conductive particles and a polymer matrix. During electroplating, it is more difficult to deposit copper in the insulating area than in the conductive particle area, which will lead to uneven plating. A copper seed layer is sputtered on the surface of the printed resistor. Copper atoms are deposited and fill the micropores on the surface of the printed resistor, forming a continuous conductive network layer. This makes the electroplating rate consistent throughout the surface of the printed resistor, resulting in a uniform plating layer and strong adhesion to the interface of the printed resistor.

[0041] A copper seed layer thickness of 50nm to 200nm can adequately meet the requirements for electroplating uniformity and interfacial adhesion. When the thickness is less than 50nm, there may be insufficient coverage of micro-pores, resulting in unplated areas that affect conductivity and adhesion. When the thickness is greater than 200nm, significant stress accumulates within the seed layer, which can easily lead to severe failures such as circuit warping or even circuit stripping.

[0042] As an optional implementation of this embodiment, after step S20 and before step S30, the following steps are also included: using laser etching to etch the upper surface of the printed resistor 4 to reduce the height of the printed resistor 4 to reduce the resistance value to the target resistance value.

[0043] Due to differences in the uniformity of filler dispersion in the resistive paste, inherent deviations in resistivity between different batches of resistive paste, and slight differences in the curing conditions of the resistive paste, the actual resistance value of the printed resistor 4 will deviate from the designed resistance value. According to the resistance formula, the resistance value of the printed resistor 4 in this embodiment is related to its height. A portion of the resistive material can be removed by laser etching of the surface layer of the printed resistor 4, thereby reducing the height of the printed resistor 4 and lowering its resistance value until the target resistance value is reached.

[0044] As an optional implementation of this embodiment, the size of the interlayer via is determined according to the following steps: Obtain the target resistance value of the printed resistor and the resistivity of the resistive paste. Height of the sealing layer Upper aperture With lower aperture The ratio; Calculate the design resistance value of printed resistors Design resistance value The ratio of the resistance to the target resistance is not less than 1.05:1; According to the resistance formula Calculate the upper diameter of the interlayer through-hole.

[0045] The target resistance value of the printed resistor and the resistivity of the resistive paste are among them. and the height of the molding layer Available according to design; upper aperture With lower aperture The ratio is obtained based on the process capability of the drilling equipment; The design resistance value is set to be greater than the target resistance value. Even if there is a positive or negative deviation in the resistance value, the actual resistance value of the printed resistor 4 is greater than the target resistance value in most cases. This makes it easier to use laser etching to etch the upper surface of the printed resistor 4 and reduce the height of the printed resistor 4 to reduce the resistance value to the target resistance value.

[0046] In a preferred embodiment, the height of the interlayer via 31 is 150 μm, and the diameter of the interlayer via is calculated with a target resistance of 10000 Ω.

[0047] In board-level packaging processes, laser drilling is typically used to form interlayer vias in the molding compound. Due to the divergence of the laser and the ablation characteristics of the material, the interlayer vias usually form a cone shape that is "larger at the top and smaller at the bottom". The industry usually requires that the ratio of the bottom diameter to the top diameter of the interlayer via is not less than 85%.

[0048] According to the resistance formula ,in To design the resistance value, The resistivity of the resistive slurry. This represents the length of the resistor, and here it represents the height of the quantitative resistor slurry. This refers to the cross-sectional area of ​​the resistance paste, which is determined by the bottom diameter of the resistance paste. With top diameter Calculation, i.e. .

[0049] Pick ; ; =0.15mm; ; Calculation yields .

[0050] That is, the top diameter of the interlayer through-hole 31 is approximately 0.087 mm.

[0051] At this time, the plane space occupied by the printed resistor 4 does not exceed Furthermore, the printed resistor 4 is embedded in the molding layer and does not occupy vertical space. Therefore, the packaged product size obtained in this embodiment can easily reach the standard package specification of DFN1006.

[0052] Furthermore, according to the formula It can be seen that the resistance value of the printed resistor 4 is inversely proportional to the diameter of the interlayer via. When a resistor with a larger resistance value needs to be packaged, the diameter of the interlayer via 31 can be reduced during the design phase. In this case, the printed resistor 4 occupies less space, and the usable space of the package structure is larger. When a resistor with a smaller resistance value is needed, it can be achieved by increasing the diameter of the interlayer via or reducing the height of the resistor paste.

[0053] In this embodiment, the resistive paste is a conductive polymer paste, the drying temperature is 80~150℃, and it is cured by ultraviolet light, which is compatible with board-level packaging process.

[0054] Example 2 like Figure 17-31 The diagram shows a packaging method for combining discrete devices and resistors according to Embodiment 2 of the present invention, which differs from Embodiment 1 in that: Step S10 also includes fabricating a first sub-circuit 51 on the separable copper foil 1; Step S20 further includes: drilling multiple interlayer vias 31 in the molding layer 3, the bottom surface of the interlayer vias 31 being the upper surface of the first sub-circuit 51 or the upper surface of the external resistor terminal 12; injecting resistor paste 41 into the multiple interlayer vias respectively; subjecting the resistor paste 41 to ultraviolet curing and thermal curing treatment to form multiple vertically placed printed resistors 4. The first sub-circuit 51 is used to connect the lower ends of two adjacent printed resistors; Step S30 also includes fabricating a second sub-circuit 52 on the surface of the molding layer using a redistribution layer process. The second sub-circuit 52 includes a chip resistor connection line 501 and a resistor upper end face connection line 502. The resistor upper end face connection line 502 is used to connect the upper end faces of two adjacent printed resistors 4. The chip base island 11, discrete device 2, interconnect via, first sub-circuit 51, second sub-circuit 52, printed resistor 4 and resistor external terminal 12 form a series circuit 5.

[0055] In one optional embodiment of this example, the number of printed resistors 4 is two, such as... Figure 17-24 As shown, the bottom surface of the interlayer vias 31 corresponding to the two printed resistors 4 is the upper surface of the first sub-circuit 51, so that the first sub-circuit 51 connects the two printed resistors 4 in series. The second sub-circuit 52 includes the connection line between the discrete device 2 and one of the printed resistors 4 and the connection line between the other printed resistor 4 and the external resistor terminal 12. The external resistor terminal 12 is connected to the corresponding printed resistor 4 through interconnecting vias. The first sub-circuit 51 and the second sub-circuit 52 together constitute the series circuit 5.

[0056] In one optional embodiment of this example, the number of printed resistors 4 is 3, such as... Figure 25-31As shown, the bottom surface of the interlayer via 31 corresponding to the two printed resistors 4 is the first sub-circuit 51, and the bottom surface of the interlayer via 31 corresponding to the third printed resistor 4 is the upper surface of the external resistor terminal 12, so that the first sub-circuit 51 connects the two printed resistors 4 in series. The second sub-circuit 52 includes the connection line between the discrete device 2 and one of the printed resistors 4 and the connection line between the other two printed resistors 4. The first sub-circuit 51 and the second sub-circuit 52 together constitute the series circuit 5.

[0057] In other optional embodiments of this example, smaller and more numerous printed resistors can be designed according to the packaging requirements to meet the packaging needs of higher-performance discrete devices. The lower limit of the printed resistor size is limited by the drilling and potting process, and the number of printed resistors is limited to the final package structure size not exceeding the corresponding standard package specification.

[0058] Example 3

[0059] A packaging structure is manufactured using any of the aforementioned packaging methods that encapsulate discrete components and resistors.

Claims

1. A packaging method for encapsulating discrete components and resistors, characterized in that, Includes the following steps: S10 A chip base island (11) and an external resistor terminal (12) are fabricated on a separable copper foil (1). A discrete device (2) is mounted on the chip base island (11). The lower surface electrode of the discrete device (2) is electrically connected to the chip base island (11). S20 The discrete device (2) and the external resistor terminal (12) are encapsulated to form a molding layer (3), the thickness of the molding layer (3) being 100 μm to 200 μm; A laser drilling device is used to drill an interlayer through hole (31) through the plastic seal layer (3), and a resistor slurry (41) is injected into the interlayer through hole (31); the resistor slurry (41) is subjected to ultraviolet curing and heat curing treatment to form a vertically placed printed resistor (4), and the lower end face of the printed resistor (4) is electrically connected to the external terminal (12) of the resistor. S30 Drill blind holes and metallize them in the molding layer (3) to form interconnect vias that communicate with the upper surface electrode of the discrete device (2). Use a redistribution layer process to fabricate chip resistor connection lines (501) on the surface of the molding layer (3). One end of the chip resistor connection line (501) is connected to the upper surface electrode of the discrete device through the interconnect vias, and the other end is electrically connected to the printed resistor (4). The chip base island (11), discrete device (2), interconnect via, chip resistor connection line (501), printed resistor (4) and resistor external terminal (12) form a series line (5); S40 The printed resistor (4) and the chip resistor connection line (501) are molded and the separable copper foil (1) is patterned and etched to form an external pad. After cutting, the packaged product is obtained.

2. The packaging method as described in claim 1, characterized in that, Drilling the interlayer through hole (31) further includes: processing a slurry flow channel (311) along the inner wall of the interlayer through hole (31), the end of the slurry flow channel (311) extending to the bottom of the interlayer through hole (31).

3. The packaging method as described in claim 2, characterized in that, The slurry guiding channel (311) has multiple branches, and the ends of the branches extend to the bottom surface of the interlayer through hole (31).

4. The packaging method as described in claim 1, characterized in that, Before pouring the quantitative resistivity slurry (41), the interlayer via (31) is treated using one or more of the following methods: a. The inner wall of the interlayer via (31) is bombarded with oxygen plasma. b. The inner wall of the interlayer through-hole (31) is cleaned with ultraviolet ozone. c. A hydrophilic molecular coating is formed on the inner wall of the interlayer via (31) by vacuum-assisted impregnation or vapor deposition. The hydrophilic molecular coating is a silane coupling agent self-assembled monolayer or a hydrophilic polymer coating.

5. The packaging method as described in claim 1, characterized in that, After step S20 and before step S30, the method further includes: laser etching the upper surface of the printed resistor (4) to reduce the height of the printed resistor (4) and reduce the resistance value.

6. The packaging method as described in claim 5, characterized in that, The dimensions of the interlayer via (31) are determined according to the following steps: Obtain the target resistance value of the printed resistor (4) and the resistivity of the resistive paste (41). Height of the sealing layer (3) and the upper diameter of the interlayer through hole (31) With lower aperture The ratio; Calculate the design resistance value of the printed resistor (4). The design resistance value The ratio of the resistance to the target resistance is not less than 1.05:1; According to the resistance formula Calculate the upper diameter of the interlayer through hole (31).

7. The packaging method as described in claim 1, characterized in that, The grouting resistance slurry (41) is carried out under a vacuum of ≤-0.1MPa, and the pressure is maintained for 3-10 minutes after grouting.

8. The packaging method as described in claim 1, characterized in that, In step S30, before fabricating the chip resistor connection line (501) on the surface of the molding layer (3) using the redistribution layer process, a copper seed layer with a thickness of 50nm to 200nm is sputtered on the surface of the printed resistor (4).

9. The packaging method as described in claim 1, characterized in that, Step S10 further includes fabricating a first sub-circuit (51) on the separable copper foil (1). Step S20 further includes: drilling multiple interlayer vias (31) in the encapsulation layer (3), wherein the bottom surface of the multiple interlayer vias (31) is the upper surface of the first sub-circuit (51) or the upper surface of the external resistor terminal (12); injecting resistor paste (41) into the multiple interlayer vias (31); and subjecting the resistor paste (41) to ultraviolet curing and thermal curing treatment to form multiple vertically placed printed resistors (4). The first sub-line (51) is used to connect the lower end faces of two adjacent printed resistors (4); Step S30 further includes fabricating a second sub-circuit (52) on the surface of the molding layer (3) using a redistribution layer process. The second sub-circuit (52) includes a chip resistor connection line (501) and a resistor upper end face connection line (502). The resistor upper end face connection line (502) is used to connect the upper end faces of two adjacent printed resistors (4). The chip base island (11), discrete device (2), interconnect via, first sub-line (51), second sub-line (52), printed resistor (4) and resistor external terminal (12) form a series circuit (5).

10. A packaging structure, characterized in that, It is manufactured using the packaging method described in any one of claims 1 to 9.

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