Interconnect stacks and their formation methods

Abstract

This application provides a method for forming an interconnect stack, the method comprising: providing a first semiconductor wafer having a plurality of first semiconductor cells, each first semiconductor cell having a set of first conductive interconnect structures extending through the first semiconductor wafer; providing a second semiconductor wafer having a plurality of second semiconductor cells, each second semiconductor cell having a set of second conductive interconnect structures extending through the second semiconductor cell; dicing the second semiconductor wafer into a plurality of second semiconductor dies; vertically aligning each second semiconductor die with a first semiconductor cell; bonding each second semiconductor die to a first semiconductor cell by hybrid bonding; dicing the first semiconductor wafer into a plurality of first semiconductor dies to form a plurality of double-layer interconnect sub-stacks; testing each double-layer interconnect sub-stack to select a plurality of qualified double-layer interconnect sub-stacks; and bonding two qualified double-layer interconnect sub-stacks to form an interconnect stack.

Description

Technical Field

[0001] This application relates generally to semiconductor technology, and more specifically, to an interconnect stack and a method of forming the same. Background Technology

[0002] The semiconductor industry has always faced complex integration challenges as consumers demand smaller, faster, and higher-performing electronic devices, packing more and more functionality into a single device. To meet these requirements, electronic modules, such as wafers or chips, can be stacked and bonded together to form multi-layered electronic packages with multiple functions.

[0003] In recent years, hybrid bonding has emerged as an advanced interconnect technology, bonding stacked electronic modules together to form interconnect stacks with higher density, thereby achieving high device performance, smaller form factor, and lower power consumption. However, for interconnect stacks containing multiple layers of electronic modules, the stacking and bonding of each layer may face potential challenges in alignment accuracy, which could adversely affect the yield of the interconnect stack and lead to higher costs.

[0004] Therefore, a method for forming interconnect stacks with higher yield and lower cost is needed. Summary of the Invention

[0005] One objective of this application is to provide a method for forming interconnect stacks with higher yield and lower cost.

[0006] According to one aspect of this application, a method for forming an interconnect stack is provided. The method includes: providing a first semiconductor wafer having a first top dielectric layer at its top surface and a first bottom dielectric layer at its bottom surface, wherein the first semiconductor wafer includes a plurality of first semiconductor cells, each first semiconductor cell having a set of first conductive interconnect structures extending through the first semiconductor wafer; providing a second semiconductor wafer having a second top dielectric layer at its top surface and a second bottom dielectric layer at its bottom surface, wherein the second semiconductor wafer includes a plurality of second semiconductor cells, each second semiconductor cell having a set of second conductive interconnect structures extending through the second semiconductor wafer; dicing the plurality of second semiconductor cells of the second semiconductor wafer into a plurality of second semiconductor dies; and connecting each of the plurality of second semiconductor dies to one of the first semiconductor cells of the first semiconductor wafer. The cells are vertically aligned to stack them together; each of the plurality of second semiconductor dies is bonded to one of the plurality of first semiconductor cells using hybrid bonding, such that the second top dielectric layer of the second semiconductor die and the set of second conductive interconnect structures are vertically aligned and bonded to the first top dielectric layer and the set of first conductive interconnect structures of the first semiconductor cell, respectively; the plurality of first semiconductor cells of the first semiconductor wafer are diced into a plurality of first semiconductor dies, such that each of the plurality of first semiconductor dies is bonded to one of the plurality of second semiconductor dies to form a plurality of double-layer interconnect sub-stackings; each of the plurality of double-layer interconnect sub-stackings is tested to select a plurality of qualified double-layer interconnect sub-stackings from the plurality of double-layer interconnect sub-stackings; and at least two qualified double-layer interconnect sub-stackings are bonded together to form the interconnect stack.

[0007] According to another aspect of this application, a method for forming an interconnect stack is provided. The method includes: providing a first semiconductor wafer having a first top dielectric layer at its top surface and a first bottom dielectric layer at its bottom surface, wherein the first semiconductor wafer includes a plurality of first semiconductor cells, each first semiconductor cell having a set of first conductive interconnect structures extending through the first semiconductor wafer; providing a second semiconductor wafer having a second top dielectric layer at its top surface and a second bottom dielectric layer at its bottom surface, wherein the second semiconductor wafer includes a plurality of second semiconductor cells, each second semiconductor cell having a set of second conductive interconnect structures extending through the second semiconductor wafer; vertically aligning the second semiconductor wafer with the first semiconductor wafer to stack them together; and bonding each of the plurality of second semiconductor cells to the first semiconductor wafer using hybrid bonding. One of the plurality of first semiconductor cells is bonded such that the second top dielectric layer of the second semiconductor cell and the set of second conductive interconnect structures are vertically aligned and bonded to the first top dielectric layer of the first semiconductor cell and the set of first conductive interconnect structures, respectively; the plurality of first semiconductor cells of the first semiconductor wafer and the plurality of second semiconductor cells of the second semiconductor wafer are individually diced into a plurality of first semiconductor dies and a plurality of second semiconductor dies, such that each of the plurality of first semiconductor dies is bonded to one of the plurality of second semiconductor dies to form a plurality of double-layer interconnect sub-stacks; each of the plurality of double-layer interconnect sub-stacks is tested to select a plurality of qualified double-layer interconnect sub-stacks from the plurality of double-layer interconnect sub-stacks; and at least two qualified double-layer interconnect sub-stacks are bonded together to form the interconnect stack.

[0008] According to another aspect of this application, an interconnect stack is provided. The interconnect stack includes a first double-layer interconnect sub-stack and a second double-layer interconnect sub-stack bonded together, wherein each of the first double-layer interconnect sub-stack and the second double-layer interconnect sub-stack includes: a first semiconductor die having a first top dielectric layer at its top surface and a first bottom dielectric layer at its bottom surface, and the first semiconductor die having a set of first conductive interconnect structures extending through the first semiconductor die; and a second semiconductor die having a second top dielectric layer at its top surface and a second bottom dielectric layer at its bottom surface, and the second semiconductor die having a set of second conductive interconnect structures extending through the second semiconductor die; and the first semiconductor die is bonded to the second semiconductor die by hybrid bonding such that the first top dielectric layer and the set of first conductive interconnect structures of the first semiconductor die are vertically aligned and bonded to the second top dielectric layer and the set of second conductive interconnect structures of the second semiconductor die, respectively.

[0009] It should be understood that both the above general description and the following detailed description are exemplary and explanatory only and do not limit the invention. Furthermore, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Attached Figure Description

[0010] The accompanying drawings, which are incorporated herein by reference, form part of this specification. Unless expressly indicated otherwise in the detailed description, the features shown in the drawings illustrate only some embodiments of this application, and not all embodiments thereof, and should not be construed as implying to the reader of this specification that all embodiments are possible. Figures 1A to 1K The various steps of a method for forming an interconnect stack according to a first embodiment of this application are shown.

[0011] Figure 2 The diagram illustrates a single-cutting step of a first semiconductor cell in a method for forming an interconnect stack according to a second embodiment of this application.

[0012] Figures 3A to 3D The various steps of a method for forming an interconnect stack according to a third embodiment of this application are shown.

[0013] Throughout the diagram, the same reference numerals will be used to refer to the same or similar parts. Detailed Implementation

[0014] The following detailed description of exemplary embodiments of this application takes into account the accompanying drawings, which form a part of the description. The drawings illustrate specific exemplary embodiments in which this application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice this application. Those skilled in the art may further utilize other embodiments of this application and make logical, mechanical, and other changes without departing from the spirit or scope of this application. Therefore, the reader of the following detailed description should not interpret the description in a limiting sense, and the scope of the embodiments of this application is defined only by the appended claims.

[0015] In this application, unless otherwise expressly stated, the use of the singular includes the plural form. In this application, unless otherwise stated, the use of “or” means “and / or”. Furthermore, the use of the term “comprising” is not restrictive. Additionally, unless otherwise expressly stated, terms such as “element” or “assembly” cover both elements and assemblies comprising one unit and elements and assemblies comprising more than one sub-unit. Furthermore, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0016] As used herein, for ease of description, spatial relative terms such as “below,” “under,” “above,” “upper,” “upper,” “lower,” “left,” “right,” “vertical,” “horizontal,” and “side” may be used to describe the relationship between an element or feature and another element (or feature) or feature (or feature), as shown in the diagrams. In addition to the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, the element may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0017] As mentioned above, electronic modules such as wafers or chips can be stacked and bonded together using hybrid bonding processes to form interconnect stacks with multiple functions. However, for interconnect stacks containing multiple layers of electronic modules (such as interconnect vias), the stacking and hybrid bonding of these layers may face challenges in alignment accuracy. For example, in some cases, individual electronic modules are stacked and bonded simultaneously to form an interconnect stack. If the stacking and hybrid bonding between any two electronic modules causes an unsatisfactory defect, the entire interconnect stack should be discarded. This can lead to lower interconnect stack yields and higher manufacturing costs.

[0018] To address the aforementioned problems, a method for forming interconnect stacks according to some embodiments of this application is provided. The method includes bonding a plurality of first semiconductor cells and a plurality of second semiconductor dies within a first semiconductor wafer using hybrid bonding. Next, the first semiconductor wafer is subjected to a single-cutter process to form a plurality of bilayer interconnect sub-stacks, each bilayer interconnect sub-stack including a first semiconductor die and a second semiconductor die bonded thereon. Then, each of the bilayer interconnect sub-stacks is tested to select qualified bilayer interconnect sub-stacks. At least two qualified bilayer interconnect sub-stacks are then bonded together to form an interconnect stack. Therefore, this method not only utilizes a hybrid bonding process to form bilayer interconnect sub-stacks with high bonding quality but also implements a testing process to select qualified bilayer interconnect sub-stacks before further stacking them together. These steps can help address the alignment accuracy challenges when multiple layers of semiconductor dies are stacked and bonded together, resulting in improved interconnect stack yield and reduced manufacturing process costs.

[0019] Figures 1A to 1K An interconnect stack according to a first embodiment of this application is shown.

[0020] like Figure 1A As shown, a first semiconductor wafer 100 is provided. The first semiconductor wafer 100 includes a first wafer body 110, the first wafer body having... Figure 1A The top surface is shown facing upwards. The first wafer body 110 also includes a bottom surface opposite the top surface. In some embodiments, the first wafer body 110 may include silicon or other semiconductor materials suitable for hybrid bonding. In some embodiments, the first semiconductor wafer 100 may have undergone both front-end processing (FEOL) and back-end processing (BEOL) processes.

[0021] Furthermore, the first semiconductor wafer 100 may also include a first top dielectric layer 111 on the top surface of the first wafer body 110 and a first bottom dielectric layer on the bottom surface of the first wafer body 110. In this manner, the exposed surface of the first top dielectric layer 111 may be referred to as the top surface of the first semiconductor wafer 100, and the exposed surface of the first bottom dielectric layer may be referred to as the bottom surface of the first semiconductor wafer 100. In some embodiments, the first top dielectric layer 111 and the first bottom dielectric layer may comprise silicon oxide, silicon oxynitride, or a polymer.

[0022] Additionally, the first semiconductor wafer 100 may include a plurality of first semiconductor cells 101. In some embodiments, the first semiconductor wafer 100 further includes a plurality of first dicing regions 102, and each of the first dicing regions 102 is located between two adjacent first semiconductor cells 101. That is, the first semiconductor cells 101 and the first dicing regions 102 may be different portions of the first semiconductor wafer 100. The first dicing region 102 may be a dummy region without functional modules, which may be designed for single-dicing steps in subsequent processes. In some embodiments, the first semiconductor cells 101 may have the same structure. In some other embodiments, the first semiconductor cells 101 may be different from each other.

[0023] exist Figure 1A In the illustrated embodiment, each of the first semiconductor cells 101 may further include a set of first conductive interconnect structures 112 extending through the first semiconductor wafer 100. In other words, the first conductive interconnect structures 112 may extend through the first top dielectric layer 111, the first wafer body 110, and the first bottom dielectric layer, thereby exposing the top and bottom surfaces of the first conductive interconnect structures 112 from the top surface of the first top dielectric layer 111 and the bottom surface of the first bottom dielectric layer, respectively. It should be noted that the first conductive interconnect structures 112 may not be formed within the first dicing region 102. In some other embodiments, multiple sets of conductive pads may be formed on the top and bottom surfaces of the first semiconductor wafer 100 for mounting the first semiconductor cells 101. It is understood that the multiple sets of conductive pads may be exposed portions of the multiple sets of first conductive interconnect structures 112 formed within the first semiconductor wafer 100. For example, the multiple sets of conductive pads may be portions of the multiple sets of first conductive interconnect structures 112 embedded within the first top dielectric layer 111 and the first bottom dielectric layer. In some embodiments, the first conductive interconnect structure 112 may include a metal, such as copper.

[0024] Next, as Figure 1B As shown, the carrier 120 can be attached to the bottom surface of the first semiconductor wafer 100. The carrier 120 can serve as a mechanical support during subsequent surface treatment processes and hybrid bonding processes of the first semiconductor wafer 100. In some embodiments, an adhesive can be applied between the bottom surface of the first semiconductor wafer 100 and the top surface of the carrier 120.

[0025] Next, as Figure 1CAs shown, the top portion of a first semiconductor wafer 100, including the top portion of a first top dielectric layer 111 and the top portion of a first conductive interconnect structure 112, can be polished to form a relatively flat top surface of the first semiconductor wafer 100. In some embodiments, a metal oxide layer may be formed on the top surface of the first conductive interconnect structure 112, which may adversely affect hybrid bonding. Thus, the polishing process can remove the metal oxide layer to prepare the first semiconductor wafer 100 for subsequent bonding processes. In some embodiments, a chemical mechanical polishing (CMP) process can be performed to polish the top portion of the first semiconductor wafer 100. During the polishing process, an polishing slurry can be applied to the top surface of the first semiconductor wafer 100 to improve lubrication between the wafer 100 and the polishing head, thereby promoting the polishing effect of the first semiconductor wafer 100. The polishing slurry may also include a corrosive liquid to enhance polishing efficiency. In some other embodiments, the polishing process (e.g., a CMP process) can form a flat top surface of the first top dielectric layer 111 while achieving slight recesses in the first conductive interconnect structure 112 (e.g., on a scale of a few nanometers). The height difference between the top surface of the first top dielectric layer 111 and the top surface of the first conductive interconnect structure 112 relative to the carrier 120 may be caused by the difference in material composition between the first top dielectric layer 111 and the first conductive interconnect structure 112. Furthermore, the first semiconductor wafer 100 can be cleaned with deionized water throughout the polishing process, which helps prevent unwanted surface contamination.

[0026] Next, as Figure 1D As shown, a surface treatment process, such as a plasma surface activation process, is performed on the top surface of the first semiconductor wafer 100 to prepare the top surface of the first semiconductor wafer 100 for subsequent bonding processes.

[0027] like Figure 1E As shown, a second semiconductor wafer 200 is provided. In some embodiments, the first semiconductor wafer 100 and the second semiconductor wafer 200 may include memory chips, such as high-bandwidth memory (HBM) or dynamic random access memory (DRAM).

[0028] The second semiconductor wafer 200 has a similar structure and composition to the first semiconductor wafer 100. More specifically, the second semiconductor wafer 200 includes a second wafer body 210, the second wafer body 210 having a... Figure 1EThe top surface is shown facing upwards. The second wafer body 210 also includes a bottom surface opposite the top surface. The second semiconductor wafer 200 may also include a second top dielectric layer 211 on the top surface of the second wafer body 210 and a second bottom dielectric layer on the bottom surface of the second wafer body 210. Furthermore, the second semiconductor wafer 200 may include a plurality of second semiconductor cells 201 and a plurality of second dicing regions 202. Each of the second dicing regions 202 is located between two adjacent second semiconductor cells 201. Additionally, each of the second semiconductor cells 201 may further include a set of second conductive interconnect structures 212 extending through the second semiconductor wafer 200. Next, an additional carrier 220 is attached to the bottom surface of the second semiconductor wafer 200. Next, the top portion of the second semiconductor wafer 200 may be polished, for example, by a chemical mechanical polishing process, to form a relatively flat top surface of the second semiconductor wafer 200.

[0029] Next, as Figure 1F As shown, the plurality of second semiconductor units 201 are individually diced from the second semiconductor wafer 200 into a plurality of second semiconductor dies 221. Specifically, for example, the second semiconductor units 201 can be individually diced at the second dicing area 202 using a saw blade, a laser cutting tool, or a plasma dicing process. Next, as... Figure 1G As shown, a surface treatment process, such as plasma surface activation, is performed on the top surface of the second semiconductor die 221 to prepare the top surface for subsequent bonding processes. In some other embodiments, a polishing process may be performed after the dicing process of the second semiconductor wafer 200 to improve the planarization of the semiconductor die after the dicing process, since fragments or debris may be generated during the dicing process.

[0030] In some preferred embodiments, the first semiconductor wafer 100 and the second semiconductor wafer 200 can be polished simultaneously, and the surfaces of the first semiconductor wafer 100 and the second semiconductor die 221 can be activated simultaneously. Thus, the first semiconductor wafer 100 and the second semiconductor die 221 can have similar surface conditions for subsequent bonding processes. It is also understood that the polishing processes and / or surface treatment processes of the first semiconductor wafer 100 and the second semiconductor wafer 200 / second semiconductor die 221 can be performed sequentially.

[0031] Next, as shown in 1H, the second semiconductor die 221 is flipped so that its top surface faces the top surface of the first semiconductor wafer 100. Then, each second semiconductor die 221 is vertically aligned with one of the plurality of first semiconductor cells 101 of the first semiconductor wafer 100 and placed on top of the first semiconductor cell 101, such that they are stacked together. Specifically, each set of first conductive interconnect structures 112 included in the respective first semiconductor cell 101 is vertically aligned with a set of second conductive interconnect structures 212 included in the respective second semiconductor die 221. In some embodiments, alignment marks may be formed on the first semiconductor cell 101 and / or the second semiconductor die 221 to ensure precise alignment between the plurality of sets of first conductive interconnect structures 112 and the plurality of sets of second conductive interconnect structures 212. Furthermore, the top surfaces of the first top dielectric layer 111 and the second top dielectric layer 211 are in direct contact with each other.

[0032] Next, a hybrid bonding process is performed to bond each of the second semiconductor dies 221 to one of the first semiconductor cells 101. Specifically, the first top dielectric layer 111 of the first semiconductor wafer 100 is bonded to the second top dielectric layer 211, and the set of first conductive interconnect structures 112 in each first semiconductor cell 101 is vertically aligned and bonded to the set of second conductive interconnect structures 212 in one of the second semiconductor dies 221. Details of the hybrid bonding process are described in... Figure 1H and 1I As shown in the image.

[0033] like Figure 1H As shown, in some embodiments, after the second semiconductor die 221 is placed onto the corresponding first semiconductor cell 101, the second semiconductor die 221 is pressed against the first semiconductor cell 101 by a bonding head 214. During this process, adhesion occurs between the polished top surfaces of the first semiconductor cell 101 and the second semiconductor die 221. This generates a strong attraction between the surfaces and closes the gap from the center region to the edge of each pair of aligned first semiconductor cells 101 and second semiconductor dies 221. This process can be performed at room temperature to ensure direct and close contact between the top surfaces of the first semiconductor cells 101 and the second semiconductor die 221, which serve as the bonding surfaces for the subsequently formed hybrid bonding structure.

[0034] Next, as Figure 1IAs shown, an annealing process is performed on the second semiconductor die 221 and the first semiconductor cell 101. A fusion bond can be established between the plurality of first conductive interconnect structures 112 and the plurality of second conductive interconnect structures 212 to form a strong metal-to-metal interconnect. Furthermore, the first top dielectric layer 111 and the second top dielectric layer 211 can expand to allow for closer contact between them, thereby forming sufficient bonding therebetween. In this way, a durable hybrid bond can be formed, combining dielectric-to-dielectric bonding between the first top dielectric layer 111 and the second top dielectric layer 211 with metal-to-metal bonding between the first conductive interconnect structure 112 and the second conductive interconnect structure 212. In some embodiments, the annealing process is performed at a temperature between 250°C and 400°C and can last for 20 to 230 minutes.

[0035] It is understood that the steps and conditions described above for hybrid bonding are exemplary and not mandatory. In some other embodiments, the first conductive interconnect structure 112 and the second conductive interconnect structure 212 may have slight recesses at their top surfaces, and their top surfaces may be lower than the top surfaces of the first top dielectric layer 111 and the second top dielectric layer 211, respectively. In these cases, an initial bond can be established when the first top dielectric layer 111 and the second top dielectric layer 211 are in direct contact with each other at room temperature. Next, since the coefficients of thermal expansion of the first conductive interconnect structure 112 and the second conductive interconnect structure 212 are greater than those of the first top dielectric layer 111 and the second top dielectric layer 211, a heating process can be applied to close the gap between the first conductive interconnect structure 112 and the second conductive interconnect structure 212. Then, an annealing process is performed to form a hybrid bond.

[0036] Next, as Figure 1J As shown, the plurality of first semiconductor cells 101 of the first semiconductor wafer 100 are diced into a plurality of first semiconductor dies 121. Each of the first semiconductor dies 121 is thus bonded to one of the second semiconductor dies 221. In this manner, a plurality of double-layer interconnect sub-stacks 231 are formed, each of which includes a first semiconductor die 121 and a second semiconductor die 221 bonded thereon. The plurality of first semiconductor cells 101 can be diced along the plurality of first dicing regions 102 of the first semiconductor wafer 100.

[0037] In this embodiment, hybrid bonding allows for direct connection between the first semiconductor die 121 and the second semiconductor die 221, which enables the subsequently formed electronic devices to achieve improved performance and reduced power consumption. Furthermore, interconnects with extremely fine pitch are used to establish electrical connections between these semiconductor dies.

[0038] Next, a testing process is performed on each of the plurality of double-layer interconnect sub-stackings 231. During this process, each of the plurality of double-layer interconnect sub-stackings 231 may undergo various types of electrical or non-electrical tests to test their characteristics and defects, such as whether there is a lack of alignment accuracy between the first semiconductor die 121 and the second semiconductor die 221. In this way, qualified double-layer interconnect sub-stackings with satisfactory bonding quality and electrical performance are selected, while unqualified double-layer interconnect sub-stackings with problematic bonding defects can be discarded. Next, two of the qualified double-layer interconnect sub-stackings are further bonded together. In some embodiments, the two qualified double-layer interconnect sub-stackings are bonded by hybrid bonding, the hybrid bonding having with Figure 1H and Figure 1I The structure and forming process shown are similar to those described, and will not be described in detail here. Therefore, an interconnect stack 240 is formed, as shown in 1K.

[0039] In some embodiments, additional qualified dual-layer interconnect sub-stacks 231 may be further stacked onto interconnect stack 240 to form a larger interconnect stack with six or more layers by, for example, hybrid bonding. It is also understood that, after each bonding process, the formed interconnect stack may be subjected to testing and sorting processes.

[0040] In some other embodiments, after forming a plurality of four-layer interconnect stacks 240, each of the four-layer interconnect stacks may be subjected to another testing process to select qualified four-layer interconnect stacks. At least two qualified four-layer interconnect stacks 240 are further bonded together, for example, by hybrid bonding, to form a highly integrated interconnect stack with multiple layers.

[0041] In this embodiment, a testing process is performed after two semiconductor dies are vertically aligned and bonded using hybrid bonding. In this way, double-layer interconnect sub-stackings with defects and poor electrical performance can be identified and discarded at an early stage, minimizing losses in subsequent manufacturing of interconnect stacks with more layers. In some preferred embodiments, testing and sorting processes can be performed after each hybrid bonding process between two semiconductor dies or two interconnect sub-stackings. Therefore, the resulting interconnect stack can have improved yield and reduced cost.

[0042] In some embodiments, the plurality of first semiconductor dies 121 may have dimensions similar to those of the plurality of second semiconductor dies 221. That is, the plurality of second dicing regions 202 may have dimensions similar to those of the plurality of first dicing regions 102. In some alternative embodiments, the plurality of second semiconductor dies 221 may have dimensions smaller than those of the plurality of first semiconductor dies 121, and the plurality of second dicing regions 202 may have dimensions larger than those of the plurality of first dicing regions 102. Examples of this alternative embodiment are provided below.

[0043] Figure 2 The diagram illustrates a single-cutting step of a first semiconductor cell in a method for forming an interconnect stack according to a second embodiment of this application.

[0044] like Figure 2 As shown, a first semiconductor wafer 300 and a second semiconductor wafer are provided. The first semiconductor wafer 300 may include a plurality of first semiconductor cells and a plurality of first dicing regions 302. Each first dicing region 302 is located between two adjacent first semiconductor cells. Similarly, the second semiconductor wafer may include a plurality of second semiconductor cells and a plurality of second dicing regions. The size of the plurality of second dicing regions is larger than the size of the plurality of first dicing regions 302, and the size of the plurality of second semiconductor cells is smaller than the size of the plurality of first semiconductor cells.

[0045] In this embodiment, the plurality of second semiconductor units of the second semiconductor wafer are individually diced along the second dicing region of the second semiconductor wafer. Therefore, a plurality of second semiconductor dies 421 are formed with relatively large dicing gaps 402, wherein each dicing gap 402 is located between two adjacent second semiconductor dies 421.

[0046] Therefore, as Figure 2 As shown, in a single-cutting process that separates a first semiconductor wafer 300 into multiple first semiconductor dies, for example using a saw blade, a laser cutting tool, or a plasma dicing process, the first semiconductor wafer 300 is single-cut along a first cutting region 302 at an exposed cutting gap 402. Since the second cutting regions have a larger size than the plurality of first cutting regions 302, the target area for the single-cutting process on the first semiconductor wafer 300 is smaller than the corresponding exposed cutting gaps 402 above them. Thus, when the single-cutting process is performed along the first cutting regions, the second semiconductor dies 421 can be unaffected due to the relatively large cutting gaps 402 between adjacent second semiconductor dies 421.

[0047] Further details of the method for forming an interconnect stack in the second embodiment can be found in... Figures 1A to 1KThe details of the method shown are the same and will not be repeated here. Finally, an interconnect stack is formed having two layers of interconnect sub-stacks bonded together, and each of the two layers of interconnect sub-stacks may include a semiconductor die with a smaller size and another semiconductor die with a larger size bonded thereto.

[0048] In some alternative embodiments, the interconnect stack may include both hybrid bonding and solder bump bonding to bond the multilayer semiconductor dies together, which will be detailed below.

[0049] Figures 3A to 3D The various steps of a method for forming an interconnect stack according to a third embodiment of this application are shown.

[0050] like Figure 3A As shown, a first semiconductor wafer 500 is provided. The first semiconductor wafer 500 includes a first wafer body 510, the first wafer body 510 having a... Figure 3A The top surface is shown facing upwards. The first wafer body 510 also includes a bottom surface opposite the top surface. The first semiconductor wafer 500 includes a first top dielectric layer 511 on the top surface of the first wafer body 510 and a first bottom dielectric layer on the bottom surface of the first wafer body 510. Furthermore, the first semiconductor wafer 500 includes a plurality of first semiconductor cells 501 and a plurality of first dicing regions 502. Each of the first dicing regions 502 is located between two adjacent first semiconductor cells 501. Each of the first semiconductor cells 501 may further include a set of first conductive interconnect structures 512 extending through the first semiconductor wafer 500.

[0051] Additionally, each of the first semiconductor cells 501 may further include a plurality of solder bumps 515, each of which is formed on the bottom surface of a first conductive interconnect structure 512. In some embodiments, the solder bumps 515 may be exposed from the first bottom dielectric layer. It is also understood that at least a portion of the solder bumps 515 may be embedded within the first bottom dielectric layer, while at least a portion of the bottom surface of the solder bumps 515 remains exposed from the first bottom dielectric layer for external electrical connection.

[0052] Next, the carrier is attached to the bottom surface of the first semiconductor wafer 500. In some preferred embodiments, the carrier may include a flexible material such as silicone resin, which can deform to accommodate solder bumps 515.

[0053] like Figure 3BAs shown, a second semiconductor wafer is provided. The second semiconductor wafer includes a second wafer body 610 having a top surface and a bottom surface opposite the top surface. The second semiconductor wafer includes a second top dielectric layer 611 on the top surface of the second wafer body 610 and a second bottom dielectric layer on the bottom surface of the second wafer body 610. Furthermore, the second semiconductor wafer may include a plurality of second semiconductor cells and a plurality of second dicing regions. Each second semiconductor cell may further include a set of second conductive interconnect structures 612 extending through the second semiconductor wafer. Next, the plurality of second semiconductor cells are individually diced from the second semiconductor wafer into a plurality of second semiconductor dies 621.

[0054] It is understood that polishing and plasma surface activation processes can be performed on the first semiconductor wafer 500 and the second semiconductor wafer / second semiconductor die at appropriate steps, and these appropriate steps can be similar to... Figure 1C , 1D Or those steps shown in 1G.

[0055] Next, as Figure 3C As shown, a hybrid bonding process is implemented to bond each second semiconductor die 621 to a first semiconductor cell 501. Specifically, the first top dielectric layer 511 and the second top dielectric layer 611 are vertically aligned and bonded, and the plurality of first conductive interconnect structures 512 and the plurality of second conductive interconnect structures 612 are vertically aligned and bonded.

[0056] Then, the plurality of first semiconductor cells 501 of the first semiconductor wafer 500 are individually diced into a plurality of first semiconductor dies. This forms a plurality of double-layer interconnect sub-stackings, each of which includes a first semiconductor die with exposed solder bumps 515 and a second semiconductor die 621 bonded thereto by hybrid bonding. A testing process is performed to select qualified double-layer interconnect sub-stackings. Then, at least two of the qualified double-layer interconnect sub-stackings are stacked together, with solder bumps 515 disposed therebetween. The solder bumps 515 can then be reflowed to establish an electrical connection between the two adjacent qualified double-layer interconnect sub-stackings. Thus, an interconnect stack 640 with hybrid bonding and solder bump bonding (as shown in 3D) is formed, which allows for flexibility in improving the electrical connection pattern and layout between the stacked semiconductor dies according to actual requirements.

[0057] Finally, an encapsulation layer 635 is formed between at least two adjacent qualified double-layer interconnect sub-stacks to encapsulate the plurality of solder bumps 515.

[0058] In addition to the die-to-wafer hybrid bonding process described with reference to the above embodiments, a wafer-to-wafer bonding process can also be used to form interconnect stacks, which will be detailed below.

[0059] More specifically, a first semiconductor wafer and a second semiconductor wafer can first be bonded using hybrid bonding, such that each second semiconductor cell is vertically aligned and bonded to a corresponding first semiconductor cell. Then, the first semiconductor cells of the first semiconductor wafer and the second semiconductor cells of the second semiconductor wafer are simultaneously diced into multiple first semiconductor dies and multiple second semiconductor dies to form multiple double-layer interconnect sub-stackings. Next, each double-layer interconnect sub-stacking is tested to select qualified double-layer interconnect sub-stackings from the multiple double-layer interconnect sub-stackings. Finally, at least two of the qualified double-layer interconnect sub-stackings are bonded together to form an interconnect stack.

[0060] In some other embodiments, die-to-die bonding can also be used to form interconnect stacks. More specifically, firstly, a first semiconductor wafer and a second semiconductor wafer are individually diced into first semiconductor dies and second semiconductor dies, respectively. Then, each of the first semiconductor dies is bonded to one of the second semiconductor dies to form a double-layer interconnect sub-stack. Next, each of the double-layer interconnect sub-stacks is tested to select qualified double-layer interconnect sub-stacks. Finally, at least two of the qualified double-layer interconnect sub-stacks are bonded together to form an interconnect stack.

[0061] Although exemplary interconnect stacks and methods for forming interconnect stacks have been described in conjunction with corresponding figures, those skilled in the art will understand that modifications and adaptations can be made to the interconnect stacks and methods without departing from the scope of the invention.

[0062] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and alterations can be made thereto, and additional embodiments can be implemented, without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art upon consideration of the description and practice of one or more embodiments of the invention disclosed herein. Therefore, the examples in this application and herein are intended to be considered exemplary only, and the true scope and spirit of the invention are indicated by the list of exemplary claims appended.

Claims

1. A method for forming an interconnect stack, characterized in that, include: A first semiconductor wafer is provided, the first semiconductor wafer having a first top dielectric layer at its top surface and a first bottom dielectric layer at its bottom surface, wherein the first semiconductor wafer includes a plurality of first semiconductor units, each first semiconductor unit having a set of first conductive interconnect structures extending through the first semiconductor wafer; A second semiconductor wafer is provided, the second semiconductor wafer having a second top dielectric layer at its top surface and a second bottom dielectric layer at its bottom surface, wherein the second semiconductor wafer includes a plurality of second semiconductor units, each second semiconductor unit having a set of second conductive interconnect structures extending through the second semiconductor wafer; The plurality of second semiconductor units of the second semiconductor wafer are individually diced into a plurality of second semiconductor bare dies; Each of the plurality of second semiconductor dies is vertically aligned with one of the plurality of first semiconductor units of the first semiconductor wafer to stack them together; By using hybrid bonding, each of the plurality of second semiconductor dies is bonded to one of the plurality of first semiconductor units, such that the second top dielectric layer of the second semiconductor die and the set of second conductive interconnect structures are vertically aligned and bonded to the first top dielectric layer and the set of first conductive interconnect structures of the first semiconductor unit, respectively. The plurality of first semiconductor units of the first semiconductor wafer are individually diced into a plurality of first semiconductor dies, such that each of the plurality of first semiconductor dies is bonded to one of the plurality of second semiconductor dies to form a plurality of double-layer interconnect sub-stacks; Test each of the plurality of double-layer interconnect sub-stacks to select a plurality of qualified double-layer interconnect sub-stacks from the plurality of double-layer interconnect sub-stacks; and At least two qualified two-layer interconnect sub-stacks are bonded together to form the interconnect stack.

2. The method according to claim 1, characterized in that, The first semiconductor wafer further includes a plurality of first dicing regions, each of the plurality of first dicing regions being located between two adjacent first semiconductor units; and the second semiconductor wafer further includes a plurality of second dicing regions, each of the plurality of second dicing regions being located between two adjacent second semiconductor units.

3. The method according to claim 2, characterized in that, The size of the second dicing region is larger than the size of the first dicing region, and the size of the second semiconductor unit is smaller than the size of the first semiconductor unit.

4. The method according to claim 2, characterized in that, The process of dicing the plurality of second semiconductor units of the second semiconductor wafer into a plurality of second semiconductor dies includes: dicing the plurality of second semiconductor units along the plurality of second dicing regions of the second semiconductor wafer; and The process of dicing the plurality of first semiconductor units of the first semiconductor wafer into a plurality of first semiconductor dies includes: dicing the plurality of first semiconductor units along the plurality of first dicing regions of the first semiconductor wafer.

5. The method according to claim 1, characterized in that, Before vertically aligning each of the plurality of second semiconductor dies with one of the plurality of first semiconductor cells of the first semiconductor wafer to stack them together, the method further includes: Plasma surface activation is performed on the top surface of the first semiconductor wafer; and plasma surface activation is performed on the top surfaces of the plurality of second semiconductor dies.

6. The method according to claim 5, characterized in that, The process of bonding each of the plurality of second semiconductor dies to one of the plurality of first semiconductor units further includes: The top surface of each of the plurality of second semiconductor dies is bonded to the top surface of one of the plurality of first semiconductor cells.

7. The method according to claim 1, characterized in that, The process of bonding each of the plurality of second semiconductor dies to one of the plurality of first semiconductor cells using hybrid bonding includes: Pressing the plurality of second semiconductor dies against the plurality of first semiconductor units; and Annealing process is performed on the plurality of second semiconductor dies and the plurality of first semiconductor units.

8. The method according to claim 1, characterized in that, The process of bonding at least two qualified bilayer interconnect sub-stacks together includes: bonding at least two qualified bilayer interconnect sub-stacks by using hybrid bonding.

9. The method according to claim 1, characterized in that, Each of the plurality of first semiconductor units further includes: a plurality of solder bumps, each solder bump being formed on the bottom surface of one of the plurality of first conductive interconnect structures; and The process of bonding at least two qualified double-layer interconnects together includes bonding at least two qualified double-layer interconnects together by soldering.

10. The method according to claim 9, characterized in that, After bonding at least two qualified double-layer interconnect sub-stacks together, the method further includes forming an encapsulation layer between at least two adjacent qualified double-layer interconnect sub-stacks to encapsulate the plurality of solder bumps.

11. A method for forming an interconnect stack, characterized in that, include: A first semiconductor wafer is provided, the first semiconductor wafer having a first top dielectric layer at its top surface and a first bottom dielectric layer at its bottom surface, wherein the first semiconductor wafer includes a plurality of first semiconductor units, each first semiconductor unit having a set of first conductive interconnect structures extending through the first semiconductor wafer; A second semiconductor wafer is provided, the second semiconductor wafer having a second top dielectric layer at its top surface and a second bottom dielectric layer at its bottom surface, wherein the second semiconductor wafer includes a plurality of second semiconductor units, each second semiconductor unit having a set of second conductive interconnect structures extending through the second semiconductor wafer; The second semiconductor wafer is vertically aligned with the first semiconductor wafer to stack them together; By using hybrid bonding, each of the plurality of second semiconductor units is bonded to one of the plurality of first semiconductor units, such that the second top dielectric layer of the second semiconductor unit and the set of second conductive interconnect structures are vertically aligned and bonded to the first top dielectric layer and the set of first conductive interconnect structures of the first semiconductor unit, respectively. The plurality of first semiconductor units of the first semiconductor wafer and the plurality of second semiconductor units of the second semiconductor wafer are individually diced into a plurality of first semiconductor dies and a plurality of second semiconductor dies, such that each of the plurality of first semiconductor dies is bonded to one of the plurality of second semiconductor dies to form a plurality of double-layer interconnect sub-stacks; Test each of the plurality of double-layer interconnect sub-stacks to select a plurality of qualified double-layer interconnect sub-stacks from the plurality of double-layer interconnect sub-stacks; and At least two qualified two-layer interconnect sub-stacks are bonded together to form the interconnect stack.

12. An interconnect stack, characterized in that, include: A first double-layer interconnect sub-stack and a second double-layer interconnect sub-stack are bonded together, wherein each of the first double-layer interconnect sub-stack and the second double-layer interconnect sub-stack comprises: A first semiconductor die, having a first top dielectric layer at its top surface and a first bottom dielectric layer at its bottom surface, and having a set of first conductive interconnect structures extending through the first semiconductor die; as well as The second semiconductor die has a second top dielectric layer on its top surface and a second bottom dielectric layer on its bottom surface, and the second semiconductor die has a set of second conductive interconnect structures extending through the second semiconductor die; and The first semiconductor die is bonded to the second semiconductor die by hybrid bonding, such that the first top dielectric layer of the first semiconductor die and the set of first conductive interconnect structures are vertically aligned and bonded to the second top dielectric layer and the set of second conductive interconnect structures of the second semiconductor die, respectively.

13. The interconnect stack according to claim 12, characterized in that, The size of the second semiconductor die is smaller than the size of the first semiconductor die.

14. The interconnect stack according to claim 12, characterized in that, The first double-layer interconnect sub-stack and the second double-layer interconnect sub-stack are bonded together by hybrid bonding.

15. The interconnect stack according to claim 12, characterized in that, The first double-layer interconnect sub-stack and the second double-layer interconnect sub-stack are bonded together by a plurality of solder bumps.

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