Processor resource isolation

Abstract

A method for allocating processor resources is described. A coloring scheme for the processor resources is obtained, wherein the coloring scheme has a coloring function that indexes both shared and private resources of the processor and provides protection against information leakage through the processor's shared resources between trust domains. According to the coloring scheme, a first set of colors from a plurality of unassigned colors is assigned to a first trust domain. According to the first set of colors, first resources are allocated to the first trust domain, wherein each of the first resources has an assigned color from the first set of colors.

Description

Background Technology

[0001] Cloud computing aims to provide scalable and cost-effective resources to a wide range of tenants. This involves sharing resources among tenants (e.g., trust domains) while isolating tenants from each other and from the cloud provider to ensure their security. For example, a modern cloud processor may include hundreds of physical threads sharing terabytes of memory, all of which can be flexibly assigned to many independent trust domains (e.g., virtual machines, containers, etc.).

[0002] Cloud security typically relies on architectural isolation between trust domains, implemented by the underlying hardware and, in the case of virtual machines, by the hypervisor through access control and permissions. For example, certain resources may be private to processor cores (e.g., registers, L1 cache, L2 cache), and these cores may be exclusively allocated to individual virtual machines. Therefore, virtual machines cannot read or write to private registers within different processor cores or memory addresses allocated to different virtual machines. Unfortunately, implicit sharing of other resources within the processor (such as caches, buffers, cache coherence directories, and memory banks) can also allow information leakage between different virtual machines or other trust domains. For example, information about the first virtual machine can be inferred (e.g., by a second virtual machine) by analyzing time latency associated with the use of shared resources, analyzing eviction sets of shared caches, or through other side-channel attacks.

[0003] Embodiments have been described in consideration of these and other general considerations. Furthermore, although relatively specific problems have been discussed, it should be understood that the embodiments should not be limited to solving the specific problems identified in the background art. Summary of the Invention

[0004] Various aspects of this disclosure relate to improving isolation between trust domains, even in the presence of available side channels.

[0005] In one aspect, a method for allocating processor resources is provided. A coloring scheme for the processor resources is obtained, wherein the coloring scheme has a coloring function that indexes the processor's shared and private resources and provides protection against information leakage through the processor's shared resources between trust domains. A first set of colors from a plurality of unassigned colors is assigned to a first trust domain according to the coloring scheme. First resources are allocated to the first trust domain according to the first set of colors, wherein each of the first resources has an assigned color from the first set of colors.

[0006] In another aspect, a computing device is provided for allocating processor resources. The computing device includes a processor and a non-transient computer-readable storage, wherein the processor is configured to execute instructions from the storage, the instructions configuring the computing device to: identify a first linear function indexing a first resource in the processor resources, wherein the first resource is a first shared resource of the processor; identify a second linear function indexing a second resource in the processor resources; combine the first and second linear functions to generate a coloring function that indexes the first shared resource and the second resource based on whether the second resource is a second shared resource or a private resource, wherein the generated coloring function maximizes the available colors of a coloring scheme and avoids partitioning private resources; assigns a first set of colors from a plurality of unassigned colors to a first trust domain according to the coloring scheme; and allocates at least some of the processor resources in the processor resources to the first trust domain using the coloring function and according to the first color set, wherein each of the allocated resources has an assigned color from the first color set, and provides protection against information leakage between the first trust domain and one or more second trust domains.

[0007] In another aspect, a method for allocating processor resources is provided. A first linear function is identified to index a first resource among the processor resources, wherein the first resource is a first shared resource of the processor. A second linear function is identified to index a second resource among the processor resources. The first and second linear functions are combined to generate a coloring function that indexes the first shared resource and the second resource based on whether the second resource is a second shared resource or a private resource, wherein the generated coloring function maximizes the available colors of the coloring scheme and avoids partitioning private resources. A first set of colors from a plurality of unassigned colors is assigned to a first trust domain according to the coloring scheme. At least some processor resources among the processor resources are allocated to the first trust domain using the coloring function and according to the first color set, wherein each of the allocated resources has an assigned color from the first color set, and protection against information leakage between the first trust domain and one or more second trust domains is provided.

[0008] This summary is provided to introduce, in a simplified form, the concepts further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. Attached Figure Description

[0009] Non-restrictive and non-exhaustive examples are described with reference to the following figures.

[0010] Figure 1A block diagram of an example processor based on one aspect is shown, in which resources can be allocated to various trust domains.

[0011] Figure 2 A block diagram of an example system of hardware and software for resource allocation is shown.

[0012] Figure 3 A schematic diagram of an example indexing function based on one aspect of processor resources is shown.

[0013] Figure 4 A schematic diagram of an example memory allocation based on one aspect is shown.

[0014] Figure 5 A flowchart of an example method for allocating processor resources according to an example embodiment is shown.

[0015] Figure 6 A flowchart of another example method for allocating processor resources according to an example embodiment is shown.

[0016] Figure 7 This is a block diagram illustrating example physical components of a computing device that can implement various aspects of the present disclosure.

[0017] Figure 8 It is a simplified block diagram of a computing device that can implement the various aspects of this disclosure. Detailed Implementation

[0018] In the following detailed description, reference is made to the accompanying drawings, which form a part of the present invention, and specific embodiments or examples are illustrated therein. These aspects may be combined, other aspects may be utilized, and structural changes may be made without departing from this disclosure. The embodiments may be practiced as methods, systems, or devices. Therefore, the embodiments may take the form of hardware implementations, entirely software implementations, or implementations combining software and hardware aspects. Consequently, the following detailed description should not be considered limiting, and the scope of this disclosure is defined by the appended claims and their equivalents.

[0019] This disclosure describes various examples of resource allocation performed on a processor in a manner that improves isolation between trust domains by preventing information leakage via side-channel attacks. A processor may be configured to have, or otherwise have, various private resources (“private resources”) and shared resources (“shared resources”). These resources can be higher-level resources (such as memory or processor cores) or microarchitectural resources (such as chiplet catalogs and caches). While private resources may be unique to the processor core and thus provide a degree of isolation, information about the processor core's operation can still be inferred from information about the shared resources because data is stored and managed by shared resources (e.g., system memory via different levels of caches) to reach the processor core, thus potentially making it vulnerable to any of the various side-channel attacks. To improve isolation between different trust domains, a coloring scheme is utilized to provide further separation of data and reduce information leakage. Instead of allocating free memory pages that can share the same cache line, the coloring scheme described herein (alternatively or additionally) is used to ensure that memory pages allocated for a trust domain are isolated from other trust domains, even if the data in the allocated memory pages is transferred via the memory subsystem (e.g., from system memory to L3 cache, L2 cache, etc.).

[0020] A coloring scheme can be applied to both shared and private resources (e.g., processor resources) and configured to promote flexibility in resource allocation while reducing or avoiding performance penalties typically caused by resource subdivision (e.g., subdivision of private resources that are not shared). A coloring scheme for processor resources is obtained. This coloring scheme has coloring functions that index both shared and private resources of the processor and provide protection against information leakage between trust domains via shared resources of the processor. A first set of colors from multiple unassigned colors is assigned to a first trust domain according to the coloring scheme. First resources are allocated to the first trust domain according to the first color set, wherein each of the first resources has the assigned color from the first color set. Improved isolation against information leakage is provided by implementing the use and allocation of resources that are associated only with specific colors of the first trust domain. Therefore, when resources are allocated to a second trust domain (e.g., according to a second set of memory colors), privacy between trust domains is improved due to adherence to the color set corresponding to each trust domain within the trust domain.

[0021] This article describes this and many other aspects of computing devices. For example, Figure 1A block diagram of an example processor 100 according to one aspect is shown, in which resources can be allocated to various trust domains. Processor 100 is a multi-core processor with multiple microarchitectural resources arranged in multiple chiplets (e.g., chiplet 110 and one or more other chiplets 120). Figure 1 In the example shown, chiplets 110 and 120 typically have the same architecture, so only chiplet 110 is described in detail. In other examples, processor 100 may have two or more different chiplet architectures for a more general resource allocation, such as high-power processing chiplets for complex processing tasks (e.g., operating at 6 GHz) and low-power processing chiplets for simple processing tasks and reduced power consumption (e.g., operating at 2 GHz, buck). As another example, processor 100 may be a monolithic design and therefore may not have multiple chiplets and / or may have different architectures. Therefore, it should be understood that while examples are described in the context of multiple chiplets and corresponding architectures, similar aspects can be used to allocate computing resources for any computing hardware in a variety of computing hardware.

[0022] Typically, the chiplet 110 includes private microarchitecture resources (“private resources”) and shared microarchitecture resources (“shared resources”). Private resources may vary depending on the processor implementation, but typically include processor cores, core-specific registers, core-specific caches (e.g., L1 data cache, L1 instruction cache, L2 cache), etc. Shared resources may also vary depending on the processor implementation, but typically include shared caches (e.g., L3 cache shared by two or more cores or chiplets), cache coherence directories, system memory, or memory channels (e.g., for dynamic random access memory), etc. Figure 1 In the example shown, chiplet 110 includes multiple cores, including core 111 (core 0) and core 112 (core 1). Each of cores 111 and 112 includes an L1 cache and an L2 cache (e.g., L1 cache 113 and L2 cache 114). In other examples, different cores within a chiplet may have different numbers or levels of cache.

[0023] exist Figure 1 In the example shown, chiplet 110 has an L3 cache slice 115 associated with core 111 and a similar L3 cache slice associated with core 112. The L3 cache can be shared between cores within chiplet 110. Although Figure 1The example shown includes one L3 cache slice per core, but the number of cache slices may be less than or greater than the number of cores within processor 100 (e.g., some cores are configured to have lower processing power and power consumption than others). Chipset 110 also includes a chipset catalog configured to manage data within private caches, such as L2 cache 114. Figure 1 In the example shown, the chiplet directory is arranged in chiplet directory slices (such as chiplet directory slice 116) distributed across the cores of processor 100, but other implementations will be apparent to those skilled in the art. Chiplet directory slice 116 is a cache coherence directory that supports data sharing between different cores within chiplet 110. Typically, chiplet directory slice 116 tracks which memory blocks are cached in each core's private cache (e.g., L2 cache).

[0024] Processor 100 also includes I / O chiplets 130 that support communication with chiplets 110 and 120. I / O chiplet 130 may also support communication between processor 100 and memory 140, such as dynamic random access memory (DRAM) banks. In some examples, I / O chiplet 130 includes a cross-chiplet directory 132 as a cache coherence directory. Similar to chiplet directory slice 116, cross-chiplet directory 132 is configured to manage data within a shareable cache, but it supports data sharing between different chiplets (i.e., chiplets 110 and 120) within processor 100.

[0025] Access to data at a memory address by a core (e.g., core 111) can be performed as follows: First, L1 cache 113 is accessed to determine if data is stored there. While accessing the L1 cache, core 111 can also identify locations within L2 cache 114 where data may be contained (e.g., by performing a virtual-to-physical address mapping). When data is not found in L1 cache 113, core 111 accesses the identified location within L2 cache 114. L1 misses that also occur in L2 cache are serviced by L3 cache slice 115. After an L3 cache miss occurs in L3 cache slice 115, core 111 probes chiplet directory slice 116. Probe hits on chiplet directory slice 116 are forwarded to cores that have cache lines in their L1 or L2 cache containing data, while probe misses are forwarded as requests to I / O chiplet 130. These requests probe across chiplet catalog 132, where a probe hit is forwarded to the chiplet owner (e.g., one of the chipsets in chiplet 120), while probe misses are served by memory 140 (e.g., via a DRAM controller, not shown). Following memory 140, data can be obtained from a disk (not shown), such as a solid-state drive (SSD), hard disk drive (HDD), or other suitable processor-readable medium, via I / O chiplet 130. As those skilled in the art will appreciate, other examples of processor 100 may have different memory request lifecycles depending on their own architecture.

[0026] Typically, the lifecycle of memory requests at several levels (L1 cache, L2 cache, L3 cache, chiplet catalog, memory) can affect resource latency observed by the processor core, allowing a first trust domain (e.g., a virtual machine or container) sharing resources with a second trust domain to use timing to predict or otherwise infer information from the shared resources servicing the requests. In some examples, these timing changes may allow memory-based side-channel attacks. To improve isolation between different trust domains and reduce the likelihood of memory-based side-channel attacks, processor 100 is configured to use a coloring scheme to provide further separation of data and reduce information leakage. The coloring scheme can be applied to both shared and private resources (e.g., based on resource requests from trust domains) and is configured to promote flexibility in resource allocation while reducing or avoiding performance penalties due to resource segmentation. Typically, the coloring scheme provides coloring functions that index both shared and private resources and provide isolation between colors. The coloring functions segment shared resources to maximize the available colors of the coloring scheme and minimize the segmentation of private resources.

[0027] Figure 2A block diagram of an example system 200 for resource allocation, based on one aspect of hardware and software, is shown. Typically, system 200 includes a hardware layer 210, a hypervisor 220 configured to manage trust domains, and one or more trust domains 230. Hardware layer 210 typically corresponds to processor 100 or other suitable computing system that can support trust domains. Hypervisor 220 is software configured to manage multiple trust domains on a single physical machine (i.e., hardware 210). In the example described herein, the trust domain is a virtual machine, but in other examples it could be a container or other software execution environment.

[0028] Hypervisor 220 allocates physical resources, such as processor cores and memory (and L3 cache partitioning in some examples), to each virtual machine. As a result of resource allocation, other microarchitectural resources may be implicitly allocated to each virtual machine. Typically, hypervisor 220 includes a memory manager 222 and a resource scheduler 224. Hypervisor 220 can also create or instantiate trust domains 230, close trust domains, and / or release resources from trust domains. Figure 2 In the example shown, hypervisor 220 creates a root virtual machine 232 and additional virtual machines 234, 236, and 238 as guest virtual machines. The root virtual machine 232 may correspond to the host operating system of hardware 210, which allows users to view the current status of hardware 210 and general information about the client virtual machines.

[0029] Memory manager 222 implements the memory coloring scheme described herein and is configured to allocate memory for virtual machines, for example, from memory 140. When data corresponding to memory addresses is routed through memory hierarchies within processor 100, the data can be mapped from a specific location within one level of the memory hierarchy to the next level according to an indexing function. To improve memory isolation, coloring functions are generated based on the indexing function of the memory hierarchy. According to the aspects described herein, the coloring functions segment shared microarchitectural resources to maximize or otherwise increase the available colors of the coloring scheme and minimize or otherwise reduce the segmentation of private microarchitectural resources, thereby ensuring that trust domains of different colors remain isolated.

[0030] Despite Figure 2The memory manager 222 is shown and described herein as an element within hypervisor 220, but other implementations of memory manager 222 may be used in other examples. In some examples, aspects of memory manager 222 are performed by different memory managers 233 within root virtual machine 232 (i.e., instead of memory manager 222). In other examples, memory manager 222 of hypervisor 220 and memory manager 233 of root virtual machine 232 cooperate to provide the features described herein with respect to memory manager 222. In one such example, memory manager 233 allocates memory but requests hypervisor 220 to map the allocated memory into the address space of a trusted domain (e.g., virtual machine 234). Memory manager 233 selects a color based on a coloring scheme and then selects a memory address within the selected color. Memory manager 222 ensures that the color of one trusted domain is not used by another trusted domain.

[0031] Resource scheduler 224 is configured to allocate processor 100 cores, chiplets, and / or other resources (or time / cycles on these resources) to virtual machines. In some examples, resource scheduler 224 partitions cores or chiplets within a processor into processor groups and then exclusively assigns processor groups to specific trust domains to improve isolation. For example, resource scheduler 224 may group cores sharing a shared L3 cache (e.g., cores 111 and 112), cores within chiplets, or chiplets within a processor. In some examples, resource scheduler 224 exclusively assigns processor groups to virtual machines throughout their lifetime.

[0032] By implementing isolation contracts for shared and private microarchitectural resources within processor 100, memory manager 222 and resource scheduler 224 together improve isolation against side-channel attacks. Typically, resources can be partitioned into computational resources (represented as hardware threads T = {t0, …, t…}). n-1}) and memory resources (represented as physical addresses M={0, …,2} m -1 To define and determine the segregation contract, mathematical partitioning is used to model exclusive allocation and association constraints.

[0033] gather S of Partition P yes S A set of disjoint, nonempty subsets whose union covers S ,Right now, P =( C i ) i∈I Among them, for all i ≠ j , Ci ∩ C j =Ø, and ∪ i∈I C i = S Each subset of the partition C i All can be called category or color A partition of a given set can be partially ordered as follows: when P Each category is included Q In the category, or (equivalently) P Two elements in the same category are also Q When in the same category, P Compare Q More detailed, recorded as .therefore, S The finest division S Each element has a singleton class, while the coarsest partition has only one class containing all elements. S Partitioning can be defined as a function. f from S The pre-image to a certain set of indices, where for each i ∈ image ( f ),category C i = f -1 ( i ),Right now, x ∈ C i If and only if f ( x )= i .

[0034] To allocate computing resources, hardware threads can be used. T Abstracting architectural primitives. For the example processor: Physical cores (e.g., cores 111 and 112) can be used to target threads. P Core ={{ t 0 , t 1} , { t 2 , t 3} ,… The cores are grouped together, with each core supporting two threads. This partitioning captures shared resources such as the L1 / L2 cache, translation back buffer (TLB), buffers, and predictor. The four-core chip can be freely divided.P Chiplet ={{ t 0 ,…, t 7} , { t 8 ,…, t 15} ,… The statement indicates that it also captures shared L3 cache and chiplet catalogs; and A complete 32-core processor can be made from P CPU ={{ t 0 ,…, t 63}} indicates that it additionally captures I / O chiplets and their sharing across chiplet directories.

[0035] For a given partition P of T, a microarchitectural resource is considered private when its implementation is confined to each category of P; otherwise, it is shared. Therefore, the L3 cache is private for chiplet partitions but shared for core partitions.

[0036] Physical memory partitioning can be defined as the preimage of a linear function, that is, from physical address... M The function to the bit vector, where each bit is defined as the XOR of some bits in the address. This is when the physical address M is interpreted as a vector space over a binary field F2. When bit-by-bit XOR (⊕) and AND (&) are used for addition and multiplication, these functions are linear mappings in a mathematical sense. Figure 3 Example indexing functions for schema pages (4K / 2M), cache sets (L2 / L3), and consistent directories (XD) are shown. Therefore, linear functions... f ( a )= a>> 12. Map memory addresses to their 4K pages (indexed by their most significant bit), and partition the physical memory. P 4K Defined as contiguous 4K pages, this reflects the typical architectural unit for memory protection. Similarly, g ( a )= a>> 21 maps addresses to huge page frame numbers and defines the partitioning of huge pages. P 2M (in P 4K P 2M ).

[0037] The system software supports different trust domains (by...) D The resource allocation of an index can be represented as a set of all resources.T ∪ M Division P D =( C d ) d∈D For each trust domain d ∈ D ,category C d Instructions assigned to d All threads and memory addresses. Resource allocation between trust domains when the use of these resources by a trust domain cannot be observed from any other trust domain. P D This can be considered isolated. Since threads and memory are typically allocated separately, they can be used independently. T and M Division P T and P M These are used to describe their allocation constraints, which will be implemented at runtime by the memory manager 222 and the resource scheduler 224. T ∪ M The final allocation of all resources is denoted as . Refine the relationships ( This expresses the phenomenon that resources are redistributed over time, leading to... P D System invariants that change. For example, This indicates that computing resources are allocated at the core granularity (i.e., cores are never split across trust domains), and memory is allocated at the 4K page granularity (i.e., pages are never split across trust domains). This indicates that computing resources are allocated at the chip-level granularity, while memory is allocated at the page-level granularity.

[0038] The allocation constraints that provide microarchitectural isolation between trust domains can be referred to as contracts in this paper. The allocation of P to the trust domain D If it is isolated, then divide. It is a resource isolation contract. Although the contract... Requiring all resources allocated to a single trust domain to be isolated is not very useful. Instead, isolation contracts are expected to provide as much flexibility and performance as possible. Even using core partitioning or chiplet partitioning is often insufficient on its own, as any remaining shared microarchitectural resources (such as cache sets and directory sets) can still create observable side-channels and break isolation. These side-channels can be prevented by using memory partitioning (also known as memory coloring using a coloring scheme).

[0039] The corresponding memory partition P M The following constraints are provided: P M It conforms to all architectural constraints, such as supporting page-based allocation: P 4K P M And ideally it is P 2M P M ; P M The partitioning is used to allocate all shared microarchitectural resources necessary to achieve isolation; and P M No private microarchitecture resources (such as L2 cache) will be allocated to avoid performance degradation.

[0040] To create isolated memory partitions, different resources, such as pages and cache sets, can be partitioned simultaneously. However, simultaneous partitioning can be viewed as a union of partitions. Given two partitions P and Q, their union P... Q is the finest division, coarser than both P and Q. For example, suppose... P L3 Divide the L3 cache into different cache groups. P L3 P 4K The partitioning is captured jointly within the constraints of the 4K page architecture, and this is done in the most granular way. Therefore, it provides the maximum number of colors to prevent L3 leaks while retaining the flexibility of the memory manager 222 in memory allocation. In form, If and only if P L3 P M and P 4K P M For example from Figure 3 As can be seen, indexing functions are actually used. h ( a )=( a i ) i=12..20 These two constraints can be achieved. On the other hand, partitioning... P L3 P 2M Demanding the partitioning of the L3 cache and the allocation of huge pages might be too demanding, as each huge page would span all L3 cache sets. Therefore, That is, dividing among multiple domains. M This is not desirable.

[0041] An algorithm is provided that efficiently identifies elements indexed by a linear indexing function. f and g Any two partitions defined P f and P g The union of these two points relies on two insights from linear algebra: 1. As a linear function f and g The partitioning of preimages can be expressed using their kernels, that is, f and g Mapped to a subspace of zero. 2. These divisions joint The corresponding core can be used sum To express. For example, the algorithm calculates f and g The basis of the kernel is then calculated, and a linear function representing their sum is computed. h Each step is completed by applying Gaussian elimination once.

[0042] The partitioning of private resources can be undesirable, leading to performance degradation. For example, suppose chiplet allocation is performed using partition Pµ to eliminate side-channeling caused by shared microarchitecture resources µ (e.g., across chiplet catalog 132), then color C ∈ Pµ could be assigned to a trust domain. However, the L3 cache is chiplet-private, so it is expected that the trust domain can fully utilize its cache set. Therefore, if a trust domain has a working set that fits just right for the L3 cache, but its color... C If it only spans half of the L3 cache set, its performance will degrade. To limit the performance degradation, each color C assigned to the trust domain should be large enough to span all its private resources, which may involve finding a coarser partition than Pµ with fewer colors than theoretically possible.

[0043] Two partitions P and Q of a set are orthogonal, denoted as (P⊥Q), if for all colors C0, C1 ∈ P and C2, C3 ∈ Q, then we have |C0∩C2| = |C1∩C3|. Specifically, a partition is defined by a linear function operating on disjoint bits of an address (e.g., ...). P L3 and P 2MThe indexes are orthogonal. This may help explain why cache indexing functions typically depend on the low-order bits of the address, such that, for example, each allocated 2MB page is split across all cache sets. More generally, given a linear function... f and g The private and shared resources of the index, and the algorithm executed by the memory manager 222 efficiently calculate the coloring index function. h The color index function h Shared resources are divided using as many colors as possible without affecting private resources. P g P h and P f ⊥ P h A key insight of this algorithm is that functions represented by linearly independent constraints have orthogonal partitions. The algorithm, executed by memory manager 222, is achieved by... g Iterative selection from f The constraints are generated independently of those already selected in previous iterations (i.e., existing constraints from the coloring function). h .

[0044] Figure 3 A schematic diagram of an example indexing function based on one aspect of processor resources is shown. Typically, a virtual address space representing a contiguous block of memory can be allocated to a virtual machine. Since the physical memory of processor 100 can be shared among multiple virtual machines, the virtual address space is mapped to physical memory via an indexing function. The indexing function can be a linear function that maps a virtual address to a physical address (e.g., in memory 140) based on the values ​​of the individual bits within the virtual address.

[0045] The address bits of a virtual address are as follows Figure 3The first column (M) shows the indexing function for memory pages (shared resources). In the second column (4K / 2M), the indexing function uses address bits a12 to a31 to provide 4K memory pages and address bits a21 to a31 to provide 2M memory pages. In other words, virtual addresses can be mapped to 4K memory pages by selecting a subset of address bits a12 to a31. In the third column, address bits a6 to a14 are used to index the L2 cache (e.g., L2 cache 114), while address bits a6 to a19 are used to index the L3 cache (e.g., L3 cache slice 115). In this example, the L2 cache is an 8-way 256-kilobyte cache, and the L3 cache is a 16-way 16-megabyte cache, but other cache sizes and configurations may be used in other examples. A similar indexing function across chiplet directories (XDs) is shown in the fourth column. Different coloring functions are shown in the fifth (XC) and sixth (XL3C) columns, as described below.

[0046] use Figure 3 The indexing function shown now describes the indexing at a small chip granularity P. chiplet Two example shader functions from the set of shader functions used for memory allocation during processor allocation (i.e., assigning chiplet 110 to the first virtual machine and assigning chiplet 120 to the second virtual machine). Figure 3 The XC in the memory manager 222 will calculate the color partition. P XC Defined as the finest partition, which is coarser than the index function of cross-directory chiplets (XD) and orthogonal to the index function of L3 cache (L3 / L2). For example... Figure 3 As shown, the first shading function, using a combination of XC and 4K pages, produces 1024 colors (i.e., using...). Figure 3 (The 10-bit value of XC shown) .

[0047] When limited to address bits within a 2M memory page address space (i.e., only bits a21 to a31), the second coloring function has a total of 3 bits (i.e., bits a21, a22, and a23), and supports 8 colors: .

[0048] Now, let's describe the situation when using core granularity P... coreTwo additional example coloring functions are used for memory allocation during processor allocation (i.e., assigning core 111 to the first virtual machine and core 112 to the second virtual machine). In these examples, L3 cache slice 115 and cross-chiplet directory 132 may need to be partitioned to provide proper isolation, for example, by partitioning cache lines across trust domains. In some examples, the hardware within processor 100 can be configured to partition cache lines. As a first option, Cache Allocation Technique (CAT) is used to partition the L3 cache, and coloring is used to partition the cross-chiplet directory 132 independently. For CAT, a Service Level (CoS) mask can be used to partition the L3 cache at the way level. For set-associative architectures, each way includes one cache line for each cache set, with a total of N cache lines per way, where N is the number of cache sets. As an example, four service levels (CoS) can be defined, each partitioning the L3 cache into 16-way paths (i.e., for a 16-way set-associative L3 cache) for scheduling each of the four cores of a chiplet split across trust domains: two CoS each comprise half the paths for scheduling cores across two equal-sized trust domains; one CoS comprises three-quarters the paths for scheduling the three cores assigned to a trust domain; and one CoS comprises all 16 paths for scheduling the cores of a chiplet assigned to a single trust domain. For coloring, partitioning is used. P XC It provides two variations of the contract: Supports 4K pages and 1024 colors, and It supports 2MB pages, but only offers 8 colors.

[0049] The advantage of the first option is that the core and physical memory can be scheduled independently of each other. In other examples, more colors can be used by removing constraints on unpartitioned L3, but this would reduce performance when assigning entire chiplets to trust domains.

[0050] As a second option, L3 cache slice 115 and the cross-chip directory are jointly partitioned, but L2 cache is not partitioned (e.g., L2 cache 114). For each chiplet partitioned across multiple trust domains, use... P XL3C To modify its memory partitioning category and use contracts .

[0051] In some examples, during creation, each virtual machine (or trust domain) is exclusively allocated a subset of the colors of the memory partition and exclusively allocated a compute partition category during initial scheduling. Based on the observation that the host is not oversubscribed, this compute partition category is allocated to the virtual machine throughout its entire lifecycle, not just within scheduling intervals. In some scenarios, this approach allows system software to amortize expensive microarchitectural refresh operations (a few milliseconds) over the virtual machine's lifecycle. The host OS (root virtual machine 232) is still responsible for allocating resources to guest virtual machines 234 and 236, but hypervisor 220 enforces resource isolation and exclusive immutability and refuses to create or schedule virtual machines that would violate the isolation contract.

[0052] While system software may zero out memory and registers between resource allocations to virtual machines, comprehensive and efficient microarchitectural refresh requires hardware support. During the initial resource allocation to a virtual machine and ultimately after the virtual machine is shut down or destroyed and before its resources are reclaimed, the resource scheduler 224 refreshes the cache hierarchy (and thereby refreshes any entries in the chiplets and across chiplet directories). Although the hypervisor 220 can use cache refresh instructions to refresh the cache hierarchy at the chiplet granularity, refreshing only a portion of the cache hierarchy (as needed when chipsets are partitioned across different virtual machines) can utilize cache eviction sets to avoid degrading the performance of other virtual machines.

[0053] Figure 4 A schematic diagram of an example memory allocation according to one aspect is shown. First trust domain 410 and second trust domain 420 each have their own virtual address spaces, as shown in virtual memory 0 for the first trust domain and virtual memory 1 for the second trust domain. Physical memory 450 (e.g., corresponding to memory 140) for the processors (not shown) hosting the first trust domain 410 and the second trust domain 420 is used to map the virtual address spaces. When a memory location in physical memory 450 is read for a trust domain, that memory location (or a suitable memory block) is read and stored in cache 470 (e.g., corresponding to L3 cache slice 115).

[0054] exist Figure 4In the example shown, cache 470 is two-way set-associative, providing two available locations within cache 470 where each memory location from physical memory 450 can be stored. Locations within physical memory 450 and cache 470 are shaded according to their available locations, and cache locations are grouped into group 0, group 1, group 2, and group 3. Therefore, memory address 0x0000 in physical memory 450 can be mapped to either the first or second location within group 0 of cache 470. Similarly, each address in memory addresses 0x4000, 0x8000, and 0xC000 can be mapped to either the first or second location within group 0, and each address in memory addresses 0x1000, 0x5000, 0x9000, and 0xD000 can be mapped to either the first or second location within group 1, and so on.

[0055] In some processor architectures, information leakage can occur when memory locations of different trust domains are mapped to the same microarchitectural structure (such as the same cache group, the same directory group, or the same memory bank). Therefore, when the first trust domain 410 is assigned memory address 0x0000 of physical memory 450, the second trust domain 420 could perform a side-channel attack based on the timing delay associated with memory address 0xC000 of physical memory 450. Memory manager 222 is configured to use the memory coloring scheme described above to prevent memory address 0xC000 of physical memory 450 from being assigned to the second trust domain 420. In one example, the memory color could correspond to the two-way groups of cache 470, for example, where group 0 corresponds to the first color, group 1 corresponds to the second color, group 3 corresponds to the third color, and so on.

[0056] In some examples, when additional cache storage is requested for a trust domain, memory manager 222 allocates colors that are adjacent to each other in the cache. For example, the first and second colors corresponding to groups 0 and 1 of cache 470 can be assigned... Figure 4 The first trust domain is shown, while the third color (corresponding to group 2) can be assigned to the second trust domain. By assigning the first and second colors to the first trust domain, the first trust domain has a contiguous cache, which can improve memory performance. Using this example, the coloring function of the first trust domain 410 maps the first four virtual memory locations (0x0000, 0x1000, 0x2000, 0x3000) to physical memory locations 0x0000, 0x1000, 0x4000, and 0x5000, respectively.

[0057] Figure 5A flowchart of an example method 500 for allocating processor resources according to one aspect is shown. For example, resource allocation can be performed according to a shading function. Unless otherwise indicated, the technical processes shown in these figures will be performed automatically. In any given embodiment, some steps of the process may be repeated (possibly using different parameters or data). The steps in the embodiments may also be performed in accordance with... Figure 5 The steps may be executed in different orders from top to bottom as specified in the diagram. The steps may be executed sequentially, partially overlapping, or entirely in parallel. Therefore, the order in which the steps of method 500 are executed may differ between one execution of the process and another. Steps may also be omitted, combined, renamed, regrouped, executed on one or more machines, or otherwise removed from the illustrated flow, provided that the executed process is operable and conforms to at least one claim. Figure 5 The steps can be performed by processor 100 (e.g., via chiplet 110 of executive administrator 220) or other suitable computing devices.

[0058] Method 500 begins at step 502. At step 502, a coloring scheme for the processor resources is obtained. The coloring scheme has a coloring function that indexes both shared and private resources of the processor and provides protection against information leakage through shared resources of the processor between trust domains.

[0059] In some aspects, obtaining a coloring scheme involves generating a set of coloring functions, each of which provides protection against information leakage. For example, the set of coloring functions may include a first coloring function for 4K memory pages and a second coloring function for 2M memory pages.

[0060] At step 504, a first set of colors from a plurality of unassigned colors is assigned to a first trust domain according to a shading scheme. For example, a first set of memory colors, including those corresponding to group 2 of cache 470, is assigned to trust domain 420. In some examples, memory manager 222 assigns colors to trust domain 420 (e.g., a virtual machine) when a trust domain is created and / or initialized on hardware 210. In one example, the assigned colors remain exclusively assigned to the trust domain for its entire lifetime. As described herein, the shading scheme corresponds to a shading function that can be generated by memory manager 222.

[0061] Typically, coloring schemes use multiple bits to define multiple colors (e.g., 2 bits for 4 colors, 3 bits for 8 colors, 4 bits for 16 colors, etc.). The number of bits can be represented as a bitmap and used as a mask to restrict available memory addresses (e.g., color masks). As an example using two bits, four color masks 00, 01, 10, and 11 can correspond to the first, second, third, and fourth colors, respectively. Memory addresses that do not contain the assigned color mask at designated locations are restricted to use by the first trust domain. These four colors can be considered free as long as they have not been assigned to a trust domain. More specifically, after the first and second colors are assigned to trust domains, only the third and fourth colors are available for subsequent assignments. The coloring scheme specifies that information disclosure is isolated from other trust domains, meaning that information regarding the use of a first resource allocated according to the first color set is isolated from other trust domains.

[0062] At step 506, a request for resources in the first trust domain is received. For example, a user can submit a request to create trust domain 420.

[0063] At step 508, a first resource is assigned to a first trust domain according to a first color set. Each first resource in the first resource has the assigned color from the first color set. For example, memory location 0xE000 is assigned to trust domain 420. Advantageously, memory manager 222 prevents the allocation of memory location 0xC000 (i.e., by having a different color) because this location would be mapped to a location within cache 470 that does not provide isolation from trust domain 410.

[0064] At step 510, an indication of the allocated resources is provided to the first trust domain. For example, memory manager 222 may provide an indication of the allocated memory location (e.g., a range of allocated addresses), a pointer to the start of the allocated memory location, etc.

[0065] In some respects, processor resources include shared resources and private resources. One or more first linear functions are configured to index private resources by mapping address bits to a first resource set, while one or more second linear functions are configured to index shared resources by mapping address bits to a second resource set. For example, hypervisor 220 can index L3 / L2 cache (L3 / L2, Figure 3 The index function of ) is identified as the first linear function, and the cross-chip catalog (XD, Figure 3The indexing function is identified as a second linear function. Method 500 may further include generating a coloring function using one or more first indexing functions and one or more second indexing functions, wherein the coloring function indexes both private and shared resources, and segments the shared resources to maximize the available colors of the coloring scheme and minimize the subdivision of the private resources. In some aspects, the coloring function supports allocating individual memory pages or individual cache blocks to a first trust domain as the allocated memory location. For example, the coloring function avoids or reduces the possibility of allocating only a portion of a memory page, which may lead to performance degradation and / or inefficient memory allocation. As another example, the coloring function may segment a shared cache or cache coherence directory, but prevents the subdivision of the private L2 cache.

[0066] In some aspects, the primary resource includes one or more of the following: physical threads, memory pages, cache lines, and microarchitectural resources. In various examples, the microarchitectural resource may be a chiplet directory slice 116, a cross-chiplet directory 132, an L1 cache 113, an L2 cache 114, an L3 cache slice 115, or other suitable microarchitectural resources.

[0067] Generating the coloring function may include: iteratively selecting constraints from one of a group of first linear functions that are independent of constraints from one of a group of second linear functions, and using the iteratively selected constraints to generate the coloring function. For subsequent iterations, generating the coloring function includes: iteratively selecting constraints from another of the group of first linear functions that are independent of constraints from the coloring function. In other words, constraints of the first linear function indexed on L2 cache 114 may be selected in the first iteration, and constraints of the second linear function indexed on L3 cache slice 115 may be selected in the second iteration.

[0068] In some respects, the first trust domain is associated with at least one of the following: a virtual machine, a container, or another suitable software execution environment.

[0069] In some aspects, allocating a first resource involves using a first color bitmap with bits corresponding to the colors of a coloring scheme. For example, the first color bitmap could have sixteen bits, each bit corresponding to a color in the coloring scheme (e.g., 16 bits for 16 colors, 1024 bits for 1024 colors, etc.). For example, setting a single bit within the first color bitmap to "1" might indicate that a first trust domain has been assigned the corresponding color. In one example, the first color bitmap is unique to the first trust domain. In other words, only the first trust domain is allowed access to the first color bitmap. This approach reduces the likelihood that another trust domain could identify which resources (i.e., colors) have been assigned to the first trust domain. In other examples, the first color bitmap is shared between the first and second trust domains (or additional second trust domains). For example, the first color bitmap could have 48 bits, using three bits per color for sixteen colors, to identify which of the seven trust domains has been assigned a particular color. As an example, the first set of 3 bits in the first color bitmap can have the value "000" to indicate that the first color has not been assigned, the second set of 3 bits can have the value "001" to indicate that the second color has been assigned to the first trust domain, the third set of 3 bits can have the value "110" to indicate that the third color has been assigned to the sixth trust domain, and so on.

[0070] In some aspects, using a first color bitmap involves iterating over the first color bitmap to allocate memory locations as first resources, such that the allocated memory locations are adjacent to each other in physical memory. (See reference) Figure 4 As an example, the first color bitmap can have 12 bits, with 3 bits used for each color, for the four colors (corresponding to group 0, group 1, group 2, and group 3) to identify which of the seven trust domains was assigned a specific color. Figure 4In the first trust domain 410, groups 0 and 1 have been assigned; the second trust domain 420, group 2 has been assigned; and group 3 has not been assigned. Therefore, the values ​​of the first color bitmap may be (001)(001)(010)(000) (parentheses inserted for clarity). Without iterating over the first color bitmap, the memory manager 222 can sequentially allocate addresses 0x0000, 0x4000, 0x8000, and 0xC000 (of physical memory 450), all within the first color (group 0). However, this approach may result in the allocated addresses being mapped to the same portion of cache 470 (i.e., within the same group), leading to unnecessary data replacement within cache 470. The memory manager 222 can be configured to iterate over a first color bitmap to allocate memory locations, thereby sequentially allocating addresses 0x0000 (from group 0), 0x1000 (from group 1), 0x4000 (from group 0), and 0x5000 (from group 1). In this way, the allocated memory pages can be mapped to different groups of the cache 470, thereby reducing the possibility that data within the cache 470 will be overwritten within the same trust domain.

[0071] In some aspects, allocating the first color set involves allocating it based on the maximum memory size allocated to the first trust domain. For example, when the first trust domain is allocated a maximum memory size of 4MB and each allocatable color spans 2MB, the memory manager 222 can only allocate two colors, even if no additional colors are allocated. This approach reduces the likelihood that colors will be reassigned to different trust domains at a later time (e.g., when a second trust domain is initialized), in which case information about the use of resources to be reassigned might be accessible (or leakable) to the second trust domain.

[0072] In some aspects, the first trust domain is a guest virtual machine, and method 500 further includes: assigning a set of memory colors from the coloring scheme to the root virtual machine, and reserving the remaining colors from the coloring scheme for the guest virtual machines. The root virtual machine may correspond to, for example, the root virtual machine 232 of the operating system of computing device 100. In other words, a subset of memory colors may be assigned to the root virtual machine 232, and the remaining colors may be freely assigned to guest virtual machines 234 and 236.

[0073] Figure 6 A flowchart of an example method 600 for allocating processor resources according to an example embodiment is shown. Unless otherwise indicated, the technical processes shown in these figures will be performed automatically. In any given embodiment, some steps of the process may be repeated (possibly using different parameters or data). The steps in the embodiments may also be performed in accordance with… Figure 6The steps may be executed in different orders from top to bottom as specified in the diagram. The steps may be executed sequentially, partially overlapping, or entirely in parallel. Therefore, the order of the steps in method 600 may differ between one execution of the process and another. Steps may also be omitted, combined, renamed, regrouped, executed on one or more machines, or otherwise removed from the illustrated flow, provided that the executed process is operable and conforms to at least one claim. Figure 6 The steps can be performed by processor 100 (e.g., via chiplet 110 of executive administrator 220) or other suitable computing devices.

[0074] Method 600 begins at step 602. At step 602, a first linear function is identified that indexes a first resource of the processor, where the first resource is a first shared resource of the processor. For example, hypervisor 220 may identify a cross-chiplet directory (XD, Figure 3 The indexing function for shared resources. In some examples, the indexing function for shared resources is provided by the manufacturer of the processor (e.g., processor 100). In other examples, the indexing function for shared resources is reverse engineered.

[0075] At step 604, a second linear function indexing the processor's second resource is identified. For example, hypervisor 220 may identify the L3 / L2 cache (L3 / L2, Figure 3 The indexing function for private resources can be provided by the processor manufacturer (e.g., processor 100) or through reverse engineering.

[0076] At step 606, the first linear function and the second linear function are combined to generate a coloring function. This coloring function indexes the first shared resource and the second resource based on whether the second resource is a second shared resource or a private resource. The generated coloring function maximizes the available colors of the coloring scheme for the second shared resource and avoids partitioning the private resource.

[0077] At step 608, a first set of colors from multiple unassigned colors is assigned to a first trust domain according to the coloring scheme.

[0078] At step 610, a coloring function is used to allocate processor resources to a first trust domain according to a first color set, wherein each of the allocated resources has the assigned color from the first color set, and protection is provided against information leakage between the first trust domain and one or more second trust domains. For example, memory addresses that do not contain an assigned color mask at a specified location within a memory address are restricted from being allocated to the corresponding trust domain by the memory manager 222.

[0079] When the second resource is a private resource, step 606 includes: iteratively selecting constraints from the first linear function that are independent of the constraints from the second linear function, and using the selected constraints to generate a coloring function. In some examples, these constraints are related to the memory partitioning P described above. M Related, specifically: P M It conforms to all architectural constraints, such as supporting page-based allocation: P 4K P M And ideally it is P 2M P M ;P M Divide all shared microarchitectural resources necessary to achieve isolation; and P M No private microarchitectural resources (e.g., L2 cache) are allocated, which would otherwise degrade performance. For example, hypervisor 220 generates the shading function XC ( Figure 3 In some respects, for example, when the shader function is computed offline or provided by the hardware vendor, the hypervisor 220 uses the shader function XC instead of generating the shader function XC directly.

[0080] When the second resource is a second shared resource, step 606 includes: modeling the first linear function as a first matrix and modeling the second linear function as a second matrix; identifying the basis of the kernel of the first matrix and the basis of the kernel of the second matrix; concatenating the basis of the kernel of the first matrix and the basis of the kernel of the second matrix to obtain a concatenated basis; transposing the concatenated basis; and modeling the coloring function as the basis of the kernel of the transposed concatenated basis.

[0081] Figure 7 and Figure 8 The associated descriptions provide a discussion of various operating environments in which the aspects of this disclosure can be practiced. However, regarding Figure 7 and Figure 8 The devices and systems described and discussed are for illustrative purposes only and are not intended to limit the wide range of computing device configurations that may be used to practice the aspects of this disclosure described herein.

[0082] Figure 7This is a block diagram illustrating the physical components (e.g., hardware) of a computing device 700 that can implement aspects of the present disclosure. The computing device components described below may have computer-executable instructions for implementing a resource allocation application 720 on a computing device (e.g., processor 100, hypervisor 220), including computer-executable instructions for the resource allocation application 720 that can be executed to implement the methods disclosed herein. In a basic configuration, the computing device 700 may include at least one processing unit 702 and system memory 704. Depending on the configuration and type of the computing device, the system memory 704 may include, but is not limited to, volatile storage devices (e.g., random access memory), non-volatile storage devices (e.g., read-only memory), flash memory, or any combination of such memories. The system memory 704 may include an operating system 705 and one or more program modules 706 suitable for running the resource allocation application 720, such as those related to… Figure 1 and Figure 2 One or more components, and specifically memory manager 721 (e.g., corresponding to memory manager 222) and resource scheduler 722 (e.g., corresponding to resource scheduler 224).

[0083] For example, operating system 705 may be suitable for controlling the operation of computing device 700. Furthermore, aspects of this disclosure can be practiced in conjunction with graphics libraries, other operating systems, or any other applications, and are not limited to any particular application or system. Figure 7 The basic configuration is illustrated by the components within the dashed lines 708. The computing device 700 may have additional features or functions. For example, the computing device 700 may also include additional data storage devices (removable and / or non-removable), such as disks, optical discs, or magnetic tapes. Such additional storage devices... Figure 7 The image is illustrated by removable storage device 709 and non-removable storage device 710.

[0084] As described above, multiple program modules and data files can be stored in system memory 704. When executed on processing unit 702, the processes that program module 706 (e.g., resource allocation application 720) can perform include, but are not limited to, the aspects described herein. Other program modules that can be used according to aspects of this disclosure (specifically, program modules for resource allocation) may include processor 100 and management program 220.

[0085] Furthermore, aspects of this disclosure can be implemented in circuits including discrete electronic components, in packages or integrated electronic chips containing logic gates, in circuits utilizing microprocessors, or on a single chip containing electronic components or a microprocessor. For example, aspects of this disclosure can be implemented via a system-on-a-chip (SOC), wherein... Figure 7Each or many of the components illustrated can be integrated onto a single integrated circuit. Such a SoC device may include one or more processing units, graphics units, communication units, system virtualization units, and various application functions, all integrated (or “programmed”) onto a chip substrate as a single integrated circuit. When operating via the SoC, the functions described herein with respect to the client switching protocol capability can be operated via dedicated logic integrated with other components of the computing device 700 on the single integrated circuit (chip). Aspects of this disclosure can also be practiced using other techniques capable of performing logical operations such as AND, OR, and NOT, including but not limited to mechanical, optical, fluid, and quantum technologies. Furthermore, aspects of this disclosure can be practiced within a general-purpose computer or in any other circuit or system.

[0086] The computing device 700 may also have one or more input devices 712, such as a keyboard, mouse, pen, voice or speech input device, touch or swipe input device, etc. Multiple output devices 714 may also be included, such as a display, speaker, printer, etc. The devices mentioned above are examples, and other devices may be used. The computing device 700 may include one or more communication connections 716 that allow communication with other computing devices 750. Examples of suitable communication connections 716 include, but are not limited to, radio frequency (RF) transmitters, receivers, and / or transceiver circuitry; universal serial buses (USB), parallel and / or serial ports.

[0087] As used herein, the term computer-readable medium may include computer storage media. Computer storage media may include volatile and non-volatile, removable and non-removable media implemented using any method or technology for storing information, such as computer-readable instructions, data structures, or program modules. System memory 704, removable storage device 709, and non-removable storage device 710 are examples of computer storage media (e.g., memory storage devices). Computer storage media may include RAM, ROM, electrically erasable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical storage devices, magnetic cassettes, magnetic tape, disk storage devices or other magnetic storage devices, or any other article of manufacture that can be used to store information and is accessible by computing device 700. Any such computer storage medium may be part of computing device 700. Computer storage media does not include carrier waves or other propagated or modulated data signals.

[0088] Communication media can be embodied in computer-readable instructions, data structures, program modules, or other data in modulated data signals (such as carrier waves or other transmission mechanisms), and include any information transmission medium. The term "modulated data signal" can describe a signal having one or more characteristics that are encoded by a device or altered to encode information in the signal. By way of example, and not limitation, communication media can include wired media (such as wired networks or direct wired connections) and wireless media (such as acoustic, radio frequency (RF), infrared, and other wireless media).

[0089] Figure 8 The illustration depicts a mobile computing device 800 that can implement various aspects of this disclosure, such as a mobile phone, smartphone, wearable computer (e.g., smartwatch), tablet computer, laptop computer, etc. In some aspects, the client can be a mobile computing device. Figure 8 This is a block diagram illustrating one aspect of the architecture of a mobile computing device. Specifically, the mobile computing device 800 can be incorporated into a system (e.g., architecture) 802 to implement several aspects. In one aspect, the system 802 is implemented as a "smartphone" capable of running one or more applications (e.g., a browser, email, calendar, contact manager, messaging client, game, and media client / player). In other aspects, the system 802 is integrated as a computing device, such as integrating a personal digital assistant (PDA) and a wireless phone.

[0090] One or more applications 866 may be loaded into memory 862 and run on or associated with operating system 864. Examples of applications include telephone dialer programs, email programs, personal information management (PIM) programs, word processing programs, spreadsheet programs, internet browser programs, messaging programs, etc. System 802 also includes a non-volatile storage area 868 within memory 862. The non-volatile storage area 868 may be used to store persistent information that should not be lost if system 802 is powered off. Applications 866 may use and store information in the non-volatile storage area 868, such as emails or other messages used by email applications. A synchronization application (not shown) also resides on system 802 and is programmed to interact with a corresponding synchronization application residing on the host computer to keep the information stored in the non-volatile storage area 868 synchronized with the corresponding information stored on the host computer.

[0091] System 802 has a power supply 870, which can be implemented as one or more batteries. The power supply 870 may also include an external power source, such as an AC adapter or power docking station for replenishing or charging the batteries.

[0092] System 802 may also include a radio interface layer 872, which performs the functions of transmitting and receiving radio frequency communications. Radio interface layer 872 facilitates wireless connectivity between system 802 and the "external world" via a communication carrier or service provider. Transmissions to and from radio interface layer 872 are conducted under the control of operating system 864. In other words, communications received by radio interface layer 872 can be distributed to application program 866 via operating system 864, and vice versa.

[0093] Visual indicator 820 can be used to provide visual notifications, and / or audio interface 874 can be used via audio transducer 825 (e.g., Figure 8 The illustrated audio transducer 825 generates audible notifications. In the illustrated example, the visual indicator 820 is a light-emitting diode (LED), and the audio transducer 825 can be a speaker. These devices can be directly coupled to a power supply 870 such that, when activated, they remain on for a duration specified by the notification mechanism, even if the processor 860 and other components might be turned off to conserve battery power. The LED can be programmed to remain on indefinitely until the user takes an action to indicate the device's power-on status. An audio interface 874 is used to provide audible signals to and receive audible signals from the user. For example, in addition to being coupled to the audio transducer 825, the audio interface 874 can also be coupled to a microphone to receive audible input, such as to facilitate telephone conversations. According to various aspects of this disclosure, as will be described below, the microphone can also act as an audio sensor to facilitate control of the notification. System 802 may also include a video interface 876 that enables the operation of a peripheral device 830 (e.g., a vehicle camera) to record still images, video streams, etc.

[0094] The mobile computing device 800 implementing system 802 may have additional features or functions. For example, the mobile computing device 800 may also include additional data storage devices (removable and / or non-removable), such as disks, optical discs, or magnetic tapes. Such additional storage devices... Figure 8 The diagram shows a non-volatile storage region 868.

[0095] Data / information generated or captured by mobile computing device 800 and stored via system 802 can be locally stored on mobile computing device 800, as described above, or the data can be stored on any number of storage media accessible by the device via radio interface layer 872 or a wired connection between mobile computing device 800 and a separate computing device associated with mobile computing device 800 (e.g., a server computer in a distributed computing network such as the Internet). It should be understood that such data / information can be accessed by mobile computing device 800 via radio interface layer 872 or via a distributed computing network. Similarly, according to well-known data / information transmission and storage methods (including email and collaborative data / information sharing systems), such data / information can be easily transferred between computing devices for storage and use.

[0096] It should be understood that what is disclosed in this article Figure 7 and Figure 8 This description is for illustrative purposes of the method and system and is not intended to limit this disclosure to a particular sequence of steps or a particular combination of hardware or software components.

[0097] The descriptions and illustrations of one or more aspects provided in this application are not intended to limit or restrict the scope of the claimed disclosure in any way. The aspects, examples, and details provided in this application are considered sufficient to convey ownership and enable others to make and use the claimed disclosure. The claimed disclosure should not be construed as limited to any aspect, example, or detail provided in this application. Various features (both structural and methodological features) are intended to be selectively included or omitted, whether shown and described in combination or separately, to produce examples with a particular set of features. Having provided a description and illustration of this application, those skilled in the art will anticipate variations, modifications, and alternatives falling within the spirit of the broader aspects of the general inventive concept embodied in this application, without departing from the broader scope of the claimed disclosure.

Claims

1. A method (500) for allocating processor resources among trust domains, the method comprising: Obtain (502) a coloring scheme for the processor's resources, wherein the coloring scheme has a coloring function that indexes both the processor's shared and private resources and provides protection against information leakage through the processor's shared resources between the trust domains; According to the coloring scheme, the first color set from multiple unassigned colors is assigned (504) to the first trust domain; as well as The first resource is allocated (508) to the first trust domain according to the first color set, wherein each of the first resources has the assigned color in the first color set.

2. The method according to claim 1, wherein: One or more first indexing functions are configured to index the private resource; One or more second indexing functions are configured to index the shared resource; and Obtaining the coloring scheme includes: generating the coloring function using one or more first indexing functions and one or more second indexing functions, wherein the coloring function indexes both the private resource and the shared resource, and segments the shared resource to maximize the available colors of the coloring scheme and minimize the subdivision of the private resource.

3. The method of claim 2, wherein the first resource includes one or more of the following: physical threads, memory pages, cache lines, and microarchitectural resources.

4. The method according to claim 2, wherein: The one or more first indexing functions include a first linear function configured to index the private resources by mapping address bits to a first resource set; The one or more second indexing functions include a second linear function configured to index the shared resources by mapping address bits to a second set of resources; and Generating the coloring function further includes: iteratively selecting constraints from a first linear function of the first linear functions that are independent of constraints from a second linear function of the second linear functions, and using the iteratively selected constraints to generate the coloring function.

5. The method of claim 1, wherein the first trust domain is associated with at least one of a virtual machine or a container.

6. The method of claim 1, wherein allocating the first resource comprises: A first color bitmap is used, which has bits corresponding to the colors of the coloring scheme.

7. The method of claim 6, wherein the first trust domain is a guest virtual machine, the method further comprising: Assign the memory color set from the shading scheme to the root virtual machine; as well as For the client virtual machine, the remaining colors from the shading scheme are retained.

8. A computing device (700) for allocating processor resources of a processor (702), the computing device including the processor (702) and non-transient computer-readable storage (704, 709, 710), wherein the processor is configured to execute instructions from the storage, the instructions configuring the computing device to: The identifier (602) is a first linear function that indexes a first resource in the processor resources, wherein the first resource is a first shared resource of the processor; The identifier (604) is a second linear function that indexes the second resource in the processor resources; Combine (606) the first linear function and the second linear function to generate a coloring function, the coloring function indexing the first shared resource and the second resource based on whether the second resource is a second shared resource or a private resource, wherein generating the coloring function maximizes the available colors of the coloring scheme and avoids partitioning the private resource; According to the coloring scheme, a first set of colors from multiple unassigned colors is assigned (608) to a first trust domain; as well as Using the coloring function, at least some processor resources in the processor resources are allocated (610) to the first trust domain according to the first color set, wherein each of the allocated resources has the assigned color in the first color set, and protection is provided against information leakage between the first trust domain and one or more second trust domains.

9. The computing device of claim 8, wherein the processor is further configured to execute instructions from the memory, the instructions configuring the computing device to: When the second resource is the second shared resource: The first linear function is modeled as a first matrix, and the second linear function is modeled as a second matrix; Identify the basis for the kernel of the first matrix and the basis for the kernel of the second matrix; The basis for the kernel of the first matrix and the basis for the kernel of the second matrix are spliced ​​together to obtain a spliced ​​basis; Transpose the splicing base; and The coloring function is modeled as a basis of the kernel of the transposed splicing basis.

10. A method (600) for allocating processor resources, the method comprising: The identifier (602) is a first linear function that indexes a first resource in the processor resources, wherein the first resource is a first shared resource of the processor; The identifier (604) is a second linear function that indexes the second resource in the processor resources; Combine (606) the first linear function and the second linear function to generate a coloring function, the coloring function indexing the first shared resource and the second resource based on whether the second resource is a second shared resource or a private resource, wherein generating the coloring function maximizes the available colors of the coloring scheme and avoids partitioning the private resource; According to the coloring scheme, a first set of colors from multiple unassigned colors is assigned (608) to a first trust domain; as well as Using the coloring function, at least some processor resources in the processor resources are allocated (610) to the first trust domain according to the first color set, wherein each of the allocated resources has the assigned color in the first color set, and protection is provided against information leakage between the first trust domain and one or more second trust domains.

11. The method of claim 2, wherein obtaining the coloring scheme further comprises generating a set of coloring functions, each coloring function providing protection against information leakage.

12. The method of claim 4, wherein generating the coloring function further comprises iteratively selecting constraints from another first linear function of the first linear functions that are independent of existing constraints from the coloring function.

13. The method of claim 6, wherein using the first color bitmap includes iterating over the first color bitmap to allocate memory locations as the first resource, such that the allocated memory locations are adjacent to each other in physical memory.

14. The computing device of claim 8, wherein the processor is further configured to execute instructions from the memory, the instructions configuring the computing device to: When the second resource is the private resource: Iteratively select constraints from the first linear function that are independent of the constraints from the second linear function; and The coloring function is generated using the constraints that are selected iteratively.

15. The method of claim 10, wherein: When the second resource is the second shared resource, combining the first linear function and the second linear function to generate the coloring function includes: The first linear function is modeled as a first matrix, and the second linear function is modeled as a second matrix; Identify the basis for the kernel of the first matrix and the basis for the kernel of the second matrix; The basis for the kernel of the first matrix and the basis for the kernel of the second matrix are spliced ​​together to obtain a spliced ​​basis; Transpose the splicing base; and The coloring function is modeled as a basis of the kernel of the transposed splicing basis.

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