Processor and memory access methods

Abstract

This application relates to a processor and a memory access method. The processor includes: a UAV instruction sending unit, a UAV register management unit, a general-purpose register unit, a UAV data cache unit, and a load memory unit; the load memory unit is configured to: receive SIMD instructions; read resource information of the target UAV register from the UAV register management unit according to the address information of the target UAV register; if the SIMD instruction is determined to be a load instruction based on the opcode, read the channel logical address information of each channel from the general-purpose register unit; if it is determined that the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive, calculate the memory access address of the first channel, and calculate the memory access addresses of the remaining channels based on the memory access address of the first channel; and generate a memory access request based on the memory access addresses of each channel.

Description

Technical Field

[0001] This application relates to the field of processors, and more particularly to a processor and memory access method. Background Technology

[0002] In graphics processing units (GPUs) or general-purpose computing on graphics processing units (GPGPUs), the instruction type used in programmable units is usually Single Instruction Multiple Data (SIMD). For load-memory instructions, the access addresses between different channels are independent of each other.

[0003] Unordered Access Views (UAVs) allow different threads to randomly read and write data resources such as textures and buffers through load and store instructions, without strictly adhering to a sequential order. Therefore, UAVs are widely used in scientific computing, physics simulations, and artificial intelligence inference. For example, in AI inference tasks, massive matrix multiplication operations are required. Applications typically load input feature matrices or weight matrices through UAVs and write the multiplication results to caches or memory. The performance of load and store instructions directly impacts the word generation speed of the inference task. Therefore, improving the throughput of load and store instructions in UAVs is crucial for hardware performance.

[0004] However, since the existing graphics processor's load-memory instruction processing unit independently calculates the memory addresses accessed by different channels of the SIMD instruction through several arithmetic logic units (ALUs), the throughput of load-memory instructions is mostly limited by the number of ALUs, meaning that the ALU becomes a performance bottleneck.

[0005] Therefore, it is particularly important to improve the throughput of load-store instructions without increasing the number of additional memory address calculation ALUs, in order to optimize hardware architecture design, reduce hardware costs, and achieve high-performance computing. Invention Overview Technical issues

[0006] The technical problem to be solved by this application is to provide a processor and memory access method that improves the throughput of load-store instructions limited by the number of ALUs. Technical solution

[0007] To solve the above-mentioned technical problems, according to a first aspect of the present invention, a processor is provided, comprising: a UAV instruction sending unit, a UAV register management unit, a general-purpose register unit, a UAV data cache unit, and a load memory unit, wherein the UAV instruction sending unit, the UAV register management unit, the general-purpose register unit, and the UAV data cache unit are all connected to the load memory unit;

[0008] The loading storage unit is configured as follows:

[0009] Receive SIMD instructions, which are sent by the UAV instruction sending unit;

[0010] The opcode of the SIMD instruction, the address information of the target general-purpose register, and the address information of the target UAV register are obtained by parsing.

[0011] The resource information of the target UAV register is read from the UAV register management unit according to the address information of the target UAV register;

[0012] If the SIMD instruction is determined to be a load instruction based on the opcode, the channel logical address information of each channel of the SIMD instruction is read from the general-purpose register unit according to the address information of the target general-purpose register;

[0013] Based on the resource information of the target UAV register and the channel logical address, determine whether the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive;

[0014] If it is determined that the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive, the memory access address of the first channel among the multiple channels is calculated, and the memory access addresses of the other channels among the multiple channels other than the first channel are calculated based on the memory access address of the first channel.

[0015] Memory access requests are generated based on the memory access addresses of each channel according to the SIMD instructions, so as to complete the access to memory through the UAV data cache unit.

[0016] The processor's load-memory unit of this invention, based on the resource information of the target UAV register and the channel logical address, can determine whether the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive. If the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive, it calculates the memory access address of the first channel among the multiple channels, and calculates the memory access addresses of the remaining channels (excluding the first channel) based on the memory access address of the first channel, thereby reducing the number of channels requiring complete address calculation. This ensures good processor performance while reducing the load-memory unit's dependence on ALU computing resources. Without increasing the hardware overhead of additional ALUs, it improves the throughput of SIMD load or store instructions, saves on the number of memory address calculation ALUs, and reduces power consumption.

[0017] In one possible implementation of the first aspect, the load storage unit is further configured to: when the SIMD instruction is determined to be a store instruction based on the opcode, read the channel logical address information of each channel of the SIMD instruction and the data to be stored from the general-purpose register unit based on the address information of the target general-purpose register.

[0018] By incorporating storage instructions into the optimization scope, the consistency of the processor's storage operations is ensured, and the efficiency of storage operations is improved simultaneously, resulting in a comprehensive improvement in the processor's overall memory access performance.

[0019] In one possible implementation of the first aspect, the resource description information of the target UAV register includes base address, resource type, resource size, data layout, data format, and resource dimension.

[0020] By including rich resource description information, it provides a complete data foundation for subsequent address continuity determination and memory access address calculation, and can adapt to complex access patterns of different resource types and layouts.

[0021] In one possible implementation of the first aspect, the load memory unit includes an address contiguousness detection unit, which is configured to determine whether the memory addresses to be accessed by multiple channels of the SIMD instruction are contiguous based on the resource information of the target UAV register and the channel logical address:

[0022] Based on the valid bits in the target UAV register, determine whether the resource information of the target UAV register is valid;

[0023] If the resource information of the target UAV register is determined to be valid, based on the channel logical address, it is determined whether the multiple channel instruction access addresses of the SIMD instruction are consecutive, wherein the instruction access addresses of the multiple channels are the channel logical addresses of the multiple channels;

[0024] If it is determined that the instruction access addresses between different channels of the SIMD instruction are consecutive, based on the resource information of the target UAV register and the data format of the SIMD instruction, it is determined whether the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive.

[0025] By setting up a dedicated address continuity detection unit, the system first checks the validity of resources, then checks the logical address continuity, and finally combines the resource information to determine the physical address continuity, thus achieving efficient and accurate continuity detection.

[0026] In one possible implementation of the first aspect, the channel logical address includes a first-dimensional logical address, a second-dimensional logical address, and a third-dimensional logical address, and the address continuity detection unit is configured to determine whether multiple channel instruction access addresses of the SIMD instruction are continuous based on the channel logical address in the following manner:

[0027] If the data layout in the resource information of the target UAV register is a linear layout, and if the second and third logical addresses of the multiple channels of the SIMD instruction are equal, and the first logical addresses of the multiple channels of the SIMD instruction form a continuous sequence, then it is determined that the instruction access addresses of the multiple channels of the SIMD instruction are continuous.

[0028] If the data layout in the resource information of the target UAV register is Zig-zag, and if the third-dimensional logical addresses of multiple channels of the SIMD instruction are equal, and the arrangement of the first and second-dimensional logical addresses of multiple channels of the SIMD instruction matches the predefined Zig-zag pattern, then it is determined that the instruction access addresses of multiple channels of the SIMD instruction are continuous.

[0029] Specific continuity rules are defined for different data layouts, such as linear and Zig-zag layouts, enhancing support for common data storage patterns in real-world applications. This allows the processor provided in this application to go beyond idealized linear access, effectively handling more complex, non-contiguous but logically regular access patterns designed to improve cache hit rates, thus expanding its applicability.

[0030] In one possible implementation of the first aspect, the address contiguousness detection unit is configured to determine whether the memory addresses to be accessed by multiple channels of the SIMD instruction are contiguous based on the resource information of the target UAV register and the data format of the SIMD instruction:

[0031] When the resource type is a buffer resource, if the access addresses of multiple channels of the SIMD instruction are consecutive, it is determined that the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive.

[0032] When the resource type is a texture resource, if the result of a bitwise AND operation between the data channel mask of the SIMD instruction and the channel mask of the data format of the target UAV register is equal to the channel mask of the data format of the target UAV register, then it is determined that the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive.

[0033] This application differentiates the continuity criteria for buffer resources and texture resources. For buffers, logical address continuity usually implies physical address continuity; for textures, a channel mask matching check is introduced to ensure that address calculation optimization is only enabled during texture processing when all data channels are effectively accessed and the access pattern is regular. This differentiated processing approach guarantees the processor's adaptability to different resource types.

[0034] In one possible implementation of the first aspect, the load storage unit includes a memory address calculation unit configured to calculate the memory access address of the first channel among the plurality of channels in the following manner:

[0035] The memory access address of the first channel is calculated based on the base address, dimension information, and data layout in the target UAV register, as well as the channel logical address information of the first channel read from the general-purpose register unit.

[0036] This application uses a dedicated memory address calculation unit to accurately calculate the memory access address of the first channel, providing an accurate calculation basis for subsequent fast address calculation based on offset.

[0037] In one possible implementation of the first aspect, the memory address calculation unit is configured to calculate the memory access addresses of the remaining channels (excluding the first channel) among the plurality of channels based on the memory access address of the first channel in the following manner:

[0038] The address offsets of the remaining channels are determined based on the data format and number of channels of the SIMD instructions;

[0039] The access direction of the address is determined based on the continuous address detection results;

[0040] The memory access addresses of the remaining channels are calculated based on the memory access address of the first channel, the address offset of the remaining channels, and the access direction of the address.

[0041] The processor provided in this application eliminates the need for complex logical-to-physical address translation for consecutive address accesses, except for the first channel. Instead, it can be obtained through simple offset addition. This significantly reduces the consumption of ALU computing resources, simplifying multiple independent address calculations that originally required multiple cycles into a single complete calculation plus multiple fast incremental calculations. This significantly improves the efficiency of address generation, thereby directly increasing the throughput of load-memory instructions.

[0042] In one possible implementation of the first aspect, the load memory unit is further configured to: calculate the memory access address of each channel in a manner that, when it is determined that the memory addresses to be accessed by multiple channels of the SIMD instruction are not contiguous, calculate the memory access address of each channel in the following way:

[0043] Obtain the channel logical address for each channel;

[0044] Based on the base address, resource dimension, data layout, and data format of the target UAV register, the channel logical address of each channel is converted into the corresponding memory access address.

[0045] When multiple channels need to access non-contiguous memory addresses, the processor will automatically fall back to the traditional mode of calculating memory access addresses independently for each channel, thereby improving the processor's compatibility.

[0046] In one possible implementation of the first aspect, the load storage unit includes an address out-of-bounds detection unit, which is configured to:

[0047] Out-of-bounds detection is performed on the memory access addresses corresponding to each channel of the SIMD instruction, and channels that exceed the bounds are filtered out.

[0048] This application effectively prevents illegal memory access by introducing an address out-of-bounds detection unit, thereby improving the stability and security of the processor. Filtering out out-of-bounds channels avoids meaningless memory requests or exceptions, ensuring that only valid accesses are sent to the memory system, thus improving the efficiency and reliability of data transmission.

[0049] In one possible implementation of the first aspect, the loading storage unit includes a memory access request generation unit, which is configured to:

[0050] A memory access request is generated based on the memory access address of the non-outbound channel in the SIMD instruction;

[0051] The memory access request is sent to the UAV data cache unit to complete the memory access.

[0052] This application generates memory access requests by using the memory access address of an unbounded channel in the SIMD instruction, ensuring the correct submission and efficient execution of the access requests.

[0053] In one possible implementation of the first aspect, the load storage unit further includes a return data unit, the return data unit being configured to:

[0054] The data returned from the UAV data buffer unit is written to the general-purpose register unit.

[0055] For load instructions, the return data unit is responsible for receiving the data returned from the memory system and correctly writing it back to the general-purpose registers for use by subsequent instructions. This completes the entire load operation, ensuring the integrity of data processing.

[0056] According to a second aspect of the present invention, a memory access method is provided, applied to the processor described above, comprising:

[0057] SIMD commands are transmitted via the UAV command transmission unit;

[0058] SIMD instructions are received via the loading storage unit;

[0059] The opcode of the SIMD instruction, the address information of the target general-purpose register, and the address information of the target UAV register are obtained by parsing the memory unit.

[0060] The resource information of the target UAV register is read from the UAV register management unit via the loading storage unit according to the address information of the target UAV register;

[0061] When the SIMD instruction is determined to be a load instruction based on the opcode via the load storage unit, the channel logical address information of each channel of the SIMD instruction is read from the general-purpose register unit according to the address information of the target general-purpose register;

[0062] The loading storage unit determines whether the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive, based on the resource information of the target UAV register and the channel logical address.

[0063] If the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive, the memory access address of the first channel among the multiple channels is calculated by the loading storage unit, and the memory access addresses of the other channels among the multiple channels are calculated based on the memory access address of the first channel.

[0064] The loading storage unit generates a memory access request based on the memory access address of each channel of the SIMD instruction, so as to complete the memory access through the UAV data cache unit. Invention Overview Beneficial effects

[0065] Compared with the prior art, the beneficial technical effects of this application are as follows:

[0066] The memory access method provided in this application calculates the memory access address of the first channel among the multiple channels when the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive, and calculates the memory access addresses of the other channels among the multiple channels based on the memory access address of the first channel. This improves the throughput of load-store instructions with consecutive addresses, saves the number of memory address calculation ALUs, and reduces power consumption. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1 According to some embodiments of this application, a structural block diagram of a processor is shown;

[0069] Figure 2 According to some embodiments of this application, a flowchart is shown to illustrate whether the memory addresses to be accessed by multiple channels are consecutive;

[0070] Figure 3 According to some embodiments of this application, a layout method of texture2DArray in memory is shown;

[0071] Figure 4 According to some embodiments of this application, a schematic diagram of the element arrangement of a buffer resource is shown;

[0072] Figure 5According to some embodiments of this application, a schematic diagram of texture1DArray resource arrangement is shown;

[0073] Figure 6 According to some embodiments of this application, a schematic diagram of texture2DArray resource arrangement is shown;

[0074] Figure 7 According to some embodiments of this application, a schematic diagram of texture3DArray resource arrangement is shown;

[0075] Figure 8 According to some embodiments of this application, a flowchart of a memory access method is shown. Detailed Implementation

[0076] The illustrative embodiments of this application include, but are not limited to, a processor and memory access method.

[0077] To facilitate understanding of the technical solution of this application, some technical terms involved in this application will be explained below.

[0078] SIMD (Simultaneous Integrated Modeling) is a parallel computing architecture that allows a single instruction to operate on multiple data elements simultaneously, significantly improving data processing efficiency. For example, a traditional processor requires four instructions to perform four additions, while SIMD requires only one instruction. The working principle of SIMD in a GPU is as follows: The GPU organizes data into vectors, for example, four floating-point numbers form a vector. Each element in the vector is called a channel; for example, four elements have four channels. A single SIMD instruction performs the same operation on all channels simultaneously, such as performing addition on all four channels at the same time. Since image processing involves numerous scenarios where the same operation processes different data, such as applying the same filter to each pixel, applying SIMD to GPUs can greatly improve task processing efficiency.

[0079] Channel: In the SIMD architecture, one instruction processes multiple data elements, and each element is a channel. For example, a 4-channel SIMD instruction processes 4 data elements at the same time, just like 4 parallel pipelines.

[0080] Load instructions: Instructions that indicate when data needs to be loaded from GPU memory into the computing unit.

[0081] Storage instructions: Instructions that indicate the need to store the computation results from the computing unit back into GPU memory.

[0082] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0083] As mentioned earlier, the existing graphics processor's load-memory instruction processing unit calculates the memory addresses accessed by the SIMD instructions through several ALUs independently. In most cases, the throughput of load-memory instructions is limited by the number of ALUs, meaning that the ALUs become the performance bottleneck.

[0084] In view of this, the present invention provides a processor and a memory access method. By loading the memory unit, when it is determined that the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive, the memory access address of the first channel among the multiple channels is calculated, and the memory access addresses of the other channels among the multiple channels are calculated based on the memory access address of the first channel. Thus, for load-store instructions with consecutive addresses, the throughput of load-store instructions with consecutive addresses is improved, the number of memory address calculation ALUs is reduced, and power consumption is reduced.

[0085] The following is a combination of... Figure 1 The architecture of the processor 10 provided in this application will be described in detail.

[0086] Figure 1 According to some embodiments of this application, a structural block diagram of a processor 10 is provided. (See reference...) Figure 1 The processor 10 provided in this application includes: a UAV instruction sending unit 12, a UAV register management unit 13, a general-purpose register unit 14, a UAV data cache unit 15, and a load memory unit 11, wherein the UAV instruction sending unit 12, the UAV register management unit 13, the general-purpose register unit 14, and the UAV data cache unit 15 are all connected to the load memory unit 11.

[0087] UAV instruction sending unit 12 is used to send SIMD instructions to load-store unit 11. The SIMD instructions include load instructions or store instructions. Load instructions are used to read data from memory into general-purpose register unit 14, for example, loading data from a UAV resource in memory into general-purpose register unit 14; store instructions are used to write data from general-purpose register unit 14 into memory, for example, storing the calculation result in general-purpose register unit 14 into a specified UAV resource in memory. In some parts of the following text, SIMD instructions will also be referred to as load-store instructions.

[0088] UAV register management unit 13 is responsible for storing and managing UAV registers. Specifically, UAV register management unit 13 is used to receive read requests from load storage unit 11. The read request contains the address information of the target UAV register. UAV register management unit 13 is also used to return the corresponding resource information of the target UAV register to load storage unit 11 according to the address information of the target UAV register.

[0089] General-purpose register unit 14 is used to store the data required for SIMD instruction execution. Specifically, general-purpose register unit 14 is used to receive read / write requests from load memory unit 11, and write the data to the specified location according to the general-purpose register address specified in the read / write request, or read data from the specified location and return it to load memory unit 11.

[0090] UAV data caching unit 15 is used to cache data read and written by loading storage unit 11 and is responsible for handling memory access requests sent by loading storage unit 11. Upon receiving a memory access request, UAV data caching unit 15 first checks whether the requested data already exists in the cache. If the data exists, for load instructions, UAV data caching unit 15 directly reads the corresponding data from the cache and returns it to loading storage unit 11; for store instructions, it writes the data to be stored to the corresponding position in the cache. If the data does not exist, UAV data caching unit 15 first loads the target data block from memory into the cache, and then performs the corresponding read / write operations according to the request type. Through this mechanism, UAV data caching unit 15 ultimately completes the memory access requested by loading storage unit 11.

[0091] The loading storage unit 11 is configured to: receive SIMD instructions sent by the UAV instruction sending unit 12; parse the opcode of the SIMD instruction, the address information of the target general-purpose register, and the address information of the target UAV register; read the resource information of the target UAV register from the UAV register management unit 13 based on the address information of the target UAV register; if the SIMD instruction is determined to be a loading instruction based on the opcode, read the channel logical address information of each channel of the SIMD instruction from the general-purpose register unit 14 based on the address information of the target general-purpose register; determine whether the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive based on the resource information and channel logical address of the target UAV register; if the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive, calculate the memory access address of the first channel among the multiple channels, and calculate the memory access addresses of the other channels among the multiple channels based on the memory access address of the first channel; generate a memory access request based on the memory access addresses of each channel of the SIMD instruction, so as to complete the memory access through the UAV data cache unit 15.

[0092] In some embodiments, the loading storage unit 11 is further configured to: when the SIMD instruction is determined to be a storage instruction based on the opcode, read the channel logical address information of each channel of the SIMD instruction and the data to be stored from the general-purpose register unit 14 based on the address information of the target general-purpose register.

[0093] By incorporating storage instructions into the optimization scope, the consistency of the processor 10 in processing storage operations is ensured, and the efficiency of storage operations is improved simultaneously, resulting in a comprehensive improvement in the overall memory access performance of the processor 10.

[0094] In some embodiments, the opcode is a field in a SIMD instruction used to specify the operation type, and its encoded value defines the specific operation type of the SIMD instruction. For example, for the load and store instructions involved in this application, the opcode is used to distinguish whether the current SIMD instruction is performing a load operation to read data from memory or a store operation to write data to memory. The load-store unit 11 can determine the specific operation type of the instruction based on the opcode field, thereby executing the corresponding access operation process.

[0095] In some embodiments, the resource description information of the target UAV register includes base address, resource type, resource size, data layout, data format, and resource dimension. By including rich resource description information, a complete data foundation is provided for subsequent address continuity determination and memory access address calculation, which can adapt to complex access patterns of different resource types and layouts.

[0096] This base address refers to the starting physical address of the memory space occupied by the target unordered access view (UAV) resource.

[0097] The resource types include buffer resources and texture resources. Buffer resources include raw buffers and structured buffers. Texture resources include one-dimensional textures (Texture1D), one-dimensional texture arrays (Texture1DArray), two-dimensional textures (Texture2D), two-dimensional texture arrays (Texture2DArray), and three-dimensional textures (Texture3D).

[0098] Regarding resource size, for buffer resources, the size is described by the first element position and the number of elements. For texture resources, the size information includes parameters such as width, height, depth, first array slice index, array size, and level of detail (LOD).

[0099] Regarding data layout, buffer resources typically use a linear layout in memory. Texture resources can use either a linear layout or a zig-zag layout in memory.

[0100] Regarding data format, for buffer resources, the size of a single element in memory is represented by a byte stride. For texture resources, the data format is represented by a format enumeration, such as R8G8B8A8_UNORM, R16G16B16A16_FLOAT, R32G32B32A32_FLOAT, etc.

[0101] In some embodiments, the resource description information of the target UAV register also includes a valid bit, which is set to 1 only when the UAV register has been successfully bound and the resource configuration is valid. Before performing the operation, the loading memory unit 11 first checks the valid bit. If it is 0, it can be directly determined that the memory access cannot be performed, without the need for subsequent address calculation and continuity judgment.

[0102] exist Figure 1In the illustrated embodiment, the load memory unit 11 includes an address continuation detection unit 114. The address continuation detection unit 114 is configured to determine whether the memory addresses accessed by multiple channels of a SIMD instruction are continuation based on the resource information of the target UAV register and the channel logical address in the following manner: Based on the valid bits in the target UAV register, it determines whether the resource information of the target UAV register is valid; if the resource information of the target UAV register is valid, it determines whether the instruction access addresses of multiple channels of the SIMD instruction are continuation based on the channel logical address, where the instruction access address of multiple channels is the channel logical address of multiple channels; if the instruction access addresses between different channels of the SIMD instruction are continuation, it determines whether the memory addresses accessed by multiple channels of the SIMD instruction are continuation based on the resource information of the target UAV register and the data format of the SIMD instruction. By setting up a dedicated address continuation detection unit 114, first checking resource validity, then checking logical address continuity, and finally combining resource information to determine physical address continuity, efficient and accurate continuation detection is achieved.

[0103] refer to Figure 2 The address contiguousness detection unit 114 detects whether the memory addresses to be accessed by multiple channels of the SIMD instruction are contiguous, and the process includes the following steps:

[0104] Step S21: Determine if the UAV is valid. If it is, the UAV is valid and proceed to step S22. Otherwise, the UAV is invalid and the address is determined to be discontinuous.

[0105] Step S22: Determine whether the instruction access addresses between different channels are continuous. If they are, it indicates that the instruction access addresses between different channels are continuous, and proceed to step S23; otherwise, it indicates that the instruction access addresses between different channels are not continuous, and the addresses are determined to be discontinuous.

[0106] Step S23: Determine whether the memory access addresses between different channels are continuous. If they are, it means that the memory access addresses between different channels are continuous, and proceed to step S24; otherwise, it means that the memory access addresses between different channels are not continuous, and the addresses are determined to be discontinuous.

[0107] Step S24: Determine whether the access addresses of different channels are out of bounds. If they are, it means that the access addresses of different channels are out of bounds, and the addresses are determined to be discontinuous; otherwise, it means that the access addresses of different channels are not out of bounds, and the addresses are determined to be continuous.

[0108] It is understood that the execution order of steps S21 to S24 above is only an illustration. In other embodiments, other execution orders may be used, and some steps may be split or combined. This is not limited here.

[0109] In some embodiments, the channel logical address includes a first-dimensional logical address, a second-dimensional logical address, and a third-dimensional logical address. The address continuity detection unit 114 is configured to determine whether the access addresses of multiple channels of a SIMD instruction are continuous based on the channel logical addresses in the following ways: If the data layout in the resource information of the target UAV register is linear, and the second and third-dimensional logical addresses of multiple channels of the SIMD instruction are equal, and the first-dimensional logical addresses of multiple channels of the SIMD instruction form a continuous sequence, then the access addresses of multiple channels of the SIMD instruction are determined to be continuous. If the data layout in the resource information of the target UAV register is Zig-zag, and the third-dimensional logical addresses of multiple channels of the SIMD instruction are equal, and the arrangement of the first and second-dimensional logical addresses of multiple channels of the SIMD instruction matches a predefined Zig-zag pattern, then the access addresses of multiple channels of the SIMD instruction are determined to be continuous. Specific continuity judgment rules are defined for different data layouts, such as linear and Zig-zag layouts, enhancing the support capability for common data storage patterns in real-world applications. This enables the processor 10 provided in this application to not only be limited to idealized linear access, but also to effectively handle more complex, non-contiguous but logically regular access patterns designed to improve cache hit rate, thus expanding its applicability.

[0110] GPUs typically use SIMD instruction types, which allow multiple channels to be supported in a single instruction. For example, SIMD32 indicates support for 32 channels, and SIMD64 indicates support for 64 channels. This application will use the SIMD32 instruction type to illustrate the address contiguous detection method, but this method is also applicable to the SIMD64 instruction type and other SIMD instructions.

[0111] In the description of the continuous detection method below, various variables will be used. To ensure that the meaning of these variables is clear and unambiguous, each variable used in the following text will be explained in detail below:

[0112] Direct or derived variables in instructions; this application uses SIMD32 instructions as an example, therefore, the range of i in the following text is [0, 31].

[0113] InsChannelMask: Indicates the channel loaded or read in the load storage instruction, and its value is 1, 3, or 15;

[0114] InsChannelNumber: Indicates the number of data to be loaded or read in the load storage instruction; its value is 1, 2, or 4.

[0115] InsChannelNumberLog2=log2(InsChannelNumber);

[0116] InsChannelSize: Indicates the size in bytes of the data to be loaded or stored in the load / store instruction;

[0117] InsChannelSizeLog2=log2(InsChannelSize);

[0118] InsElementSize=InsChannelNumber*InsChannelSize;

[0119] InsElementSizeLog2=InsChannelNumberLog2+InsChannelSizeLog2;

[0120] Offset[i] represents the offset address of the buffer resource in bytes;

[0121] Addr0[i] represents the address of the first dimension of the texture resource; for texture1D, texture1DArray, texture2D, texture2DArray, and texture3D, it represents the x-coordinate;

[0122] Addr1[i] represents the address of the second dimension of the texture resource; for texture1DArray, it represents the index of the texture array resource; for texture2D or texture3D, it represents the y-coordinate; for other resources, its value is 0.

[0123] Addr2[i] represents the third-dimensional address of the texture resource; for texture2DArray, it represents the index value of the texture array resource; for texture3D, it represents the z-coordinate; for other resources, its value is 0.

[0124] For buffer resources or texture1D, one-dimensional addresses are typically used to access the resources; for texture1DArray and texture2D, two-dimensional addresses are typically used to access the resources; and for texture2Darray or texture3D, three-dimensional addresses are typically used to access the resources.

[0125] The direct or derived variables in the UAV register are as follows:

[0126] UAVResType: Indicates the resource type of the UAV, which can be raw buffer, structure buffer, texture1D, texture1DArray, texture2D, texture2DArray, and texture3D, etc.

[0127] UAVFormatByteSize: Indicates the byte size of the format;

[0128] UAVFormatByteSizeLog2=log2(UAVFormatByteSize);

[0129] UAVFormatChannelMask: Represents the channel mask for the format; its value is 1, 3, 7, or 15.

[0130] For example, for R16_FLOAT, channel mask = 1, R16G16_FLOAT, channel mask = 3, R5G6B5_UNORM, channel mask = 7, R16G16B16A16_FLOAT, channel mask = 15;

[0131] UAVStride: Indicates the size in bytes of a single element of the buffered resource;

[0132] UAVFirstElement: Represents the offset of the first element that the UAV view can use in the buffer resource;

[0133] UAVNumberElement: Represents the number of elements in the buffer resources that the UAV view can use;

[0134] UAVFirstArrayindexOrDepth: For texture1DArray or texture2DArray, it represents the offset of the first texture that the UAV view can use in the texture array; for texture3D, it represents the offset of the first texture that can be used in the UAV view in the height direction; texture1D and texture2D can be regarded as special cases of texture1DArray and texture2DArray, and this value is always equal to 0;

[0135] UAVArraySizeOrDepth: For texture1DArray, texture2DArray, or texture3D, it represents the number of textures that the UAV view can use; texture1D and texture2D can be regarded as special cases of texture1DArray and texture2DArray, and this value is always equal to 1;

[0136] LOD: Indicates the level of detail of the texture resources used by the UAV view;

[0137] UAVWidth: Indicates the width of the resource referenced by the UAV;

[0138] UAVHeight: Represents the height of the resource referenced by the UAV;

[0139] Linear layout refers to elements being arranged linearly and continuously in memory. For two-dimensional or multi-dimensional texture resources, such as texture2D and texture3D, either row-first or column-first methods can be used for data arrangement. The methods for detecting address contiguity are similar for both. This application uses row-first data arrangement as an example for explanation. Furthermore, to improve memory access efficiency, for multi-dimensional data, processors 10, such as GPUs, typically align the size of each dimension to a specific number of bytes, such as 1 Kbits. Therefore, for linearly arranged multi-dimensional texture resources, this application only checks whether the address of its first dimension is contiguity.

[0140] For RAW buffer resources, GPUs typically use byte offsets to access data in memory; while for structured cache resources, GPUs can use two-dimensional addresses (structIndex, offsetInStruct) to access data in memory, or they can convert the two-dimensional address to a one-dimensional byte offset address to access data in memory. The conversion formula is shown below:

[0141] offset=structIndex*UAVStride+offsetInStruct formula (1)

[0142] Where offset represents the byte offset address of the buffer resource.

[0143] structIndex is: the structure index;

[0144] offsetInStruct is the offset address inside the structure;

[0145] UAVStride is the size in bytes of a single element of the buffered resource.

[0146] For structured buffers, their two-dimensional addresses are converted to one-dimensional byte offset addresses. Next, for byte access addresses, before address contiguous detection, the logical address needs to be calculated based on the byte offset address. The conversion formula is as follows:

[0147] addr0[i]=offset[i]>>InsElementSizeLog2 Formula (2)

[0148] Where addr0[i] represents the address of the first dimension of the texture resource; for texture1D, texture1DArray, texture2D, texture2DArray, and texture3D, it represents the x-coordinate; offset[i] represents the byte offset address of the buffer resource. InsElementSize = InsChannelNumber * InsChannelSize, where InsChannelNumber represents the number of data to be loaded or read in the load-store instruction; and InsChannelSize represents the size of the data to be loaded or stored in bytes in the load-store instruction.

[0149] Check if the second and third dimension addresses of different channels are equal. If they are not equal, the access addresses are considered to be discontinuous.

[0150] Check if the first dimension address of the first channel is greater than the tail channel address. If the first channel address is greater than the tail channel address, then invert the first dimension address; otherwise, keep the first dimension address unchanged.

[0151]

[0152] Where, addr0

[31] is the address of the last channel in the SIMD32 instruction; addr0_new[i] refers to the channel address with index i after adjustment according to formula (3);

[0153] addr0[31-i] refers to the address of the channel with index "31-i";

[0154] The first dimension address of each channel is subtracted from the first dimension address of the first channel, as shown in the formula below.

[0155] delta0[i]=addr0_new[i]-addr0_new[0](i=0,1,...,31) Formula (4)

[0156] Where delta0[i] refers to the difference between the address of the channel with index i after adjustment according to formula (3) and the address of the first channel.

[0157] Determine whether delta0[i] is equal to i. If delta[i] is equal to i for all channels, then the channels are considered continuous; otherwise, they are considered discontinuous.

[0158] Zig-zag layout is a common memory arrangement method for multidimensional data in GPUs. Its core principle is to reorganize two-dimensional or multidimensional data along a zig-zag path. This arrangement aims to optimize the spatial locality of memory access. Table 1 below describes an 8x4 zig-zag data layout. The first data in the table represents the element's index in memory, and the second data represents the element's coordinates in screen space. In screen space, the top-left point is represented as (0, 0), the horizontal axis is the x-axis, and the vertical axis is the y-axis. Typically, the driver will only set the data layout of multidimensional texture resources to zig-zag. If other resources are also set to zig-zag, it is directly considered as non-contiguous address space.

[0159] Table 1

[0160]

[0161] If the data layout in the resource information of the target UAV register is Zig-zag, first check if the third dimension address is the same. If they are not the same, it is determined that the address is not contiguous. Then check if the first dimension address of the first channel is greater than the tail channel address. If the first channel address is greater than the tail channel address, the first dimension address and the second dimension address are reversed respectively. Otherwise, the first dimension address and the second dimension address remain unchanged.

[0162]

[0163]

[0164] The first and second dimension addresses of each channel are subtracted from the first and second dimension addresses of the first channel, as shown below.

[0165] delta1[i]=addr0_new[i]-addr0_new[0](i=0,1,…,31) Formula (7)

[0166] delta1[i]=addr1_new[i]-addr1_new[0](i=0,1,…,31) Formula (8)

[0167] Determine whether delta0[i] and delta1[i] are the same as the x and y coordinates of the element with index i in Table 1. If delta0 and delta1 of all channels are the same as the coordinates in Table 1, then the addresses are considered to be continuous; otherwise, the addresses are considered to be discontinuous.

[0168] In some embodiments, the address continuation detection unit 114 is configured to determine whether the memory addresses to be accessed by multiple channels of a SIMD instruction are contiguous based on the resource information of the target UAV register and the data format of the SIMD instruction in the following manner: when the resource type is a buffer resource, if the instruction access addresses of multiple channels of the SIMD instruction are contiguous, then the memory addresses to be accessed by multiple channels of the SIMD instruction are determined to be contiguous; when the resource type is a texture resource, if the result of a bitwise AND operation between the data channel mask of the SIMD instruction and the channel mask of the data format of the target UAV register is equal to the channel mask of the data format of the target UAV register, then the memory addresses to be accessed by multiple channels of the SIMD instruction are determined to be contiguous.

[0169] This application distinguishes the continuity criteria for buffer resources and texture resources. For buffers, logical address continuity usually implies physical address continuity; for textures, a channel mask matching judgment is introduced to ensure that in texture processing, address calculation optimization is only enabled when all data channels are effectively accessed and the access pattern is regular. This differentiated processing method ensures the adaptability of the processor 10 to different resource types.

[0170] In some embodiments, the loading storage unit 11 includes a memory address calculation unit 110, which is configured to calculate the memory access address of the first channel among multiple channels by: calculating the memory access address of the first channel based on the base address, dimension information, and data layout in the target UAV register, and the channel logical address information of the first channel read from the general-purpose register unit 14. This application provides an accurate calculation basis for subsequent fast address calculation based on offsets by setting up a dedicated memory address calculation unit 110 to accurately calculate the memory access address of the first channel.

[0171] In some embodiments, the memory address calculation unit 110 is configured to calculate the memory access addresses of the remaining channels (excluding the first channel) based on the memory access address of the first channel in the following manner: determining the address offset of the remaining channels according to the data format and number of channels of the SIMD instruction; determining the access direction of the address based on the address continuity detection result; and calculating the memory access addresses of the remaining channels based on the memory access address of the first channel, the address offset of the remaining channels, and the access direction of the address. For continuous address access, the processor 10 provided in this application no longer requires complex logical-to-physical address conversion for the addresses of the remaining channels (excluding the first channel), but can obtain them through simple offset addition. This greatly reduces the occupation of ALU computing resources, simplifying multiple independent address calculations that originally required multiple cycles into a single complete calculation plus multiple fast incremental calculations, significantly improving the efficiency of address generation, thereby directly improving the throughput of load-memory instructions.

[0172] In some embodiments, the load memory unit 11 is further configured to: when it is determined that the memory addresses to be accessed by multiple channels of the SIMD instruction are not contiguous, calculate the memory access address of each channel in the following manner: obtain the channel logical address of each channel; and convert the channel logical address of each channel into the corresponding memory access address based on the base address, resource dimension, data layout, and data format of the target UAV register. When the memory addresses to be accessed by multiple channels are not contiguous, the processor 10 will automatically fall back to the traditional mode of calculating the memory access address independently for each channel, thereby improving the compatibility of the processor 10.

[0173] In other words, if it is determined that the memory addresses accessed by multiple channels of a SIMD instruction are consecutive, the memory access addresses of the remaining channels can be quickly calculated based on the memory access address of the first channel. This calculation method is referred to as the fast address calculation method below. Otherwise, the conventional method is used to calculate the memory access addresses of each channel. The formula for calculating memory access addresses varies depending on the UAV resource type and data layout. In addition, different hardware manufacturers may also use different memory access address calculation methods.

[0174] The following example, using a linearly arranged texture2DArray, illustrates the difference between conventional memory address calculation methods and methods based on fast address calculation. Figure 3 This represents a layout method for texture2DArray in memory, where pixels are arranged in units of 10 ... Figure 3 Taking point C0 as the starting point, along... Figure 3 The directions of the dashed arrows are arranged sequentially in memory.

[0175] For the conventional address calculation method: the memory address of each channel can be obtained by adding the three parts in the following formula (9):

[0176] VA=UAVBaseAddr+LevelOffset+Offset formula (9)

[0177] in, UAVBaseAddr represents the starting virtual address in memory of the resource referenced by the UAV; LevelOffset represents the offset of the LOD level of the pixel relative to UAVBaseAddr; offset represents the offset of the pixel in the LOD level.

[0178] Next, we will introduce the calculation methods for LevelOffset and offset. First, the calculation method for LevelOffset is shown in the following formula (10):

[0179]

[0180] Where LOD represents the LOD set in the UAV register, and SubResourceSize(i) represents the size of the sub-resource when LOD = i, and its calculation method is as follows:

[0181] SubResourceSize(i)=UAVArraySizeOrDepth*max(UAVWidth>>i, 1)*max(UAVHeight>>i, 1) Formula (11)

[0182] Then, the Offset is calculated as follows:

[0183] offset=addr0+addr1*max(UAVWidth>>i, 1)+addr2*max(UAVWidth>>LOD, 1)*max(UAVHeight>>LOD, 1) Formula (12)

[0184] Where addr0 represents the x-coordinate used when the channel accesses the texture2DArray in the SIMD32 instruction; addr1 represents the y-coordinate used when the channel accesses the texture2DArray in the SIMD32 instruction; and addr2 represents the arrayIdx coordinate used when the channel accesses the texture2DArray in the SIMD32 instruction.

[0185] Figure 3 The Chinese meaning of MipMap LOD in this context is: Mip Map Level of Detail.

[0186] Array index means: array index;

[0187] LOD stands for Level of Detail;

[0188] Sub Resource means: a sub-resource;

[0189] UAV Width indicates the width of the resource referenced by the UAV.

[0190] UAV Height indicates the height of the resource referenced by the UAV;

[0191] UAV Array Size or Depth indicates the number of textures that can be used by the UAV view for texture1DArray, texture2DArray, or texture3D; texture1D and texture2D can be considered special cases of texture1DArray and texture2DArray, and this value is always equal to 1.

[0192] For the fast address calculation method, for the first channel, i = 0, according to formulas (9), (10), (11) and (12), and the addresses of channel 0, addr0[0], addr1[0] and addr2[0], the memory address VA[0] of the first channel can be calculated;

[0193] For all channels except the first channel, i! = 0, then the address VA[i] of the i-th channel (excluding the first channel) can be calculated using the following formula (13):

[0194] VA[i]=VA[0]+FlipFlag*i*UAVFormatByteSize formula (13)

[0195] Here, FlipFlag indicates that if addr is sorted in ascending order, the value of FlipFlag is 0; otherwise, its value is -1.

[0196] UAVFormatByteSize represents the size in bytes of the data type corresponding to an element in a UAV.

[0197] If the address is reversed during continuous address detection, the FligFlag value is set to -1; otherwise, the FlipFlag value is set to 1.

[0198] By comparing the conventional address calculation method and the fast address calculation method, it can be found that for channels 1 to 31, the fast address calculation method uses one multiplication and one addition, while the conventional address calculation method uses three multiplications and three additions. For resources with higher dimensions, such as texture2DArray and texture3D, the memory access address calculation process becomes more complex, requiring more adders and multipliers. However, the fast address calculation method still only uses one multiplication and one addition for channels 1 to 31. Therefore, the fast address calculation method significantly reduces the computational load and the consumption of ALU computing resources.

[0199] Assuming a single SIMD32 store instruction, the access addresses for different channels are as follows:

[0200] (32, 0, 0), (33, 0, 0), (34, 0, 0), (35, 0, 0),

[0201] (36, 0, 0), (37, 0, 0), (38, 0, 0), (39, 0, 0),

[0202] (40, 0, 0), (41, 0, 0), (42, 0, 0), (43, 0, 0)

[0203] (44, 0, 0), (45, 0, 0), (46, 0, 0), (47, 0, 0)

[0204] (48, 0, 0), (49, 0, 0), (50, 0, 0), (51, 0, 0),

[0205] (52, 0, 0), (53, 0, 0), (54, 0, 0), (55, 0, 0),

[0206] (56, 0, 0), (57, 0, 0), (58, 0, 0), (59, 0, 0)

[0207] (60, 0, 0), (61, 0, 0), (62, 0, 0), (63, 0, 0)

[0208] In Example 1, it is assumed that the instruction storage data format is UINT8 and the instruction storage data channel mask is .xy. The UAV resource type is texture2D, the UAV resource format is R16G16B16A16_UINT, the UAV data layout is linear, the UAV memory base address is 0, the UAV resource width is 64, and the UAV resource height is 64. First, it is determined whether the instruction access address is continuous. The delta[i] calculated according to formula (4) is as follows: Delta[0]=32–32=0, delta[1]=33-32=1,…, delta

[31] =62-32=31. The calculated delta[i]==i. Therefore, it can be determined that the instruction access address is continuous. According to the following formula (14), it can be determined that the memory access address is not continuous.

[0209] UAVFormatChannelMask & InsChannelMask==UAVFormatChannelMask formula (14)

[0210] UAVFormatChannelMask&InsChannelMask=3 UAVFormatChannelMask=15 UAVFormatChannelMask&InsChannelMask! =UAVFormatChannelMask

[0211] In Example 2, based on Example 1 above, the data channel mask for the stored instructions is changed from .xy to .xyzw, and the UAV resource width is changed from 64 to 60. The instruction access addresses are continuous, please refer to Example 1 above; according to formula (10), it can be determined that the memory access addresses are continuous;

[0212] Formula (15) can be used to determine if the first dimension address has exceeded the bounds;

[0213] max(addr0[0], addr0

[31] )=63>UAVWidth=60addr1[0]<addr1[1]<…<addr1

[31] ≤max(addr1[0], addr1

[31] ) Formula (15)

[0214] In Example 3, the UAV resource width is changed from 60 to 64, based on Example 2. The instruction access address is continuous, please refer to Example 1; the memory access address is continuous, please refer to Example 2; it can be determined by formula (15) that the channel address has not exceeded the boundary.

[0215] max(addr0[0], addr0

[31] )=63<UAVWidth=64 max(addr1[0], addr1

[31] )=0<UAVHeight=64 addr2

[31] =0<UAVArraySize=1

[0216] The first three conditions were all met, therefore, it can be determined that the memory instruction addresses are consecutive. Since the memory instruction addresses are consecutive, their addresses can be calculated using a fast method:

[0217] The memory address of the first channel, i.e., the first channel, is calculated using formulas (9), (10), (11) and (12): VA[0] = 0 + 32 * 8 + 0 * 64 + 0 * 64 * 64 = 256.

[0218] The memory addresses of other channels are calculated using formula (13). The access addresses do not flip, therefore, FligFlag = 1. VA[1] = 256 + 8 * 1 = 264; VA[2] = 256 + 8 * 2 = 272; ... VA

[31] = 256 + 8 * 31 = 504.

[0219] In some embodiments, the load memory unit 11 includes an address out-of-bounds detection unit 111, which is configured to perform out-of-bounds detection on the memory access addresses corresponding to each channel of the SIMD instruction and filter out out-of-bounds channels. By introducing the address out-of-bounds detection unit 111, this application effectively prevents illegal memory accesses, improving the stability and security of the processor 10. Filtering out out-of-bounds channels avoids generating meaningless memory requests or exceptions, ensuring that only valid accesses are sent to the memory system, thus improving the efficiency and reliability of data transmission.

[0220] The address accessed in a load-store instruction may exceed the resource size specified in the UAV register. This can lead to out-of-bounds reads and writes. Out-of-bounds reads and writes not only increase memory access volume, but out-of-bounds writes may also corrupt critical data of the current process or other processes, causing GPU malfunctions. Therefore, for out-of-bounds reads and writes, the GPU does not actually send a read / write request to memory. For out-of-bounds writes, the GPU typically discards the write operation, while for out-of-bounds reads, the GPU usually returns a default value.

[0221] Out-of-bounds read / write operations do not actually access memory, thus disrupting the continuity of memory access for load-store instructions. For instructions that have already passed the continuity check for memory access addresses and instruction access addresses, only the addresses of the first and last channels of the instruction need to be checked for out-of-bounds access. If the addresses of the first and last channels are within the valid range, then the addresses of other channels are also within the valid range. Different resource types require different address out-of-bounds detection methods, specifically:

[0222] Regarding buffer resources, for instructions that are continuously detected by memory access address and instruction access address, the following two inequalities can be derived, at least one of which is true, and the maximum values ​​from offset[0] to offset

[31] are all less than or equal to max(offset[0], offset

[31] );

[0223] offset[0]<offset[1]<…<offset

[31] ≤max(offset[0], offset

[31] ) offset

[31] <offset

[30] <…<offset[0]≤max(offset[0], offset

[31] )

[0224] From the above two inequalities, it can be seen that the maximum address of all channels in the SIMD32 instruction is max(offset[0], offset

[31] ). Therefore, by judging whether the maximum address of a channel is out of bounds, it can be inferred whether other channels are out of bounds. If the maximum address is not out of bounds, it can be determined that none of the channels are out of bounds. The size of the buffer resource in memory space can be calculated by UAVStride * UAVNumberElement, and its meaning is as follows: Figure 4 As shown.

[0225] Based on the above analysis, the formula for detecting address out of bounds of buffer resources can be obtained as shown in the following formula (16). If the judgment condition is false, it means that the address is out of bounds; otherwise, it means that the address is valid.

[0226] max(offset[0], offset

[31] )<UAVStride*UAVNumberElement formula (16)

[0227] For a one-dimensional texture array (Texture1DArray), for instructions that have been continuously detected by memory access address and instruction access address, it can be deduced that at least one of the following two inequalities is true, and the values ​​of addr0[0] to addr0

[31] are all less than or equal to max(addr0[0], addr0

[31] ).

[0228] addr0[0]<addr0[1]<…<addr0

[31] ≤max(addr0[0], addr0

[31] ) addr0

[31] <addr0

[30] <…<addr0[0]≤max(addr0[0], addr0

[31] )

[0229] Through these two inequalities, it can be seen that the maximum address value of all channels in the SIMD32 instruction is max(addr0[0], addr0

[31] ). We can determine whether other channels are out of bounds by checking if the maximum address value of addr0 is out of bounds. If the maximum address value is not out of bounds, then none of the channels are out of bounds. Different LOD values ​​in the UAV register correspond to different sizes of their corresponding sub-resources, such as... Figure 5 As shown, different LOD values ​​have different UAV Widths. Therefore, when performing out-of-bounds checks, the size of the resource corresponding to the current LOD needs to be used.

[0230] Based on the above analysis, we can obtain the formula for address out-of-bounds detection of a one-dimensional texture array. If the judgment condition is false, it means that the address is out of bounds; otherwise, it means that the address is valid.

[0231] max(addr0[0], addr0

[31] <max(1, UAVWidth>>LOD)(addr1[0]=addr1[1]=…=addr1

[31] )<UAVArraySizeOrDepth Formula (17)

[0232] Among them, such as Figure 5 As shown, Addr0 corresponds to the x-coordinate, addr1 corresponds to the array index, and LOD represents the detail level of the mipmap.

[0233] For a two-dimensional texture array (Texture2DArray), for instructions that have been continuously detected by memory access address and instruction access address, it can be deduced that at least one of the following two inequalities is true, and the values ​​of addr1[0] to addr1

[31] are all less than or equal to max(addr1[0], addr1

[31] ).

[0234] addr1[0]<addr1[1]<…<addr1

[31] ≤max(addr1[0], addr1

[31] ) addr1[0]<addr1[1]<…<addr1

[31] ≤max(addr1[0], addr1

[31] )

[0235] Through these two inequalities and the above formula (17), it can be seen that the maximum address values ​​of addr0 and addr1 for all channels in the SIMD32 instruction are max(addr0[0], addr0

[31] ) and max(addr1[0], addr1

[31] ). It can be determined whether other channels are out of bounds by judging whether the maximum values ​​of addr0 and addr1 are out of bounds. If the maximum address value is not out of bounds, then all channels are not out of bounds. Different LOD values ​​in the UAV register correspond to different sizes of their corresponding sub-resources, such as... Figure 6 As shown, different LOD values ​​have different UAVWidth and UAVHeight. Therefore, when performing out-of-bounds checks, the size of the resource corresponding to the current LOD needs to be used.

[0236] Based on the above analysis, we can obtain the formula for detecting out-of-bounds addresses in a two-dimensional texture array. If the condition is false, it means that the address is out of bounds; otherwise, it means that the address is valid.

[0237] max(addr0[0], addr0

[31] )<max(1, UAVWidht>>LOD) max(addr1[0],addr1

[31] )<max(1,UAVHeight>>LOD) (addr2[0]=addr2[1]=…=addr2

[31] )<UAVArraySizeOrDepth formula (18)

[0238] Among them, such as Figure 6 As shown, Addr0 corresponds to the x-coordinate, addr1 corresponds to the y-coordinate, and addr2 corresponds to the array index.

[0239] For a 3D texture array, for instructions that have been continuously detected by memory access addresses and instruction access addresses, such as... Figure 7 As shown, different LOD values ​​have different UAV Width, UAVHeight, and UAVArraySizeOrDepth. Therefore, when performing out-of-bounds checks, the size of the resource corresponding to the current LOD needs to be used. Through formulas (17) and (18), it can be known that the maximum values ​​of addr0 and addr1 are max(addr0[0], addr0

[31] ) and max(addr1[0], addr1

[31] ). Therefore, the following formula can be used to determine whether the address of the three-dimensional texture array is out of bounds; if the judgment condition is false, it means that the address is out of bounds; otherwise, it means that the address is valid.

[0240] max(addr0[0], addr0

[31] )<max(1, UAVWidht>>LOD) max(addr1[0], addr1

[31] )<max(1, UAVHeight>>LOD) (addr2

[31] =addr2

[30] =…=addr2[0])<max(1, UAVArraySizeOrDepth>>LOD) Formula (19)

[0241] Among them, such as Figure 7 As shown, addr0 corresponds to the x-coordinate, addr1 corresponds to the y-coordinate, and addr2 corresponds to the z-coordinate.

[0242] In some embodiments, the loading storage unit 11 includes a memory access request generation unit 112, which is configured to: generate a memory access request based on the memory access address of an unbounded channel in the SIMD instruction; and send the memory access request to the UAV data cache unit 15 to complete the memory access. This application generates memory access requests using the memory access address of an unbounded channel in the SIMD instruction, ensuring the correct submission and efficient execution of the access request.

[0243] In some embodiments, the load storage unit 11 further includes a return data unit 113, which is configured to write data returned from the UAV data buffer unit 15 to the general-purpose register unit 14. For load instructions, the return data unit 113 is responsible for receiving the data returned from the memory system and correctly writing it back to the general-purpose register for use by subsequent instructions. In this way, the entire load operation is completed, ensuring the integrity of data processing.

[0244] Furthermore, this application also provides a memory access method applied to a processor 10, wherein the processor 10 includes a UAV instruction sending unit 12, a UAV register management unit 13, a general-purpose register unit 14, a UAV data cache unit 15, and a load memory unit 11, wherein the UAV instruction sending unit 12, the UAV register management unit 13, the general-purpose register unit 14, and the UAV data cache unit 15 are all connected to the load memory unit 11. (See reference...) Figure 8 The memory access method provided in this application includes the following steps:

[0245] Step S81: Send SIMD instructions via UAV instruction sending unit 12;

[0246] Step S82: Receive SIMD instructions via the loading storage unit 11;

[0247] Step S83: The opcode of the SIMD instruction, the address information of the target general-purpose register, and the address information of the target UAV register are obtained by parsing the memory unit 11.

[0248] Step S84: Read the resource information of the target UAV register from the UAV register management unit 13 according to the address information of the target UAV register via the load storage unit 11;

[0249] Step S85: If the SIMD instruction is determined to be a load instruction based on the opcode via the load storage unit 11, the channel logical address information of each channel of the SIMD instruction is read from the general-purpose register unit 14 according to the address information of the target general-purpose register.

[0250] Step S86: Based on the resource information of the target UAV register and the channel logical address, the loading storage unit 11 determines whether the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive.

[0251] Step S87: If the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive, the memory access address of the first channel among the multiple channels is calculated by the loading storage unit 11, and the memory access addresses of the other channels among the multiple channels are calculated based on the memory access address of the first channel.

[0252] Step S88: A memory access request is generated by the loading storage unit 11 based on the memory access addresses of each channel according to the SIMD instructions, so as to complete the access to memory through the UAV data cache unit 15.

[0253] The memory access method provided in this application calculates the memory access address of the first channel among the multiple channels when the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive, and calculates the memory access addresses of the other channels among the multiple channels based on the memory access address of the first channel. This improves the throughput of load-store instructions with consecutive addresses, saves the number of memory address calculation ALUs, and reduces power consumption.

[0254] The implementation details of each step from S81 to S88 have been described in detail in the previous section on multiple embodiments of the processor's loading memory unit, and will not be repeated here.

[0255] It is understood that the execution order of steps S81 to S88 above is only an illustration. In other embodiments, other execution orders may be used, and some steps may be split or combined. This is not limited here.

[0256] The various embodiments of the mechanisms disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.

[0257] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a Digital Signal Processor (DSP), a microcontroller, an Application Specific Integrated Circuit (ASIC), or a microprocessor.

[0258] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.

[0259] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other forms of propagated signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.

[0260] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order may not be necessary. Rather, in some embodiments, these features may be arranged in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular figure does not imply that such features are required in all embodiments, and in some embodiments, these features may be omitted or may be combined with other features.

[0261] It should be noted that all units / modules mentioned in the device embodiments of this application are logical units / modules. Physically, a logical unit / module can be a physical unit / module, a part of a physical unit / module, or a combination of multiple physical units / modules. The physical implementation of these logical units / modules themselves is not the most important factor; the combination of functions implemented by these logical units / modules is the key to solving the technical problems proposed in this application. Furthermore, to highlight the innovative aspects of this application, the above-described device embodiments of this application have not introduced units / modules that are not closely related to solving the technical problems proposed in this application. This does not mean that the above-described device embodiments do not contain other units / modules.

[0262] It should be noted that in the examples and description of this patent, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Industrial applicability

[0263] The processor and memory access method of this application can be used in the processing unit of a graphics processor's load-memory instruction. By independently calculating the memory addresses accessed by different channels of SIMD instructions through several Arithmetic Logic Units (ALUs), the throughput of load-memory instructions is not limited by the number of ALUs. Therefore, while improving the throughput of load-memory instructions, it is not necessary to increase the number of ALUs for calculating additional memory addresses. This method can be applied to optimize hardware architecture design, reduce hardware costs, and achieve high-performance computing.

[0264] Although this application has been illustrated and described with reference to certain preferred embodiments thereof, those skilled in the art should understand that various changes in form and detail may be made thereto without departing from the spirit and scope of this application.

Claims

1. A processor, comprising: The loading storage unit includes a UAV instruction sending unit, a UAV register management unit, a general-purpose register unit, and a UAV data buffer unit connected thereto; wherein the loading storage unit is configured as follows: Receive SIMD instructions, which are sent by the UAV instruction sending unit; The opcode of the SIMD instruction, the address information of the target general-purpose register, and the address information of the target UAV register are obtained by parsing. The resource information of the target UAV register is read from the UAV register management unit according to the address information of the target UAV register; If the SIMD instruction is determined to be a load instruction based on the opcode, the channel logical address information of each channel of the SIMD instruction is read from the general-purpose register unit according to the address information of the target general-purpose register; Based on the resource information of the target UAV register and the channel logical address, determine whether the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive; If it is determined that the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive, the memory access address of the first channel among the multiple channels is calculated, and the memory access addresses of the remaining channels other than the first channel are calculated based on the memory access address of the first channel; and Memory access requests are generated based on the memory access addresses of each channel according to the SIMD instructions, so as to complete the access to memory through the UAV data cache unit.

2. The processor according to claim 1, wherein, The loading storage unit is further configured to: when the SIMD instruction is determined to be a storage instruction based on the opcode, read the channel logical address information of each channel of the SIMD instruction and the data to be stored from the general-purpose register unit based on the address information of the target general-purpose register.

3. The processor according to claim 1, wherein, The resource description information of the target UAV register includes base address, resource type, resource size, data layout, data format, and resource dimension.

4. The processor according to claim 3, wherein, The load memory unit includes an address contiguousness detection unit, configured to determine whether the memory addresses to be accessed by multiple channels of the SIMD instruction are contiguous based on the resource information of the target UAV register and the channel logical address: Based on the valid bits in the target UAV register, determine whether the resource information of the target UAV register is valid; If the resource information of the target UAV register is determined to be valid, based on the channel logical address, it is determined whether the multiple channel instruction access addresses of the SIMD instruction are consecutive, wherein the instruction access addresses of the multiple channels are the channel logical addresses of the multiple channels; and If it is determined that the instruction access addresses between different channels of the SIMD instruction are consecutive, based on the resource information of the target UAV register and the data format of the SIMD instruction, it is determined whether the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive.

5. The processor according to claim 4, wherein, The channel logical address includes a first-dimensional logical address, a second-dimensional logical address, and a third-dimensional logical address. The address continuity detection unit is configured to determine whether multiple channel instruction access addresses of the SIMD instruction are consecutive based on the channel logical address in the following manner: If the data layout in the resource information of the target UAV register is linear, and if the second and third logical addresses of multiple channels of the SIMD instruction are equal, and the first logical addresses of multiple channels of the SIMD instruction form a continuous sequence, then it is determined that the instruction access addresses of multiple channels of the SIMD instruction are continuous; and If the data layout in the resource information of the target UAV register is Zig-zag, and if the third-dimensional logical addresses of multiple channels of the SIMD instruction are equal, and the arrangement of the first and second-dimensional logical addresses of multiple channels of the SIMD instruction matches the predefined Zig-zag pattern, then it is determined that the instruction access addresses of multiple channels of the SIMD instruction are continuous.

6. The processor according to claim 4, wherein, The address contiguousness detection unit is configured to determine whether the memory addresses to be accessed by multiple channels of the SIMD instruction are contiguous based on the resource information of the target UAV register and the data format of the SIMD instruction in the following manner: When the resource type is a buffer resource, if the access addresses of multiple channels of the SIMD instruction are consecutive, then it is determined that the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive; and When the resource type is a texture resource, if the result of a bitwise AND operation between the data channel mask of the SIMD instruction and the channel mask of the data format of the target UAV register is equal to the channel mask of the data format of the target UAV register, then it is determined that... The memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive.

7. The processor according to claim 3, wherein, The loading storage unit includes a memory address calculation unit, configured to calculate the memory access address of the first channel among the plurality of channels in the following manner: The memory access address of the first channel is calculated based on the base address, dimension information, and data layout in the target UAV register, as well as the channel logical address information of the first channel read from the general-purpose register unit.

8. The processor according to claim 7, wherein, The memory address calculation unit is configured to calculate the memory access addresses of the remaining channels (excluding the first channel) among the plurality of channels based on the memory access address of the first channel in the following manner: The address offsets of the remaining channels are determined based on the data format and number of channels of the SIMD instructions; The access direction of the address is determined based on the results of continuous address detection; and The memory access addresses of the remaining channels are calculated based on the memory access address of the first channel, the address offset of the remaining channels, and the access direction of the address.

9. The processor according to claim 3, wherein, The load memory unit is further configured to: calculate the memory access address of each channel in the case that the memory addresses to be accessed by multiple channels of the SIMD instruction are not contiguous, by means of the following method: Obtain the channel logical address for each channel; and Based on the base address, resource dimension, data layout, and data format of the target UAV register, the channel logical address of each channel is converted into the corresponding memory access address.

10. The processor according to claim 1, wherein, The load storage unit includes an address out-of-bounds detection unit, which is configured to: Out-of-bounds detection is performed on the memory access addresses corresponding to each channel of the SIMD instruction, and channels that exceed the bounds are filtered out.

11. The processor according to claim 10, wherein, The loading storage unit includes a memory access request generation unit, configured as follows: A memory access request is generated based on the memory access address of the non-out-of-bounds channel in the SIMD instruction; and The memory access request is sent to the UAV data cache unit to complete the memory access.

12. The processor according to claim 1, wherein, The loading storage unit also includes a return data unit, configured as follows: The data returned from the UAV data buffer unit is written to the general-purpose register unit.

13. A memory access method, applied to the processor as described in claim 1, comprising: SIMD commands are transmitted via the UAV command transmission unit; SIMD instructions are received via the loading storage unit; The opcode of the SIMD instruction, the address information of the target general-purpose register, and the address information of the target UAV register are obtained by parsing the memory unit. The resource information of the target UAV register is read from the UAV register management unit via the loading storage unit according to the address information of the target UAV register; When the SIMD instruction is determined to be a load instruction based on the opcode via the load storage unit, the channel logical address information of each channel of the SIMD instruction is read from the general-purpose register unit according to the address information of the target general-purpose register; The resource information of the target UAV register is obtained through the loading storage unit. Channel logical address, to determine whether the memory addresses to be accessed by multiple channels of the SIMD instruction are consecutive; If the memory addresses to be accessed by the multiple channels of the SIMD instruction are consecutive, the memory access address of the first channel among the multiple channels is calculated by the loading storage unit, and the memory access addresses of the other channels among the multiple channels are calculated based on the memory access address of the first channel. The loading storage unit generates a memory access request based on the memory access address of each channel of the SIMD instruction, so as to complete the memory access through the UAV data cache unit.

Images