Apparatus and method for encoding monotonic counters

Abstract

An apparatus and method for encoding monotonic counters stored in a settable memory are described. The disclosed embodiments statically allocate intervals in the settable memory and arrange multiple unary encoded monotonic counters in each interval. The monotonic counter encoding technique can efficiently utilize the bits of the settable memory and significantly reduce counter increment failures. An extended interval is also disclosed, which enables the counter to successfully increment after its statically allocated intervals are filled. The disclosed embodiments are ideally suited to support rollback protection during secure boot and can allow significantly more version updates to occur before experiencing version increment failures.

Description

Technical Field

[0001] The disclosed embodiments generally relate to computer security, and more specifically, to methods and apparatus for providing rollback protection during a secure boot process. Background Technology

[0002] In computing, Secure Boot is a process that prevents unauthorized software and firmware images from being loaded onto a computing device during the boot phase. Trusted vendors cryptographically sign authorized images. During loading, the boot process verifies the signature before loading the image. While signature verification ensures integrity and authenticity, it does not provide protection against rollback attacks. A rollback attack refers to loading an older version of an authorized image that includes known vulnerabilities instead of an updated image that fixes those vulnerabilities. Rollback protection aims to prevent the loading of outdated images.

[0003] To support rollback protection, software vendors typically include a version number in each signed image. The bootloader then checks this version against a monotonic counter maintained in the computing device to record the highest known version number of the image being loaded. When the monotonic counter value is greater than the version number signed into the image, a rollback-protected bootloader will refuse to load the image.

[0004] A monotonic counter is an encoding of an integer variable that can be read and incremented, but never decremented. Monotonic counters can be implemented as unary encoded counters stored in set-only computer memory, such as eFuse memory, thereby incrementing the counters and preventing them from decrementing. Multiple counters can be allocated within set-only memory using a fixed size or by using unwritten bits as delimiters.

[0005] Traditional monotonic counter schemes statically allocate space for multiple counters in settable memory. When the allocated space for a counter is insufficient, the counter may exhaust the remaining space and thus fail to increment further. While allocating space based on assumed update probabilities can reduce counter failures, predicting the update frequency is very difficult and often unreliable.

[0006] Therefore, there is a need for improved apparatus and methods for encoding monotonic counters, which can efficiently store rollback-protected counters in settable memory while reducing the occurrence of counter increment failures. Therefore, there is a need to provide methods and apparatus that solve at least some of the above-mentioned problems. Summary of the Invention

[0007] The disclosed embodiments relate to apparatus and methods for encoding monotonic counters. The disclosed embodiments can significantly reduce the occurrence of counter increment failures in systems where monotonic counters are stored in settable computer memory. These benefits are achieved through novel encoding schemes that avoid counter failures by supporting efficient use of the same pre-allocated intervals of settable memory by multiple monotonic counters.

[0008] According to a first aspect, to achieve the above and other objects and advantages, an apparatus includes: a processor communicatively coupled to random access memory, non-volatile memory, and locatable memory. The processor is configured to allocate one or more intervals within the locatable memory, wherein a first interval of the one or more intervals includes a first unary coded counter arranged in a header segment and a second unary coded counter arranged in a tail segment. The first counter and the second counter are separated by one or more unset bits. The processor checks whether there is sufficient space between the first counter and the second counter, and when sufficient space is available, the processor increments one of the first counter and the second counter. Incrementing the first counter includes setting the next unset bit adjacent to the first counter, and incrementing the second counter includes setting the previous unset bit adjacent to the second counter.

[0009] In one possible implementation, the first interval further includes a third counter, arranged within the middle section and spaced apart from each of the first and second counters by one or more unset bits. The processor is further configured to increment the third counter by setting one of a previous unset bit and a next unset bit, wherein the previous unset bit and the next unset bit are adjacent to the third counter, when sufficient space is available. Including a third counter within an interval also reduces the probability of counter failure when these counters are used during a safe startup process with rollback protection.

[0010] In one possible implementation, the midpoint of the third counter is located centrally between the first and second counters. Centering the starting point of the third counter provides an easy-to-implement method for locating the third counter while still significantly reducing counter failures.

[0011] In one possible implementation, the starting point of the middle section is selected based on the current length and relative size of the first and second counters to proportionally divide the space between the first and second counters. Selecting the starting point of the third counter based on the current length and relative size of the first and second counters can also reduce the probability of counter failure by taking into account the number of counter increments that the first and second counters have experienced during the selection period.

[0012] In one possible implementation, allocating the settable memory further includes allocating an extension region, and the processor is further configured to: associate a first counter extension region with a first fill counter when space is insufficient, wherein the first counter extension region is arranged adjacent to a first end of the extension region and includes a first associated counter indication and a first counter extension region value. The processor is configured to: increment the first fill counter by setting the next unset bit adjacent to the first counter extension region value.

[0013] In one possible implementation, the processor is further configured to: associate a second counter extension region with a second fill counter when space is insufficient, wherein the second counter extension region is arranged adjacent to the second end of the extension interval and includes a second associated counter indication and a second counter extension region value. The processor is configured to: increment the second fill counter by setting a preceding unset bit adjacent to the second counter extension region value.

[0014] In one possible implementation, the first counter, the second counter, and the third counter each comprise zero or more consecutive set bits. This ensures unary encoding of these counters.

[0015] In one possible implementation, the one or more ranges are statically allocated prior to runtime. Static allocation allows for efficient use of the settable-only memory.

[0016] In one possible implementation, the non-volatile memory comprises a plurality of images, and each of the first counter and the second counter corresponds to a single image among the plurality of images. The monotonic counter encoding technique performed by the device is ideally suited for tracking the version of the software image to support rollback protection during a secure boot process.

[0017] In one possible implementation of the device, the length of each of the one or more intervals is based on the known prior probabilities of the plurality of images.

[0018] According to the second aspect, the above and other objects and advantages are achieved by a method for encoding monotonic counters. The method includes allocating one or more intervals within a settable memory, wherein a first interval of the one or more intervals includes a first unary encoded counter arranged in a head segment and a second unary encoded counter arranged in a tail segment. The first counter and the second counter are separated by one or more unset bits. The method then checks whether there is sufficient space between the first counter and the second counter, and when sufficient space is available, increments one of the first counter and the second counter. Incrementing the first counter includes setting the next unset bit adjacent to the first counter, and incrementing the second counter includes setting the previous unset bit adjacent to the second counter.

[0019] In one possible implementation of the method, the first interval further includes a third counter, which is arranged within the middle section and spaced apart from each of the first and second counters by one or more unset bits. The method further includes incrementing the third counter by setting one of a preceding unset bit and a next unset bit, wherein the preceding unset bit and the next unset bit are adjacent to the third counter. Including the third counter also reduces the possibility of counter failure.

[0020] In one possible implementation of the method, allocating the one or more intervals within the settable memory further includes allocating an extended interval, and the method further includes associating a first counter extension region with a first fill counter when space is insufficient. The first counter extension region is arranged adjacent to a first end of the extended interval and includes a first associated counter indication and a first counter extension region value. The method increments the first fill counter by setting the next unset bit adjacent to the first counter extension region value. Associating the first extended counter with a first failure counter also reduces the occurrence of counter failures.

[0021] In one possible implementation of the method, when space is insufficient, the method further includes associating a second counter extension region with a second fill counter, wherein the second counter extension region is arranged adjacent to the second end of the extension interval and includes a second associated counter indication and a second counter extension region value. The method increments the second fill counter by setting the preceding unset bit adjacent to the second counter extension region value. Associating the second extension counter with the second fill counter also reduces the occurrence of counter failures, while arranging the two counter extension regions in the same extension interval supports efficient use of the allocated settable memory.

[0022] In one possible implementation of the method, each of the first and second counters is associated with a single image among a plurality of images. The method for encoding monotonic counters is ideally suited for tracking software image versions to support rollback protection during a secure boot process.

[0023] These and other aspects, implementations, and advantages of the exemplary embodiments will become apparent from the embodiments described herein in conjunction with the accompanying drawings. However, it should be understood that the description and drawings are for illustrative purposes only and are not intended to define limitations on the disclosed invention, for which reference should be made to the appended claims. Additional aspects and advantages of the invention will be set forth in the following description, and some aspects and advantages will be apparent from the description or may be learned by practicing the invention. Furthermore, aspects and advantages of the invention may be realized and obtained by means or combinations particularly pointed out in the appended claims. Attached Figure Description

[0024] In the following detailed sections of the invention, aspects of the disclosed embodiments will be explained in more detail with reference to exemplary embodiments shown in the accompanying drawings, wherein like reference numerals denote like elements: Figure 1 A diagram illustrates an exemplary apparatus for encoding a plurality of monotonic counters in a settable memory, incorporating aspects of the disclosed embodiments; Figure 2 The illustration depicts an exemplary technique for encoding three monotonic counters within a single statically allocated interval of settable memory bits, incorporating aspects of the disclosed embodiments. Figure 3 The illustration depicts an exemplary technique for locating the starting point of a monotonic counter, incorporating aspects of the disclosed embodiments. Figure 4 Exemplary techniques for encoding a monotonic counter with an extended range, incorporating aspects of the disclosed embodiments, are shown; Figure 5 A flowchart is shown of an exemplary method for encoding a monotonic counter incorporating aspects of the disclosed embodiments; Figure 6 A diagram illustrating an exemplary simulation of a monotonic counter encoding technique incorporating various aspects of the disclosed embodiments is shown; Figure 7 A graph showing a comparative analysis of the failure rates of various monotonic counter encoding techniques in conjunction with aspects of the disclosed embodiments is provided. Figure 8A graph is shown illustrating a comparative analysis of the number of successful counter increments before the first counter failure for various monotonic counter encoding techniques, incorporating aspects of the disclosed embodiments. Detailed Implementation

[0025] refer to Figure 1 A block diagram of an exemplary apparatus 100 incorporating aspects of the disclosed embodiments is shown, the apparatus being used to encode a plurality of monotonic counters 154, 156 in a locatable memory 108. The exemplary apparatus 100 of the disclosed embodiments relates to a computing device 100 employing an improved monotonic counter encoding technique 174 to store counters in the locatable memory 108. The exemplary apparatus 100 reduces the occurrence of version counter failures due to image updates, thereby improving rollback protection provided by the secure boot process.

[0026] like Figure 1 As shown, in one embodiment, exemplary device 100 includes a processor 102 communicatively coupled to random-access memory (RAM) 104, non-volatile memory (NVM) 106, and configurable memory. Processor 102 is typically used to allocate one or more intervals 150, 152 within configurable memory 108. A first interval 150 of the one or more intervals 150, 152 includes a unary encoded first counter 154 arranged in a header segment 162 and a unary encoded second counter 156 arranged in a tail segment 164. The first counter 154 and the second counter (156) are separated by one or more unset bits 172.

[0027] Processor 102 is also used to check whether there is sufficient space 172 between the first counter 154 and the second counter 156. When sufficient space is available, processor 102 increments one of the first counter 154 and the second counter 156.

[0028] In one embodiment, incrementing the first counter 154 includes setting the next unset bit 166 adjacent to the first counter 154. Incrementing the second counter 134 includes setting the previous unset bit 168 adjacent to the second counter 156.

[0029] Processor 102 typically includes any suitable processing device suitable for use in general-purpose or special-purpose processing devices. Examples of suitable processors 102 include: high-performance multi-core computer processing devices, such as those used in large cloud computing data centers; multi-core or single-core microprocessors, such as those used in workstations and laptops; processing devices embedded in systems, such as systems-on-a-chip (SoCs); or any suitable or special-purpose processing device, such as those used in mobile communication devices; telecommunications equipment; and smart devices configured for the Internet of Things (IoT).

[0030] RAM 104 serves as the main memory of device 100 and provides storage for program instructions and data currently used by processor 102. Any suitable type of random access memory may be advantageously used in exemplary device 100 as needed.

[0031] NVM 106 retains data when device 100 is powered off and can include any suitable type of system memory, such as a disk drive, solid-state drive, or other non-volatile or read-only memory, as needed. Software images 110, 112, and 114 are stored in NVM 106, in which they can be read and loaded into RAM 104 or other desired runtime program memory via boot loader 120 or other processes. Advantageously, boot loader 120 or other software loader may include a secure boot process to ensure the integrity and authenticity of the loaded images. Additionally, boot loader 120 may include rollback protection to prevent loading outdated images when needed.

[0032] Settable memory 108 is included in exemplary device 100 and is used to store an encoded monotonic counter. The monotonic counter is well-suited for recording version information that can be used to support rollback protection during secure boot.

[0033] As used herein, the term "settable memory" refers to a class of computer memories in which each bit is initially unset and can be set by software, firmware, or hardware. However, once a bit has been set, it can never be returned to an unset state. A common type of settable memory is called an electronic fuse (eFuse) memory, in which each bit is constructed as a tiny electronic fuse. Initially, the fuse is either in a conducting or unset state, and during operation, the fuse may blow, i.e., become non-conducting. Importantly, once the fuse blows, i.e., a bit becomes its set or non-conducting state, it cannot be returned to an unset or conducting state. The eFuse memory is merely one example of a settable memory and is discussed herein only for the purpose of aiding understanding. Without departing from the spirit and scope of the invention, any suitable type of settable memory can be advantageously used as settable memory 108 in the embodiments disclosed herein.

[0034] Secure boot is a process that prevents unauthorized software and firmware from being loaded or executed on a computing device, such as the exemplary device 100, during startup. In a typical secure boot process, a trusted software vendor, for example, cryptographically signs the image using an asymmetric encryption key and includes the signature in the metadata associated with the image. During startup, a boot loader that enables secure boot verifies the image signature before supporting loading the image.

[0035] Signature verification authorizes images and prevents the loading of corrupted images; however, it is insufficient to prevent rollback attacks. Even after a software image is released and put into field use, vulnerabilities or other security flaws may still be identified. When this happens, a new version may be released that fixes known flaws present in the previous version. A rollback attack occurs when a malicious actor causes an earlier version, including known vulnerabilities and a valid signature, to be loaded and then exploits those vulnerabilities.

[0036] Rollback protection refers to the process designed to prevent the loading of outdated software and firmware images. For rollback protection purposes, an image is considered outdated if the vendor has already signed a newer version of it. To enable a rollback-protected bootloader to determine if an image is outdated, the vendor can include a version number in the signed image metadata. A monotonic counter can be maintained in a settable memory 108 and used to record the highest known version number of the image. The monotonic counter is an encoding of an integer variable that can be read and incremented, but never decremented. When the version number included in the signed image is lower than the monotonic counter value, a rollback-protected bootloader will refuse to load the image, thus preventing rollback attacks.

[0037] When a newer version of an image is released, the associated version counter needs to be incremented to reflect the new version number. Any suitable method for updating the counter can be advantageously employed. For example, when a newer version of the image is received, the computing device (e.g., device 100) can update the associated monotonic counter. Alternatively, the boot process can optionally update the version counter when a newer version is encountered during image loading. In some embodiments, it may be necessary to enable the vendor to use any appropriate security mechanisms to control the counter incrementing.

[0038] Unary codes are integer encoding methods that encode non-negative integer values ​​as sequences of set bits, where the number of set bits corresponds to the integer value. When storing a unary encoded monotonic counter in memory, it may be necessary to follow the sequence of set bits with one or more unset bits to act as terminators or delimiters, thus separating the monotonic counter values ​​stored in memory. In unary codes, each set bit in the code contributes equally to the encoded value. In contrast, other binary codes, such as binary integer codes, assign different values ​​to each set bit based on its position in the codeword. The advantage of unary codes is that incrementing the encoded value is achieved by setting additional bits. Incrementing a unary encoded value never requires de-setting a bit. This characteristic of unary codes allows them to be stored and incremented in set-only memory, and once incremented, they are never decremented.

[0039] For illustrative purposes, unset bits are represented herein as logic zero (0), and set bits are represented herein as logic one (1). Those skilled in the art will readily recognize that these logic states can be converted without departing from the spirit and scope of the invention, i.e., logic one (1) can be used to represent unset bits, and logic zero (0) can be used to represent set bits.

[0040] Refer again Figure 1 A depiction of an exemplary technique 174 for encoding monotonic counters in configurable memory 108 can be seen. Exemplary technique 174 statically allocates intervals 150, 152 in configurable memory 108 and increments each counter in a manner that efficiently utilizes storage space while also reducing the risk of counter failure. When needed, each monotonic counter 154, 156 can be associated 126 with software images 110, 112, 114 and used to support rollback protection. Counter failure, as used herein, refers to a situation where counter incrementing fails due to insufficient storage space.

[0041] As used herein, intervals are contiguous bit arrays in a configurable memory. For illustrative purposes, intervals allocated in the configurable memory 108, such as intervals 150 and 152, are depicted in the figures as memory bit arrays, for example, a sixteen-bit memory bit array used to depict interval 150. Memory bit array 150 is described as beginning at a first or left-hand end 160 and ending at a second or right-hand end 170. Following this convention, relative orientation language is used to refer to various bits and positions within the configurable memory. The first unconfigured bit 166 adjacent to and to the right of the head segment 162 is referred to as the "next" unconfigured bit 166 adjacent to the first counter 154, and the first unconfigured bit 168 adjacent to and to the left of the tail segment 164 is referred to as the "previous" unconfigured bit 168 adjacent to the second counter 156.

[0042] Before incrementing any counter, processor 102 statically allocates or pre-divides one or more intervals 150, 152 within settable memory 108. Once interval 124 is allocated, its size remains fixed and does not change. The time during which processor 102 increments the counter is referred to herein as “runtime.” As used herein, intervals are statically allocated prior to runtime, and counters are incremented during runtime.

[0043] Depending on the requirements, the sizes of each statically allocated interval 150, 152 can be the same or different. In one embodiment, the available settable memory bits are evenly distributed across the allocated intervals 152, 154. Alternatively, the interval sizes can be different. It is known that some types of images may receive more frequent updates or are more likely to require repair. In some embodiments, it may be beneficial to use known prior probabilities of image updates to help determine the length of each interval.

[0044] In one embodiment, the locatable memory can be divided into fixed-width intervals based on the number of images for which version information needs to be tracked. Using the illustrated monotonic counter encoding technique 174, two counters are stored in each interval, one adjacent to the first end 160 of interval 150 and the other adjacent to the second end 170. When there are N images, N / 2 fixed-width intervals are created, where the number of bits in each interval is half the total number of bits in the locatable memory divided by the number of images. When the division is not exact, the remaining bits can be included entirely in the last interval or distributed among the intervals in any suitable manner. For example, the remaining bits can be included in the interval where the version number is most likely to increment. Exemplary technique 174 is shown using two intervals 150, 152, each with sixteen bits; however, any number or number of intervals, each with any desired number of bits, can be advantageously used.

[0045] Two monotonic counters 154 and 156 are arranged in an interval 150, the interval having a first counter 154 with unary encoding arranged in the head segment 162 of the interval 150 and a second counter 156 with unary encoding arranged in the tail segment 164 of the interval 150. The first counter 154 and the second counter 156 are separated by one or more unset bits 172.

[0046] As used herein, the term "head segment" 162 refers to the continuous string of set bits at the first end 160 of the adjacent interval 150, and the term "tail segment" 164 refers to the continuous string of set bits at the second end 170 of the adjacent interval 150. Each string of set bits 162, 164 represents the integer value of a unary encoded counter. When needed, a continuous string of set bits may include zero set bits to represent an integer value of zero.

[0047] When using unary coded counters to support rollback protection, each counter 154, 156 is associated with a software image 126, and the integer value of the associated counter represents the highest known version number of the corresponding image. If the version number embedded in the image is lower than the corresponding monotonic counter, the rollback protection initiation process will not load the image.

[0048] During operation, the processor executes bootloader 120 or other suitable software components and begins loading images 110, 112, and 114 into memory 104, where the images can subsequently be executed by processor 102. Bootloader 120 reads 142 the next image 112 to be loaded from NVM 106 and decodes 118 the corresponding monotonic counter from settable memory 108. The value of the corresponding counter... C i This indicates the highest known version of image 112 for device 100. A bootloader with rollback protection enabled verifies image 112, for example, via digital signature verification, and reads the version number embedded in the signed image 112. X Then, set the counter value. C i With image version number X The comparison is performed, and when the image version number is lower than the counter value, i.e. X < C i At that time, the image was considered outdated, and the startup loader 120 refused to load the image. When the image version number... X Higher than or equal to the counter value, i.e. X≥C iAt this time, the bootloader loads the image and transfers control to the next bootloader stage, which may be an entry point in the loaded image. When needed, the image version number can be updated by encoding a new version number (116) and writing it to a settable memory (146). X .

[0049] When the software image is updated, the associated monotonic counter needs to be incremented accordingly. Processor 102 identifies 128 the counters associated with the image being updated and locates the interval 150 where the counters are located. The interval 150 located by 130 is checked to determine if there is enough space, i.e., whether there are enough unset bits 172 between the counters, which can be used to increment the identified counter 154.

[0050] An incrementing unary encoded monotonic counter requires setting an unset bit adjacent to the current monotonic counter value. For example, when incrementing the first counter 154, the adjacent unset bit 166 is set. At least two adjacent unset bits 172 are needed to increment the counter 154, one unset bit 166 must be set during the increment, and the second unset bit acts as a delimiter to define the boundary between the first counter 154 and the second counter 156. When there is not enough space available (130N), a counter failure occurs 136, and the fill counter can no longer increment. As used herein, the term "fill counter" refers to a counter with only one adjacent unset bit.

[0051] When sufficient space is available (130Y), that is, when there are two or more unset bits 172 between the first counter 154 and the second counter 156, the processor increments the counter identified by 134. Either counter 154 or 156 within the interval 150 where space is available can be incremented. Incrementing the first counter requires setting the next unset bit 166 adjacent to the first counter 154, and incrementing the second counter 156 requires setting the previous unset bit 168 adjacent to the second counter 156.

[0052] Figure 2 Illustrations are shown of an exemplary technique 200 for encoding three monotonic counters 154, 156, and 202 within a single statically allocated interval 150 of settable memory bits, in conjunction with aspects of the disclosed embodiments. Exemplary technique 200 is suitable for encoding monotonic counters in any suitable computing device, such as the exemplary device 100 described above. Exemplary technique 200 supports storing three monotonic counters 154, 156, and 202 within a single statically allocated interval 150 of settable memory in a manner that efficiently utilizes the allocated space and significantly reduces the occurrence of counter failures.

[0053] The exemplary encoding technique 200 is similar to the encoding technique 172 described above, wherein the first counter 154 of the unary encoding is arranged in the head segment 162 of the first end 160 of the adjacent interval 150, and the second counter 156 of the unary encoding is arranged in the tail segment 164 of the second end 170 of the adjacent interval 150. In the exemplary technique 200, the third counter 202 is arranged in the middle segment 204 located between the head segment 162 and the tail segment 164, and is spaced apart from each of the first counter 154 and the second counter by one or more unset bits 210, 212.

[0054] During the incrementing process, the first counter 154 begins at the first end 160 of interval 150 and increments towards the second end 170, while the second counter begins at the second end 170 of interval 150 and increments towards the first end 160. The third counter 202 begins at the middle start of the unset space between the first counter 154 and the second counter 156 and increments in either direction, either towards the first end 160 or towards the second end 170, as needed. As used herein, the term "middle start" refers to the first bit set when the third counter initially increments.

[0055] When the third counter 202 is positioned within the middle segment 204, the middle segment start point 214 is selected. The middle segment start point 214 becomes the first bit to be set when the third counter is incremented. In one embodiment, the middle segment start point may be centered at an unset bit located midway between the head segment 162 and the tail segment 164. Alternatively, the middle segment start point may be located midway between the first end 160 and the second end 170 of the interval 150.

[0056] Figure 3 Illustrations are shown in conjunction with aspects of the disclosed embodiments, depicting an exemplary technique 300 for locating a midpoint start 308 for a monotonic counter 310. Consider an embodiment where a first counter 304 is arranged in a head segment 162, a second counter 306 is arranged in a tail segment, and a third counter needs to be arranged in the unset bits between the first counter 304 and the second counter 306. Choosing the midpoint start 308 may be advantageous such that the number of unset bits reserved for the growth of the head segment 162 and the tail segment 164 is proportional to the amount of space currently occupied by the set bits in the head segment 162 and the tail segment 164. For counters that have received more increments, reserving more unset bits in their vicinity may be advantageous.

[0057] As an example of proportional selection, the number of unset bits that can be used in header 304 can be calculated as shown in Equation 1:

[0058] inx This indicates the number of unset bits that can be used for header expansion. h This indicates the current length of the first counter 304. t This indicates the current length of the second counter 306. l This represents the total length of the interval 302. As shown in Equation 2, for Equation 1... x Solving for the number of bits, we obtain:

[0059] Since the index of the middle segment's starting point is equal to the current length of the beginning segment. h=6 Adding the number of unset bits reserved for the growth of the header segment, the starting point of the middle segment (assuming a zero-based index) is thus given by Equation 3:

[0060] like Figure 3 As shown, the middle start point 308 supports a proportional number of unset bits for each of the first counter 304 and the second counter 306 to increase.

[0061] Figure 4 Exemplary technique 400 for extending an encoded monotonic counter, incorporating aspects of the disclosed embodiments, is illustrated. Over time, the monotonic counter may grow to consume all available space, causing it to fail. Extending the interval 450 is a mechanism to help avoid counter failure by associating additional space with a filling counter at runtime. Exemplary technique 400 illustrates two statically allocated intervals 150, 152, with three counters 402, 404, 406 in the first interval 150 and three counters 408, 410, 412 in the second interval.

[0062] Extended interval 450 can be statically allocated together with one or more intervals 150, 152, and like one or more allocated intervals, extended interval 450 does not change size during runtime. Extended interval 450 provides space for two counter extension areas, namely a first counter extension area 414 arranged adjacent to the first end 426 of extended interval 450 and a second counter extension area 416 arranged adjacent to the second end 428 of extended interval 450. Each counter extension area 414, 416 includes counter indicators 418, 422 for identifying associated counters and counter extension area values ​​420, 422 for providing additional space for counter incrementing.

[0063] As discussed above, before incrementing the counter, the exemplary device 100 checks whether 130 has sufficient space to perform the increment, and a counter failure occurs when space is unavailable (130N). When the counter extension area is available, counter failure can be avoided by associating the available counter extension area with the fill counter at runtime.

[0064] For example, such as Figure 4 As shown, there is only one unset bit 418 between the first counter 402 and the second counter 404. Therefore, there is not enough space to increment the first counter 402, and the first counter can be referred to as a fill counter. To increment the first fill counter 402, the first counter extension region 414 is associated with the first fill counter 402, and the next unset bit 430 adjacent to the first counter extension region value 420 is set. Similarly, the second fill counter 410 can be incremented by associating the second counter extension region 416 with the second fill counter 410 and setting the previous unset bit 432 adjacent to the second counter extension region value 424. Note that... Figure 4 The extended interval 450 shown depicts the state of the extended interval 450 after the first and second fill counter increments are completed.

[0065] In the illustrated embodiment 400, a semi-fixed-length code is used to indicate which fill counters 402, 410 are associated with each counter extension region 414, 416. When using a low-order short semi-fixed-length code, the first associated counter indication 402 (counter A) is indicated by setting the first associated counter indication 418 to the binary value '01', and the fifth counter 410 (counter E) is indicated by setting the second associated counter indication 422 to the binary value '111'. The semi-fixed-length code is merely one example of a suitable counter indication. Those skilled in the art will readily recognize that any suitable counter indication can be advantageously employed as counter indications 418, 422 without departing from the spirit and scope of the embodiments disclosed in this invention.

[0066] Figure 5 A flowchart illustrating an exemplary method 500 for encoding a monotonic counter incorporating aspects of the disclosed embodiments is shown. The exemplary method 500 is suitable for encoding a monotonic counter stored in a settable memory in a computing device such as the exemplary device 100 described above. The exemplary method 500 significantly reduces the occurrence of counter failures in applications where the monotonic counter is used as a version counter to support rollback protection during a secure boot process.

[0067] In one embodiment, an exemplary method 500 is used in a computing device having a locatable memory for storing a plurality of monotonic counters. One or more intervals are allocated 502 within the locatable memory. Once allocated, the size of the allocated intervals remains unchanged. These intervals may be all the same size, or they may be different sizes, as needed. Each statically allocated interval includes a first unary coded counter arranged in the head segment of the interval and a second unary coded counter arranged in the tail segment of the interval. The first counter is adjacent to a first end of the interval, and the second counter is adjacent to a second end of the interval. The first counter and the second counter are spaced apart by one of a plurality of unset bits.

[0068] When either the first counter or the second counter needs to be incremented, the interval described in 504 is checked to determine if there is sufficient space between the first counter and the second counter to support the counter increment. For the counter to increment, there need to be two or more unset bits between the first counter and the second counter; one unset bit is used for the delimiter, and the second unset bit is to be set when the counter is incremented. Therefore, sufficient space, as used herein, refers to two or more unset bits between these counters.

[0069] When there is sufficient space available (506), one of the first and second counters (510) can be incremented. The first counter, adjacent to the first end of the interval, is incremented by setting the next unset bit of the adjacent first counter. Setting the next adjacent bit increments the number of consecutive set bits in the unary-coded counter by one, thus incrementing the counter's value by one. Similarly, the second counter, adjacent to the second end of the interval, is incremented by setting the previous unset bit of the adjacent second counter.

[0070] In one embodiment, including a third counter disposed in the middle of the interval may be advantageous, wherein the third counter is spaced apart from each of the first and second counters by one or more unset bits. At least one unset bit is required between any two counters within the same interval to support the differentiation of set bits belonging to one counter from set bits belonging to the other counter. The third counter can be incremented when space is available (504), i.e., when there are two or more bits separating the third counter from another counter within the same interval. The third counter disposed between the other two counters can increase in either direction, and thus can be incremented (510) by setting either the next unset bit on one side adjacent to the third counter or the previous unset bit on the other side adjacent to the third counter.

[0071] In some embodiments, it may be advantageous to include additional protection against counter failure by incorporating an extended interval. An extended interval 502 may also be allocated when one or more intervals 502 are allocated. The extended interval is statically allocated along with the one or more intervals and, like the one or more intervals, does not change size once allocated.

[0072] An extension interval can be used to support two counter extension regions. A first counter extension region can be arranged adjacent to the first end of the extension interval, and a second counter extension region can be arranged adjacent to the second end of the extension interval. Each counter extension region includes a counter indicator, also referred to as a fill counter indicator, indicating the counter associated with this counter extension region. Along with the fill counter indicator, each extended counter also includes a counter extension region value. The counter extension region value provides additional space for use when incrementing the fill counter.

[0073] When it is determined that 508 does not have enough space available for the increment counter, a first counter extension region is associated with a first fill counter 516. The first counter extension region is adjacent to the first end of the extension region and includes a first fill counter indicator and a first counter extension region value. Associating the first counter extension region with the first fill counter 516 is achieved by setting the first fill counter indicator to the value corresponding to the first fill counter. The first fill counter can then be incremented 518 by logically extending the first fill counter to the first counter extension region value and setting the next unset bit adjacent to the first counter extension region value.

[0074] Similarly, when it is determined that the second counter 508 does not have enough space available for incrementing, the second counter extension region is associated with the second padding counter 520. The second padding counter can then be incremented 522 by logically extending the second counter extension region value and setting the preceding unset bit of the adjacent second counter extension region value.

[0075] Figure 6 A diagram is shown illustrating an exemplary simulation of a monotonic counter encoding technique incorporating aspects of the disclosed embodiments. The exemplary simulation combines the two encoding techniques described above. Figure 1 The two monotonic counters shown are arranged in the first and last segments of the statically allocated interval, in coding technique 174. Figure 4 The counter extension region shown is combined with the extension interval technique 400 associated with each of the first fill counter and the second fill counter.

[0076] Analog 600 is based on twelve (12) counters and assumes a 256-bit settable memory. Thirty-two (32) bits are statically allocated to the extended interval 604, and the remaining 224 bits are divided into six intervals 602 to accommodate the twelve counters. For the first technique 174, each interval includes two counters, so six intervals 602 are needed to support twelve counters, and each interval will have 224 / 6 = 37 bits, with two remaining bits added to the last interval 602. For ease of reading, each of the seven intervals (the six counter intervals 602 and the extended interval 604) is shown in a different row in the diagram.

[0077] As the image is updated, the associated counter increments, and the state of the settable memory is updated. Figure 600 shows three memory states at different points in the simulation. A version-updated memory state 606 shows a set bit 612 in the eleventh counter. A second memory state 608 shows an intermediate state 608 where many counter increments have been performed, but no counter failure has occurred. In the simulation, counter increments occur randomly, resulting in some counters receiving large increments while others receive only small increments.

[0078] The final state 610 shown in the figure depicts a settable memory state that occurs after the two counters have filled their intervals 622 and overflowed into the counter extension regions arranged in the extension intervals 604. As discussed above, each counter extension region includes version indicators 618, 620 and a counter extension region value. In the illustrated embodiment, a low-order short semi-fixed-length code 614 is used to indicate which counter is associated with each counter extension region 604. The first counter extension region 618 is associated with counter index 8, and the second counter extension region 620 is associated with counter index 9. For reference, the final counter value for each image represented by the final settable memory state 610 is listed 624 below the final settable memory state 602.

[0079] Comparative analysis of the monotonic counter encoding technique disclosed in this invention shows significant improvements compared to conventional methods. Experimental results comparing conventional techniques with several embodiments disclosed in this invention are discussed below. The conventional techniques used for comparison pre-divide the settable memory into intervals and implement a single monotonic counter in each interval.

[0080] The comparative analysis was performed by running simulations on each technique using a 256-bit settable memory. In the following experimental results, uppercase letters... N Indicates the number of counters used in the experiment, in lowercase letters. nThis represents the total number of counter updates during the experiment. The counter increment probability is based on a Zipf distribution and is randomly assigned to each counter. The counter update probability is: ,in It is the first N The simulation calculated the number of counter failures. The counter failure count represents the number of times the counter failed to increment due to running out of bits. The simulation was repeated 512 times, with 128 image updates. n =128, and different numbers of images, N =8, 12, 16 and 18.

[0081] Figure 7 Figure 700 illustrates a comparative analysis of the failure rates of various monotonic counter encoding techniques in conjunction with aspects of the disclosed embodiments. The results shown in Figure 700 include three embodiments disclosed in this invention. Technique 1 corresponds to the one described above and relating to... Figure 1 The described technique 174 combines two counters arranged in the head and tail segments (head + tail) for each interval. Technique 2 corresponds to the one described above and regarding... Figure 2 The described technique 200 combines three counters arranged in the head, tail, and middle sections (head + middle + tail) for each interval. Technique 3 combines Technique 2 and the techniques described above and regarding... Figure 4 The described technique 400 incorporates an extended range (32 runtime-allocated bits).

[0082] Figure 700 depicts the average number of version increment failures encountered during 512 simulation runs, increasing along the vertical axis, and shows the results of each simulation technique grouped by the number of counters used in each simulation run along the horizontal axis. As can be seen in Figure 700, the technique disclosed herein for encoding monotonic counters significantly reduces the average number of version increment failures encountered when incrementing counters stored in settable memory.

[0083] Figure 8 Figure 800 illustrates a comparative analysis of the number of successful counter increments prior to the first counter failure, showing various monotonic counter encoding techniques incorporating aspects of the disclosed embodiments. It depicts the average number of successful counter increments prior to the first failure increment, increasing upwards along the vertical axis. Figure 8 The simulation techniques used and the horizontal axis depiction are the same as those mentioned above and about Figure 7 The description is identical. As can be seen in Figure 800, the disclosed embodiment provides significantly more successful counter increments than conventional schemes before encountering counter failure.

[0084] The improvements provided by the disclosed embodiments can be summarized as follows: Compared to existing technologies, the embodiments disclosed in this invention significantly reduce the average number of times the failure version counter increments. Compared to the twenty-nine (29) images of the prior art, this invention has sixteen images ( N The disclosed embodiments of the present invention (=16) encountered an average of three (3) failures. Having eight images ( N The embodiments of the present invention disclosed in (=8) did not encounter any failures (zero failures), while the prior art encountered an average of sixteen (16) failures.

[0085] Regarding the skewed (non-uniform) version update probability, the embodiments disclosed in this invention significantly reduce the likelihood of running out of bits in the settable memory. With sixteen images ( N The prior art solution (=16) failed in the fifty-fourth (54th) update, while the embodiment disclosed in this invention did not fail for the first time until the one hundred and sixteenth (116th) update.

[0086] Therefore, although the essential novel features of the invention have been shown, described, and pointed out in accordance with exemplary embodiments thereof, it should be understood that those skilled in the art can make various omissions, substitutions, and changes to the form and details of the illustrated devices and methods and their operation without departing from the spirit and scope of the invention. Furthermore, all combinations of those elements that are explicitly desired to perform substantially the same function in substantially the same manner to achieve the same results are within the scope of the invention. Moreover, it should be recognized that structures and / or elements shown and / or described in connection with any form or embodiment of the disclosed invention can be incorporated as general design choices into any other form or embodiment disclosed, described, or suggested. Therefore, the invention is limited to the scope set forth in the appended claims.

Claims

1. An apparatus (100), characterized in that, include: A processor (102) is communicatively coupled to a random access memory (104), a non-volatile memory (106), and a settable-only memory (108), wherein the processor (102) is used to: One or more intervals (150, 152) are allocated in the settable memory (108), wherein the first interval (150) of the one or more intervals (150, 152) includes a first unary code counter (154) arranged in the head segment (162) and a second unary code counter (156) arranged in the tail segment (164), wherein the first counter (154) and the second counter (156) are separated by one or more unset bits (172); Check if there is sufficient space (172) between the first counter (154) and the second counter (156); when there is sufficient space available, Increment one of the first counter (154) and the second counter (156). Incrementing the first counter (154) includes setting the next unset bit (166) adjacent to the first counter (154), and incrementing the second counter (134) includes setting the previous unset bit (168) adjacent to the second counter (156).

2. The apparatus (100) according to claim 1, characterized in that, The first interval (150) further includes a third counter (202), which is arranged within the middle section (204) and separated from each of the first counter (154) and the second counter (156) by one or more unset bits (210, 212), and, The processor (102) is also used for: When there is enough space available, the third counter (202) is incremented by setting one of the previous unset bit (206) and the next unset bit (208), wherein the previous unset bit (206) and the next unset bit (208) are adjacent to the third counter (202).

3. The apparatus (100) according to any one of the preceding claims, characterized in that, The middle starting point (214) of the third counter (202) is located in the middle position between the first counter (154) and the second counter (156).

4. The apparatus (100) according to any one of the preceding claims, characterized in that, The middle starting point (308) is selected based on the current length and relative size of the first counter (304) and the second counter (306) to proportionally divide the space (312) between the first counter (304) and the second counter (306).

5. The apparatus (100) according to any one of the preceding claims, characterized in that, Allocating the settable memory (108) also includes allocating an extended range (450). Furthermore, the processor (102) is also used to: when space is insufficient: The first counter extension region (414) is associated with the first fill counter (402), wherein the first counter extension region (414) is arranged adjacent to the first end (426) of the extension interval (450) and includes a first associated counter indication (418) and a first counter extension region value (420). The first fill counter (402) is incremented by setting the next unset bit (430) adjacent to the first counter extension area value (420).

6. The apparatus (100) according to any one of the preceding claims, characterized in that, The processor (102) is also used to: when space is insufficient (130N): The second counter extension area (416) is associated with the second fill counter (410), wherein the second counter extension area (416) is arranged adjacent to the second end (428) of the extension interval (450) and includes a second associated counter indication (422) and a second counter extension area value (424). The second fill counter (410) is incremented by setting the previous unset bit (432) adjacent to the second counter extension area value (424).

7. The apparatus (100) according to any one of the preceding claims, characterized in that, The first counter (154), the second counter (156) and the third counter (202) each include zero or more consecutive set bits.

8. The apparatus (100) according to any one of the preceding claims, characterized in that, The one or more intervals (150, 152) are statically allocated before runtime.

9. The apparatus (100) according to any one of the preceding claims, characterized in that, The non-volatile memory (106) includes a plurality of images (110, 112, ..., 114), and each of the first counter (154) and the second counter (156) corresponds to a single image (110, 114) among the plurality of images.

10. A method (500) for encoding a monotonic counter, characterized in that, The method (500) includes: One or more intervals are allocated in the settable memory (502), wherein the first interval of the one or more intervals includes a first counter of unary code arranged in the head segment and a second counter of unary code arranged in the tail segment, wherein the first counter and the second counter are separated by one or more unset bits. Check (504) whether there is sufficient space between the first counter and the second counter; when there is sufficient space available (506), Increment (510) one of the first counter and the second counter, wherein incrementing the first counter includes setting the next unset bit adjacent to the first counter, and incrementing the second counter includes setting the previous unset bit adjacent to the second counter.

11. The method (500) according to claim 10, characterized in that, The first interval further includes a third counter, which is arranged in the middle section and spaced apart from each of the first counter and the second counter by one or more unset bits, and the method (500) further includes: The third counter is incremented (510) by setting one of the previous unset bit and the next unset bit, wherein the previous unset bit and the next unset bit are adjacent to the third counter.

12. The method (500) according to claim 10 or 11, characterized in that, Allocating (502) the one or more intervals within the settable memory further includes allocating extended intervals, and the method (500) further includes: when space is insufficient (508): Associate the first counter extension region with the first fill counter (516), wherein the first counter extension region is arranged adjacent to the first end of the extension region and includes a first associated counter indication and a first counter extension region value; The first fill counter is incremented (518) by setting the next unset bit adjacent to the first counter extension value.

13. The method (500) according to claim 12, characterized in that, Also includes: When space is insufficient (508): Associate the second counter extension region with the second fill counter (520), wherein the second counter extension region is arranged adjacent to the second end of the extension region and includes a second associated counter indication and a second counter extension region value; The second fill counter is incremented (522) by setting the previous unset bit adjacent to the value of the second counter extension area.

14. The method (500) according to any one of claims 10 to 13, characterized in that, Each of the first counter and the second counter is associated with a single image among a plurality of images.

Images