stitch bonding with nanotwin copper-plated leads

Abstract

An electronic device (100) includes: a package structure (108); conductive terminals (114) exposed outside the package structure (108) and having a nanotwin coating layer (116); a semiconductor die (112) located in the package structure (108); and bonding wires (115) enclosed by the package structure (108) and having a first end (117) and a second end (119), the first end (117) being connected to the semiconductor die (112) via a first bonding member (118) and the second end (119) being connected to the nanotwin coating layer (116) via a second bonding member (120). A method includes: performing a plating process to form a nanotwin plating layer (116) on a conductive terminal (114); and performing a wire bonding process to form a bonding wire (115) having a first end (117) connected to a semiconductor die (112) via a first bonding member (118) and a second end (119) connected to the nanotwin plating layer (116) via a second bonding member (120).

Description

Background Technology

[0001] Low-strength connections between the bonding wire / stitch bond and the leadframe can negatively impact bondability and reliability. Different wire bonding connection types (e.g., ball bump over stitchbond and stitch bond over ball bump) can improve the connection strength between the bonding wire / stitch bond and the leadframe, but these techniques prolong the wire bonding process and increase manufacturing costs. Lower-cost stitch bonding to the intended lead or other leadframe features can present problems. The leadframe can be treated with surface etching, stamping, and / or cutting to create semi-etched features to improve molding compound adhesion and enhance product reliability. Bare copper-to-copper (Cu-Cu) bonding reduces manufacturing costs in terms of material cost and significantly reduces leadframe manufacturing time. However, surface grain increases with decreasing roughness, which can cause delamination between the leadframe and the molding compound. Furthermore, bare Cu-Cu bonding is thermally constrained, where higher wire bonding process temperatures induce oxidation, affecting manufacturability and reliability. Compared to thermocompression bonding, ultrasonic wire bonding can enhance bond strength by increasing copper atom diffusion, but ultrasonic bonding increases costs. Another method uses patterned wedge tips instead of granular tips to form the wire bond, providing more gripping force on the lead during bonding and reducing severe wedge indentation caused by lead slippage during bonding, but this also increases manufacturing costs and complexity. Summary of the Invention

[0002] In one aspect, an electronic device includes a package structure; conductive terminals exposed outside the package structure and having a nanotwin coating; a semiconductor die located within the package structure; and bonding wires enclosed by the package structure. The bonding wires firstly have a first end connected to the semiconductor die via a first bonding member and a second end connected to the nanotwin coating via a second bonding member.

[0003] In another aspect, a system includes a circuit board and an electronic device attached to the circuit board, wherein the electronic device includes a package structure; conductive terminals exposed outside the package structure and soldered to the circuit board; conductive features; the conductive terminals having a nanotwin plating layer; and the electronic device including a semiconductor die within the package structure and bonding wires enclosed by the package structure. The bonding wires firstly have a first end connected to the semiconductor die via a first bonding member and a second end connected to the nanotwin plating layer via a second bonding member.

[0004] In another aspect, a method of manufacturing an electronic device includes performing a plating process to form a nanotwin plating layer on a conductive terminal; and performing a wire bonding process to form a bonding wire having a first end connected to a semiconductor die via a first bonding member and a second end connected to the nanotwin plating layer via a second bonding member.

[0005] In another embodiment, the lead frame includes conductive terminals and a nanotwin coating on the outer surface of the conductive terminals. Attached Figure Description

[0006] Figure 1 This is a top perspective view of an electronic device with bonding wires having multiple bonding elements connected to a nanotwin coating on a conductive terminal.

[0007] Figure 1A It is an electronic device along Figure 1 The side view of the section cut by line 1A-1A.

[0008] Figure 1B This is a partial cross-sectional view of a portion of the nanotwin coating.

[0009] Figure 1C It is a simplified crystal structure view of the twin boundary between the matrix grains and twin grains of the nanotwin coating.

[0010] Figure 1D The crystallographic orientations of copper molecules at 100, 110, and 111 are shown.

[0011] Figure 1E This is a simplified crystalline structure view of the grain boundaries between non-twinned copper grains.

[0012] Figure 2 It is a flowchart of a method for manufacturing electronic devices using the included wire bonding method.

[0013] Figure 2A This is a flowchart of an example nanotwin deposition method utilizing optional pulse deposition.

[0014] Figure 2B This is a curve showing the current density of an example pulsed nanotwin deposition process.

[0015] Figures 3 to 7 yes Figures 1 to 1C Electronic devices have undergone a process according to Figure 2 and 2A A partial side view of the manufacturing process of the method. Detailed Implementation

[0016] In the figures, the same reference numerals refer to the same elements throughout, and various features are not necessarily drawn to scale. Furthermore, the term "couple" encompasses indirect or direct electrical or mechanical connections, or combinations thereof. For example, if a first device is coupled to or with a second device, the connection can be a direct electrical connection or an indirect electrical connection via one or more intervening devices and connections. The following describes one or more operational characteristics of various circuits, systems, and / or components in the context of function, which in some cases arise from the configuration and / or interconnection of various structures when the circuit system is energized and operated. Example structures include layers or materials described as being on or above another layer or material, which may be directly on and in contact with the other layer or material, wherein other materials (e.g., impurities or man-made products or residual materials from manufacturing processes) may be present between the layer or material and the other layer or material. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. For ease of description in conjunction with specific figures, one or more structures, features, aspects, components, etc., may be referred to herein as first, second, third, etc., such as first and second terminals, first, second, and third wells, etc., wherein such descriptions shall not be construed as limiting the claims. The various structures and methods disclosed herein can be advantageously applied to electronic devices, and to electronic devices for manufacturing and / or operating, such as integrated circuits. While such examples may provide various improvements, this disclosure does not require a particular outcome unless expressly stated in a particular claim.

[0017] First refer to Figures 1 to 1C , Figure 1 An electronic device 100 is shown with bonding wires 115 having multiple bonding elements to a nanotwin plating layer 116 leading to conductive terminals 114 (e.g., leads). Figure 1A Display electronic device 100 along Figure 1 Side elevation view of the section cut by line 1A-1A. Figure 1B A partial cross-sectional view showing a portion of the nanotwinned coating 116, and Figure 1C A simplified crystalline structure view showing the twin boundaries between the substrate and twin grains of the nanotwin coating 116. Figure 1 and 1A An electronic device 100 installed in the system is shown, wherein the electronic device 100 is attached to the circuit board 130, for example, by attaching the bottom solder of the conductive terminal 114 to the conductive pad of the circuit board 130.

[0018] like Figure 1 and 1AAs shown, the electronic device 100 has an encapsulation structure 108 with a generally rectangular shape, the rectangular shape comprising opposing first sides 101 and second sides 102 (e.g., bottom and top sides), and laterally oriented third sides 103, fourth sides 104, fifth sides 105, and sixth sides 106. In one example, the encapsulation structure 108 is a molded plastic structure. In another embodiment, the encapsulation structure is or comprises a ceramic material (not shown). Figure 1 and 1A In the illustration, electronic device 100 is shown in an instance position or orientation in three-dimensional space having a first direction X, a second direction Y perpendicular to (or orthogonal to) the respective first direction X and second direction Y, and a third direction Z perpendicular to (or orthogonal to) the respective first direction X and second direction Y, and structures or features along any two of these respective directions are orthogonal to each other. In the illustrated orientation, the respective first side 101 and second side 102 are spaced apart from each other along the third direction Z, the respective third side 103 and fourth side 104 are spaced apart from each other along the first direction X, and the respective fifth side 105 and sixth side 106 are spaced apart from each other along the second direction Y.

[0019] Electronic device 100 includes die attachment pads 110 and a semiconductor die 112 attached to the die attachment pads 110 in a package structure 108, for example, by solder or adhesive (not shown). Electronic device 100 has conductive metal wing-shaped terminals 114 along each of the respective third sides 103 and fourth sides 104. In other instances, the electronic device may have conductive terminals of different types and forms, such as J-type terminals, terminals on ceramic or organic multilayer package substrates, through-hole terminals, etc. (not shown). In various embodiments, the conductive terminals may be located on one or more of sides 101, 103, 104, 105, and 106, and the terminals may be flush with and / or extend at least partially outward from the associated side of the package structure 108, having surfaces exposed to the outside of the package structure 108 to allow soldering or socket connections to connect the circuitry of the semiconductor die 112 to a host printed circuit board (PCB, not shown).

[0020] Individual bonding wires 115 are or contain copper and are enclosed by package structure 108. For example... Figure 1A As shown, each bonding wire 115 has a first end 117 and a second end 119. In this example, the first end 117 of each corresponding bonding wire 115 is connected to the semiconductor die 112 via a first bonding member 118, for example, to a conductive metal bonding pad (not shown). In one example, the first bonding member 118 is a ball bond. The second end 119 of each corresponding bonding wire 115 is connected to the nanotwin plating layer 116 of the corresponding conductive terminal 114 via a second bonding member 120. In one example, the second bonding member 120 is a stitch bond.

[0021] In one example, the conductive lead 114 is or comprises copper, wherein the nanotwin plating layer 116 extends along and contacts the outer surface of the respective conductive lead 114. In the illustrated example, the nanotwin plating layer 116 extends along the entire outer surface of the conductive lead 114 except for trimmed or cut ends of the conductive lead 114, which are or comprise bare copper. In another example, the nanotwin plating layer 116 may extend over portions of one or more sides of the associated conductive lead 114. For example, a plating mask (not shown) may be used during lead frame manufacturing to form the nanotwin plating layer 116 on a portion of the top side of the respective conductive lead 114, with the second end 119 of the respective bonding wire 115 connected to the nanotwin plating layer via a stitch bond 120.

[0022] In the illustrated example, each conductive terminal 114 includes an external portion extending and exposed outside the package structure 108. The internal portion of the corresponding conductive terminal 114 has a nanotwin plating layer 116, and a stitch bond 120 connects a second end 119 of the corresponding bonding wire 115 to the nanotwin plating layer, wherein the stitch bond 120 is enclosed by the package structure 108. In the illustrated example, except for trimmed or cut ends of the conductive lead 114 that are not plating 116 on their trimmed surfaces, the external portion of the corresponding conductive lead 114 also includes a portion of the nanotwin plating layer 116 exposed outside the package structure 108. In one example, the nanotwin plating layer 116 completely covers the outer surface of the internal portion of the conductive terminal 114 within the package structure 108.

[0023] The conductive terminal 114 contains copper, and the nanotwinned plating layer 116 also contains copper. For example... Figure 1B The diagram further illustrates that the nanotwin coating 116 contains nanotwinned copper grains in grain boundaries with crystalline displacement segments, wherein the lattice on each edge is connected by mirror symmetry across the twin plane or twin boundary TB. Figure 1B The illustrated portion of the nanotwin coating 116 includes a first portion 121 (e.g., a matrix grain or portion) on either side of the second portion 122 (e.g., a twin grain or portion) and two instances of the corresponding twin boundary TB between the first portion 121 and the second portion 122, wherein the lattices on each side of the twin boundary TB are connected by mirror symmetry.

[0024] Figure 1C Examples of crystal structures and orientations a, b, and c of copper molecule M on either side of the twin boundary TB between the matrix grain 121 and the twin grain 122 of the nanotwin coating 116 are illustrated. Figure 1D The display has corresponding Figure 1CExamples of the orientation of copper molecules M in three-dimensional space, along the axes a, b, and c, and examples of crystallographic alignment of copper molecules in planes 100, 110, and 111. Figure 1E A crystalline structure view showing the grain boundary GB between non-twinned copper grains (grain 1 and grain 2) of copper molecule M.

[0025] The coherent twin boundaries TB are arranged to divide the internal grains into two parts 121 and 122. In one example, the lattice composition of the twins and the substrate sheet is symmetrical with respect to the twin boundaries TB, and the lattice composition follows the ordered arrangement of the nanoscale twin sheets within the nanotwin coating 116. Copper electrodeposited with nanotwin crystal orientation exhibits excellent mechanical and electrical properties through improved mechanical reliability and resistance to electromigration.

[0026] The nanotwinned plating 116 facilitates bonding of the copper bonding wire 115 to the conductive lead 114 with enhanced bonding strength. In the illustrated example, the second bonding element 120 is a stitch bond, which facilitates a cost-effective and rapid wire bonding process during the manufacture of the electronic device 100 compared to lead frames plated with expensive nickel-palladium (NiPd) or nickel-palladium-gold (NiPdAu), and the increased processing may extend the lead frame manufacturing process. Furthermore, the nanotwinned plating 116 facilitates high-strength stitch bonding to connect the bonding wire 115 to the conductive lead 114 without increasing the process complexity and cost associated with bonding using patterned wedge tips.

[0027] Furthermore, the nanotwinned plating layer 116 provides higher temperature capability for wire bonding processes while mitigating oxidation, and facilitates lower-cost hot pressing processes (such as stitch bonding) without increasing the cost of ultrasonic wire bonding. The bonding between the wire 115 and the nanotwinned plating layer 116 enhances mechanical stability and resistance to electromigration, and promotes the mechanical strength of the second bond 120. The nanotwins in the plating layer 116 provide mechanical stability to the interconnect structure, and in some instances, the nanotwinned plating layer 116 exhibits improved hardness and higher nanotwin density compared to bare unplated copper.

[0028] Also refer to Figures 2 to 7 , Figure 2 This demonstrates a method 202 for fabricating a leadframe using the included nanotwin deposition method 202 and a method 200 for fabricating an electronic device using the included wire bonding process. Figure 2A An example implementation of a nanotwin deposition method 202 with optional pulsed deposition is shown. Figure 2B This is a curve showing the current density of an example pulsed nanotwin deposition process, and Figures 3 to 7 Presentation experience based on Figure 2 and 2AThe manufacturing process of electronic device 100 by method 200.

[0029] exist Figure 1 At position 202, a plating process is performed to form a nanotwinned plating layer 116 on all or a portion of the conductive terminal 114. Various embodiments are possible, such as using specific nanotwinned copper plating chemicals, pulse plating, shock plating, and / or combinations thereof, or other suitable techniques and equipment. In one example, the plating process is performed during the fabrication of the lead frame into an array of strips or panels having multiple unit areas arranged in rows and columns. Figure 3 An example is shown in which an electroplating process 300 is performed, forming a nanotwinned plating layer 116 on all or part of the conductive terminals 114 and forming die attachment pads 110 in the illustrated unit areas of the leadframe panel array. In this example, individual unit areas of the leadframe panel array include the illustrated die attachment pads 110 and examples of conductive features that are ultimately formed as conductive leads 114 (e.g., leads), which are connected together, for example, by tie rods (not shown) between adjacent unit areas, which are then trimmed or cut to separate the individual conductive terminals 114 from each other. In one embodiment, the initial leadframe is or contains copper. In the illustrated example, the plating process 300 forms a nanotwinned plating layer 116 as a nanotwinned copper layer 116 on the copper conductive terminals 114. In one example, the plating process 300 forms the nanotwinned plating layer 116 to a thickness of approximately 1 μm or greater. Thinner nanotwin layers can result in weak finished wire-bonded parts or inhibit bonding. Larger coating thicknesses can be used when considering the possible trade-offs between yield, increased plating time, and increased material costs.

[0030] Furthermore, in the illustrated embodiment, plating process 300 forms a nanotwin plating layer 116 directly on the exposed surface of the copper features of the leadframe, the exposed surface including the die attachment pads 110 and the exposed surfaces of the intended leads 114. In another embodiment, a plating mask (not shown) may be formed to cover selected portions of one or more leadframe surfaces to selectively allow plating to form the nanotwin plating layer 116 at specific locations on the leadframe. For example, the plating mask may include openings to facilitate the plating of the nanotwin plating layer 116 on all or part of the upper surface, top surface, or side of the conductive leads 114, to which bonding wires will subsequently be bonded during electronic device manufacturing.

[0031] Figure 2A exhibit Figure 2 One example embodiment of the plating process at position 202 includes, for example, cleaning the manufactured lead frame 211 after stamping and etching processes. In another embodiment, cleaning at position 211 may be omitted. Figure 2A At position 212, an optional plating mask is formed and patterned. In another embodiment, no plating mask is used, and the processing at position 212 can be omitted, for example, to provide a lower-cost leadframe. Figure 2A At 213, the example plating process 202 includes impact plating of a nanotwinned plating layer 116 on a selected portion of the lead frame not covered by an optional plating mask (in the case of one formed at 212) or on all exposed sides and surfaces of the lead frame. Impact plating may be used in one example, but is not required in all possible embodiments. Any suitable electroplating process and apparatus may be used to provide the nanotwinned plating layer 116 on all or a portion of one or more sides and surfaces of the lead frame. In the illustrated example, plating process 300 forms the nanotwinned plating layer 116 as a nanotwinned copper layer 116 on the copper conductive terminal 114.

[0032] Also refer to Figure 2B In one implementation, the diagram is used as a separate step 214 and Figure 2A The pulsed deposition forms a nanotwinned coating layer 116, but can be used as... Figure 3 The single-pulse electroplating process 300 is shown in the diagram. In other embodiments, in Figure 2 At location 202, multiple plating steps are used to form the nanotwinned plating layer 116, for example, including impact plating of an initial thin portion of the nanotwinned plating layer 116, followed by pulse electroplating (e.g., immersion in a solution or drying of the electroplating tool) to form the remaining portion of the nanotwinned plating layer 116. In the illustrated example, plating process 300 is a pulse plating process, which includes... Figure 2A Pulse modulation of the plating current density is performed at position 214.

[0033] Figure 2B Graph 220 in the diagram illustrates an example with a current density curve 222, which plots the pulsed control of the plating current of process 300. The plating current is controlled, for example, by appropriately switching the plating current density between a maximum plating current density labeled "IP" and an off-state with an approximately zero current density labeled "I / O" over time. Figure 2B Examples include controlling the duty cycle of the pulse plating process 300 to, for example, about 50% or other suitable duty cycle, the duty cycle being expressed as the ratio of the on-time marked "TON" to the off-time marked "TOFF".

[0034] In various implementation schemes, the duty cycle can be controlled to be a substantially constant duty cycle, or the duty cycle can be varied, for example, to promote the formation of nanotwins with a high proportion in one instance. <111> Oriented nanotwin plating layer 116. In one embodiment, plating process 300 completely covers the outer surface of conductive terminal 114 and other exposed features of lead frame panel array with nanotwin plating layer 116. Process 300 forms nanotwin plating layer 116 to any suitable thickness to promote consistent electrical properties and bondability for subsequent formation of second bond 120 during in-line bonding (as described above). Figure 1 and 1A ).exist Figure 2A At position 215, any previously formed photoresist or plating mask is removed, and at position 216, the lead frame panel array can be etched, for example, to remove any residue from the nanotwin plating layer 116.

[0035] Method 200 in Figure 2 At point 204, the bare film attachment process will continue. Figure 4 An example is shown in which a die attachment process 400 is performed to attach a semiconductor die 112 to a die attachment pad 110. Any suitable attachment process and materials can be used, for example, adhesives (not shown) can be dispensed, printed, or otherwise formed on the top side of the die attachment pad 110 (e.g., directly on the top side of the die attachment pad 110 and / or on any included nanotwin plating 116 previously plated on the top side of the die attachment pad 110). For example, an automated pick-and-place apparatus (not shown) is used to set the semiconductor die 112 onto the adhesive, and the attachment process 400 may include adhesive curing, for example, by heating, UV exposure, etc.

[0036] Method 200 in Figure 2 Wire bonding continues at position 206 to create one or more bonded wire interconnects in electronic device 100. Figures 5A to 5I Here's an example where the formation of bond line 115 is performed (e.g., as described above). Figure 1 and 1AWire bonding process 500, one or more examples, wherein the bonding wire has a first end 117 connected to a semiconductor die 112 via a first bonding member 118 and a second end 119 connected to an associated conductive terminal 114 via a second bonding member 120. In the illustrated example, wire bonding process 500 forms the first bonding member 118 as a ball bond and the second bonding member 120 as a stitch bond 120. Example wire bonding process 500 uses a wire bonding tool having: a nozzle 501 with concentric channels through which a conductive wire 502 can be translated along a third direction Z; and a clamp 504 for automatically controlling and selectively suppressing the translation of the wire 502.

[0037] The wire bonding at 206 can comprise any type or form of bonding wire bonding element and technique, such as one or more of ball bonding, stitch bonding, wedge bonding, flexible bonding, etc., with or without externally applied heat, using any suitable conductive wire 502, for example, the conductive wire being or comprising copper of any suitable wire diameter. In one embodiment, the wire bonding at 206 comprises attaching wires 115 at both ends for welding, for example, using one or more of downward pressure, ultrasonic energy, and heat in a low-cost thermoforming wire bonding process, wherein the externally applied heat may optionally be used to soften the metal. In another embodiment, the wire bonding may comprise a thermo-acoustic bonding implementation that combines external heat with ultrasonic energy during one or more bonding steps.

[0038] The wire bond at 202 includes the formation of the first bond element when the bond wire is generated. Figure 5A An example is shown where a molten metal sphere is formed using a flame-off process. A position control device (not shown) moves a nozzle 501 close to an electronic flame source (not shown). In one example, the system supplies energy to the electronic flame source (not shown) to create a flame or arc that melts the end of a conductive wire 502 to form a sphere 506, which is suspended by the remainder of the wire 502 while a clamp 504 remains closed. Figure 5A As shown in the image.

[0039] exist Figure 5B A first bonding element 118 is formed, for example, to connect wire 502 to bonding pads or other conductive features of semiconductor die 112. In one example, the first bonding element 118 is formed as a ball bond. In one example, the clamp 504 opens, as... Figure 5BAs shown in FIG. 5, the position control device moves the nozzle 501 downward along direction 510 in FIG. 5 with the clamp 504 open, so that the ball 506 is moved toward the bonding pad (not shown) of the semiconductor die 112. While the clamp 504 remains open, the nozzle 501 continues to move downward, causing the ball 506 to contact the top side of the bonding pad, and the ball 506 gradually collapses and expands laterally to form a first bonding element 118 (e.g., a ball bond). In this example, the ball bond 118 couples the first end of the intended bonding line 115 to the semiconductor die 112. In one example, heat is applied during the formation of the first bonding element 118. In this or another example, the position control device may optionally cause the nozzle 501 to vibrate at a high (e.g., ultrasonic) frequency to bond the ball 506 to the top side of the bonding pad, thereby forming a bonding pad as shown in FIG. 5. Figure 5B The first bonding member 118 shown includes moving the nozzle 501 laterally back and forth along the first X direction or laterally in a circular pattern in the XY plane to form the ball bonding member 118.

[0040] like Figure 5C Further demonstrating, in this example, wire bonding formation involves retracting the nozzle while the clamp 504 is open. Position control devices cause the first wire bonding portion 116 to extend upwards along the indicated direction 520. The wire bonding process 500 continues to form the main loop of the intended wire bonding 115 to the intended lead or other conductive terminal 114 on the lead frame panel. In this example, with the clamp 504 initially open, the nozzle 501 moves laterally away from the semiconductor die bonding pads along the first direction X. Then, the clamp 504 closes, as... Figure 5D As shown in the figure, the position control device moves the nozzle 501 along the [path] while the clamp 504 remains closed. Figure 5D The direction 530 moves toward the conductive terminal 114.

[0041] In this example, the wire bonding process 500 is... Figure 5E The second end 119 of the intended bonding wire 115 is coupled to the conductive terminal 114 via the second bonding member 120. In one example, the second bonding member 120 is a stitch bond. In another example, the second bonding member 120 is a wedge bond. Then, after forming the second bonding member 120, the separating wire 502 is... Figure 5E As shown, the position control device moves the nozzle 501 further laterally in the direction of arrow 540 until the center of the bonding wire 502 in the nozzle 501 is above the first portion of the conductive terminal 114, and then moves downward in direction 542 so that the second end 119 of the first portion 116 of the intended bonding wire 115 contacts the conductive terminal 114, as shown. Figure 5EAs shown in the illustration. In various embodiments, coupling the second end 119 of the first portion 116 and the first end 123 of the second portion 122 to the conductive terminal 114 includes, for example, forming the second bond 120 as a stitch bond or a wedge bond by thermoforming it with an applied downward force along direction 542. In this or another example, the position control device may optionally cause the nozzle to vibrate at a high (e.g., ultrasonic) frequency to bond the second end 119 of the intended bonding wire 115 to the top of the first portion of the conductive terminal 114, for example, by causing the nozzle 501 to move laterally back and forth along the X direction or laterally in a circular pattern in the XY plane to form the stitch bond 120.

[0042] Wire bonding process 500 Figure 5F The nozzle 501 continues to retract to the appropriate tail height, wherein the position control device moves the nozzle 501 upward along the third direction Z as shown by the direction arrow 550 to the appropriate tail height while the clamp 504 is open. Then, the clamp 504 closes, as shown... Figure 5G As shown in the diagram, the position control device moves nozzle 501 upwards along a third direction Z, as indicated by directional arrow 550. Figure 5H As shown, the wire bonding process 500 continues with the fixture remaining closed, further retracting the nozzle along direction 550 to tear off the tail of the wire 502. This separates or disconnects the wire 502 in the nozzle 501 from the second end 119 of the completed bonded wire 115 to complete the second bond 120.

[0043] like Figure 5I As shown, repeatable wire bonding process 500 can be used to form additional bonding lines 115 for interconnecting various bonding pads of semiconductor die 112 to corresponding conductive terminals 114, and / or other bonding line interconnects according to the specific design of the electronic device.

[0044] Once in 206 and Figure 2 After wire bonding is completed at point 208, the encapsulation molding process in example electronic device manufacturing process 200 continues at point 208. Figure 6 An example is shown in which a molding process 600 is performed to form a molded package structure 108 that encloses the internal portions of a semiconductor die 112, bonding wires 115, and conductive terminals 114.

[0045] exist Figure 2 At point 210, lead trimming and forming operations are performed along with package separation and other post-processing to provide multiple finished packaged electronic device products, such as those mentioned above. Figure 1 and 1A The device 100 shown in the image. Figure 7An example is shown in which lead trimming and forming process 700 is performed, which trims or otherwise separates the conductive terminal 114 from the starting lead frame panel and bends or otherwise forms the trimmed conductive terminal 114 into a desired wing shape. In the illustrated example, the lead trimming cuts through the adjacent conductive lead portion of the starting lead frame panel array across the boundary between adjacent unit areas, and may leave an unplated trimmed rear end of the finished conductive terminal 114 of the finished electronic device 100, such as... Figure 7 As shown in the diagram. As discussed above and in other embodiments, other portions of the conductive terminal 114 (and / or all or part of the die attachment pad 110) may have bare copper surfaces with an unplated layer 116, for example, by selective plating using a plating mask during the fabrication of the start lead frame.

[0046] Within the scope of the claims, modifications may be made to the described examples, and other embodiments are possible.

Claims

1. An electronic device comprising: Packaging structure; A conductive terminal, which is exposed outside the encapsulation structure and has a nanotwin coating; A semiconductor die, located within the package structure; and A bonding wire, which is enclosed by the encapsulation structure and has a first end and a second end, the first end being connected to the semiconductor die via a first bonding member and the second end being connected to the nanotwin coating via a second bonding member.

2. The electronic device of claim 1, wherein the conductive terminal comprises copper, and the nanotwin plating layer comprises copper.

3. The electronic device according to claim 2, wherein the second bonding member is a stitch bonding member.

4. The electronic device of claim 3, wherein the nanotwin coating comprises a first portion, a second portion, and a twin boundary between the first portion and the second portion, wherein the lattices on each side of the twin boundary are connected by mirror symmetry.

5. The electronic device according to claim 1, wherein the second bonding member is a stitch bonding member.

6. The electronic device of claim 1, wherein the nanotwin coating comprises a first portion, a second portion, and a twin boundary between the first portion and the second portion, wherein the lattices on each side of the twin boundary are connected by mirror symmetry.

7. The electronic device of claim 1, wherein the nanotwin coating completely covers the outer surface of the conductive terminal inside the packaging structure.

8. A system comprising a circuit board and electronic devices attached to the circuit board, the electronic devices comprising: Packaging structure; A conductive terminal, exposed outside the package structure and having a nanotwin coating, is soldered to the conductive features of the circuit board; A semiconductor die, located within the package structure; and A bonding wire, which is enclosed by the encapsulation structure and has a first end and a second end, the first end being connected to the semiconductor die via a first bonding member and the second end being connected to the nanotwin coating via a second bonding member.

9. The system of claim 8, wherein the conductive terminal comprises copper, and the nanotwin plating layer comprises copper.

10. The system of claim 8, wherein the second bonding member is a stitched bonding member.

11. The system of claim 8, wherein the nanotwin coating comprises a first portion, a second portion, and a twin boundary between the first portion and the second portion, wherein the lattices on each side of the twin boundary are connected by mirror symmetry.

12. The system of claim 8, wherein the nanotwin coating completely covers the outer surface of the conductive terminal inside the packaging structure.

13. A method of manufacturing an electronic device, the method comprising: Perform a plating process to form a nanotwin coating layer on the conductive terminals; and A wire bonding process is performed to form a bonding wire having a first end connected to a semiconductor die via a first bonding member and a second end connected to the nanotwin coating via a second bonding member.

14. The method of claim 13, wherein the plating process forms the nanotwinned plating layer as a nanotwinned copper layer on a copper conductive terminal.

15. The method of claim 14, wherein the plating process is a pulse plating process, the pulse plating process comprising pulse modulation of the plating current density.

16. The method of claim 15, further comprising controlling the duty cycle of the pulse plating process.

17. The method of claim 14, wherein the plating process completely covers the outer surface of the conductive terminal with the nanotwin plating layer.

18. The method of claim 13, wherein the plating process is a pulse plating process, the pulse plating process comprising pulse modulation of the plating current density.

19. The method of claim 18, further comprising controlling the duty cycle of the pulse plating process.

20. The method of claim 13, wherein the wire bonding process forms the second bonding member as a stitched bonding member.

21. A lead frame, comprising: Conductive terminals; and A nanotwin coating is located on the outer surface of the conductive terminal.

22. The lead frame of claim 21, wherein the conductive terminal comprises copper, and the nanotwin plating layer comprises copper.

23. The lead frame of claim 21, wherein the nanotwin coating comprises a first portion, a second portion, and a twin boundary between the first portion and the second portion, wherein the lattices on each side of the twin boundary are connected by mirror symmetry.

24. The lead frame of claim 21, wherein the nanotwin plating completely covers the outer surface of the conductive terminal.

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