Acceleration equalization filter configuration in power management circuit

Abstract

An accelerated equalization filter configuration is provided in an envelope tracking (ET) integrated circuit (ETIC). The ETIC is configured to provide an ET voltage to a power amplifier circuit for signal amplification. Furthermore, the ETIC is configured to utilize an equalization filter to help compensate for multiple distortions (e.g., ripple) in the ET voltage. The equalization filter, typically a complex filter, is dynamically configured using an optimal set of parameters that best matches the specific configuration and / or operating conditions of the ETIC (e.g., wiring distance, load impedance, modulation bandwidth, etc.). In the embodiments disclosed herein, search control circuitry is provided in the ETIC to help accelerate the configuration of the equalization filter. Therefore, the equalization filter can be automatically adjusted in a timely manner to help improve the overall performance of the ETIC.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 622,612, filed January 19, 2024, and U.S. Provisional Patent Application Serial No. 63 / 575,899, filed April 8, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] The technology disclosed herein generally relates to configuring equalization filters in power management circuits. Background Technology

[0004] In modern society, mobile communication devices are becoming increasingly prevalent in providing wireless communication services. This widespread adoption is partly driven by the numerous features currently available on these devices. The increased processing power of these devices means that they have evolved from mere communication tools into sophisticated mobile multimedia hubs capable of enhancing the user experience.

[0005] The redefined user experience relies on higher data rates provided by advanced fifth-generation (5G) and 5G New Radio (5G-NR) technologies, which typically transmit and receive radio frequency (RF) signals in the millimeter-wave spectrum. Given that RF signals are more susceptible to attenuation and interference in the millimeter-wave spectrum, they are typically amplified by state-of-the-art power amplifiers to help increase the RF signal to higher power before transmission.

[0006] Envelope tracking (ET) is a power management technique designed to improve the efficiency and / or linearity performance of power amplifiers. In an ET power management circuit, an ET integrated circuit (ETIC) is configured to generate a time-varying ET voltage based on the time-varying voltage envelope of an RF signal and to supply this time-varying ET voltage to (multiple) power amplifiers via conductive traces. It is understood that the better the time-varying ET voltage is aligned with the time-varying voltage envelope in both time and amplitude, the better the performance (e.g., efficiency and / or linearity) achievable at the power amplifiers. However, due to a number of factors (e.g., group delay, impedance mismatch, etc.), the time-varying ET voltage may become misaligned with the time-varying voltage envelope in both time and amplitude. Furthermore, the time-varying ET voltage may be distorted at (multiple) power amplifiers when the currents in (multiple) power amplifiers interact with the inherent inductance of the conductive traces. Therefore, it is desirable to correct for the distortion of the time-varying ET voltage and maintain good alignment with the time-varying voltage envelope at all times and throughout the wide modulation bandwidth of the RF signal. Summary of the Invention

[0007] Embodiments of this disclosure relate to an accelerated equalization filter configuration in an envelope tracking (ET) integrated circuit (ETIC). The ETIC is configured to provide an ET voltage to a power amplifier circuit for signal amplification. Furthermore, the ETIC is configured to utilize an equalization filter to help compensate for multiple distortions (e.g., ripple) in the ET voltage. The equalization filter, typically a complex filter, is dynamically configured using an optimal set of parameters that best matches the specific configuration and / or operating conditions of the ETIC (e.g., wiring distance, load impedance, modulation bandwidth, etc.). In the embodiments disclosed herein, search control circuitry is provided in the ETIC to help accelerate the configuration of the equalization filter. Therefore, the equalization filter can be automatically adjusted in a timely manner to help improve the overall performance of the ETIC.

[0008] In one aspect, an ETIC (Equalization Target Voltage) is provided. The ETIC includes a voltage generation circuit. The voltage generation circuit is configured to generate an ET voltage based on an equalized ET target voltage. The ETIC also includes an equalizer circuit. The equalizer circuit is configured to search a plurality of parameter sets to determine an optimal parameter set to configure an equalization filter to compensate for distortion of the ET voltage. The equalizer circuit is further configured to apply the equalization filter to the ET target voltage to thereby generate the equalized ET target voltage. The ETIC also includes a search control circuit. The search control circuit is configured to determine a reference parameter set to thereby accelerate the search for the optimal parameter set.

[0009] In another aspect, a method for accelerating the configuration of an equalization filter in an ETIC is provided. The method includes generating an ET voltage based on an equalization target voltage. The method further includes searching multiple sets of parameters to determine an optimal set of parameters for configuring the equalization filter to compensate for distortions in the ET voltage. The method also includes applying the equalization filter to the ET target voltage to thereby generate the equalization target voltage. The method further includes determining a set of reference parameters to thereby accelerate the search for the optimal set of parameters.

[0010] In another aspect, a wireless device is provided. The wireless device includes a power amplifier circuit. The power amplifier circuit is configured to amplify a signal based on an ET voltage. The wireless device also includes an ETIC. The ETIC is coupled to the power amplifier circuit via a conductive line. The method includes generating the ET voltage based on an equalized ET target voltage. The method further includes searching a plurality of parameter sets to determine an optimal parameter set to configure an equalization filter to compensate for distortion of the ET voltage. The method further includes applying the equalization filter to the ET target voltage to thereby generate the equalized ET target voltage. The method further includes determining a reference parameter set to thereby accelerate the search for the optimal parameter set. The wireless device also includes a transceiver circuit. The transceiver circuit is configured to generate the signal and the ET target voltage.

[0011] Those skilled in the art will understand the scope of this disclosure and recognize its other aspects after reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0012] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0013] Figure 1A This is a schematic diagram of an exemplary conventional power management circuit, in which an envelope tracking (ET) integrated circuit (ETIC) is configured to generate an ET voltage; Figure 1B It is shown Figure 1A A schematic diagram of various impedances and / or inductors that may cause voltage distortion in a conventional power management circuit; Figure 1C It provides Figure 1A The exemplary illustration of the ETIC is a schematic diagram in which the ETIC is configured to correct voltage distortion based on an equalization filter; Figure 2 This is a schematic diagram of an exemplary ETIC, wherein the search control circuitry is configured according to embodiments of the present disclosure to accelerate... Figure 1C Configuration of the equalization filter in the system; Figure 3 It includes Figure 2 A schematic diagram of an exemplary power management circuit for an ETIC; Figure 4 It can be made by Figure 2 A schematic diagram of an exemplary test waveform used by ETIC to extrapolate a set of reference parameters to help accelerate the configuration of the equalization filter; Figure 5 This is a schematic diagram of an exemplary communication device, in which the following can be provided: Figure 3 The power management circuit; and Figure 6 This is a flowchart of an exemplary process, based on which Figure 2 The ETIC can be configured to correct (multiple) ET voltage errors. Detailed Implementation

[0014] The embodiments described below illustrate the information necessary to enable those skilled in the art to practice the embodiments and demonstrate the best mode of practice. After reading the following description with reference to the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will appreciate the application of these concepts, even those not specifically set forth herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0015] It should be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] It should be understood that when an element, such as a layer, region, or substrate, is referred to as "on another element" or "extending to another element," it may be directly located on or directly extended to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly located on another element" or "directly extended to another element," no intermediate elements are present. Similarly, it should be understood that when an element, such as a layer, region, or substrate, is referred to as "on top of another element" or "extending over another element," it may be directly located on top of or directly extended over the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly located on top of another element" or "extending directly over another element," no intermediate elements are present. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected to or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0017] Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It should be understood that these terms and those discussed above are intended to include different orientations of the device other than those depicted in the figures.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a”, “an”, and “described” are intended to include the plural forms as well. It should also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that the terms used herein shall be interpreted as having the same meaning as in the context of this specification and related art, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0020] Embodiments of this disclosure relate to an accelerated equalization filter configuration in an envelope tracking (ET) integrated circuit (ETIC). The ETIC is configured to provide an ET voltage to a power amplifier circuit for signal amplification. Furthermore, the ETIC is configured to utilize an equalization filter to help compensate for multiple distortions (e.g., ripple) in the ET voltage. The equalization filter, typically a complex filter, is dynamically configured using an optimal set of parameters that best matches the specific configuration and / or operating conditions of the ETIC (e.g., wiring distance, load impedance, modulation bandwidth, etc.). In the embodiments disclosed herein, search control circuitry is provided in the ETIC to help accelerate the configuration of the equalization filter. Therefore, the equalization filter can be automatically adjusted in a timely manner to help improve the overall performance of the ETIC.

[0021] From Figure 2 Before discussing the ETIC disclosed herein, first refer to Figure 1A-1C An overview of conventional power management circuitry is provided to help understand the technical problem this article addresses.

[0022] Figure 1A It is configured to generate ET voltage V CC A schematic diagram of an exemplary conventional power management circuit 10. The conventional power management circuit 10 includes a transceiver circuit 12, an ET integrated circuit (ETIC) 14, a power amplifier circuit 16, and conductive lines 18 (e.g., conductive traces) coupling the ETIC 14 to the power amplifier circuit 16.

[0023] Transceiver circuit 12 is configured to generate a time-varying power envelope P ENV The associated RF signal 20 is provided to the power amplifier circuit 16. The transceiver circuit 12 is also configured to track (also known as follow) the time-varying power envelope P. ENV Generate target voltage V TGT ETIC 14 is configured based on the target voltage V. TGT Generate ET voltage V CC Furthermore, the power amplifier circuit 16 is configured based on the ET voltage V. CC Amplify the RF signal by 20. Given the target voltage V... TGT Tracking the time-varying power envelope P ENV And based on the target voltage V TGT Generate ET voltage V CC ET voltage V CC It should also be related to the time-varying power envelope P ENV alignment.

[0024] However, due to various factors, ET voltage V CC At input 22 of power amplifier circuit 16, distortion and / or distortion relative to the time-varying power envelope P may occur. ENV Misalignment, these factors will be taken into account Figure 1B Further explanation. Figure 1B It shows that it may lead to Figure 1A ET voltage V CC Distortion and / or relative to the time-varying power envelope P ENV A diagram illustrating the various factors contributing to misalignment. Figure 1A and 1B Common elements between them are indicated by common element designations and will not be described again in this document.

[0025] In this paper, ETIC 14 has an equivalent inductance L ETIC The modeled inherent impedance, and the conductor 18 has an equivalent trace inductance L. TRACE The inherent trace inductance is modeled. Therefore, the voltage path 24 between ETIC 14 and the input 22 of the power amplifier circuit 16 will have an equivalent inductance L. ETIC and equivalent trace inductance L TRACE The sum ( The total equivalent inductance L) E .

[0026] The power amplifier circuit 16 can be modeled as having a modulation current I CC The current source, and has an equivalent capacitance C PA Therefore, the equivalent source impedance Z at input 22 of power amplifier circuit 16 is... SOURCEIt can be determined as shown in the following equation (Equation 1).

[0027] (Equation 1)

[0028] In equation (Equation 1), s represents the s-transform symbol, which can be expressed as: Modulation current I CC With target voltage V TGT It is in a certain proportion and can be approximated as in the following equation (Equation 2).

[0029] (Equation 2)

[0030] In the above equation (Equation 2), R ICC This represents the equivalent resistance at input 22 (e.g., collector) of power amplifier circuit 16. It is worth noting that when power amplifier circuit 16 receives voltage ET at input 22 via voltage path 24... CC At that time, the modulation current I CC Possibly related to the total equivalent inductance L E Interacting to achieve the desired voltage V at ET CC This generates ripple (also known as voltage distortion). When the power amplifier circuit 16 is based on the ET voltage V... CC When the RF signal 20 is amplified, it can be represented as The ripple may cause distortion in the RF signal 20.

[0031] Fortunately, the ET voltage V CC Voltage distortion in the voltage can be corrected by applying an equalization filter H(s) to the target voltage V. TGT To correct it. Figure 1C This is a schematic diagram of ETIC 14, in which the equalizer circuit 26 can be configured to correct based on the equalizer filter H(s). Figure 1B Voltage distortion in the system. Figure 1A-1C Common elements between them are indicated by common element designations and will not be described again in this document.

[0032] Specifically, the equalizer circuit 26 is configured to apply the equalization filter H(s) to the target voltage V. TGT To generate the equilibrium target voltage V TGT-E ETIC 14 also includes a voltage generation circuit 28, which is configured to equalize a target voltage V. TGT-E Generate ET voltage V CC Therefore, by applying the equalization filter H(s) to the target voltage V TGT And based on the balanced target voltage V TGT-E Generate ET voltage V CC It can correct the ET voltage V CCVoltage distortion in the system.

[0033] In this embodiment, the equalization filter H(s) can be defined in the following equation (Equation 3).

[0034] (Equation 3)

[0035] The equalization filter H(s) in equation (Equation 3) can be obtained by using I in equation (Equation 2). CC The substitution equation (Equation 3) for I CC This can be further represented as in equation (Equation 4).

[0036] (Equation 4)

[0037] The equalization filter H(s) shown in equation (Equation 4) can be further defined by a pair of parameters Q( ) and ω The definition is as shown in equation (Equation 5).

[0038] (Equation 5)

[0039] As can be seen from equation (Equation 5), the equalization filter H(s) is a second-order complex zero-point filter defined by the set of parameters Q and ω. Therefore, in order to properly determine the equalization filter H(s) to correct voltage distortion, it is necessary to appropriately determine the set of parameters Q and ω.

[0040] However, since each parameter in the set of parameters Q and ω is the equivalent capacitance C PA Equivalent resistance R ICC and / or total equivalent inductance L E The function of ω means that the set of parameters Q and ω can vary greatly depending on the configuration and / or operating conditions of the conventional power management circuit 10. For example, the fabrication process and / or materials used to manufacture ETIC 14 may affect the equivalent inductance L. ETIC Furthermore, the length and / or material of the conductive line 18 may affect the equivalent trace inductance L. TRACE Additionally, since the power amplifier circuit 16 may be supplied by different vendors, the equivalent capacitance C... PA and equivalent resistance R ICC It can also change significantly. Furthermore, the modulation frequency of the RF signal 20 may also affect the sign of the s-transformation (which can be represented as...). The change in ) and therefore the modulation current I CC The changes contribute to this. Therefore, ETIC 14 must be configured to cover as many changes as possible.

[0041] Specifically, ETIC 14 may include a configuration lookup table (LUT) 30. The configuration LUT 30 is pre-configured to store multiple parameter sets (Q1, ω1) - (Q... N , ω N The equalizer circuit 26 is configured to scan the configuration LUT 30 to find the parameter set (Q1, ω1)-(Q). N , ω N The optimal one that best matches the configuration and / or operating conditions of ETIC 14 is selected from the configuration LUT 30, and the equalization filter H(s) is configured accordingly. However, due to the parameter set (Q1, ω1)-(Q) stored in the configuration LUT 30, N , ω N The time required to configure the LUT 30 and the equalizer H(s) using the ETIC 14 scan is potentially very large, thus requiring a considerable amount of time. Therefore, the technical problem this paper aims to address is to accelerate the configuration of the equalizer H(s) with minimal changes to the ETIC 14.

[0042] In this regard, Figure 2 This is a schematic diagram of an exemplary ETIC 32, wherein the search control circuit 34 is configured according to an embodiment of the present disclosure to accelerate the configuration of the equalization filter H(s). To minimize... Figure 1C The changes made to ETIC 14 are omitted, and ETIC 32 reuses the LUT 30 configuration as is. ETIC 32 also includes an equalizer circuit 36, which can determine the parameter set (Q1,ω1)-(Q N , ω N The optimal one of the following is selected to configure the equalization filter H(s) and apply the equalization filter H(s) to the target voltage VET. TGT To generate the equalized ET target voltage V TGT-E .

[0043] The difference between ETIC 32 and ETIC 14 is that the search control circuit 34 is configured to determine the reference parameter set (Q). R , ω R ), to help equalizer circuit 36 ​​accelerate the search for parameter set (Q1, ω1)-(Q) in configuration LUT 30. N , ω N The optimal one among them. In an embodiment, ETIC 32 can replace ETIC 14 in conventional power management circuit 10 without changing transceiver circuit 12 and power amplifier circuit 16. Figure 3 It includes Figure 1A The transceiver circuit 12 and the power amplifier circuit 16 in the middle are Figure 2 A schematic diagram of an exemplary power management circuit 38 of the ETIC 32. Figure 1A-1Cand Figure 2 Common components are shown with common component designations and will not be described again herein. The aforementioned technical problem can be effectively solved with minimal changes to the conventional power management circuit 10 by replacing ETIC 14 with ETIC 32 in the power management circuit 38.

[0044] Return to reference Figure 2 The ETIC 32 includes a voltage generation circuit 40. The voltage generation circuit 40 can be configured to include a voltage amplifier 42, a offset capacitor 44, a switching circuit 46, and a controller 48. The voltage amplifier 42 is powered by a supply voltage V. SUP Power supply, based on the equalization ET target voltage V TGT-E Generate initial ET voltage V AMP The offset capacitor 44 is configured to apply the initial ET voltage V. AMP Increase offset voltage V OFF This generates an ET voltage V at output 50 of the ETIC 32. CC .

[0045] Switching circuit 46 is configured to operate according to the equalization target voltage V ET determined by controller 48. TGT-E The determined duty cycle signal 52 generates a low-frequency current I at output 50. DC When ET voltage V CC When below the peak range, the low-frequency current I DC It can be used to maintain the offset voltage V across the offset capacitor 44. OFF And in modulation voltage I CC The DC content is provided, and the voltage amplifier 42 is also configured to provide DC content when the ET voltage V CC When within the peak range, at the modulation current I CC The AC supply content is specified. Voltage amplifier 42 is configured based on the feedback voltage V from output 50. CC-FB To adjust AC current I AC And generate sensing current I SENSE To indicate AC current I AC The quantity. Because voltage amplifier 42 will only operate at ET voltage V. CC Supply AC current I in the peak region AC Therefore, the sensing current I SENSE It can be used to approximate the modulation current I CC The maximum amount.

[0046] In one embodiment, ETIC 32 further includes a peak detector 54 to detect the ET voltage V. CC Whether it is within the peak region. Specifically, the peak detector 54 can generate the sensing voltage V. SENSETo indicate ET voltage V CC The peak value. Therefore, the search control circuit 34 can be configured based on the sensed voltage V. SENSE and sensing current I SENSE Estimate the output impedance Z at 50 ohms. EST ( ), and from the estimated output impedance Z EST Extrapolation reference parameter set (Q) R , ω R ).

[0047] As can be understood from the previous discussion, the search control circuit 34 must know the equivalent capacitance C. PA Equivalent resistance R ICC Total equivalent inductance L E To determine the reference parameter set (Q) R , ω R Given that in determining the set of reference parameters (Q) R , ω R The problem involves three unknown parameters, and the search control circuit 34 must estimate at least three different output impedances Z under at least three different test conditions. EST extrapolating the equivalent capacitance C PA Equivalent resistance R ICC Total equivalent inductance L E .

[0048] In one embodiment, ETIC 32 also includes a waveform generator 56, which can be configured to generate a test waveform 58 to modify the equalization ET target voltage. VTGT-E The test waveform 58 can be generated at different frequencies to thereby change the output impedance Z at output 50 of the ETIC 32. EST .

[0049] In this paper, the search control circuit 34 is configured to control the waveform generator 56 to generate test waveforms 58 at at least three different frequencies f1, f2, f3, thereby modifying the equalization ET target voltage under at least three different test conditions. Therefore, the search control circuit can estimate at least three output impedances Z at output 50. EST From this, the equivalent capacitance C can be deduced. PA Equivalent resistance R ICC Total equivalent inductance L E In an embodiment, the search control circuit 34 can use linear calculations of a network or lumped elements consisting of inductors, capacitors, and resistors to determine the estimated output impedance Z. EST Extrapolated equivalent capacitance C PA Equivalent resistance R ICC Total equivalent inductance L E .

[0050] In a non-limiting example, the test waveform 58 can be a continuous wave (CW) waveform, a pulse waveform, a square wave waveform, a multi-CW waveform, etc. Figure 4 It is provided so that in Figure 2 A schematic diagram of an exemplary illustration of a test waveform 58 generated by creating at least three test conditions in ETIC 32.

[0051] In this document, test waveform 58 is a square wave generated at frequencies f1, f2, f3 (f3 > f2 > f1). In this embodiment, frequencies f1, f2, and f3 are all within the frequency range (also known as bandwidth) in which ETIC 32 is configured to operate. More specifically, frequencies f1, f2, and f3 are selected to induce an output impedance Z at output 50 of ETIC 32. EST The variation. In this paper, each of frequencies f1, f2, and f3 is separated from each other by an interval factor, which can be one-fifth or one-tenth of the highest frequency f3.

[0052] Return to reference Figure 2 Upon receiving the reference parameter set (Q) R , ω R At the same time, the equalizer circuit 36 ​​is also configured to search the configuration LUT 30 to determine the reference parameter set (Q). R , ω R The optimal set of parameters that best matches (identical or closest). In an embodiment, the search control circuit 34 can be configured to refine the reference parameter set (Q) through multiple iterations. R , ω R ). In determining the reference parameter set (Q) R , ω R After that, the search control circuit 34 can also disable the waveform generator 56.

[0053] Can be provided in communication devices Figure 3 The power management circuit 38 is configured to support the embodiments described above. In this regard, Figure 5 This is a schematic diagram of an exemplary communication device 100, in which a communication device can be provided. Figure 3 The power management circuit 38.

[0054] In this document, communication device 100 can be any type of communication device, such as a mobile terminal, smartwatch, tablet computer, computer, navigation device, access point, base station (e.g., eNB, gNB, etc.), and any other wireless communication device that supports wireless communication, such as cellular, wireless local area network (WLAN), Bluetooth, ultra-wideband (UWB), and near-field communication. Communication device 100 will typically include a control system 102, a baseband processor 104, a transmitting circuit system 106, a receiving circuit system 108, an antenna switching circuit system 110, multiple antennas 112, and a user interface circuit system 114. In a non-limiting example, for example, the control system 102 may be a field-programmable gate array (FPGA). In this regard, the control system 102 may include at least multiple microprocessors, multiple embedded memory circuits, and multiple communication bus interfaces. The receiving circuit system 108 receives radio frequency signals from one or more base stations via antennas 112 and through the antenna switching circuit system 110. A low-noise amplifier and a filter work together to amplify and eliminate broadband interference in the received signal for processing. Then, a downconversion and digitization circuitry system (not shown) downconverts the filtered received signal to an intermediate frequency (IF) or baseband frequency signal, and then uses (multiple) analog-to-digital converters (ADCs) to digitize the IF or baseband frequency signal into one or more digital streams.

[0055] The baseband processor 104 processes the digitized received signal to extract the information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations, as will be discussed in more detail below. The baseband processor 104 is typically implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0056] For transmission, baseband processor 104 receives digitized data representing voice, data, or control information from control system 102 and encodes it for transmission. The encoded data is output to transmit circuitry system 106, where multiple digital-to-analog converters (DACs) convert the digitized data into analog signals, and a modulator modulates the analog signals into carrier signals at one or more desired transmission frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and delivers it to antenna 112 via antenna switching circuitry system 110. Multiple antennas 112 and replicated transmit circuitry system 106 and receive circuitry system 108 provide spatial diversity. Those skilled in the art will understand the modulation and processing details.

[0057] In one embodiment, transceiver circuitry 12 may be provided in transmitting circuitry system 106. ETIC 32 and power amplifier circuitry 16 may be provided between transmitting circuitry system 106 and antenna switching circuitry system 110. More specifically, ETIC 32 may be coupled to transmitting circuitry system 106, and power amplifier circuitry 16 may be coupled to antenna switching circuitry system 110.

[0058] In an embodiment, Figure 2 The ETIC 32 can be configured to correct voltage distortion based on process conditions. In this regard, Figure 6 This is a flowchart of an exemplary process 200, according to which Figure 2 The ETIC 32 can be configured to correct voltage distortion.

[0059] In this paper, process 200 includes equalization based on the target voltage V of ET. TGT-E Generate ET voltage V CC (Step 202). Process 200 also includes searching the parameter set (Q1, ω1)-(Q N , ω N To determine the optimal set of parameters for configuring the equalization filter H(s) to compensate for the ET voltage V CC The distortion (step 204). Process 200 also includes applying an equalization filter H(s) to the ET target voltage V. TGT To generate the equalization target voltage V of ET. TGT-E (Step 206). Process 200 also includes determining a set of reference parameters (Q). R ,ω R This accelerates the search for the optimal set of parameters (step 208).

[0060] Those skilled in the art will appreciate improvements and modifications to the preferred embodiments of this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the claims below.

Claims

1. An envelope tracking (ET) integrated circuit (ETIC), the envelope tracking integrated circuit comprising: A voltage generation circuit, configured to generate an ET voltage based on an equalized ET target voltage; Equalizer circuit, the equalizer circuit being configured to: Multiple parameter sets are searched to determine the optimal parameter set in order to configure the equalization filter to compensate for the distortion of the ET voltage; as well as The equalization filter is applied to the ET target voltage to generate the equalized ET target voltage. as well as A search control circuit is configured to determine a set of reference parameters to accelerate the search for the optimal set of parameters.

2. The ETIC according to claim 1, wherein each of the plurality of parameter sets is a function of one or more of the following: The ETIC and the equivalent total inductance of the conductive lines configured to couple the ETIC to the power amplifier circuit. The equivalent capacitance of the power amplifier circuit; and The equivalent resistance of the power amplifier circuit.

3. The ETIC according to claim 2, wherein the search control circuit is further configured to: Determine the corresponding output impedance of the ETIC under each of at least three different test conditions; The equivalent total inductance, equivalent capacitance, and equivalent resistance are extrapolated based on the corresponding output impedance determined under each of the at least three different test conditions; and The reference parameter set is determined based on the extrapolated equivalent total inductance, extrapolated equivalent capacitance, and extrapolated equivalent resistance.

4. The ETIC of claim 3 further includes a waveform generator configured to generate a test waveform to modify the equalized ET target voltage, wherein the search control circuit is further configured to cause the waveform generator to generate the test waveform at at least three different frequencies to thereby modify the equalized ET target voltage under the at least three different test conditions.

5. The ETIC of claim 4, wherein the waveform generator is configured to generate the test waveform at at least three different frequencies falling within the bandwidth of the ETIC.

6. The ETIC of claim 4, wherein the search control circuit is further configured to deactivate the waveform generator after the set of reference parameters has been determined.

7. The ETIC according to claim 3, wherein the search control circuit is further configured to: Estimate the corresponding peak voltage and peak current at the output of the ETIC under each of the at least three different test conditions; and The corresponding output impedance of the ETIC is determined based on the corresponding peak voltage and the corresponding peak current estimated under each of the at least three different test conditions.

8. The ETIC of claim 1 further includes a configuration lookup table (LUT) pre-configured to store the plurality of parameter sets, wherein the equalizer circuitry is further configured to search the plurality of parameter sets in the configuration LUT to determine the optimal parameter set that best matches the reference parameter set.

9. A method for configuring equalization filters in an accelerated envelope tracking (ET) integrated circuit (ETIC), comprising: ET voltage is generated based on the balanced ET target voltage; Multiple parameter sets are searched to determine the optimal parameter set in order to configure the equalization filter to compensate for the distortion of the ET voltage; The equalization filter is applied to the ET target voltage to generate the equalized ET target voltage. as well as A reference parameter set is determined to accelerate the search for the optimal parameter set.

10. The method of claim 9, wherein each of the plurality of parameter sets is a function of one or more of the following: The ETIC and the equivalent total inductance of the conductive lines configured to couple the ETIC to the power amplifier circuit. The equivalent capacitance of the power amplifier circuit; and The equivalent resistance of the power amplifier circuit.

11. The method of claim 10, further comprising: Determine the corresponding output impedance of the ETIC under each of at least three different test conditions; The equivalent total inductance, the equivalent capacitance, and the equivalent resistance are extrapolated based on the corresponding output impedance determined under each of the at least three different test conditions. as well as The reference parameter set is determined based on the extrapolated equivalent total inductance, extrapolated equivalent capacitance, and extrapolated equivalent resistance.

12. The method of claim 11, further comprising: Modify the equalization ET target voltage using the test waveform; as well as The test waveforms are generated at at least three different frequencies to modify the equalized ET target voltage under the at least three different test conditions.

13. The method of claim 12, further comprising generating the test waveform at the at least three different frequencies falling within the bandwidth of the ETIC.

14. The method of claim 11, further comprising: Estimate the corresponding peak voltage and corresponding peak current at the output of the ETIC under each of the at least three different test conditions; as well as The corresponding output impedance of the ETIC is determined based on the corresponding peak voltage and the corresponding peak current estimated under each of the at least three different test conditions.

15. The method of claim 9, further comprising: The multiple parameter sets are stored in a configuration lookup table (LUT); as well as The configuration LUT searches the multiple parameter sets to determine the optimal parameter set that best matches the reference parameter set.

16. A wireless device, the wireless device comprising: A power amplifier circuit configured to amplify a signal based on envelope tracking (ET) voltage. An ET integrated circuit (ETIC), coupled to the power amplifier circuit via a conductive line, and comprising: A voltage generation circuit, configured to generate an ET voltage based on an equalized ET target voltage; Equalizer circuit, the equalizer circuit being configured to: Searching multiple parameter sets to determine the optimal parameter set for configuring an equalization filter to compensate for the distortion of the ET voltage; and The equalization filter is applied to the ET target voltage to generate the equalized ET target voltage; and A search control circuit, configured to determine a set of reference parameters to accelerate the search for the optimal set of parameters; and A transceiver circuit configured to generate the signal and the ET target voltage.

17. The wireless device of claim 16, wherein each of the plurality of parameter sets is a function of one or more of the following: The equivalent total inductance of the ETIC and the conductive line; The equivalent capacitance of the power amplifier circuit; and The equivalent resistance of the power amplifier circuit.

18. The wireless device of claim 17, wherein the search control circuit is further configured to: Determine the corresponding output impedance of the ETIC under each of at least three different test conditions; The equivalent total inductance, equivalent capacitance, and equivalent resistance are extrapolated based on the corresponding output impedance determined under each of the at least three different test conditions; and The reference parameter set is determined based on the extrapolated equivalent total inductance, extrapolated equivalent capacitance, and extrapolated equivalent resistance.

19. The wireless device of claim 18, wherein the ETIC further comprises a waveform generator configured to generate a test waveform to modify the equalized ET target voltage, wherein the search control circuitry is further configured to cause the waveform generator to generate the test waveform at at least three different frequencies to thereby modify the equalized ET target voltage under the at least three different test conditions.

20. The wireless device of claim 18, wherein the search control circuit is further configured to: Estimate the corresponding peak voltage and peak current at the output of the ETIC under each of the at least three different test conditions; and The corresponding output impedance of the ETIC is determined based on the corresponding peak voltage and the corresponding peak current estimated under each of the at least three different test conditions.

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