Circuit board and semiconductor package including the circuit board

Abstract

A circuit board according to one embodiment may include: a first insulating layer; a second insulating layer disposed on the first insulating layer; one or more electronic devices disposed in the second insulating layer; a connecting member that overlaps with the electronic devices in a horizontal direction and is disposed in the second insulating layer; a first via electrode disposed in the second insulating layer and disposed on the electronic devices; and a second via electrode disposed in the second insulating layer and disposed on the connecting member, wherein the horizontal width of the first via electrode is different from the horizontal width of the second via electrode.

Description

Technical Field

[0001] Each embodiment relates to a circuit board and a semiconductor package. Background Technology

[0002] With the continuous improvement of the performance of electrical / electronic products, the technology of placing more semiconductor devices on circuit boards of limited size has been proposed and studied. However, since typical semiconductor packages are basically configured to mount only one semiconductor device on them, there are limitations in obtaining the required performance.

[0003] Therefore, semiconductor packages that utilize multiple substrates to arrange multiple semiconductor devices have recently been provided. Such semiconductor packages have a structure in which multiple semiconductor devices are interconnected on a circuit board in a horizontal and / or vertical direction. Therefore, this semiconductor package has the advantages of effectively utilizing the mounting area of ​​the semiconductor devices and transmitting high-speed signals through short signal transmission paths between the semiconductor devices.

[0004] Meanwhile, the circuit board includes a multilayer insulator containing an insulating layer and a multilayer wiring structure disposed on the multilayer insulator. For example, the circuit board may refer to a structure in which the mounting positions of each semiconductor device are predetermined for mounting at least one semiconductor device, and a multilayer wiring structure connected to the semiconductor device is disposed on the multilayer insulator. The multilayer wiring structure includes wiring layers disposed on the surfaces of the respective insulating layers and via electrodes for connecting the wiring layers in a vertical direction. The semiconductor device is mounted on the circuit board and can transmit and receive signals through the multilayer wiring structure.

[0005] Recently, techniques for embedding electronic devices within a package substrate have been studied. These electronic devices are used to consume, store, and release power supplied within the motherboard of an electronic device. For example, various passive devices such as capacitors, inductors, and resistors are required to operate active devices such as memory devices, application processors (APs), or RF semiconductors. Techniques for embedding electronic devices such as deep trench capacitors (DTCs) within the package substrate are being developed to achieve high capacity and high performance based on the high integration and multifunctionality of the circuit board.

[0006] Meanwhile, in traditional circuit boards, electronic components are placed in a core layer to ensure the board's rigidity. However, when electronic components are placed in the core layer, the distance between the external chips mounted on the circuit board and the electronic components in the core layer increases, leading to signal transmission loss. Summary of the Invention

[0007] Technical issues

[0008] One of the technical problems of the embodiments is to prevent signal transmission loss between electronic devices and external chips.

[0009] Furthermore, one of the technical problems of the embodiments is to reduce the thickness of the circuit board.

[0010] Furthermore, one of the technical problems of the embodiments is preventing the warping of the circuit board.

[0011] The technical problems of the embodiments are not limited to those described in this section, but also include technical problems that can be understood from the description of this disclosure.

[0012] Technical solution

[0013] A circuit board according to one embodiment includes: a first insulating layer and a second insulating layer disposed on the first insulating layer; one or more electronic devices disposed in the second insulating layer; a connecting member overlapping the electronic devices in a horizontal direction and disposed in the second insulating layer; a first via electrode disposed in the second insulating layer and disposed on the electronic devices; and a second via electrode disposed in the second insulating layer and disposed on the connecting member, wherein the horizontal width of the first via electrode may be different from the horizontal width of the second via electrode.

[0014] Furthermore, in one embodiment, the horizontal width of the first via electrode may be greater than the horizontal width of the second via electrode.

[0015] Furthermore, in one embodiment, the height of the upper surface of the first via electrode and the height of the upper surface of the second insulating layer can be the same.

[0016] Furthermore, in one embodiment, the amount of reinforcing member in the second insulating layer may be less than the amount of reinforcing member in the first insulating layer.

[0017] In addition, one embodiment may include: the upper surface of the first insulating layer includes a trench region, the second insulating layer further includes a protrusion that overlaps with the first insulating layer in the horizontal direction and is disposed in the trench region of the first insulating layer, and the electronic device may be disposed in the trench region.

[0018] In addition, one embodiment may include a protective layer disposed on the second insulating layer and in contact with the first via electrode.

[0019] In addition, one embodiment may include a third insulating layer disposed between the second insulating layer and the protective layer, and the content of reinforcing members in the third insulating layer may be greater than the content of reinforcing members in the second insulating layer.

[0020] In addition, one embodiment may include a cylindrical bump disposed in the second insulating layer and overlapping the electronic device in the horizontal direction.

[0021] Furthermore, in one embodiment, the sum of the horizontal widths of the first via electrode and the second via electrode may be less than the horizontal width of the cylindrical bump.

[0022] Furthermore, in one embodiment, the height of the upper surface of the first via electrode and the height of the upper surface of the cylindrical bump can be the same.

[0023] A semiconductor package according to one embodiment includes any of the circuit substrates described above.

[0024] Beneficial effects

[0025] The circuit board and semiconductor package including the circuit board according to the embodiment have the technical effect of preventing signal transmission loss between electronic devices and external chips.

[0026] For example, in one embodiment, the electronic device is disposed in a second insulating layer adjacent to the outermost layer of the circuit board, thereby reducing the electrical connection distance to external devices or the board and preventing signal loss.

[0027] Furthermore, one embodiment has the technical effect of controlling signal transmission with the connected external chip by separately controlling the horizontal width of the via electrodes of the electronic device and the connecting member.

[0028] For example, refer to Figure 2 One embodiment can control signal transmission with externally connected chips by setting the first width of the first via electrode of the electronic device and the second width of the second via electrode of the connecting member to be different from each other.

[0029] In addition, one embodiment has the technical effect of reducing the thickness of the circuit board.

[0030] For example, refer to Figure 3 In one embodiment, since the electronic components and connecting members are disposed in the recessed area, the thickness of the second insulating layer can be reduced, thereby reducing the thickness of the circuit board.

[0031] In addition, one embodiment has the technical effect of preventing circuit board warping problems.

[0032] For example, refer to Figure 4 In one embodiment, a fifth insulating layer is disposed between the second insulating layer and the first protective layer, and the fifth insulating layer has a higher content of reinforcing members than the second insulating layer, thereby preventing warping of the circuit board.

[0033] The technical effects of the embodiments are not limited to those described in this section, but also include effects that can be understood from the description of this disclosure. Attached Figure Description

[0034] Figure 1 This is a cross-sectional view of the circuit board 100 according to the first embodiment.

[0035] Figure 2 yes Figure 1 A magnified view of area A1.

[0036] Figure 3 This is a cross-sectional view of the circuit board 101 according to the second embodiment.

[0037] Figure 4 This is a cross-sectional view of the circuit board 102 according to the third embodiment.

[0038] Figure 5 This is a cross-sectional view of the semiconductor package 103 according to an embodiment. Detailed Implementation

[0039] The preferred embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0040] However, the technical spirit of this disclosure is not limited to the embodiments described herein, but can be implemented in various different forms, and within the scope of the technical spirit of this disclosure, the constituent elements of one or more embodiments can be selectively combined, substituted, and used.

[0041] Furthermore, the terms (including technical and scientific terms) used in the embodiments of this disclosure, unless otherwise specifically defined, are to be interpreted as meaning commonly understood by one of ordinary skill in the art to which this disclosure pertains, and generally used terms, such as those defined in a dictionary, may be interpreted taking into account the contextual meaning of the relevant technical field. Moreover, the terminology used in the embodiments of this disclosure is for describing embodiments and is not intended to limit this disclosure.

[0042] In this specification, unless the context otherwise requires, singular expressions may include plural expressions, and when described as "at least one (or one or more) of A and / or B and C", it may include one or more of all possible combinations of A, B, and C. Furthermore, when describing the constituent elements of embodiments of this disclosure, terms such as first, second, A, B, (a), and (b) may be used.

[0043] In this specification, for ease of description, the constituent elements can be described in terms of horizontal and vertical directions. The vertical direction refers to the area above (above) or below (below) each constituent element, while the horizontal direction refers to the direction perpendicular to the vertical direction. Furthermore, the horizontal direction can include a first horizontal direction and a second horizontal direction. Here, when following a Cartesian coordinate system, the first horizontal direction can refer to the X-axis direction, the second horizontal direction can refer to the Y-axis direction, and the vertical direction can refer to the Z-axis direction. When using a cylindrical coordinate system, the first horizontal direction can refer to the direction along the azimuth angle, and the second horizontal direction can refer to the direction towards the radius; these directions can be selectively combined. Furthermore, the direction along the azimuth angle can be called the circumferential direction, and the direction towards the radius can be called the radial direction.

[0044] These terms are used only to distinguish one constituent element from another, and do not limit the nature, order, or sequence of the respective constituent elements. Furthermore, when a constituent element is described as "connected," "joined," or "attached" to another constituent element, the constituent element includes not only cases where it is directly connected, joined, or attached to the other constituent element, but also cases where it is "connected," "joined," or "attached" to the other constituent element through another constituent element inserted therebetween.

[0045] Furthermore, the meaning of "component A is exposed from component B" should not be understood as component A being exposed from the entire product, but rather as component A being exposed from component B. That is, when component A is described as being exposed from component B, it should be understood that component A is at least partially covered by component C.

[0046] Furthermore, when component A is described as being in "contact" with component B, this includes not only the case of direct "contact" with another component, but also the case of "contact" with another component through another component inserted therein. Therefore, when component A should be understood only as being in "direct contact" with component B, it is described as "direct contact".

[0047] Furthermore, when a constituent element A is described as being “covered” by a constituent element B, it should be understood that constituent element A is covered by constituent element B so that the part that achieves the intended function and purpose is covered. Unless there are special circumstances, it should not be understood that the whole of constituent element A is necessarily covered by constituent element B.

[0048] Furthermore, when element A is described as "fixed" to element B, it should be understood that element A is not only directly linked to and fixed to element B, but also indirectly fixed to element B through element C and / or element D, taking into account the intended function and purpose, unless otherwise specified. When element A should be understood only as "directly fixed" to element B, it is described as "directly fixed".

[0049] Furthermore, when described as being formed or positioned "above" or "below" each constituent element, the terms "above" or "below" include not only cases where two constituent elements are in direct contact, but also cases where one or more additional constituent elements are formed or positioned between the two constituent elements. Additionally, when expressed as "above" or "below," the expression can include not only an upward direction relative to a constituent element, but also a downward direction.

[0050] (Example)

[0051] Figure 1 This is a cross-sectional view of the circuit board 100 according to an embodiment.

[0052] Reference Figure 1 According to an embodiment, the circuit board 100 includes a multilayer structure 110 and electronic devices 150. The multilayer structure 110 includes a multilayer insulator 112, a multilayer wiring structure, and protective layers 125 and 126. The multilayer structure 110 can serve as a stacked circuit for connection with electronic devices, motherboards, etc.

[0053] The multilayer insulator 112 includes a single insulating layer or multiple stacked insulating layers and provides insulation properties between multilayer wiring structures. The multilayer insulator 112 may include, but is not limited to, a first insulating layer 115, a second insulating layer 116, a third insulating layer 117, and a fourth insulating layer 118.

[0054] One of the insulating layers of the laminated insulator 112 may be a molded layer. For example, the second insulating layer 116 disposed on the upper side of the laminated insulator 112 may be a molded layer, but is not limited thereto.

[0055] Furthermore, one of the insulating layers of the laminated insulator 112 may be a core layer. A third insulating layer 117 disposed at the center of the laminated insulator 112 may be a core layer, but is not limited thereto.

[0056] The core layer ensures the overall mechanical rigidity of the circuit board and suppresses warping. Because it suppresses warping that occurs during manufacturing and product handling, the core layer improves the yield and reliability of the circuit board.

[0057] The core layer may include horizontally extending reinforcing members, such as glass fibers, and resin surrounding the reinforcing members, and its mechanical stiffness can be adjusted according to the density of the reinforcing members. The reinforcing members of the core layer can be disposed within the resin layer in a state of being spaced apart from each other and stacked vertically. According to another embodiment, the core layer may be made of glass. When made of glass, the density of via electrodes penetrating the core layer can be increased, and the spacing between the via electrodes can be easily controlled. Furthermore, due to the higher mechanical stiffness compared to resin containing glass fibers, the circuit board can be made thinner. The core layer is not limited to the above description, and materials that can ensure mechanical stiffness can be freely selected considering factors such as yield and cost.

[0058] The laminated insulator 112 may include an upper laminated insulator disposed on the upper surface of the core layer and a lower laminated insulator disposed on the lower surface of the core layer. For example, the laminated insulator 112 may include a third insulating layer 117 serving as the core layer, a first insulating layer 115 and a second insulating layer 116 serving as the upper laminated insulator disposed on the upper surface of the core layer, and a fourth insulating layer 118 serving as the lower laminated insulator disposed on the lower surface of the core layer.

[0059] The upper and lower stacked insulators are used to set the wiring layers or via electrodes of the stacked wiring structure, ensure insulation between circuits, and control the impedance or insertion loss caused by the circuit, respectively. The upper and lower stacked insulators include an insulating layer containing at least one of thermosetting resin, photocurable resin, and optically isotropic film, taking into account dielectric constant, mechanical rigidity, and processability.

[0060] For example, the insulating layer of the multilayer insulator 112 may be a thermosetting material and may include at least one of Ajinomoto Build-up Film (ABF), epoxy resin, polyimide, phenolic resin, BT (bismaleimide triazine) resin and silicone resin.

[0061] In addition, for example, the insulating layer of the multilayer insulator 112 may be a photocurable material and may contain at least one of photosensitive dielectric (PID) resin, photosensitive polyimide, liquid photosensitive solder resist (LPI), photosensitive epoxy resin and photosensitive acrylic resin.

[0062] For example, photocurable resins can form fine patterns of through-holes or openings through exposure and development processes, eliminating the need for stoppers in cavity formation processes. Furthermore, the content of ceramic particles such as silica (SiO2) in the insulating layer containing the photocurable resin can be higher than that in the insulating layer containing the thermosetting resin, thus allowing for the differentiation of the interface between the photocurable and thermosetting resins. For instance, when performing XPS (X-ray photoelectron spectroscopy) analysis on photocurable resins, relatively high peak values ​​can be detected in both acrylic and epoxy resins. Conversely, when performing XPS analysis on thermosetting resins, peak values ​​can be detected only in epoxy resins.

[0063] Furthermore, the insulating layer of the multilayer insulator 112 may include an optically isotropic film and may contain at least one of COC (cyclic olefin copolymer), COP (cyclic olefin polymer), optically isotropic polycarbonate (PC), and optically isotropic polymethyl methacrylate (PMMA).

[0064] Furthermore, the insulating layer of the multilayer insulator 112 may include a prepreg, thereby having a strength equal to or greater than a predetermined level capable of improving the warpage characteristics of the circuit board. The prepreg constituting the insulating layer may have a structure in which epoxy resin or the like is impregnated into a glass fiber layer existing in the form of a fabric sheet such as glass fabric.

[0065] Next, the multilayer wiring structure of the circuit board 100 includes wiring layers 131 disposed on the surface of corresponding insulating layers and via electrodes 132 for connecting the corresponding wiring layers 131 in the vertical direction. The wiring layers 131 are capable of transmitting signals and / or power to semiconductor devices disposed on the circuit board 100 and are capable of performing impedance matching functions. The wiring layers 131 may be referred to as wiring pattern layers, metal wiring, or wiring portions.

[0066] The via electrode 132 is formed in a through-hole that penetrates the corresponding insulating layer, and the through-hole can be formed by any of machining, laser processing, and chemical processing. When forming the through-hole by machining, methods such as milling, drilling, and contouring can be used. When forming by laser processing, ultraviolet laser or CO2 laser methods can be used, and for chemical processing, chemicals containing aminosilanes, ketones, etc., can be used.

[0067] The via electrode 132 can be formed by forming a through hole that penetrates the insulating layer and filling the interior of the formed through hole with a conductive material.

[0068] When forming a via, the via electrode 132 can be formed by filling the interior of the via with a conductive material. The metallic material forming the via electrode 132 can be at least one material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). Furthermore, the filling with a conductive material can be achieved using any one or a combination of electroless plating, electroplating, screen printing, sputtering, vapor deposition, inkjet printing, and dispensing.

[0069] The multilayer wiring structure can be formed from at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), aluminum (Al), silicon (Si), and zinc (Zn). Furthermore, the multilayer wiring structure can be formed from a paste or solder paste containing at least one metallic material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), said metallic material having excellent bonding strength.

[0070] Next, according to one embodiment, the circuit board includes a wiring layer 131 connected to the via electrode 132.

[0071] Wiring layer 131 includes pads and / or traces (or connection patterns) for connection to via electrodes 132 and / or semiconductor devices and / or capacitors. The traces may be signal wiring connecting multiple pads.

[0072] In this configuration, the pads of wiring layer 131 include bonding pads or connection pads. Connection pads may be mounting pads on which electronic devices or semiconductor chips are mounted, or terminal pads connected to an external substrate. Connection pads are contact portions that contact via electrodes and may include lateral extensions with a horizontal width greater than the trace to ensure alignment allowance.

[0073] The wiring layer 131 can be formed by circuit board manufacturing processes such as additive, subtractive, MSAP (modified semi-additive), and SAP (semi-additive).

[0074] Next, according to one embodiment, the circuit board includes protective layers 125 and 126 disposed on the wiring layer of the uppermost insulating layer or the lowermost insulating layer. For example, protective layers 125 and 126 may include a first protective layer 125 disposed on the second insulating layer 116 and a second protective layer 126 disposed below the fourth insulating layer 118.

[0075] Protective layers 125 and 126 prevent oxidation or delamination of the multilayer structure due to the penetration of moisture and / or external contaminants. Furthermore, the protective layers can be made of materials with low solder wettability to prevent short circuits between adjacent solders when the multilayer structure is connected to electronic devices or a motherboard, thereby preventing bridging short circuits between adjacent solders.

[0076] Protective layers 125 and 126 comprise insulating materials and include various materials capable of being cured by heat or light after coating to protect the surfaces of the insulating layers and wiring layers. Protective layers 125 and 126 may be photoresist layers. For example, protective layers 125 and 126 may be solder resist layers comprising organic polymer materials. As an example, protective layers 125 and 126 comprise epoxy acrylate resins. More specifically, protective layers 125 and 126 comprise resins, curing agents, photoinitiators, pigments, solvents, fillers, additives, acrylic monomers, etc. However, the embodiments are not limited thereto, and protective layers 125 and 126 may be any of photoresist layers, cover films, and polymer materials.

[0077] On the other hand, electronic devices can be disposed in a third insulating layer 117, which serves as the core layer. Furthermore, external devices or substrates can be attached to the multilayer structure 110. Additional multilayers can be disposed between the electronic devices and the external devices or substrates, thus increasing the distance between them, which may lead to signal loss problems during transmission.

[0078] To address the aforementioned problems, in a circuit board 100 according to one embodiment, an electronic device 150 may be disposed in a second insulating layer 116 disposed on a multilayer insulator. For example, in an embodiment including a core layer, the second insulating layer 116 may be disposed on an upper multilayer layer. For ease of description, when the uppermost surface of the upper multilayer layer is provided as the upper surface of the first insulating layer 115, the electronic device 150 may be disposed in the second insulating layer 116 disposed on the first insulating layer 115. The second insulating layer 116 may not include reinforcing members such as glass fibers. Furthermore, the second insulating layer 116 may have a lower reinforcing member content than the first insulating layer 115 and / or the third insulating layer 117. Furthermore, the second insulating layer 116 may be a molded layer, but is not limited thereto.

[0079] Furthermore, a first adhesive layer 157 may be disposed on the upper surface of the first insulating layer 115. The first adhesive layer 157 can fix the mounted electronic device 150 and can buffer the stress applied to the electronic device 150 when mounting external devices or substrates on the multilayer structure 110. The electronic device 150 is disposed in the second insulating layer 116 and may include a first electronic device 150a and a second electronic device 150b spaced apart from each other.

[0080] For now, refer to Figure 2 The electronic device 150 includes a first pad 161 on its upper surface, and a first via electrode 162 may be disposed on the first pad 161. Furthermore, a first pad 163 may be disposed on the first via electrode 162. The first pad 163 is connected to a first connection portion 164, enabling the electronic device 150 to be electrically connected to an external device or substrate.

[0081] According to one embodiment, the circuit board 100 has the following technical effect: since the electronic device 150 is disposed in the second insulating layer 116 of the outermost layer adjacent to the multilayer structure 110, the electrical connection distance with external devices or the board is shortened, thereby preventing signal loss.

[0082] Refer again Figure 1 The embodiment may further include a connecting member 155 disposed in the second insulating layer 116. The connecting member 155 may be configured to overlap with the electronic device 150 in the horizontal direction. The connecting member 155 may be disposed between the first electronic device 150a and the second electronic device 150b.

[0083] The connection member 155 may be a bridging substrate connecting multiple semiconductor devices disposed on the circuit board 100, may be semiconductor devices stacked on a silicon substrate, or may be an organic substrate including an insulating layer, circuit layer, vias, and protective layer formed of the same material provided in the circuit board 100, but is not limited thereto. The connection member 155 may include finer circuitry with a higher density than the multilayer wiring structure of the circuit board 100, and may not only minimize signal transmission loss between chips connected by the connection member 155, but also facilitate signal transmission between semiconductor devices, enabling multiple semiconductor devices to operate as a single semiconductor device. The electronic device 150 and the connection member 155 may be molded from a second insulating layer 116.

[0084] The second-1 pad 166 can be disposed on the upper surface of the connecting member 155. The second via electrode 167 can be disposed on the second-1 pad 166. In addition, the second-2 pad 168 can be disposed on the second via electrode 167. The second-2 pad 168 is connected to the second connection portion 169, so that the connecting member 155 can be electrically connected to an external device or substrate.

[0085] Furthermore, a cylindrical bump 145 connected to the via electrode 132 may be disposed in the second insulating layer 116. The cylindrical bump 145 may overlap with the electronic device 150 and the connecting member 155 in the horizontal direction. Therefore, when another upper circuit board (not shown) is disposed on the semiconductor device and / or circuit board 100, the cylindrical bump 145 facilitates power and / or signal transmission, thereby facilitating the operation of the electronic device 150 and / or the connecting member 155. In addition, a third pad 138 may be disposed on the cylindrical bump 145, and the third pad 138 may be connected to the third connection portion 139.

[0086] Next, Figure 2 yes Figure 1 An enlarged view of region A1 of the circuit board 100 in the embodiment.

[0087] Reference Figure 2 The first protective layer 125 may be disposed on the second insulating layer 116. As described above, since the first protective layer 125 takes into account solder wettability and functions to protect the circuit board 100 from external moisture or contaminants, the first protective layer 125 may not be provided when the second insulating layer 116 performs the above functions. However, although the first protective layer 125 is shown in the embodiment for ease of description, the embodiment is not limited thereto, and the first protective layer 125 may not be provided depending on the function or need of the second insulating layer 116.

[0088] Refer again Figure 2A second insulating layer 116 may be disposed on the first insulating layer 115. A first adhesive layer 157 and a second adhesive layer 159 may be disposed on the upper surface of the first insulating layer 115 to prevent positional displacement during the arrangement of the electronic device 150 and / or the connecting member 155. Furthermore, the electronic device 150 may be disposed on the first adhesive layer 157. A first-1 pad 161 may be disposed on the upper surface of the electronic device 150. Furthermore, a first via electrode 162 may be disposed on the first-1 pad 161. A first-2 pad 163 may be disposed on the first via electrode 162.

[0089] Furthermore, the connecting member 155 may be disposed on the second adhesive layer 159. The second-first pad 166 may be disposed on the upper surface of the connecting member 155. The second via electrode 167 may be disposed on the second-first pad 166. Furthermore, the second-second pad 168 may be disposed on the second via electrode 167.

[0090] Furthermore, the electronic device 150 and the connecting member 155 can be configured to overlap each other in the horizontal direction. By setting the electronic device 150 and the connecting member 155 to have the same height on the upper side of the circuit board 100 relative to the bottom surface of the laminated structure, the integrity of signal and / or power transmission of the circuit board 100 can be improved. Additionally, for insulation purposes, the thickness of the electronic device 150 and the connecting member 155 can be less than the thickness of the second insulating layer 116.

[0091] Meanwhile, the horizontal width of the first width W1 of the first via electrode 162 connected to the electronic device 150 and the horizontal width of the second width W2 of the second via electrode 167 connected to the connecting member 155 can be different from each other. More specifically, the first width W1 of the first via electrode 162 can be greater than the second width W2 of the second via electrode 167. Therefore, this embodiment has the following technical effects: by differentially controlling the horizontal width of the via electrodes of the electronic device and the connecting member, signal transmission with external chips respectively connected thereto can be controlled, and connectivity with external terminals can be improved.

[0092] Furthermore, to ensure alignment allowance, the horizontal width of the first-1 pad 161 connected to the first via electrode 162 may differ from the horizontal width of the second-1 pad 166 connected to the second via electrode 167. Similarly, the horizontal width of the first-2 pad 163 connected to the first via electrode 162 may differ from the horizontal width of the second-2 pad 168 connected to the second via electrode 167. The horizontal width of the first-2 pad 163 may be greater than the horizontal width of the second-2 pad 168.

[0093] The height of the upper surface of the first via electrode 162 can be the same as the height of the upper surface of the second insulating layer 116. Furthermore, the height of the upper surface of the second via electrode 167 can be the same as the height of the upper surface of the second insulating layer 116. The height of the upper surface of the first via electrode 162 can be the same as the height of the upper surface of the second via electrode 167.

[0094] Furthermore, the first-second pad 163 and the second-second pad 168 can be disposed on the upper surface of the second insulating layer 116. The height of the lower surface of the first-second pad 163 and the second-second pad 168 can be the same as the height of the upper surface of the second insulating layer 116.

[0095] For ease of description, height should be understood as referring to the length of the lower surface of the reference layered structure in the vertical direction.

[0096] Furthermore, a cylindrical bump 145 may be disposed in the second insulating layer 116. The cylindrical bump 145 may include, but is not limited to, copper. The cylindrical bump 145 may overlap with the electronic device 150 and the connecting member 155 in the horizontal direction. The height of the upper surface of the cylindrical bump 145 may be the same as the height of the upper surface of the second insulating layer 116. The cylindrical bump 145 may serve as a channel for electrically connecting the multilayer wiring structure to external devices or substrates. A third pad 138 may be disposed on the cylindrical bump 145, and the third pad 138 may be disposed on the upper surface of the second insulating layer 116.

[0097] Meanwhile, the third width W3 of the cylindrical bump 145 in the horizontal direction can be greater than the first width W1 of the first via electrode 162 of the electronic device 150. In addition, the third width W3 of the cylindrical bump 145 in the horizontal direction can be greater than the second width W2 of the second via electrode 167 of the connecting member 155.

[0098] Furthermore, the third width W3 of the cylindrical bump 145 can be greater than the sum of the first width W1 of the first via electrode 162 of the electronic device 150 and the second width W2 of the second via electrode 167 of the connecting member 155. Considering ensuring the integrity of signal and / or power transmission, mechanical rigidity, and stress with the stacked structure, the cylindrical bump 145 can be configured to have the aforementioned horizontal width.

[0099] Next, Figure 3 This is a cross-sectional view of the circuit board 101 according to the second embodiment. The technical features of the first embodiment can be applied to the second embodiment. For example, in the second embodiment, the horizontal width of the first via electrode 162 disposed on the electronic device 150 may be different from the horizontal width of the second via electrode 167 disposed on the connecting member 155 with a high-density fine pattern.

[0100] Subsequently, referring to Figure 3 The laminated insulator 112 may include a first insulating layer 115c, a third insulating layer 115b, and a fourth insulating layer 115a disposed sequentially from top to bottom. Furthermore, a second insulating layer 116 may be disposed on the first insulating layer 115c, and the first insulating layer 115c may contact the second insulating layer 116.

[0101] Furthermore, the multilayer insulator 112 may include a trench region 115T on its upper surface. The trench region 115T can penetrate at least a portion of the multilayer insulator from its upper surface toward its lower surface. In this embodiment, the trench region 115T is illustrated as penetrating the first insulating layer 115c, but is not limited thereto; it may be formed to penetrate portions of the first insulating layer 115c and the third insulating layer 115b, or only penetrate a portion of the first insulating layer 115c.

[0102] According to this embodiment, the trench region 115T can be formed on the upper surface of the multilayer insulator, and the second insulating layer 116 can be configured to fill the trench region 115T. Accordingly, the second insulating layer 116 may include a horizontal portion 116-1 disposed on the first insulating layer 115c and a protrusion 116-2 overlapping the first insulating layer 115c in the horizontal direction. There may be multiple protrusions 116-2, which may be spaced apart from each other. The protrusions 116-2 of the second insulating layer 116 may be disposed within the trench region 115T of the multilayer insulator 112.

[0103] Furthermore, the electronic device 150 can be disposed within the trench region 115T. Additionally, the connecting member 155 can be disposed within the horizontal portion 116-1 of the second insulating layer 116. Furthermore, the connecting member 155 can be disposed on the first insulating layer 115c. The electronic device 150 can be configured to overlap with the first insulating layer 115c in the horizontal direction. The electronic device 150 can also be configured not to overlap with the first insulating layer 115c in the vertical direction. Accordingly, the second embodiment has the following technical effect: since the electronic device 150 is disposed within the trench region 115T, the thickness of the second insulating layer 116 covering the electronic device 150 can be reduced, thereby reducing the thickness of the laminated structure 110.

[0104] Furthermore, the cylindrical bump 145 can be configured to overlap with the first insulating layer 115c in the vertical direction. When the thickness of the second insulating layer 116 covering the electronic device 150 decreases, the thickness of the cylindrical bump 145 can also be reduced. Accordingly, the second embodiment has the following technical advantages: since the electronic device 150 is disposed within the trench region 115T, the thickness of the cylindrical bump 145 can be reduced, and signal transmission loss can be prevented.

[0105] Furthermore, the second embodiment has the following technical effects: since the electronic device 150 is disposed in the trench region 115T, even if the thickness of the electronic device 150 increases, the electronic device 150 can still be covered by the second insulating layer 116, thereby improving the degree of freedom of the chip.

[0106] Figure 4 This is a cross-sectional view of the circuit board 102 according to the third embodiment.

[0107] Reference Figure 4 The third embodiment may further include a fifth insulating layer 119 disposed on the second insulating layer 116. The fifth insulating layer 119 may be disposed between the second insulating layer 116 and the first protective layer 125. The fifth insulating layer 119 may include a first-1 via electrode 162-1 disposed on the first via electrode 162. The horizontal width of the first-1 via electrode 162-1 may be the same as the horizontal width of the first via electrode 162, but is not limited thereto. Furthermore, the fifth insulating layer 119 may include a second-1 via electrode 167-1 disposed on the second via electrode 167. The horizontal width of the second-1 via electrode 167-1 may be the same as the horizontal width of the second via electrode 167, but is not limited thereto.

[0108] Meanwhile, the fifth insulating layer 119 can have a higher density of reinforcing members than the second insulating layer 116. Furthermore, the thickness of the fifth insulating layer 119 can be less than the thickness of the second insulating layer 116. Accordingly, the third embodiment has the following technical effect: since the fifth insulating layer 119, including more reinforcing members, is disposed on the second insulating layer 116 on which electronic devices are disposed, warping that may occur on the upper surface of the laminated structure 110 can be prevented.

[0109] Furthermore, although the fifth insulating layer 119 is in Figure 4 The diagram shows a single layer, but the fifth insulating layer 119 may include multiple insulating layers. The multiple insulating layers of the fifth insulating layer 119 may include multiple wiring structures, and the multiple wiring structures may be electrically connected to at least one of the first-1 via electrode 162-1, the second-1 via electrode 167-1, and the cylindrical bump 145.

[0110] Refer again Figure 2The horizontal widths of the second-1 pad 166 and the second via electrode 167 disposed on the connecting member are different from the horizontal widths of the first-1 pad 161 and the first via electrode 162 disposed on the electronic device. Therefore, due to differences in the magnitude of the current applied during the electroplating process or differences in process conditions such as the amount of electroplating solution penetration, the upper surfaces of the first-2 pad 163 and the second-2 pad 168 may have different thicknesses. As described above, when a semiconductor device is mounted on pads with different thicknesses, a problem of reduced connection reliability between the semiconductor device and the circuit board 100 may occur. To prevent this problem, such as... Figure 4 As shown, a fifth insulating layer 119 can be stacked to prevent electroplating deviation problems.

[0111] When the width of the second via electrode 167 disposed on the connecting member is smaller than the width of the first via electrode 162 disposed on the electronic device, the second-2 pad 168 disposed on the lower surface of the fifth insulating layer 119 can extend horizontally to achieve a second-1 via electrode 167-1 having the same width as the via disposed on the electronic device. Here, the same width refers to a width where the plating deviation is smaller, and when the plating deviation does not cause torsion during semiconductor device mounting, the widths between vias can be designed to be somewhat different from each other.

[0112] Figure 5 This is a cross-sectional view of a semiconductor package 103 according to one embodiment.

[0113] This embodiment may include having Figure 1 The circuit substrate 100 of the multilayer structure 110 serves as a semiconductor package 103, but is not limited thereto, and may also include... Figure 3 or Figure 4 The circuit board shown.

[0114] Reference Figure 5 According to this embodiment, the semiconductor package 103 may include first-second pads 163 disposed on the lower surface of the electronic device 150, and a first connection portion 164 may be disposed on the first-second pads 163. Furthermore, a second-second pad 168 may be disposed on the connecting member 155, and a second connection portion 169 may be disposed on the second-second pad 168. Additionally, a third pad 138 may be disposed on the cylindrical bump 145, and a third connection portion 139 may be disposed on the third pad 138. The first connection portion 164, the second connection portion 169, and the third connection portion 139 may have a spherical shape. For example, the cross-section of the first connection portion 164, the second connection portion 169, and the third connection portion 139 may have a circular or semi-circular shape. The first connection portion 164, the second connection portion 169, and the third connection portion 139 may be solder balls, but are not limited thereto.

[0115] Furthermore, the circuit board may also include bonding portions on the first protective layer 125. The bonding portions may be disposed on the upper surface of the first protective layer 125 for thermo-press bonding with a semiconductor device, and may be used when the spacing of the first-second pads 163 of the semiconductor device becomes fine and difficult to achieve by conventional soldering. The semiconductor package 103 according to this embodiment may include a chip 200 or a device 200 disposed on the multilayer structure 110. The chip 200 may be a processor chip. For example, the chip 200 may be an application processor (AP) chip, including any one of a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller. The lower surface of the chip 200 may include terminals 205, and multiple terminals 205 may be provided. For example, terminals 205 may include a first terminal 205a, a second terminal 205b, a third terminal 205c, and a fourth terminal 205d. The first terminal 205a may be electrically connected to the second-second pad 168 of the multilayer structure 110 via a first connection portion 164. Furthermore, the second terminal 205b can be electrically connected to the second-second pad 168 via the second connection portion 169. Furthermore, the third terminal 205c can be electrically connected to the first-second pad 163 via the first connection portion 164. Furthermore, the fourth terminal 205d can be electrically connected to the third pad 138 via the third connection portion 139.

[0116] Meanwhile, the semiconductor package 103 according to this embodiment may include a plurality of chips disposed on a circuit substrate and spaced apart from each other in the horizontal direction. For example, chip 200 may include a first chip 201 and a second chip 202. The first chip 201 and the second chip 202 may be application processor (AP) chips of different types. Accordingly, a plurality of second-second pads 168 of the connection member 155 may be connected to the first chip 201 and the second chip 202 respectively to electrically connect the first chip 201 and the second chip 202.

[0117] Furthermore, the semiconductor package 103 according to this embodiment may further include a connection portion disposed on the lower surface of the fourth wiring layer 131-4, and the connection portion may be used for coupling with the motherboard (or motherboard) of an external device.

[0118] (Semiconductor packaging)

[0119] A semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package includes a motherboard (not shown). The motherboard may be physically and / or electrically connected to various components. For example, the motherboard may be electrically connected to the circuit board according to an embodiment. Various devices may be mounted on the circuit board.

[0120] For example, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM) and flash memory, application processor chips such as central processing units (e.g., CPU), graphics processing units (e.g., GPU), antenna chips, digital signal processors, encryption processors, microprocessors and microcontrollers, and logic chips such as analog-to-digital converters and ASICs (Application-Specific Integrated Circuits) can be mounted on a circuit board.

[0121] For example, at least one of various types of passive and active devices can be mounted on the circuit board.

[0122] In this context, the semiconductor package can be a smartphone, personal digital assistant, digital camcorder, digital camera, network system, computer, display, tablet computer, laptop computer, netbook, television, video game device, smartwatch, or automotive device. However, this embodiment is not limited to these; it can certainly be any other electronic device that processes data.

[0123] Furthermore, when a circuit board with the above-described features is used in IT equipment or home appliances such as smartphones, server computers, or televisions, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board with the features of this disclosure performs a semiconductor packaging function, it can safely protect the semiconductor chip from external moisture or contaminants, and can solve problems such as leakage current, electrical short circuits between terminals, or electrical open circuits at the terminals supplying power to the semiconductor chip. In addition, when performing a signal transmission function, it can solve noise problems. Therefore, a circuit board with the above-described features can maintain the stable function of IT equipment or home appliances, enabling the entire product and the circuit board using this disclosure to achieve functional integrity or technical interoperability.

[0124] When a circuit board with the above-described features is used in transportation equipment such as vehicles, signal distortion transmitted to the transportation equipment can be resolved, or the semiconductor chips controlling the transportation equipment can be safely protected from external influences. Furthermore, by addressing issues such as leakage current, electrical short circuits between terminals, or electrical open circuits at terminals supplying power to the semiconductor chips, the stability of the transportation equipment can be further improved. Accordingly, the transportation equipment and the circuit board using this disclosure can achieve functional integrity or technical interoperability.

[0125] Industrial applicability

[0126] The circuit board or semiconductor package according to this embodiment can be applied to any one of CSP (chip-scale package), FC-CSP (flip-chip-chip-scale package), FC-BGA (flip-chip ball grid array), POP (package stack-up), and SIP (system-in-package).

[0127] In addition, circuit boards or semiconductor packages can be used in smartphones, personal digital assistants, digital camcorders, digital cameras, vehicles, high-performance servers, network systems, computers, monitors, tablets, laptops, netbooks, televisions, video game devices, smartwatches, or automotive devices, but are not limited to these.

[0128] The features, structures, effects, etc., described in the above embodiments are included in at least one embodiment of this disclosure, and are not necessarily limited to only one embodiment. Furthermore, the various features, structures, effects, etc., illustrated in the embodiments can be combined or modified by those skilled in the art for use in other embodiments. Therefore, matters relating to such combinations and modifications should be understood to be included within the scope of this application.

[0129] The foregoing has primarily described embodiments, but these are merely examples and do not limit the scope of this disclosure. Those skilled in the art will understand that various modifications and applications, not specifically illustrated above, can be made without departing from the essential characteristics of the embodiments. For example, modifications and implementations can be made to each component specifically shown in the embodiments. Differences related to these modifications and applications should be understood to be included within the scope defined by the appended claims.

Claims

1. A circuit board, comprising: A first insulating layer and a second insulating layer disposed on the first insulating layer; One or more electronic devices disposed in the second insulating layer; A connecting member that overlaps with the electronic device in the horizontal direction and is disposed in the second insulating layer; A first via electrode is disposed in the second insulating layer and on the electronic device; as well as A second via electrode is disposed in the second insulating layer and on the connecting member. The horizontal width of the first via electrode is different from the horizontal width of the second via electrode.

2. The circuit board according to claim 1, in, The horizontal width of the first via electrode is greater than the horizontal width of the second via electrode.

3. The circuit board according to claim 1, in, The height of the upper surface of the first via electrode is the same as the height of the upper surface of the second insulating layer.

4. The circuit board according to claim 1, in, The content of reinforcing members in the second insulating layer is less than the content of reinforcing members in the first insulating layer.

5. The circuit board according to claim 1, in, The first insulating layer includes a trench region on its upper surface. The second insulating layer further includes a protrusion that overlaps with the first insulating layer in the horizontal direction and is disposed in a portion of the trench region, and The electronic device is disposed in another region of the trench region.

6. The circuit board according to claim 1, further comprising: A protective layer disposed on the second insulating layer and in contact with the first via electrode.

7. The circuit board according to claim 6, further comprising: A third insulating layer is disposed between the second insulating layer and the protective layer. The content of reinforcing members in the third insulating layer is greater than the content of reinforcing members in the second insulating layer.

8. The circuit board according to claim 1, further comprising: A cylindrical bump disposed in the second insulating layer and overlapping the electronic device in the horizontal direction.

9. The circuit board according to claim 8, in, The sum of the horizontal width of the first via electrode and the horizontal width of the second via electrode is less than the horizontal width of the cylindrical bump.

10. A semiconductor package, comprising: The circuit board according to any one of claims 1 to 9.

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