Three-dimensional memory device and its fabrication method

Abstract

A three-dimensional (3D) memory device and its fabrication method are disclosed. One disclosed semiconductor device includes: a stacked structure comprising an array region and a contact region, and a gate slot structure extending vertically through the stacked structure and laterally along a first lateral direction to divide the stacked structure into memory blocks. The gate slot structure includes: a first dummy channel structure located at the boundary between the array region and the contact region, a first gate slot portion extending laterally from the first dummy channel structure into the array region, and a second gate slot portion extending laterally from the first dummy channel structure into the contact region.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology, and more specifically to three-dimensional (3D) memory devices and methods for fabricating three-dimensional (3D) memory devices. Background Technology

[0002] Planar memory cells can be scaled to smaller sizes through improvements in process technology, circuit design, programming algorithms, and fabrication techniques. However, planar processes and fabrication technologies become challenging and costly as the feature size of memory cells approaches its lower limit. Similarly, the storage density of planar memory cells is approaching its upper limit. Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells.

[0003] With advancements in semiconductor technology, 3D memory devices, such as 3D NAND flash memory, are continuously scaling up to more film layers to improve wafer area utilization. In some existing 3D NAND flash memory devices, due to the increased number of film layers and their more complex structures, the silicon substrate used as the film layer carrier may not be able to support wafer warping caused by film stress, potentially leading to curved wafers. Furthermore, the increased number of oxide / nitride (ON) layers results in a corresponding increase in the etch depth of the gate gap (GLS), altering the critical size of the GLS and increasing the risk of unstable structures due to stress and other factors. Such unstable structures can lead to memory finger bending / collapse, wafer bowing, and affect subsequent 3D memory device fabrication processes, such as increasing overlay errors in photolithography alignment processes. Summary of the Invention

[0004] One aspect of this disclosure provides a semiconductor device comprising: a stacked structure including an array region and a contact region located on one side of the array region in a first lateral direction; and a gate gap (GLS) structure extending vertically through the stacked structure and laterally along the first lateral direction. The GLS structure includes: a dielectric structure extending vertically through the stacked structure and located at the boundary between the array region and the contact region; a first GLS structure portion extending laterally from the dielectric structure along the first lateral direction to the contact region; and a second GLS structure portion extending laterally from the dielectric structure along the first lateral direction to the array region, wherein the dielectric structure separates the first GLS structure portion from the second GLS structure portion, and a first dimension of the dielectric structure in the first lateral direction is smaller than a second dimension of the dielectric structure in a second lateral direction perpendicular to the first lateral direction.

[0005] In some embodiments, the first GLS structure portion includes a first filler wall sandwiched between the first spacer layers along a second lateral direction; and the second GLS structure portion includes a second filler wall sandwiched between the second spacer layers along a second lateral direction.

[0006] In some embodiments, the dielectric structure is a single oxide layer having a first dimension in a first lateral direction that is greater than the sum of a first thickness of a first spacer layer in a second lateral direction and a second thickness of a second spacer layer in a second lateral direction.

[0007] In some embodiments, the dielectric structure is a composite structure comprising: an intermediate sublayer having a first material; a first spacer sublayer between the intermediate sublayer and a first GLS structure portion, having a second material different from the first material but the same as the first spacer layer of the first GLS structure portion; and a second spacer sublayer between the intermediate sublayer and a second GLS structure portion, having a third material different from the first material but the same as the second spacer layer of the second GLS structure portion.

[0008] In some embodiments, the first material is an oxide material; and the second and third materials are the same and are deposited on both sides of the intermediate sublayer in the first lateral direction.

[0009] In some implementations, the intermediate sublayer has a curved wall structure.

[0010] In some implementations, the curved wall structure protrudes toward the second GLS structure portion.

[0011] In some embodiments, the sidewalls of the first GLS structural portion and the second GLS structural portion in the second transverse direction include curved surfaces.

[0012] In some embodiments, each of the first and second filling walls includes an upper portion and a lower portion, wherein the upper portion has a larger dimension along the second transverse direction than the lower portion.

[0013] In some embodiments, the lower portion of the first filling wall includes a protrusion of a lateral surface and a bottom surface, each surrounded by a first spacer layer from all lateral and bottom directions; and the lower portion of the second filling wall includes a protrusion of a lateral surface and a bottom surface, each surrounded by a second spacer layer from all lateral and bottom directions.

[0014] In some embodiments, the first height of the first protrusion of the first filling wall in the vertical direction is greater than the second height of the second protrusion of the second filling wall in the vertical direction.

[0015] In some embodiments, the semiconductor device further includes a semiconductor layer located between the stacked structure and the substrate. The top surface of the semiconductor layer is lower than the bottom surface of the upper portion of the first filler wall, and the bottom surface of the semiconductor layer is higher than the bottom surface of the upper portion of the second filler wall.

[0016] In some embodiments, the first protrusion and the second protrusion extend vertically into the upper part of the substrate.

[0017] In some embodiments, the semiconductor layer in the contact region includes: an end extending into the second spacer layer; and a separated portion between the first protrusions, each having a lateral surface, a bottom surface, and a top surface surrounded by the first spacer layer in all lateral, bottom, and top directions.

[0018] In some implementations, the first dimension is in the range of about 30 nm to about 200 nm, and the second dimension is in the range of about 500 nm to about 1000 nm.

[0019] In some embodiments, the semiconductor device further includes: a channel structure, each extending vertically through the stacked structure and located in the array region; and a dummy channel structure, each extending vertically through the stacked structure and located in the contact region.

[0020] In some embodiments, the stacked structure in the array region includes a conductive layer and a first dielectric layer that are alternately stacked in the vertical direction, and the stacked structure in the contact region includes: a first stack portion adjacent to the first GLS structure portion and including a conductive layer and a first dielectric layer that are alternately stacked in the vertical direction, and a second stack portion separated from the first GLS structure portion by the first stack portion and including a first dielectric layer and a second dielectric layer that are alternately stacked in the vertical direction.

[0021] In some implementations, a first semiconductor structure, including a stacked structure and a GLS structure, is bonded to a second semiconductor structure including peripheral circuitry.

[0022] Another aspect of this disclosure provides a method for forming a semiconductor device, the method comprising: forming a stacked structure including an array region and a contact region located on one side of the array region in a first lateral direction; and forming a gate gap (GLS) structure extending vertically through the stacked structure and laterally along the first lateral direction. Forming the GLS structure includes: forming a dielectric structure extending vertically through the stacked structure and located at the boundary between the array region and the contact region; forming a first GLS structure portion extending laterally from the dielectric structure along the first lateral direction to the contact region; and forming a second GLS structure portion extending laterally from the dielectric structure along the first lateral direction to the array region, wherein the dielectric structure separates the first GLS structure portion from the second GLS structure portion, and a first dimension of the dielectric structure in the first lateral direction is smaller than a second dimension of the dielectric structure in a second lateral direction perpendicular to the first lateral direction.

[0023] In some embodiments, forming a stacked structure includes: forming an insulating layer on a substrate; forming a semiconductor layer on the insulating layer; forming a first dielectric layer and a second dielectric layer that are alternately stacked in a vertical direction on the semiconductor layer; and forming an array of first through holes in a contact region and an array of second through holes in an array region, wherein each first through hole and each second through hole extends vertically through the stacked structure into the substrate.

[0024] In some embodiments, forming a GLS structure includes: forming a first trench extending in a first lateral direction by etching a row of an array of first through holes; removing a portion of a second dielectric layer at a contact region through the first trench to form a first gap; filling the first trench and the first gap with a sacrificial material; forming a second trench extending in the first lateral direction by etching a row of a second through hole; removing a portion of a second dielectric layer at an array region through the second trench to form a second gap; removing sacrificial material from the first trench and the first gap; filling the first gap and the second gap with a conductive material; and forming a first GLS structure portion in the first trench and a second GLS structure portion in the second trench.

[0025] In some embodiments, after forming the first trench, the method further includes: widening the first trench by removing portions of the first dielectric layer and the second dielectric layer exposed by the first trench; and oxidizing the semiconductor layer and substrate exposed by the widened first trench.

[0026] In some embodiments, after forming the second trench, the method further includes: enlarging the second trench by removing portions of the first dielectric layer and the second dielectric layer exposed by the second trench; removing portions of the semiconductor layer and the sacrificial material exposed by the enlarged second trench; and oxidizing the side surfaces of the sacrificial material in the first trench to form an intermediate sublayer composed of a first material, wherein the side surfaces of the sacrificial material in the first trench are exposed by the enlarged second trench.

[0027] In some embodiments, filling the first trench and the first gap with a sacrificial material includes filling the first trench and the first gap with a sacrificial semiconductor material.

[0028] In some embodiments, forming an intermediate sublayer includes forming an intermediate sublayer having a curved wall structure, wherein the curved wall structure protrudes toward the second GLS structure portion.

[0029] In some embodiments, the method further includes depositing a second material on both sides of the intermediate sublayer.

[0030] In some embodiments, forming a first GLS structure portion in a first trench and forming a second GLS structure portion in a second trench includes: depositing a first spacer sublayer on the inner wall of the first trench; depositing a second spacer sublayer on the inner wall of the second trench; and filling the first trench and the second trench with a filler material.

[0031] In some embodiments, filling the first trench and the second trench with a filler material includes filling the first trench and the second trench with a conductive material.

[0032] In some embodiments, the method further includes forming a dummy channel structure in other first through holes and forming a channel structure in other second through holes.

[0033] Another aspect of this disclosure provides a memory device comprising: a memory array; and peripheral circuitry disposed on at least one side of the memory array. The memory array includes: a stacked structure comprising an array region and a contact region located on one side of the array region in a first lateral direction; and a gate slot (GLS) structure extending vertically through the stacked structure and laterally along the first lateral direction. The GLS structure includes: a dielectric structure extending vertically through the stacked structure and located at the boundary between the array region and the contact region; a first GLS structure portion extending laterally from the dielectric structure along the first lateral direction to the contact region; and a second GLS structure portion extending laterally from the dielectric structure along the first lateral direction to the array region, wherein the dielectric structure separates the first GLS structure portion from the second GLS structure portion, and a first dimension of the dielectric structure in the first lateral direction is smaller than a second dimension of the dielectric structure in a second lateral direction perpendicular to the first lateral direction.

[0034] In some implementations, the peripheral circuitry is electrically connected to the memory array via conductive interconnects formed in the contact area.

[0035] In some implementations, peripheral circuitry is disposed on both sides of the memory array, symmetrically positioned relative to the array region, and connected by lateral interconnects extending along a first lateral direction.

[0036] Other aspects of this disclosure may be understood by those skilled in the art based on the description, claims, and drawings of this disclosure. Attached Figure Description

[0037] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the specification, explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0038] Figure 1 A block diagram of a system having a memory device according to some aspects of this disclosure is shown.

[0039] Figure 2A A schematic diagram of a memory card having a memory device according to some embodiments is shown.

[0040] Figure 2B A schematic diagram of a solid-state drive (SSD) with memory is shown according to some embodiments.

[0041] Figure 3 A top view of a 3D memory device according to some embodiments of the present disclosure is shown.

[0042] Figure 4 A perspective view of a portion of a 3D storage array structure according to some embodiments of the present disclosure is shown.

[0043] Figure 5A A top perspective view of a portion of a 3D storage array structure according to some embodiments of the present disclosure is shown.

[0044] Figure 5B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 5A A schematic diagram of the cross-sectional side view of line AA' shown.

[0045] Figure 5B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 5A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0046] Figure 5B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 5A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0047] Figure 5C A top perspective view of a portion of a 3D storage array structure according to some embodiments of the present disclosure is shown.

[0048] Figure 5D A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 5C A schematic diagram of the cross-sectional side view of the CC' line shown.

[0049] Figure 6 A flowchart of a method for forming a 3D memory device according to some embodiments of the present disclosure is shown.

[0050] Figure 7A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0051] Figure 7B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7A A schematic diagram of the cross-sectional side view of line AA' shown.

[0052] Figure 7B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0053] Figure 7B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0054] Figure 7C Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0055] Figure 7D1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7C A schematic diagram of the cross-sectional side view of line AA' shown.

[0056] Figure 7D2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7C A schematic diagram of the cross-sectional side view of the BB' line shown.

[0057] Figure 7D3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7C A schematic diagram of the cross-sectional side view of the CC' line shown.

[0058] Figure 8A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0059] Figure 8B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 8A A schematic diagram of the cross-sectional side view of line AA' shown.

[0060] Figure 8B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 8A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0061] Figure 8B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 8A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0062] Figure 9A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0063] Figure 9B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 9A A schematic diagram of the cross-sectional side view of line AA' shown.

[0064] Figure 9B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 9A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0065] Figure 9B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 9A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0066] Figure 10A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0067] Figure 10B1A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 10A A schematic diagram of the cross-sectional side view of line AA' shown.

[0068] Figure 10B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 10A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0069] Figure 10B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 10A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0070] Figure 11A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0071] Figure 11B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 11A A schematic diagram of the cross-sectional side view of line AA' shown.

[0072] Figure 11B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 11A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0073] Figure 11B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 11A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0074] Figure 12A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0075] Figure 12B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 12A A schematic diagram of the cross-sectional side view of line AA' shown.

[0076] Figure 12B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 12A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0077] Figure 12B3A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 12A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0078] Figures 13A1 to 13A3 A schematic diagram of a 3D structure according to some embodiments of the present disclosure is shown in a cross-sectional side view.

[0079] Figure 14A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0080] Figure 14B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 14A A schematic diagram of the cross-sectional side view of line AA' shown.

[0081] Figure 14B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 14A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0082] Figure 14B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 14A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0083] Figure 15A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0084] Figure 15B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 15A A schematic diagram of the cross-sectional side view of line AA' shown.

[0085] Figure 15B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 15A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0086] Figure 15B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 15A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0087] Figures 16A1 to 16A3 A schematic diagram of a 3D structure according to some embodiments of the present disclosure is shown in a cross-sectional side view.

[0088] Figure 17A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0089] Figure 17B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 17A A schematic diagram of the cross-sectional side view of line AA' shown.

[0090] Figure 17B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 17A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0091] Figure 17B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 17A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0092] Figure 18A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0093] Figure 18B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 18A A schematic diagram of the cross-sectional side view of line AA' shown.

[0094] Figure 18B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 18A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0095] Figure 18B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 18A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0096] Figure 19A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0097] Figure 19B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 19A A schematic diagram of the cross-sectional side view of line AA' shown.

[0098] Figure 19B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 19A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0099] Figure 19B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 19A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0100] Figure 20A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0101] Figure 20B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 20A A schematic diagram of the cross-sectional side view of line AA' shown.

[0102] Figure 20B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 20A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0103] Figure 20B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 20A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0104] Figure 21A Some embodiments of the present disclosure are shown. Figure 6 A schematic diagram of a portion of the 3D memory device at a specific manufacturing stage in the method shown, in a top perspective view.

[0105] Figure 21B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 21A A schematic diagram of the cross-sectional side view of line AA' shown.

[0106] Figure 21B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 21A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0107] Figure 21B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 21A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0108] Figure 22AA schematic diagram of a portion of a 3D memory according to some embodiments of the present disclosure is shown in a top perspective view.

[0109] Figure 22B A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 22A A schematic diagram of the cross-sectional side view of line AA' shown.

[0110] Embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0111] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0112] It should be noted that references to "one embodiment," "implementation," "example embodiment," "some embodiments," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly stated or not, incorporating other embodiments to affect such feature, structure, or characteristic will be within the understanding of those skilled in the art.

[0113] Generally, terms can be understood at least in part from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as “a,” “an,” or “described” can again be understood to convey either a singular or a plural usage.

[0114] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest manner, such that “on” means not only “directly on” but also includes “on” with intermediate features or layers, and that “above” or “on top of” means not only “above” or “on top of” but also includes “above” or “on top of” without intermediate features or layers (i.e., directly on).

[0115] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or feature as shown in the figure and one or more other elements or features. In addition to the orientations shown in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein will be interpreted accordingly.

[0116] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0117] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a range smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of transverse planes at the top and bottom surfaces of a continuous structure. A layer may extend laterally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where contacts, interconnects, and / or vias are formed) and one or more dielectric layers.

[0118] As used herein, the term "nominal / nominal value" refers to the expected or target value of a characteristic or parameter of a component or process operation set during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. The range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0119] As used herein, the term "3D memory device" refers to a semiconductor device having vertically oriented strings of memory cell transistors (i.e., regions referred to herein as "memory strings," such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate. As used herein, the term "vertical" refers to a surface nominally perpendicular to the lateral surface of the substrate.

[0120] Figure 1 A block diagram of a system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or it may be a system-on-a-chip (SoC), such as an application processor (AP). The host 108 may be configured to send data to or receive data from the memory device 104.

[0121] Memory device 104 can be any memory device disclosed herein, such as a NAND flash memory device. Consistent with the scope of this disclosure, memory controller 106 can control multi-pass programming on memory device 104 such that NGS operation is enabled on all memory cells during non-last programming passes, even those memory cells that have passed the corresponding verification operation. Peripheral circuitry, such as word line drivers, can apply a low voltage, such as ground (GND), to the DSG of each memory string coupled to the selected word line, and can apply a low or negative voltage to the selected word line to enable NGS operation on all memory cells coupled to the selected word line during non-last programming passes.

[0122] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMC), as data storage devices for mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 106 can be configured to control the operation of memory device 104, such as read, erase, and program operations. Memory controller 106 can also be configured to manage various functions regarding data stored or to be stored in memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 106 is also configured to process error correction codes (ECC) for data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable function, such as programming the memory device 104. The memory controller 106 may communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with an external device via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0123] The memory controller 106 and one or more memory devices 104 can be integrated into various types of memory devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2AIn one example shown, the memory controller 206 and a single memory device 204 can be integrated into the memory card 202. The memory card 202 can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 208 is coupled to the host 108. In such a... Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 can be integrated into the SSD 210. The SSD 210 may also include a connection between the SSD 210 and a host (e.g., Figure 1 The SSD connector 218 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 210 is greater than the storage capacity and / or operating speed of the memory card 202.

[0124] Figure 3 A top view of a 3D memory device 300 according to some embodiments of the present disclosure is shown. The 3D memory device 300 may be a memory chip (package), a memory chip, or any part of a memory chip, and may include one or more memory surfaces 301, each of which may include a plurality of memory blocks 303. Identical and concurrent operations may occur at each memory surface 301. A memory block 303, which may be megabyte (MB) in size, may be the smallest unit for performing an erase operation. Figure 3 As shown, the 3D memory device includes four storage surfaces 301, and each storage surface 301 includes six memory blocks 303. Each memory block 303 may include multiple memory cells, wherein each memory cell can be addressed via interconnects such as bit lines and word lines. The bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively) to form an array of metal lines. Figure 3 In this disclosure, the direction of the word lines is referred to herein as the first lateral direction and is denoted as the X direction, and the direction of the bit lines is referred to herein as the second lateral direction and is denoted as the Y direction. In this disclosure, memory block 303 is also referred to as a "memory array" or "array". A memory array is a core area in a memory device that performs memory functions.

[0125] The 3D memory device 300 may include a peripheral region 305, which is the area surrounding the memory surface 301. The peripheral region 305 may accommodate multiple digital, analog, and / or mixed-signal circuits to support the functions of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., which will be apparent to those skilled in the art. It should be noted that... Figure 3 The arrangement of storage surfaces 301 in the 3D memory device 300 shown and the arrangement of storage blocks 303 in each storage surface 301 are provided as examples only and do not limit the scope of this disclosure.

[0126] Figure 4 A perspective view of a portion of a 3D memory array structure 400 according to some embodiments of the present disclosure is shown. The memory array structure 400 includes: a substrate 430, an insulating film 431 over the substrate 430, one or more layers of bottom select gates (BSGs) 432 over the insulating film 431, and multiple layers of control gates 433 (also referred to as “word lines (WLs)”) stacked on top of the BSGs 432 to form a stacked structure 435 of alternating conductive and dielectric layers. For clarity, the dielectric layers adjacent to the layers of the control gates are not shown on the substrate. Figure 4 As shown in the image.

[0127] Each level of control gate 433 is separated by slot structures 416-1 and 416-2 passing through the stacked structure 435. The memory array structure 400 may include one or more top select gates (TSGs) 434 above the stacked body of control gates 433. The stacked body of TSG 434, control gates 433, and BSG 432 is also referred to as a “gate structure”. The memory array structure 400 also includes doped source pole regions 444 in the portions of memory strings 412 and substrate 430 between adjacent BSGs 432. Each memory string 412 includes a channel via 436 extending through the stacked structure 435 of insulating film 431 and alternating conductive and dielectric layers. The memory string 412 may also include a memory film 437 (also referred to as a “functional layer”) on the sidewalls of the channel via 436, a channel layer 438 above the memory film 437, and a core fill film 439 surrounded by the channel layer 438. Memory cell 440 may be formed at the intersection of control gate 433 and memory string 412. Memory array structure 400 also includes multiple bit lines (BLs) 441 connected to memory string 412 above TSG 434. Memory array structure 400 may include multiple metal interconnects 443 connected to the gate structure via multiple gate line contact structures 414.

[0128] exist Figure 4For illustrative purposes, three levels of control gates 433-1, 433-2, and 433-3, one level of TSG 434, and one level of BSG 432 are shown together. In this example, each memory string 412 may include three memory cells 440-1, 440-2, and 440-3 corresponding to control gates 433-1, 433-2, and 433-3, respectively. In some embodiments, the number of control gates and memory cells may be more than three to increase storage capacity. The memory array structure 400 may also include other structures, such as TSG cutouts, common source contacts, and dummy channel structures. For simplicity, these structures are not shown. Figure 4 As shown in the image.

[0129] refer to Figure 5A The enlarged top view and cross-sectional side view respectively show some embodiments of the 3D memory device according to the present disclosure, such as... Figure 3 A schematic diagram of part 500 of region 308. Figure 5B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 5A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 5B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 5A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 5B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 5A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0130] A portion 500 of the 3D memory device may be bonded to another semiconductor structure including peripheral circuitry electrically connected to the memory array via conductive interconnects formed in the contact regions. In some embodiments, the peripheral circuitry is disposed on both sides of the memory array, symmetrically positioned relative to the array region, and connected by lateral interconnects extending along a first lateral direction.

[0131] like Figure 5A and Figures 5B1-5B3As shown, a portion 500 of the 3D memory device may include a stacked structure 515, and the stacked structure 515 may have an array region 525 including a plurality of channel structures 550, and a contact region 520 including a plurality of dummy channel structures 555 and a plurality of gate line contact structures 575. The contact region 520 is located on one side of the array region 525 in a first lateral direction (i.e., the X direction). A slot may extend laterally parallel to the first direction and extend vertically through the stacked structure 515. A gate slot (GLS) structure 530 may be formed in the slot to divide the memory array into two memory fingers 540. The GLS structure 530 extends vertically through the stacked structure 515 and laterally along the first lateral direction. Each memory finger 540 may include multiple rows (e.g., four rows) of channel structures 550 arranged in an interleaved manner. The channel structures 550 may extend vertically through the conductive / dielectric stacked structure.

[0132] In such Figure 5A In some embodiments shown, the GLS structure 530 (e.g.) Figure 5A The structure shown (encircled by a dashed rectangle) may include: a dielectric structure 535 extending vertically through the stacked structure 515 and located at the boundary between the array region 525 and the contact region 520; a first GLS structure portion 531 extending laterally from the dielectric structure 535 along a first lateral direction to the contact region 520; and a second GLS structure portion 532 extending laterally from the dielectric structure along the first lateral direction to the array region 525. The dielectric structure 535 separates the first GLS structure portion 531 and the second GLS structure portion 532. The first dimension D1 of the dielectric structure 535 in the first lateral direction (e.g., ...) Figure 5B3 (As shown) is smaller than the second dimension D2 of the dielectric structure 535 in the second lateral direction (i.e., the Y direction) perpendicular to the first lateral direction (as shown). Figure 5A (As shown). The first dimension D1 can range from approximately 30 nm to approximately 200 nm, while the second dimension D2 can range from approximately 500 nm to approximately 1000 nm.

[0133] like Figure 5A and Figures 5B1-5B3As shown, in some embodiments, each of the first GLS structure portion 531 and the second GLS structure portion 532 includes a wall structure extending laterally in a first lateral direction (X direction) and insulated from the conductive layer 514 of the stacked structure 515. In some embodiments, the first GLS structure portion 531 is located in the contact region 520, the second GLS structure portion 532 is located in the array region 525, and the dielectric structure 535 may be located at the boundary between the array region 525 and the contact region 520. The first GLS structure portion 531 includes a first filler wall 531-1 sandwiched between the first spacer layers 531-2 along a second lateral direction. The second GLS structure portion 532 includes a second filler wall 532-1 sandwiched between the second spacer layers 532-2 along a second lateral direction. Figure 5A As shown, the sidewalls of the first GLS structural portion 531 and the second GLS structural portion 532 in the second lateral direction may include curved surfaces.

[0134] like Figures 5B1-5B3 As shown, in some embodiments, each of the first filler wall 531-1 and the second filler wall 532-1 includes an upper portion and a lower portion, and the dimension of the upper portion along the second lateral direction is larger than the dimension of the lower portion along the second lateral direction. The lower portion of the first filler wall 531-1 may include a protrusion of each having a lateral surface and a bottom surface surrounded by the first spacer layer 531-2 from all lateral directions and the bottom direction. The lower portion of the second filler wall 532-1 may also include a protrusion of each having a lateral surface and a bottom surface surrounded by the second spacer layer 532-2 from all lateral directions and the bottom direction. Figures 5B1-5B2 As shown, in some embodiments, the first protrusion of the first filling wall 531-1 has a first height h1 in the vertical direction (e.g., Figure 5B2 (As shown) The second height h2 in the vertical direction of the second protrusion of the second filling wall 532-1 is greater than that of the second filling wall 532-1 (as shown) Figure 5B1 (As shown). In some embodiments, the first protrusion of the first filling wall 531-1 and the second protrusion of the second filling wall 532-1 extend vertically into the upper part of the substrate 510.

[0135] In some implementations, such as Figures 5B1-5B3As shown, a portion 500 of the 3D memory device may include a semiconductor layer 516 located between the stacked structure 515 and the substrate 510. The top surface of the semiconductor layer 516 is lower than the bottom surface of the upper portion of the first filler wall 531-1, and the bottom surface of the semiconductor layer 516 is higher than the bottom surface of the upper portion of the second filler wall 532-1. In some embodiments, the semiconductor layer 516 includes a plurality of ends extending into the second spacer layer 532-2, and a plurality of separate portions located between first protrusions of the first filler wall 531-1. Each separate portion has a lateral surface, a bottom surface, and a top surface surrounded by the first spacer layer 531-2 in all lateral, bottom, and top directions.

[0136] In some implementations, such as Figure 5B3 As shown, the dielectric structure 535 is a composite structure, comprising: an intermediate sublayer 535-1, a first spacer sublayer 535-2 between the intermediate sublayer 535-1 and the first GLS structure portion 531, and a second spacer sublayer 535-3 between the intermediate sublayer 535-1 and the second GLS structure portion 532. In some embodiments, the intermediate sublayer 535-1 may include a first material, the first spacer sublayer 535-2 may include a second material different from the first material but the same as the first spacer sublayer 531-2 of the first GLS structure portion 531, and the second spacer sublayer 535-3 may include a third material different from the first material but the same as the second spacer sublayer 532-2 of the second GLS structure portion 532. In some embodiments, the first material may be an oxide material, such as silicon dioxide (SiO2). The second material can be another oxide material, such as aluminum oxide (Al2O3) or hafnium oxide (HfO2), or it can be a nitride material, such as silicon nitride (Si3N4) or aluminum nitride (AlN). The third material can include the same oxide or nitride material as the second material, selected to be compatible with the specific properties required by the dielectric structure. In some embodiments, the second and third materials are deposited on both sides of the intermediate sublayer 535-1 in the first transverse direction. In some embodiments, the cross-section of the intermediate sublayer 535-1 along the transverse plane (i.e., the XY plane) can have a curved wall structure, and the curved wall structure protrudes toward the second GLS structure portion 531.

[0137] In some embodiments, the dielectric structure 535 is as follows: Figure 5C and Figure 5D The single oxide layer is shown. The dielectric structure has a first dimension in the first lateral direction that is larger than the first spacer layer 531-2, and a first thickness D5 in the second lateral direction (e.g., ...). Figure 5B2 (as shown) and the second spacer layer 535-2 with a second thickness D6 in the second transverse direction (as shown) Figure 5B1shown).

[0138] like Figure 5A As shown, each storage finger 540 in the contact area 520 may include a conductive / dielectric stack region 580 adjacent to the first GLS structure portion 531, and a dielectric stack region 570 located on the side of the conductive / dielectric stack region 580 away from the first GLS structure portion 531. In some embodiments, each conductive / dielectric stack region 580 includes a conductive / dielectric stack comprising a conductive layer 514 and a first dielectric layer 512 alternately stacked in the vertical direction (Z direction).

[0139] like Figure 5A and Figures 5B1-5B3 As shown, multiple dummy channel structures 555 may be located in the conductive / dielectric stack region 580 of the contact region 520, and multiple gate line contact structures 575 may be located in the dielectric stack region 570 of the contact region 520. In some embodiments, the channel structure 550 and the dummy channel structure 555 may include similar structures. For example, each of the channel structure 550 and the dummy channel structure 555 may include a functional layer, a channel layer, and a fill structure, which will be described in detail below.

[0140] like Figure 5A As shown, multiple gate line contact structures 575 can extend vertically within the dielectric stack region 570 of the contact region 520. In some embodiments, each gate line contact structure 575 includes a conductive via structure extending vertically through the upper portion of the dielectric stack structure, and a conductive landing layer contacting the lower end of the conductive via. The conductive landing layer can be laterally connected to a corresponding conductive layer of the conductive / dielectric stack in the conductive / dielectric stack region 580.

[0141] In some embodiments, the stacked structure 515 in array region 525 includes conductive layers 514 and a first dielectric layer 512 alternately stacked in the vertical direction (i.e., the Z direction). The stacked structure 515 in contact region 520 includes a first stacked portion adjacent to the first GLS structure portion 531 and a second stacked portion separated from the first GLS structure portion 531. The first stacked portion includes conductive layers 514 and a first dielectric layer 512 alternately stacked in the vertical direction. The second stacked portion includes a first dielectric layer 512 and a second dielectric layer (not shown) alternately stacked in the vertical direction.

[0142] refer to Figure 6 The diagram shows a flowchart of a method 600 for forming a 3D memory device according to some embodiments of the present disclosure. Figure 7A , Figures 7B1-7B3 , Figure 7C , Figures 7D1-7D3 , Figure 8A , Figures 8B1-8B3 , Figure 9A , Figures 9B1-9B3 , Figure 10A , Figures 10B1-10B3 , Figure 11A , Figures 11B1-11B3 , Figure 12A , Figures 12B1-12B3 , Figures 13A1-13A3 , Figure 14A , Figures 14B1-14B3 , Figure 15A , Figures 15B1-15B3 , Figures 16A1-16A3 , Figure 17A , Figures 17B1-17B3 , Figure 18A , Figures 18B1-18B3 , Figure 19A , Figures 19B1-19B3 , Figure 20A , Figures 20B1-20B3 , Figure 21A , Figures 21B1-21B3 , Figure 22A and Figure 22B Various views illustrate various embodiments of the present disclosure. Figure 6 This is a schematic diagram of a portion of a 3D memory device at a specific fabrication stage of method 600. It should be understood that the operations shown in method 600 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some of these operations may be performed simultaneously or in different sequences. Figure 6 Execute in the order shown.

[0143] like Figure 6 As shown, the method can begin at operation 610, where a stacked structure can be formed to include an array region and a contact region located on one side of the array region in the first lateral direction. Figure 7A A schematic diagram of a 3D structure after a stacked structure is formed at operation 610, according to some embodiments of the present disclosure, is shown in a top perspective view. Figure 7B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 7B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 7B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0144] like Figures 7B1-7B3As shown, in some embodiments, an insulating layer 711 may be formed on a substrate 710. The substrate 710 may be any suitable semiconductor substrate having any suitable structure, such as a single-crystal monolayer substrate, a polycrystalline silicon (polysilicon) monolayer substrate, a polycrystalline silicon and metal multilayer substrate, etc. The insulating layer 711 may comprise any suitable dielectric material having any suitable structure, such as silicon dioxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). A semiconductor layer 716 may be formed on the insulating layer 711. The semiconductor layer 716 may comprise a semiconductor material such as single-crystal silicon, polycrystalline silicon, or germanium. A stacked structure 715 may be formed on the semiconductor layer 716.

[0145] In some implementations, such as Figures 7B1 to 7B3 As shown, the stacked structure 715 may include multiple silicon oxide / silicon nitride layer pairs. For example, each dielectric layer pair includes a silicon oxide layer and a silicon nitride layer. The stacked structure 715 may be formed by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The multiple oxide / nitride layer pairs are also referred to herein as “alternating oxide / nitride stacks”. That is, in the stacked structure 715, multiple oxide layers 712 and multiple nitride layers 713 alternate in the vertical direction (i.e., the Z direction). In other words, in addition to the top and bottom layers of the given alternating oxide / nitride stacks, each of the other oxide layers 712 may be sandwiched between two adjacent nitride layers 713, and each of the nitride layers 713 may be sandwiched between two adjacent oxide layers 712.

[0146] The oxide layers can each have the same thickness or different thicknesses. For example, the thickness of each oxide layer can range from 10 nm to 100 nm, preferably about 25 nm. Similarly, the nitride layers can each have the same thickness or different thicknesses. For example, the thickness of each nitride layer can range from 10 nm to 100 nm, preferably about 35 nm.

[0147] It should be noted that in this disclosure, the oxide layer 712 and / or the nitride layer 713 may comprise any suitable oxide material and / or nitride material. For example, the oxide material may comprise a silicide, and the elements in the nitride material may include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped silicon, silicides, or any combination thereof. In some embodiments, the oxide layer may be a silicon oxide layer, and the nitride layer may be a silicon nitride layer.

[0148] The stacked structure 715 may include any suitable number of oxide layers 712 and nitride layers 713. In some embodiments, the total number of oxide layers 712 and nitride layers 713 in the stacked structure 715 is equal to or greater than 64. That is, the number of oxide / nitride layer pairs may be equal to or greater than 32. In some embodiments, the alternating oxide / nitride stack includes more oxide layers of different materials and / or thicknesses or more nitride layers of different materials and / or thicknesses than the oxide / nitride layer pairs.

[0149] like Figure 7A and Figures 7B1-7B3 As shown, at operation 610, a plurality of through holes 770 can be formed in the contact region 720 and the array region 725 of the stacked structure 715. In some embodiments, the plurality of through holes are laterally aligned along a first lateral direction (X direction), and each extends vertically through the stacked structure 715. In some embodiments, the plurality of through holes 770 includes a first through hole 771 located in both the array region 725 and the contact region 720. In some embodiments, the plurality of through holes 770 may also include a second through hole 773 located in the array region 725. The second through holes 773 may be arranged in an alternating array in the array region 725. In some embodiments, the plurality of through holes 770 may also include a third through hole 775 located in the contact region 720. In some embodiments, the first through hole 771, the second through hole 773, and the third through hole 775 may be formed simultaneously.

[0150] The process of forming a plurality of through-holes 770 may include forming a hard mask layer (not shown) on a stacked structure 715 and coating a photoresist layer (not shown) on the hard mask layer. A patterning process may be performed to pattern the hard mask layer. Using the hard mask layer as a mask, an etching process may subsequently be performed to etch the stacked structure 715 to form a plurality of through-holes 770. Each of the plurality of through-holes 770 may completely penetrate the stacked structure 715 and extend into the substrate 710. The etching process used to form the plurality of through-holes 770 may be dry etching, wet etching, or a combination thereof. After the etching process, the photoresist layer and the hard mask layer may be removed. In some embodiments, a plurality of through-holes 770 may be formed in the same patterning process using a single mask.

[0151] like Figure 7C and Figures 7D1-7D3 As shown, at operation 610, multiple sacrificial fill structures 760 can be formed in multiple first through holes 771 of the stacked structure 715, multiple channel structures 750 can be formed in the second through holes 773 in the array region 725 of the stacked structure 715, and multiple dummy channel structures 755 can be formed in the third through hole 775 in the contact region 720 of the stacked structure 715. Figure 7C It shows the corresponding Figure 7A A schematic diagram of a 3D structure at a specific stage of operation 610 after the formation of multiple sacrificial fill structures 760, multiple channel structures 750 and multiple dummy channel structures 755. Figure 7D1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7C A schematic diagram of the cross-sectional side view of line AA' shown. Figure 7D2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7C A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 7D3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 7C A schematic diagram of the cross-sectional side view of the CC' line shown.

[0152] In some embodiments, to form multiple sacrificial fill structures 760, a deposition process can be performed to fill the through-holes 771 with any suitable sacrificial material (e.g., a carbon-based material). It should be noted that the sacrificial material of the sacrificial fill structure 760 can have sufficiently high etch selectivity for the materials of the oxide layer 712, nitride layer 714, semiconductor layer 716, insulating layer 711, and substrate 710, such that subsequent etching processes of the sacrificial fill structure 760 have minimal impact on the oxide layer 712, nitride layer 714, semiconductor layer 716, insulating layer 711, and substrate 710.

[0153] like Figure 7C and Figures 7D1-7D3 As shown, in some embodiments, multiple channel structures 750 may be formed in a second through-hole 773 in array region 725, and multiple dummy channel structures may be formed in a third through-hole 775. Each channel structure 750 and dummy channel structure 755 may extend vertically through the stack structure 715 into the substrate 710. In some embodiments, the channel structure 750 and dummy channel structure 755 may include similar structures, including: an optional high-k dielectric layer (not shown), a functional layer on or covering the high-k dielectric layer on the sidewalls of the channel hole, a channel layer covering the functional layer, and a filling structure surrounded by the channel layer. In some embodiments, the functional layer may include a barrier layer, a storage layer, and a tunneling layer. In some embodiments, the multiple dummy channel structures 755 may have an elliptical cross-section in the lateral plane (XY plane) with the major axis in the word line direction (X direction).

[0154] In some embodiments, the multiple channel structures 750 may be arranged in an interleaved array. In some embodiments, the array of channel structures 750 may include multiple rows of channel structures 750. Each row of channel structures 750 may be aligned along the word line direction (X direction). Adjacent rows of channel structures 750 may be misaligned. In some embodiments, the array of channel structures 750 may include multiple columns of channel structures 750. Each column of channel structures 750 may be aligned along the bit line direction (Y direction). Adjacent columns of channel structures 750 may be misaligned.

[0155] In some embodiments, the fabrication process for forming the channel structure 750 and the dummy channel structure 755 may include forming an epitaxial layer at the bottom of each channel via / dummy channel via. In some embodiments, the epitaxial layer may be a polycrystalline silicon (PSS) layer formed using a selective epitaxial growth (SEG) process. For example, a SEG pre-cleaning process may be performed to clean the multiple channel vias. Subsequent deposition processes may be performed to form a PSS layer at the bottom of each channel via. In some embodiments, any suitable doping process, such as ion metal plasma (IMP) processing, may be performed on the PSS layer to form the epitaxial layer. In some embodiments, the epitaxial layer may not be formed directly on the surface of the substrate 710. One or more layers may be formed between the epitaxial layer and the substrate 710. That is, the epitaxial layer is overlaid on the substrate 710.

[0156] In some embodiments, the fabrication process for forming the channel structure 750 and the dummy channel structure 755 may include forming an optional high-k dielectric layer (not shown) on the sidewall of each channel hole, and forming a functional layer to cover the high-k dielectric layer. The functional layer may be a composite dielectric layer, such as a combination of a barrier layer, a storage layer, and a tunneling layer. The high-k dielectric layer and the functional layer including the barrier layer, storage layer, and tunneling layer may be formed by one or more thin-film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0157] In some embodiments, a barrier layer and / or a high-k dielectric layer may be formed between the storage layer and the sidewalls of the via / dummy via. The barrier layer and / or high-k dielectric layer can be used to block the outflow of electronic charge. In some embodiments, the barrier layer may be a silicon oxide layer or a combination of silicon oxide / silicon nitride / silicon oxide (ONO) layers. In some embodiments, the high-k dielectric layer comprises any suitable high-dielectric-constant (high-k value) dielectric (e.g., aluminum oxide).

[0158] A storage layer can be formed between the tunneling layer and the barrier layer. Electrons or holes from the channel layer can tunnel through the tunneling layer to the storage layer. The storage layer can be used to store electronic charges (electrons or holes) for memory operation. The storage or removal of charge in the storage layer can affect the on / off state and / or conductivity of the semiconductor channel. The storage layer can include one or more material films, including but not limited to silicon nitride, silicon oxynitride, silicon oxide, and combinations of silicon nitride, or any combination of the foregoing. In some embodiments, the storage layer can include a nitride layer formed using one or more deposition processes.

[0159] A tunneling layer can be formed on the sidewalls of the storage layer. The tunneling layer can be used to tunnel electronic charges (electrons or holes). The tunneling layer can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the tunneling layer can be an oxide layer formed using a deposition process.

[0160] Refer again Figure 6 The method proceeds to operation 615, in which the sacrificial fill structure can be removed and a gate gap (GLS) structure can be formed in the stacked structure. The GLS structure extends vertically through the stacked structure and laterally along a first lateral direction. In some embodiments, operation 615 may include: operation 6151, forming a dielectric structure that extends vertically through the stacked structure and is located at the boundary between the array region and the contact region; operation 6152, forming a first GLS structure portion that extends laterally from the dielectric structure along the first lateral direction to the contact region; and operation 6153, forming a second GLS structure portion that extends laterally from the dielectric structure along the first lateral direction to the array region.

[0161] Figure 8A , Figures 8B1-8B3 , Figure 9A , Figures 9B1-9B3 , Figure 10A , Figures 10B1-10B3 , Figure 11A , Figures 11B1-11B3 , Figure 12A , Figures 12B1-12B3 , Figures 13A1-13A3 , Figure 14A , Figures 14B1-14B3 , Figure 15A , Figures 15B1-15B3 , Figures 16A1-16A3 , Figure 17A , Figures 17B1-17B3 , Figure 18A , Figures 18B1-18B3 , Figure 19A , Figures 19B1-19B3 , Figure 20A , Figures 20B1-20B3 , Figure 21A and Figures 21B1-21B3A schematic diagram of a 3D structure during a specific phase of operation 615 is shown according to some embodiments of the present disclosure.

[0162] In some embodiments, the sacrificial filler structure 760 in the first through hole 771 in the contact area 720 may be removed to form a plurality of first slit openings 859 in the contact area 720. Figure 8A It shows the corresponding Figure 7C A schematic diagram of the 3D structure after removing multiple sacrificial fill structures 760 in the array region 725 and multiple dummy channel structures 755 in the contact region 720 without affecting the operation 610 at a specific stage. Figure 8B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 8A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 8B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 8A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 8B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 8A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0163] like Figure 8A and Figures 8B1-8B3 As shown, in some embodiments, a plurality of first slot openings 859 can be formed by forming a mask layer (not shown) over a stacked structure 715 in the contact region 720 and patterning the mask using, for example, photolithography. Suitable etching processes such as dry etching and / or wet etching can be performed to remove the sacrificial fill structure 760 to form the plurality of first slot openings 859.

[0164] In some embodiments, the plurality of first slit openings 859 can be enlarged such that the plurality of first slit openings 859 are connected to each other to form a shape such as Figure 9A and Figures 9B1-9B3 The first groove 960 is shown. Figure 9A It shows the corresponding Figure 8A A schematic diagram of the 3D structure after expanding multiple first slit openings 859 in a top perspective view without affecting multiple channel structures 750 in the array region 725 and multiple dummy channel structures 755 in the contact region 720 at a specific stage of operation 610. Figure 9B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 9A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 9B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 9A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 9B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 9A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0165] Suitable etching processes, such as dry etching and / or wet etching, can be performed to enlarge the plurality of first slot openings 859 to form first trenches 960. Each of the first trenches 960 can extend vertically through the stacked structure 715 into the substrate 710. In some embodiments, a doped region (not shown) can be formed at the bottom of the first trench 960 in the substrate 710 using any suitable doping process, such as ion implantation and / or thermal diffusion. The dopant in the doped region can be any suitable N+ or P+ ions. After conductive walls are formed in the first trench 960 in a subsequent process, the lower end of each conductive wall can contact the corresponding doped region.

[0166] In some implementations, such as Figure 10A and Figures 10B1-10B3 As shown, a first oxidation process can be performed to oxidize the substrate 710 and semiconductor layer 716 exposed by the first trench 960 to form a first oxide layer 1020. Figure 10A It shows the corresponding Figure 9A A schematic diagram in a top perspective view of the 3D structure after the formation of the first oxide layer 1020 without affecting the multiple channel structures 750 in the array region 725 and the multiple dummy channel structures 755 in the contact region 720 at a specific stage of operation 610. Figure 10B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 10A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 10B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 10A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 10B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 10A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0167] The first oxidation process can be performed by exposing the substrate to an oxygen-containing atmosphere at an elevated temperature. The temperature and duration of the oxidation process can be controlled to achieve the desired thickness of the oxide layer. In some embodiments, depending on the specific requirements of the application, the first oxidation process may involve dry oxidation or wet oxidation. Dry oxidation can be used to form a denser and thinner oxide layer, while wet oxidation can produce a thicker oxide layer more quickly. The first oxide layer 1020 can act as a protective barrier for the substrate 710 during subsequent processing steps, preventing contamination or damage. In some embodiments, such as Figure 10B2 and Figure 10B3 As shown, the semiconductor layer 716 exposed by the first trench 960 can also be oxidized during the oxidation of the substrate 710.

[0168] In some implementations, such as Figure 11A and Figures 11B1-11B3 As shown, the portion of the nitride layer 713 exposed by the first trench 960 in the contact area 720 and the portion of the nitride layer 713 exposed by the first trench 960 in the array area 725 can be removed to form the first gap 1113. Figure 11A It shows the corresponding Figure 10A A schematic diagram of the 3D structure after the removal of the nitride layer 713 in the sector region 1122 in a top perspective view. The sector region 1122 is mainly located in the contact region 720 and partially located in the array region 725. Figure 11B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 11A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 11B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 11A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 11B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 11A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0169] Selective removal of the nitride layer 713 in the fan-shaped region 1122 can be performed using dry etching techniques such as reactive ion etching (RIE) to ensure accuracy and minimize damage to the surrounding structure. That is, only the nitride layer 713 exposed by the first trench 960 in the contact region 720 is removed, without affecting the nitride layer 713, substrate 710, semiconductor layer 716, and first oxide layer 1020 in the array region 725. Etching parameters, including gas composition and etching time, can be adjusted to target only the exposed nitride layer, leaving other materials intact. Since the removal of the nitride layer 713 occurs through the first trench 960, and the first trench is located in the contact region 720, most of the removal of the nitride layer 713 occurs in the contact region 720. Furthermore, as... Figure 11B3 As shown, the nitride layer 713 exposed by the first trench 960 in the array region 725 can also be removed. For example... Figure 11B1 and Figure 11B2 As shown, the selective removal of the nitride layer 713 does not affect the channel structure 750 in the array region 725 or the dummy channel structure 755 in the contact region.

[0170] In some implementations, such as Figure 12A and Figures 12B1-12B3 As shown, after the first gap 1113 is formed, the first gap 1113 and the first groove 960 can be filled with sacrificial material to form the sacrificial structure 1213. Figure 12A It shows the corresponding Figure 11A A schematic diagram of the 3D structure after the sacrificial structure 1213 is formed in a top perspective view without affecting the multiple channel structures 750 in the array region 725 and the multiple dummy channel structures 755 in the contact region 720 at a specific stage of operation 610. Figure 12B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 12A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 12B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 12A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 12B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 12A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0171] The sacrificial structure can be formed by deposition processes such as chemical vapor deposition (CVD) to ensure uniform coverage over the gaps. Depending on the subsequent removal process, the sacrificial material can be a material such as polycrystalline silicon or amorphous carbon. Once deposited, the sacrificial material can undergo planarization processes such as chemical mechanical polishing (CMP) to ensure the surface is flush with the surrounding structure, such as... Figures 12B1-12B3As shown. In some implementations, such as Figure 12B1 and Figure 12B2 As shown, during the formation of the sacrificial structure, the multiple channel structures 750 in the array region 725 and the multiple dummy channel structures 755 in the contact region 720 are not affected.

[0172] In some embodiments, after forming the sacrificial structure 1213, a cap layer 1315 may be formed to cover both the contact region 720 and the array region 725, such as Figures 13A1-13A3 As shown, Figures 13A1-13A3 The diagram shows the corresponding to each Figures 12B1-12B3 A schematic diagram of the 3D structure after the formation of the cap layer 1315 in a cross-sectional side view. The cap layer 1315 can be formed by deposition of materials such as silicon oxynitride (SiON) via a chemical vapor deposition (CVD) process. The CVD process can be performed under specific conditions to achieve the desired thickness and uniformity of the cap layer 1315, ensuring effective coverage in both regions. The cap layer 1315 provides protection during subsequent processing, acting as a barrier against contamination and serving as structural support.

[0173] In some implementations, the sacrificial filler structure 760 in the first through hole 771 in the array region 725 may be removed to form a plurality of second slit openings 1459 in the array region 725. Figure 14A It shows the corresponding Figure 12A A schematic diagram of the 3D structure after forming multiple second slit openings 1459 in a top perspective view without affecting the multiple channel structures 750 in the array region 725 and the multiple dummy channel structures 755 in the contact region 720 at a specific stage of operation 610. Figure 14B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 14A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 14B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 14A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 14B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 14A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0174] A plurality of second slit openings 1459 can be formed by forming a mask layer (not shown) over a cap layer 1315 in array region 725 and patterning the mask using, for example, photolithography. Appropriate etching processes such as dry etching and / or wet etching can be performed to remove the sacrificial fill structure 760 in array region 725 to form, as shown in the image. Figure 14A , Figure 14B1 and Figure 14B3 Multiple second slit openings 1459 are shown. For the removal of only the filling structure, the etching process can be selective, leaving other parts of the 3D structure unaffected. For example, as... Figure 14B1 and Figure 14B2 As shown, the channel structure 750 in the array region and the dummy channel structure 755 in the contact region are not affected by the removal of the sacrificial fill structure 760.

[0175] In some implementations, a plurality of second slot openings 1459 may be etched and enlarged such that the second slot openings 1459 are connected to each other to form a second trench 1560 in the array region 725. Figure 15A It shows the corresponding Figure 14A A schematic diagram in a top perspective view of the 3D structure after forming the second trench 1560 without affecting the array region 725 of multiple channel structures 750 and the contact region 720 of multiple dummy channel structures 755 at a specific stage of operation 610. Figure 15B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 15A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 15B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 15A A schematic diagram of the cross-sectional side view of the BB' line shown.

[0176] Figure 15B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 15A A schematic diagram of the cross-sectional side view of the CC' line shown. The second trench 1560 can extend vertically and penetrate the stacked structure 715 into the substrate 710.

[0177] Suitable etching processes, such as dry etching and / or wet etching, can be performed to enlarge the second slot opening 1459 until the second trench 1560 is formed to expose the sacrificial structure 1213 and the substrate 710. In some embodiments, when the etching process is sufficiently selective, the etching process for enlarging the second slot opening 1459 can be stopped by the sacrificial structure 1213. That is, as... Figure 15A As shown, the second trench 1560 stops at the side surface of the sacrificial structure 1213 without affecting the sacrificial structure 1213. In some embodiments, a doped region (not shown) can be formed at the bottom of the second trench 1560 in the substrate 710 by using any suitable doping process such as ion implantation and / or thermal diffusion. The dopant in the doped region can be any suitable N+ or P+ ions. After forming conductive walls in the second trench 1560 in a subsequent process, the lower end of each conductive wall can contact the corresponding doped region.

[0178] In some embodiments, during the widening of the second slit opening 1459 to form the second groove 1560, such as Figure 15B3 As shown, because only the sacrificial fill structure 760 was selectively removed, the portion of the sacrificial structure 1213 in the array region 725 remains intact. The retained sacrificial material can then be removed by performing a recess process. Figures 16A1-16A3 As shown, the remaining portion of the sacrificial structure 1213 in the second trench 1560 is removed, and as... Figures 16A1-16A2 As shown, the channel structure 750 in the array region 725 and the dummy channel structure 755 in the contact region 720 are maintained without affecting the channel structure 750.

[0179] The recessed process involves selective etching techniques, which can use either wet etching or dry etching, such as reactive ion etching (RIE). These techniques carefully remove sacrificial material without damaging the surrounding structure. Optimization of etching parameters, including etchant, pressure, and etching time, ensures precise control over the removal of sacrificial material.

[0180] During the recess process, the side surfaces of the sacrificial structure 1213 in the first trench 960 may also be etched. The etching may form a curved surface for the sacrificial structure 1213, depending on specific etching conditions such as whether wet or dry etching is used and the duration of the etching process. The curved surface may bulge toward the array region or toward the contact region.

[0181] In some implementations, such as Figure 17A and Figures 17B1-17B3 As shown, a second oxidation process can be performed to oxidize the side surfaces of the sacrificial structure 1213 exposed by the second trench 1560 to form an intermediate sublayer 1735. The second oxidation process can be performed by exposing the sacrificial structure 1213 to an oxygen-containing atmosphere at elevated temperatures. The temperature and duration of the oxidation process can be controlled to achieve the desired thickness of the oxide layer. In some embodiments, depending on the specific requirements of the application, the second oxidation process may involve dry oxidation or wet oxidation. Dry oxidation can be used to form denser and thinner oxide layers, while wet oxidation can produce thicker layers more quickly. Depending on the oxidation conditions, the thickness of the intermediate sublayer 1735 can range from approximately 30 nm to approximately 200 nm. In addition to the oxidation of the side surfaces of the sacrificial structure 1213, in some embodiments, the surfaces of the substrate 710 and the semiconductor layer 716 exposed by the second trench 1560 can be oxidized to form, as shown in the diagram. Figure 17B1 and Figure 17B3 The second oxide layer 1720 is shown. (As shown) Figure 17B1 and Figure 17B2 As shown, the channel structure 750 in the array region 725 and the dummy channel structure 755 in the contact region are not affected by oxidation.

[0182] In some implementations, such as Figure 18A and Figures 18B1-18B3 As shown, the nitride layer 713 exposed by the second trench 1560 in the array region 725 can be removed to form the second gap 1813. Figure 18A It shows the corresponding Figure 15A A schematic diagram in a top perspective view of the 3D structure after the nitride layer is removed by the second trench 1560 without affecting the multiple channel structures 750 in the array region 725 and the multiple dummy channel structures 755 in the contact region 720 at a specific stage of operation 610. Figure 18B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 18A A schematic diagram of the cross-sectional side view of line AA' shown.

[0183] Figure 18B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 18A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 18B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 18A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0184] Selective removal processes can be performed using dry etching techniques such as reactive ion etching (RIE) to ensure accuracy and minimize damage to surrounding structures. Etching parameters, including gas composition and etching time, can be adjusted to target only the exposed nitride layer 713, leaving other materials intact. For example, as... Figure 18B1 The channel structure 750 in the array region 725 shown, such as Figure 18B2 The dummy channel structure 755 in the contact area 720 shown, and as shown Figure 18B3 The intermediate sublayer 1735 on the side surface of the sacrificial structure 1213 shown is unaffected by the removal of the nitride layer 713. Since the removal of the nitride layer 713 occurs through the second trench 1560, and the second trench 1560 is located in the array region 725, the removal of the nitride layer 713 primarily occurs in the array region 725, as shown by... Figure 18A The shaded area 1822 is shown. After selective removal of the nitride layer 713 is performed through the second trench 1560, as... Figure 18A As shown, the nitride layer 713 in the shaded region 1822 and the fan-shaped region 1122 is removed.

[0185] In some implementations, the sacrificial structure 1213 can be selectively removed without affecting the intermediate sublayer 1735. Figure 19A It shows the corresponding Figure 18A A schematic diagram of the 3D structure after removing the sacrificial structure 1213 without affecting the multiple channel structures 750 in the array region 725 and the multiple dummy channel structures 755 in the contact region 720, in a top perspective view. Figure 19B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 19A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 19B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 19A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 19B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 19A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0186] like Figure 19A and Figure 19B3 As shown, the specific material of the sacrificial structure 1213 can be used as the target to make the channel structure 750 in the array region 725 (such as...) Figure 19B1 As shown), the virtual channel structure 755 in the contact area 720 (e.g.) Figure 19B2 (As shown), and this selective removal of the sacrificial structure 1213 is performed by a suitable etching process that leaves the intermediate sublayer 1735 formed by oxidizing the side surface of the sacrificial structure 1213 at the boundary between the array region 725 and the contact region 720 unaffected. Since the sacrificial structure 1213 is formed within the first trench 960 and the first gap 1113, its removal will restore the first trench 960 and the first gap 1113, as shown. Figure 19A and Figures 19B2-19B3 As shown. After selectively removing the sacrificial structure 1213, as Figure 19A and Figure 19B3 As shown, the intermediate sublayer 1735 is fully preserved and has a curved wall structure that protrudes toward the array region. In some embodiments, the curved wall structure may protrude toward the contact region (not shown).

[0187] In some embodiments, after the sacrificial structure 1213 is removed, the restored first gap 1113 and the first trench 960 can be filled with a conductive material (e.g., Figure 19B2 (as shown) and the second gap 1813 (as shown) Figure 18B1 (as shown), to form as Figure 20A and Figures 20B1-20B2The diagram shows multiple conductive layers 2014. Depending on the specific requirements of the process, conductive materials can be deposited using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Suitable conductive materials can include metals such as tungsten (W), copper (Cu), or aluminum (Al), or conductive compounds such as titanium nitride (TiN). The multiple conductive layers 2014 can act as word lines and facilitate the establishment of electrical connections between various components of a 3D device.

[0188] Refer again Figure 6 The method proceeds to operation 615, in which a GLS structure is formed that extends vertically through the stack structure and laterally along a first lateral direction. Operation 615 may include: operation 6151, forming a dielectric structure that extends vertically through the stack structure and is located at the boundary between the array region and the contact region; operation 6152, forming a first GLS structure portion that extends laterally from the dielectric structure along the first lateral direction to the contact region; and operation 6153, forming a second GLS structure portion that extends laterally from the dielectric structure along the first lateral direction to the array region. Figure 21A A schematic diagram of a 3D structure during operation 615 according to some embodiments of the present disclosure is shown in a top perspective view. Figure 21B1 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 21A A schematic diagram of the cross-sectional side view of line AA' shown. Figure 21B2 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 21A A schematic diagram of the cross-sectional side view of the BB' line shown. Figure 21B3 A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 21A A schematic diagram of the cross-sectional side view of the CC' line shown.

[0189] like Figure 21A and Figures 21B1-21B3 As shown, a GLS structure 2130 can be formed, including a first GLS structure portion 2131, a second GLS structure portion 2132, and a dielectric structure 2135. The first GLS structure portion 2131 can be formed in a first trench 960 in the contact region 720, the second GLS structure portion 2132 can be formed in a second trench 1560 in the array region 725, and the dielectric structure 2135 can be formed at the boundary between the array region 725 and the contact region 720.

[0190] In some embodiments, the operation 6151 for forming the dielectric structure 2135 may include the intermediate sublayer 1735 along a first lateral direction (i.e., as shown in the figure). Figure 21B3A second insulating layer 2111 is deposited on both sides of the intermediate sublayer 1735 (shown in the X direction). The second insulating layer 2111 can be deposited using the same material as the intermediate sublayer 1735. Alternatively, a different material can be used. Depending on the material used and the desired layer thickness, the deposition process can be performed using techniques such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). These methods ensure uniform coverage along both sides of the intermediate sublayer 1735, achieving precise control over the required insulation properties and layer thickness of the dielectric structure 2135.

[0191] In some embodiments, the operation 6152 for forming the first GLS structural portion 2131 may include depositing a first spacer sublayer 2112 on the inner wall of the first trench 960 and filling the first trench 960 with a filler material to form a first conductive wall 2113. The first spacer sublayer 2112 may be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD) to achieve a uniform and conformal coating on the inner wall of the trench. After depositing the first spacer sublayer 2112, the first trench 960 may be filled with a conductive material such as doped polysilicon, silicide, tungsten, aluminum, copper, and / or combinations thereof to form the first conductive wall 2113. Depending on the material chosen, the filling process may be performed using low-pressure chemical vapor deposition (LPCVD), electroplating, or other deposition techniques. After filling, a planarization step such as chemical mechanical polishing (CMP) may be performed to ensure that the surface of the first conductive wall 2113 is flush with the surrounding layers, completing the formation of the first GLS structural portion 2131.

[0192] In some embodiments, the operation 6153 for forming the second GLS structure portion 2132 may include depositing a second spacer sublayer 2114 on the inner wall of the second trench 1560 and filling the second trench 1560 with a filler material to form a second conductive wall 2115. The second spacer sublayer 2114 may be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD) to achieve a uniform and conformal coating on the inner wall of the trench. After depositing the second spacer sublayer 2114, the second trench 1560 may be filled with a conductive material such as doped polysilicon, silicide, tungsten, aluminum, copper, and / or combinations thereof to form the second conductive wall 2115. Depending on the material chosen, the filling process may be performed using low-pressure chemical vapor deposition (LPCVD), electroplating, or other deposition techniques. After filling, a planarization step such as chemical mechanical polishing (CMP) may be performed to ensure that the surface of the second conductive wall 2115 is flush with the surrounding layers, completing the formation of the second GLS structure portion 2132.

[0193] In some implementations, the deposition of the second insulating layer 2111, the first spacer sublayer 2112, and the second spacer sublayer 2114 can be performed simultaneously. This simultaneous deposition can be achieved by using the same deposition technique (e.g., CVD or ALD) and processing conditions, allowing these layers to be efficiently integrated into the structure. This simultaneous deposition can streamline the manufacturing process by reducing the number of individual deposition steps, thereby increasing yield and minimizing potential misalignment issues between the spacer sublayer and the insulating layer.

[0194] In some embodiments, the formation of the first conductive wall 2113 and the formation of the second conductive wall 2115 can be performed simultaneously. This simultaneous formation can be achieved by depositing the same conductive material, such as doped polysilicon, silicide, tungsten, aluminum, copper, and / or combinations thereof, into both the first trench 960 and the second trench 1560 at the same time. Techniques such as low-pressure chemical vapor deposition (LPCVD) or electroplating can be used to ensure uniform filling of the two trenches. After deposition, a single planarization step, such as chemical mechanical polishing (CMP), can be performed to ensure that the two conductive walls are flush with the surrounding structure, reducing process complexity and improving manufacturing efficiency. This simultaneous formation helps to streamline the fabrication process and ensures the consistency of conductivity between the first and second GLS structural portions.

[0195] In some implementations, the method may further include forming a plurality of gate line contact structures in a stacked structure in the contact region. Figure 22A A schematic diagram of a 3D structure after removing a subset of the dummy channel structure and forming a plurality of gate line contact structures according to some embodiments of the present disclosure is shown in a top perspective view. Figure 22B A portion of a 3D structure according to some embodiments of the present disclosure is shown along... Figure 22A A schematic diagram of the cross-sectional side view of line AA' shown.

[0196] like Figure 22A and Figure 22B As shown, a plurality of gate line contact structures 2210 can be formed in the stacked structure 715 in the contact region 720. In some embodiments, forming the gate line contact structures 2210 may include forming a plurality of contact holes in the stacked structure 715 in the contact region 720. In some embodiments, each of the plurality of contact holes may penetrate the upper portion of the stacked structure 715 in the contact region 720 and stop at a corresponding nitride layer 714. For example, one or more suitable etching processes, such as dry etching and / or wet etching, may be performed to remove portions of the stacked structure 715 in the contact region 720 to form a plurality of contact holes. During the etching process, the shape of the contact holes can be controlled using a mask layer (not shown), and various etching times can be controlled to form a plurality of contact holes with different depths.

[0197] In some embodiments, a dielectric-filled structure can be formed using any suitable deposition process to fill each contact hole. Through-hole etching can be performed to remove portions of the dielectric-filled structure to expose a corresponding nitride layer 714 at the bottom of each contact hole. The remainder of the dielectric-filled structure forms spacer layers 2233 on the sidewalls of each contact hole. A portion of the exposed nitride layer 714 can be removed using any suitable etching process to laterally expose a corresponding conductive layer 2014 at the same level as the corresponding nitride layer 714.

[0198] A conductive layer (including 2224 and 2226) can be formed using a first conductive material through any suitable thin-film deposition process to cover the spacer layer 2233 and the bottom surface of each contact hole, and the conductive layer contacts a corresponding conductive layer 2014 in the lateral direction. In some embodiments, a second conductive material can then be filled into the contact hole to form a conductive fill structure 2228. The first and second conductive materials can be deposited into the contact hole using any suitable deposition method such as CVD, PVD, PECVD, sputtering, MOCVD, and / or ALD. In some embodiments, the conductive layer (including 2224 and 2226) and the conductive fill structure 2228 may comprise any suitable conductive material, such as tungsten, aluminum, copper, cobalt, or any combination thereof.

[0199] The conductive layer 2226 and the conductive fill structure 2228 can be formed by spacer layer 2233 to create conductive vias that are isolated from other conductive layers 2014. That is, the gate line contact structure 2210 can include conductive vias (including 2226 and 2228) and a landing conductive layer 2224. The landing conductive layer 2224 can each make lateral contact with the corresponding conductive layer 2014. The conductive vias are in direct contact with the landing conductive layer 2224 and are electrically connected to the corresponding conductive layer 2014. Therefore, the formed gate line contact structure 2210 can be used as a word line contact.

[0200] The foregoing description of specific embodiments will fully reveal the general nature of this disclosure, enabling those skilled in the art to readily modify and / or adapt such specific embodiments for various applications without excessive experimentation, using knowledge in the art, without departing from the general conception of this disclosure. Therefore, based on the teachings and guidance presented herein, such modifications and alterations are intended to fall within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology used herein is for descriptive rather than limiting purposes, and that the terminology or terminology in this specification should be interpreted by those skilled in the art based on the teachings and guidance.

[0201] The embodiments of this disclosure have been described above using functional building blocks that illustrate specific functions and their relationships. For ease of description, the boundaries of these functional building blocks are arbitrarily defined herein. Alternative boundaries may be defined as long as the specific functions and their relationships are properly performed.

[0202] The summary and abstract section may set forth one or more, but not all, embodiments of this disclosure conceived by one or more inventors, and therefore is not intended to limit this disclosure and the appended claims in any way.

[0203] The scope and extent of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A memory device, comprising: A stacked structure, the stacked structure including an array region and a contact region located on one side of the array region in a first lateral direction; as well as A gate gap (GLS) structure, the GLS structure extending vertically through the stacked structure and laterally along the first lateral direction, the GLS structure comprising: A dielectric structure extending vertically through the stacked structure and located at the boundary between the array region and the contact region; A first GLS structural portion extends laterally from the dielectric structure along the first lateral direction to the contact region; and The second GLS structure portion extends laterally from the dielectric structure along the first lateral direction to the array region. The dielectric structure separates the first GLS structure portion from the second GLS structure portion, and the first dimension of the dielectric structure in the first lateral direction is smaller than the second dimension of the dielectric structure in the second lateral direction perpendicular to the first lateral direction.

2. The memory device according to claim 1, wherein: The first GLS structure portion includes a first filler wall sandwiched between the first spacer layers along the second lateral direction; and The second GLS structure portion includes a second filler wall sandwiched between the second spacer layers along the second transverse direction.

3. The memory device according to claim 2, wherein, The dielectric structure is a single oxide layer, and the first dimension of the single oxide layer in the first lateral direction is greater than the sum of the first thickness of the first spacer layer in the second lateral direction and the second thickness of the second spacer layer in the second lateral direction.

4. The memory device according to claim 2, wherein, The dielectric structure is a composite structure, and the composite structure includes: An intermediate sublayer having a first material; A first spacer sublayer, located between the intermediate sublayer and the first GLS structural portion, and having a second material different from the first material but the same as the first spacer layer of the first GLS structural portion; and The second spacer sublayer is located between the intermediate sublayer and the second GLS structure portion, and has a third material that is different from the first material but the same as the second spacer layer of the second GLS structure portion.

5. The memory device according to claim 4, wherein: The first material is an oxide material; and The second material and the third material are the same and are deposited on both sides of the intermediate sublayer in the first lateral direction.

6. The memory device according to claim 4, wherein, The intermediate sublayer has a curved wall structure.

7. The memory device according to claim 6, wherein, The curved wall structure protrudes toward the second GLS structure portion.

8. The memory device according to claim 1, wherein: The sidewalls of the first GLS structural portion and the second GLS structural portion in the second transverse direction include curved surfaces.

9. The memory device according to claim 2, wherein, Each of the first filling wall and the second filling wall includes an upper portion and a lower portion, wherein the upper portion has a larger dimension along the second transverse direction than the lower portion has a larger dimension along the second transverse direction.

10. The memory device according to claim 9, wherein: The lower portion of the first filling wall includes: Each has a protrusion on its lateral and bottom surfaces surrounded by the first spacer layer from all lateral and bottom directions; and The lower portion of the second filling wall includes: Each has a protrusion on its lateral and bottom surfaces surrounded by the second spacer layer from all lateral and bottom directions.

11. The memory device according to claim 10, wherein: The first protrusion of the first filling wall has a first height in the vertical direction that is greater than the second protrusion of the second filling wall has a second height in the vertical direction.

12. The memory device of claim 11, further comprising a semiconductor layer located between the stacked structure and the substrate, wherein: The top surface of the semiconductor layer is lower than the bottom surface of the upper part of the first filling wall; and The bottom surface of the semiconductor layer is higher than the bottom surface of the upper part of the second filling wall.

13. The memory device according to claim 12, wherein, The first protrusion and the second protrusion extend vertically into the upper part of the substrate.

14. The memory device according to claim 12, wherein, The semiconductor layer in the contact region includes: The end extends into the second spacer layer; and The separated portions are located between the first protrusions, and each has a lateral surface, a bottom surface, and a top surface surrounded by the first spacer layer from all lateral directions, the bottom direction, and the top direction.

15. The memory device according to claim 1, wherein: The first size is in the range of approximately 30 nm to approximately 200 nm; and The second dimension is in the range of approximately 500 nm to approximately 1000 nm.

16. The memory device of claim 1, further comprising: A channel structure, each of which extends vertically through the stacked structure and is located in the array region; as well as A dummy channel structure, each of which extends vertically through the stacked structure and is located in the contact area.

17. The memory device according to claim 1, wherein: The stacked structure in the array region includes a conductive layer and a first dielectric layer that are alternately stacked in the vertical direction; and The stacking structure in the contact area includes: A first stacked portion, adjacent to the first GLS structure portion, and comprising the conductive layer and the first dielectric layer alternately stacked in the vertical direction, and The second stack portion, which is separated from the first GLS structure portion by the first stack portion, includes a first dielectric layer and a second dielectric layer that are alternately stacked in the vertical direction.

18. The memory device according to claim 1, wherein, A first semiconductor structure, including the stacked structure and the GLS structure, is bonded to a second semiconductor structure including peripheral circuitry.

19. A method for forming a memory device, comprising: A stacked structure is formed, comprising an array region and a contact region located on one side of the array region in the first lateral direction; as well as Forming a gate slot (GLS) structure that extends vertically through the stacked structure and laterally along the first lateral direction, comprising: A dielectric structure is formed that extends vertically through the stacked structure and is located at the boundary between the array region and the contact region; Forming a first GLS structure portion extending laterally from the dielectric structure along the first lateral direction to the contact region; and A second GLS structure portion is formed, extending laterally from the dielectric structure along the first lateral direction to the array region. The dielectric structure separates the first GLS structure portion from the second GLS structure portion, and the first dimension of the dielectric structure in the first lateral direction is smaller than the second dimension of the dielectric structure in the second lateral direction perpendicular to the first lateral direction.

20. The method according to claim 19, wherein, Forming the stacked structure includes: An insulating layer is formed on the substrate; A semiconductor layer is formed on the insulating layer; A first dielectric layer and a second dielectric layer are formed on the semiconductor layer, stacked alternately in a vertical direction; and An array of first through holes is formed in the contact region and an array of second through holes is formed in the array region, wherein each first through hole and each second through hole extends vertically through the stacked structure into the substrate.

21. The method according to claim 20, wherein, Forming the GLS structure includes: A first trench extending along the first lateral direction is formed by etching one row of the array of the first through holes; The first trench removes a portion of the second dielectric layer located at the contact area to form a first gap; The first trench and the first gap are filled with sacrificial material; A second trench extending along the first lateral direction is formed by etching one row of the array of second through holes; The second trench removes a portion of the second dielectric layer located in the array region to form a second gap; Remove the sacrificial material from the first trench and the first gap; Fill the first gap and the second gap with a conductive material; and The first GLS structure portion is formed in the first trench, and the second GLS structure portion is formed in the second trench.

22. The method according to claim 21, wherein, After forming the first trench, the method further includes: The first trench is enlarged by removing portions of the first and second dielectric layers exposed by the first trench; and Oxidation occurs on the semiconductor layer and the substrate exposed by the enlarged first trench.

23. The method according to claim 22, wherein, After forming the second trench, the method further includes: The second trench is enlarged by removing portions of the first and second dielectric layers exposed by the second trench; Remove the portion of the semiconductor layer and the sacrificial material exposed by the enlarged second trench; and The side surfaces of the sacrificial material in the first trench are oxidized to form an intermediate sublayer composed of a first material, wherein the side surfaces of the sacrificial material in the first trench are exposed by an enlarged second trench.

24. The method according to claim 23, wherein, Filling the first trench and the first gap with the sacrificial material includes: The first trench and the first gap are filled with a sacrificial semiconductor material.

25. The method according to claim 24, wherein, Forming the intermediate sublayer includes: The intermediate sublayer is formed having a curved wall structure, wherein the curved wall structure protrudes toward the second GLS structure portion.

26. The method of claim 25, further comprising: A second material is deposited on both sides of the intermediate sublayer.

27. The method according to claim 21, wherein, Forming the first GLS structure portion in the first trench and forming the second GLS structure portion in the second trench includes: A first spacer sublayer is deposited on the inner wall of the first trench; A second spacer sublayer is deposited on the inner wall of the second trench; and The first and second trenches are filled with filler material.

28. The method according to claim 27, wherein, Filling the first trench and the second trench with the filling material includes: The first trench and the second trench are filled with conductive material.

29. The method of claim 19, further comprising: A virtual channel structure is formed in the other first through holes; as well as A channel structure is formed in the other second through holes.

30. A memory device, comprising: Storage array; as well as Peripheral circuitry, wherein the peripheral circuitry is disposed on at least one side of the storage array. The storage array includes: A stacked structure, the stacked structure including an array region and a contact region located on one side of the array region in a first lateral direction; and A gate gap (GLS) structure, the GLS structure extending vertically through the stacked structure and laterally along the first lateral direction, the GLS structure comprising: A dielectric structure extending vertically through the stacked structure and located at the boundary between the array region and the contact region; A first GLS structural portion extends laterally from the dielectric structure along the first lateral direction to the contact region; and The second GLS structure portion extends laterally from the dielectric structure along the first lateral direction to the array region. The dielectric structure separates the first GLS structure portion from the second GLS structure portion, and the first dimension of the dielectric structure in the first lateral direction is smaller than the second dimension of the dielectric structure in the second lateral direction perpendicular to the first lateral direction.

31. The memory device according to claim 30, wherein, The peripheral circuitry is electrically connected to the memory array via conductive interconnects formed in the contact region.

32. The memory device according to claim 31, wherein, The peripheral circuits are disposed on both sides of the storage array, symmetrically placed with respect to the array region, and connected by lateral interconnects extending along the first lateral direction.

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