Floating Substrate Switching Method and Circuit for Gallium Nitride Field-Effect Transistors

Abstract

A gallium nitride field-effect transistor (GaNFET) power switch includes a substrate, a metal layer, and a control circuit. The control circuit controls the potential of the metal layer based on the potential of the gate of the GaNFET power switch. The control circuit can control the potential of the metal layer according to at least a first mode and a second mode, wherein the first mode is determined by the off state of the GaNFET power switch, and the second mode is determined by the on state of the GaNFET power switch. In the first mode, the potential of the metal layer can be floating, and in the second mode, the potential of the metal layer can be the same as the source, or the same as the gate, or proportional to the potential of the gate, or a monotonic function of the potential of the gate.

Description

[0001] Related applications This application claims the benefit of the filing date of U.S. Patent Application 63 / 624,590, filed on January 24, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention generally relates to the field of high-voltage power electronic devices using gallium nitride (GaN) and gallium arsenide (GaAs) field-effect transistors (FETs), particularly high electron mobility transistors (HEMTs). More specifically, this invention relates to methods for controlling floating substrates of GaN and GaAs HEMTs to achieve effective control of high-voltage leakage current and dynamic on-resistance in high-voltage power switching applications. Background Technology

[0003] Gallium nitride field-effect transistors (GaNFETs) used in power electronic switching applications are typically made of gallium nitride grown on a silicon substrate. During packaging, the substrate is conductively connected to a bottom lead frame, which is usually also the source. This method suffers from a significant substrate leakage current because the resistivity of silicon substrates is typically low (around 100 ohms), and high resistance values ​​cannot be achieved.

[0004] To address this drawback, several solutions have been proposed. For example, in U.S. Patent No. 11,107,755, granted August 31, 2021, the silicon substrate of a GaN-FET is fixed to a bottom lead frame structure (which is typically also the source) using insulating adhesive or other insulating media. This prevents substrate leakage, thereby significantly improving the breakdown voltage of the GaN-FET. In this configuration, the gate can be effectively switched: the gate (typically p-type gallium nitride) can deplete channel carriers (turn off the device) and accumulate channel carriers (turn on the device). However, this results in the substrate being electrically floating, making it difficult for the device to conduct at high frequencies, leading to a higher dynamic on-resistance R. ON (or R) DSON This is attributed to parasitic capacitance generated by defects and traps between the drain and gate; such parasitic capacitance can negatively affect channel conduction due to the virtual back gate (see Wang et al., “Analysis of dynamic on-resistance decay mechanism of commercial gallium nitride HEMT using dual-pulse test”, Vol. 10, p. 1201, Electronics, 2021).

[0005] In another existing method, the gallium nitride epitaxial layer is grown on a sapphire substrate, which also leads to high dynamic range (R). DSON The problem is that in gallium nitride / sapphire structures, the suppression of vertical leakage current is essentially achieved by using sapphire—a natural insulator with low thermal conductivity.

[0006] Therefore, existing methods have performance limitations and have failed to solve a common problem: GaNFETs with such insulating layer configurations are prone to current collapse due to material defects, which affects their dynamic characteristics and reliability. Summary of the Invention

[0007] One aspect of the present invention relates to a field-effect transistor (FET) power switch, comprising: a substrate and a metal layer; two or more layers comprising a gallium-based material; a source, a gate, and a drain; and a control circuit that controls the potential of the metal layer according to the potential of the gate of the FET power switch.

[0008] In one embodiment, the substrate comprises a semiconductor material; the metal layer is disposed below the substrate and electrically connected to the substrate; and the two or more layers comprising gallium-based material are disposed above the substrate.

[0009] In one embodiment, the substrate comprises a non-conductive material; the metal layer is disposed above the substrate; and the two or more layers comprising gallium-based material are disposed above the metal layer.

[0010] In one embodiment, the control circuit controls the potential of the metal layer according to at least a first mode and a second mode; wherein the first mode is determined by the off state of the FET power switch, and the second mode is determined by the on state of the FET power switch.

[0011] According to one embodiment, in the first mode, the potential of the metal layer is floating.

[0012] According to one embodiment, in the second mode, the potential of the metal layer is the same as the potential of the source electrode.

[0013] According to one embodiment, in the second mode, the potential of the metal layer is the same as the potential of the gate.

[0014] According to one embodiment, in the second mode, the potential of the metal layer is proportional to the potential of the gate.

[0015] According to one embodiment, in the second mode, the potential of the metal layer is a monotonic function of the potential of the gate.

[0016] In one embodiment, the control circuit includes a smaller FET having a source, a gate, and a drain; wherein the source and gate of the smaller FET are respectively connected to the source and gate of the FET power switch; wherein the drain of the smaller FET is connected to the metal layer.

[0017] In one embodiment, the smaller FET includes a GaNFET, a GaAsFET, a silicon FET, or a silicon carbide FET.

[0018] In one embodiment, the control circuit includes a smaller FET having a source, a gate, and a drain; wherein the source and gate of the smaller FET are connected together and connected to the gate of the FET power switch; wherein the drain of the smaller FET is connected to the metal layer.

[0019] In one embodiment, the smaller FET includes a GaNFET, a GaAsFET, a silicon FET, or a silicon carbide FET.

[0020] In one embodiment, the control circuit includes a diode; wherein the anode of the diode is connected to the gate of the FET power switch, and the cathode of the diode is connected to the metal layer.

[0021] In one embodiment, the diode includes a GaN diode, a GaAs diode, a silicon diode, or a silicon carbide diode.

[0022] Another aspect of the present invention relates to a bidirectional switch comprising two FET power switches, each FET power switch comprising control circuitry for controlling the potential of a metal layer based on the potential of the gate of the FET power switch, as described in the embodiments herein.

[0023] Another aspect of the present invention relates to a method for controlling a gallium-based FET power switch, comprising: disposing a substrate and a metal layer together with the FET power switch; and using control circuitry to control the potential of the metal layer according to the potential of the gate of the FET power switch.

[0024] In one embodiment of the method, the substrate comprises a semiconductor material, and the metal layer is disposed below the substrate and electrically connected to the substrate; and the FET power switch is disposed above the substrate.

[0025] In one embodiment of the method, the substrate comprises a non-conductive material, and the metal layer is disposed above the substrate; and the FET power switch is disposed above the metal layer.

[0026] In one embodiment of the method, the control circuit controls the potential of the metal layer according to at least a first mode and a second mode; wherein the first mode is determined by the off state of the FET power switch, and the second mode is determined by the on state of the FET power switch.

[0027] In one embodiment of the method, in the first mode, the potential of the metal layer is floating.

[0028] In one embodiment of the method, in the second mode, the potential of the metal layer is the same as the potential of the source of the FET power switch.

[0029] In one embodiment of the method, in the second mode, the potential of the metal layer is the same as the potential of the gate of the FET power switch.

[0030] In one embodiment of the method, in the second mode, the potential of the metal layer is proportional to the potential of the gate of the FET power switch.

[0031] In one embodiment of the method, in the second mode, the potential of the metal layer is a monotonic function of the potential of the gate of the FET power switch.

[0032] In one embodiment of the method, the control circuit includes a smaller FET having a source, a gate, and a drain; wherein the source and gate of the smaller FET are respectively connected to the source and gate of the FET power switch; wherein the drain of the smaller FET is connected to the metal layer. In one embodiment, the smaller FET includes a GaNFET, a GaAsFET, a silicon FET, or a silicon carbide FET.

[0033] In one embodiment of the method, the control circuitry includes a smaller FET having a source, a gate, and a drain; wherein the source and gate of the smaller FET are connected together and connected to the gate of the FET power switch; wherein the drain of the smaller FET is connected to the metal layer. In one embodiment, the smaller FET includes a GaNFET, a GaAsFET, a silicon FET, or a silicon carbide FET.

[0034] In one embodiment of the method, the control circuit includes a diode; wherein the anode of the diode is connected to the gate of the FET power switch, and the cathode of the diode is connected to the metal layer. In one embodiment, the diode includes a GaN diode, a GaAs diode, a silicon diode, or a silicon carbide diode.

[0035] Another aspect of the invention relates to a high-voltage GaNFET based on GaN / silicon technology, having a silicon substrate electrically connected to a bottom metal plate or a bottom metal coating layer (i.e., a bottom metal), the bottom metal being attached to a bottom lead frame using an insulating medium.

[0036] One embodiment includes an electronic control circuit synchronized with a main high-voltage GaNFET gate drive PWM signal, wherein the control circuit is used to control the potential of the bottom metal.

[0037] In one embodiment, the control circuit is configured such that the bottom metal potential is floating when the main GaNFET is in the off state.

[0038] In one embodiment, the control circuit is configured such that when the main GaNFET is in the on state, the bottom metal potential is connected to the source of the main GaNFET.

[0039] In one embodiment, the control circuit is configured such that when the main GaNFET is in the ON state, the bottom metal potential is connected to the gate of the main GaNFET.

[0040] In one embodiment, the control circuit includes a sub-GaNFET integrated on the same GaN die as the main GaNFET, and the sub-GaNFET shares a common source and gate with the main GaNFET, and the drain of the sub-GaNFET is connected to the bottom metal by wire bonding or other means.

[0041] In one embodiment, the control circuit includes a sub-GaNFET integrated on the same GaN die as the main GaNFET, wherein the gate and source of the sub-GaNFET are connected together and connected to the gate of the main GaNFET, and the drain of the sub-GaNFET is connected to the bottom metal by wire bonding or other means.

[0042] In one embodiment, the control circuitry includes a silicon integrated circuit co-packaged with the main GaNFET within the same leadframe, power module, or PCBA.

[0043] In one embodiment, the control circuitry includes a silicon or SiC integrated circuit co-packaged with the main GaNFET within the same leadframe, power module, or PCBA.

[0044] In one embodiment, the high-voltage GaNFET is implemented as a bidirectional GaNFET, wherein the gate of the GaNFET is connected to the bottom metal using a diode or a smaller GaNFET with a source-gate short circuit. Attached Figure Description

[0045] To better understand the present invention and to more clearly demonstrate its implementation, embodiments will be described by way of example with reference to the accompanying drawings, wherein: Figure 1A is a basic structural diagram of a GaNFET grown on a silicon substrate according to the prior art, in which the dummy gate VG is indicated below the gate, and potential defects and traps between the gate and drain that may lead to parasitic capacitance are shown.

[0046] Figure 1B is a basic structural diagram of a GaNFET grown on a silicon substrate with encapsulated lead frame metal, as shown in Figure 1A, according to the prior art.

[0047] Figure 2 is an equivalent circuit model of a GaNFET on a silicon substrate including substrate parasitic elements according to the prior art, wherein the trap defects are described by parasitic capacitances and the substrate is connected to the source contacts of the GaNFET.

[0048] Figure 3 is an equivalent circuit model of a GaNFET on a silicon substrate including substrate parasitic elements according to the prior art, wherein the trap defects are described by parasitic capacitances and the substrate is isolated from other electrodes (floating).

[0049] Figure 4 This is an equivalent circuit model of a GaNFET on a main silicon substrate according to one embodiment, including substrate parasitic elements, wherein trap defects are described by parasitic capacitance, and control circuitry is implemented with a smaller GaNFET (integrated with or co-packaged with the main GaNFET) as a switch connecting the source of the main GaNFET and the floating substrate.

[0050] Figure 5 This is an equivalent circuit model of a GaNFET on a main silicon substrate according to one embodiment, including substrate parasitic elements, wherein trap defects are described by parasitic capacitance, and control circuitry is implemented with a smaller GaNFET (integrated with or co-packaged with the main GaNFET) as a switch to connect the main GaNFET gate to the substrate when the gate voltage is high and to isolate the main GaNFET gate from the substrate when the gate is off.

[0051] Figure 6A and Figure 6B The prior art circuits shown in Figures 2 and 3 are illustrated respectively (Vsub=0 and Vsub floating state, respectively). Figure 4 and Figure 5 Simulation result curves for the illustrated embodiments (representing Vsub s-switch and Vsub g-switch states, respectively): Figure 6A The complete range of voltage waveforms at the virtual gate locations of each circuit is displayed; Figure 6B This shows the waveform at the virtual gate location of the circuit, which is close to zero voltage.

[0052] Figure 7A This is a structural diagram of a main GaNFET and a smaller GaNFET, which serves as a substrate switching device, grown together on a silicon substrate according to one embodiment. The structure includes a metal insert and a lead frame metal, wherein the drain of the smaller GaNFET is connected to the metal insert between the silicon substrate and the bottom lead frame platform.

[0053] Figure 7BThis is a partial layout diagram of a main GaNFET and a smaller GaNFET serving as a substrate switching device at the full GaN-IC level according to one embodiment, wherein two adjacent finger pairs are separated to isolate the smaller GaNFET from the main power switching GaNFET.

[0054] Figure 7C This is a partial layout diagram of a main GaNFET and a smaller GaNFET serving as a substrate switching device at the full GaN-IC level according to one embodiment, wherein the smaller GaNFET is isolated from the main GaNFET, and the SG electrode of the smaller GaNFET is connected together using a metal via, the PWM-in is connected to the S, and the drain of the smaller GaNFET is connected to an open pad that allows wire bonding to the bottom metal plate.

[0055] Figure 8 This is a structural diagram according to one embodiment, showing a main GaNFET and a smaller GaNFET, serving as a substrate switching device, grown together on a sapphire substrate and encapsulated with a leadframe metal. A metal thin film or thin film mesh is used between the sapphire and GaN epitaxial layers, and metal vias connect the substrate switching device (the drain of the smaller GaNFET) downwards to the substrate thin film to achieve substrate potential switching. The sub-GaNFET is configured similarly to... Figure 7B Or 7C.

[0056] Figure 9A The diagram shows two GaNFETs in a common package, where the larger one is the main power switching GaNFET with an input voltage regulator integrated between the main PWM-in input (Vin) and the main GaNFET gate (G), and the smaller GaNFET is used as a switching device to control the substrate potential, according to one embodiment.

[0057] Figure 9B It is shown according to one embodiment Figure 9A The diagram shows the two devices co-packaged in a TO247-4 leadframe, with the smaller GaNFET switching device having an SG short and connected to the PWM-in input.

[0058] Figure 9C It is shown according to one embodiment Figure 9A The diagram shows two devices co-packaged in a TO247-4 leadframe, with the smaller GaNFET switch implementing common source and common gate connections.

[0059] Figure 10A This is a diagram illustrating the package of a GaNFET die for a main power switch according to one embodiment, wherein the control circuitry is implemented using a diode, wherein the PWM-in or gate is connected to the anode of the diode, and the cathode of the diode is connected to a floating metal plate.

[0060] Figure 10B Is it used as Figure 10A The diagram shows a space-saving configuration of the main GaNFET structure for the diode, where the bare diode die is stacked on top of the V-in (or PWM-in or gate) pad of the main GaNFET.

[0061] Figure 11A This is a diagram illustrating a package of a bidirectional main power GaNFET die according to one embodiment, wherein the control circuitry is implemented using two diodes for connecting to the gates G1 and G2 of the two GaNFETs M1 and M2, respectively, to a bottom metal plate.

[0062] Figure 11B This is a diagram illustrating the package of a bidirectional main power GaNFET die according to one embodiment, wherein the control circuitry is implemented using two diodes and two resistors to provide proportional control.

[0063] Figure 11C This is a diagram illustrating the package of a bidirectional main power GaNFET die according to one embodiment, wherein the control circuitry is implemented using two smaller GaNFETs and two resistors to provide proportional control. Detailed Implementation

[0064] The embodiments described herein overcome the aforementioned deficiencies of existing technical solutions. The principles and features of the embodiments can be explained by referring to a GaNFET model including substrate parasitic effects and a virtual gate, as shown in Figures 1, 2, and 3.

[0065] Figure 1A illustrates the basic structure of a GaNFET grown on a silicon substrate using existing technology. This structure includes an AlGaN epitaxial layer 102 covering a two-dimensional electron gas (2DEG) gallium nitride epitaxial layer 104, which in turn is grown on a silicon substrate 106. The metal contacts or electrodes for the source (S), gate (G), and drain (D) are all located on the AlGaN epitaxial layer. Figure 1B is a typical packaged schematic of a GaNFET grown on a silicon substrate (as shown in Figure 1A), where the silicon substrate 106 is bonded to the lead frame package metal 110 using materials such as insulating adhesive 122. The area of ​​the dummy gate VG is marked below the gate. The conduction state of the GaNFET is sensitive to a negative dummy gate bias, which hinders its full conduction, thereby increasing the dynamic drain-source on-resistance R. DSON The concept of a virtual substrate gate is qualitative and, due to parameter uncertainties, is often difficult to model at the circuit level. Traps X (i.e., defects) that may exist between the gate and drain can cause parasitic capacitances, typically located as shown in Figure 1.

[0066] Figure 2 shows the equivalent circuit model of the GaNFET on the silicon substrate shown in Figure 1, where the dashed box includes substrate parasitic elements. These parasitic elements include the gate-drain capacitance Cv-gd, the gate-source capacitance Cv-gs, the gate-drain resistance R2s, the gate-source resistance R1s, and the trap defect described by the parasitic capacitance Ctrap; the substrate resistance Rs and the substrate back gate capacitance Cs are also marked in the figure. According to the prior art, the source contact of this GaNFET is connected to the silicon substrate (i.e., position 106 in Figures 1A and 1B), and the specific connection method is shown by the line connecting the source and point A.

[0067] Figure 3 illustrates an equivalent circuit model of a GaNFET in another prior art embodiment, where the silicon substrate is in an isolated or floating state, i.e., the silicon substrate (point A) is not connected to any of the S, G, or D electrodes of the GaNFET. As mentioned earlier, the conduction state of this GaNFET is highly sensitive to the negative dummy gate bias, which prevents it from fully conducting; in the prior art embodiment shown in Figure 3, this would result in extremely high dynamic Ro. DSON .

[0068] A typical high-voltage GaNFET (using the GPI65030 from GaNPower International, Vancouver, Canada as a representative switching device) was simulated using LTspice (Analog Devices). The simulation was based on the circuits shown in Figures 2 and 3, with the following configuration: total device area of ​​0.3 cm², silicon substrate thickness of 0.03 cm; operating conditions including input pulse width modulation (PWM) signal (pulse parameters 0→6→0→20 ns→20 ns→0.5 ns; on-time 0→100 ms; load resistance RLoad of 100 Ω; bus voltage Vbus of 800 V). Since the resistivity of the silicon substrate is approximately 100 Ω·cm, according to the definition of the virtual gate location, most of the substrate resistance originates from the gallium nitride epitaxial layer. Based on the substrate leakage current estimation at high voltage, the substrate resistance is on the order of MΩ (MΩ), while the substrate back gate capacitance is approximately 1 pF.

[0069] It should be noted that R1s, R2s, Cv-gd, and Cv-gs in Figures 2 and 3 are parasitic resistances and capacitances caused by the GaN epitaxial layer and the silicon substrate bulk material, and their values ​​are determined according to the corresponding device lengths. In this model, the spacing between SG and GD makes the resistance ratio R1s / R2s 1:10 and the capacitance ratio Cv-gd / Cv-gs 10:1. For qualitative analysis, the trap capacitance is set to one-tenth of the substrate capacitance. Simulation results show that if the trap-related parasitic capacitance effect is not considered, the switching waveform has minimal dependence on the substrate potential; this contrasts sharply with experimental results—experiments show that the substrate potential (i.e., whether the silicon substrate is connected to the GaNFET source or is in a floating state) significantly affects the switching behavior and the dynamic resistance characteristics in the on-state.

[0070] The circuits and methods described in this embodiment relate to field-effect transistors (FETs), also known as high electron mobility transistors (HEMTs), which are made of gallium-based semiconductor materials such as gallium nitride (GaN) and gallium arsenide (GaAs). Although the embodiments are primarily described with respect to gallium nitride field-effect transistors, it should be understood that these embodiments can be directly applied to and / or adapted to, for example, gallium arsenide field-effect transistors. The embodiments address material defect problems in such devices, such as traps within the two-dimensional electron gas gallium nitride epitaxial layer, thereby enabling effective control of high-voltage leakage current and dynamic on-resistance in applications such as high-voltage power switches.

[0071] According to specific embodiments, different operating modes can be achieved by controlling the connection between the GaNFET power switch and the substrate, and these different modes correspond to different substrate potentials. For example, specific embodiments may provide one or more of the following modes: floating substrate mode, connected substrate mode with substrate potential the same as GaNFET source potential, connected substrate mode with substrate potential the same as GaNFET gate potential, connected substrate mode with substrate potential proportional to GaNFET gate potential, and connected substrate mode with substrate potential monotonically changing with GaNFET gate potential. In one embodiment, proportional control can be achieved by using a linear element (such as an ideal resistor) during the turn-on phase of the switching cycle; while in another embodiment, a nonlinear element (such as a diode or nonlinear resistor) can be used during the turn-off phase of the switching cycle to achieve single-control functionality.

[0072] Here, two “identical” potentials mean that the two potentials are equal or substantially identical, such that any difference (if any) has a negligible effect on the operating state or performance of the embodiment.

[0073] In this document, "substrate" refers to the bulk material used to grow GaNFET power switches. The substrate can be a semiconductor material, such as silicon or aluminum nitride (AlN), or a non-conductive material such as sapphire or quartz. While this document primarily describes silicon and sapphire substrates as examples, it should be understood that the embodiments are not limited thereto.

[0074] Examples may include control circuitry for GaNFET power switching devices (also referred to herein as a floating substrate switching system). Examples may include control circuitry having at least one substrate switching device specifically designed for switching between a floating substrate mode and a connected substrate mode, with the substrate potential controlled synchronously with the gate of the GaNFET power switch, as exemplified above. The substrate switching device may be implemented using any device with power switching functionality, such as, but not limited to, a JFET, MOSFET, or FET (collectively referred to herein as FET) or a diode. In some embodiments, the substrate switching device may be a GaNFET; in other embodiments, the GaNFET substrate switching device may be integrated with the GaNFET power switch on the same chip (i.e., a monolithic structure); in some embodiments, the substrate switching device may be a FET implemented using other semiconductor technologies, such as, but not limited to, silicon, silicon carbide, or gallium arsenide; in certain embodiments, the substrate switching device may be a FET smaller than the GaNFET power switching device. Here, "smaller" means smaller in size and therefore has a lower current carrying capacity than the GaNFET power switch, but has other similar characteristics (such as the same or substantially the same breakdown voltage). Smaller size is advantageous because cost is proportional to the semiconductor wafer area.

[0075] In this specification, the following terms are used interchangeably: gate and G, drain and D, source and S, input voltage and Vin, and PWM-in (where PWM is a possible way to generate the input voltage signal).

[0076] Now combined Figure 4 The circuit diagram is used to describe one embodiment. For example... Figure 4 As shown, this embodiment includes a GaNFET main power switch M1 (e.g., a representative switch GPI65030) with parasitic resistance and capacitance, based on the model described above and as shown in Figure 2, and a control circuit implemented using a dedicated switch M2—this switch is used to switch between the source and substrate of the main power switch to provide a floating substrate mode and a connected substrate mode. In this embodiment, the additional switch M2 is implemented using a field-effect transistor, which can be smaller than the main power switch M1, and can be manufactured using gallium nitride material (e.g., a representative switch GPIW100 (GaNPower International Inc.)) or other semiconductor technologies (such as silicon). Therefore, in Figure 4In the illustrated embodiment, the control circuit can switch between a floating substrate mode and a connected substrate mode, in which case the substrate (i.e., the bottom metal layer) potential is the same as the source terminal potential of the main power switch M1. This embodiment can also utilize conductive adhesive (also referred to herein as conductive glue, bonding agent, etc.) or other conductive media to create a metal embedding layer (i.e., the bottom metal layer) beneath the substrate, ensuring that the potential of the metal embedding layer matches the substrate potential.

[0077] exist Figure 4 In the illustrated embodiment, the gate of the smaller field-effect transistor M2 (also referred to as the substrate switching device) is connected to the gate of the main power switch M1, the drain of M2 is connected to the substrate, and the sources of M1 and M2 are interconnected. Since the width / size of the smaller field-effect transistor M2 may be much smaller than the main GaNFET M1, its additional cost and any side effects on the main GaNFET are negligible. Figure 4 As shown, when the input drive voltage Vin (or VPWM) is low, the smaller field-effect transistor M2 is in the off state; at this time, the substrate is always suspended in the off state of the main field-effect transistor, thereby achieving a higher breakdown voltage. When the drive voltage VPWM is high, the smaller field-effect transistor M2 is turned on; at this time, the substrate is connected to the source of the main GaNFET M1, forming a substrate connection mode, which effectively prevents substrate leakage and increases the breakdown voltage of the main GaNFET. Using gallium nitride to fabricate the substrate switching device M2 allows it to be integrated with the main power switch in an all-GaN integrated circuit, thereby reducing cost and simplifying the implementation process. In other embodiments, the smaller switch M2 can also be fabricated using other semiconductor technologies such as silicon, and can be selectively co-packaged with the main power switch M1.

[0078] Another implementation method is as follows Figure 5 The circuit diagram is shown below. (And...) Figure 4 The illustrated embodiment is similar. Figure 5 The embodiments also adopted the model described above (and in Figure 5 The diagram illustrates a GaNFET main power switch M1 (e.g., the representative model GPI65030) designed to exhibit its parasitic resistance and capacitance characteristics, along with a control circuit consisting of an additional smaller switch M2 (e.g., the representative model GPIW100, manufactured by GaNPower International Inc.). Figure 5 In this scheme, the additional switch M2 is specifically used to establish a connection between the gate of the main power switch M1 and the substrate through the reverse conduction (or fourth quadrant conduction) of the small-size field-effect transistor M2. For example... Figure 5As shown, the gate and source of the small switch M2 are interconnected and connected to the gate of the main GaNFET M1; the drain of M2 is directly connected to the substrate. When the substrate voltage is higher than the gate voltage of the main GaNFET M1, the smaller field-effect transistor M2 is turned off, thus keeping the substrate in a floating state with the main GaNFET M1 off, achieving a floating substrate operating mode with high breakdown voltage. When the gate drive voltage Vin (VPWM) increases, the smaller field-effect transistor M2 will turn on. In this connected substrate mode, the substrate is connected to the gate of the main GaNFET M1, applying a positive voltage to the floating substrate, causing the virtual gate to also present a positive voltage state, thereby facilitating the opening of the main field-effect transistor's conduction channel. Using gallium nitride to manufacture the smaller switch M2 allows it to become a component of an all-gallium nitride integrated circuit together with the main power switch M1. In other embodiments, the smaller switch M2 can also be manufactured using other semiconductor technologies such as silicon and can be selectively co-packaged with the main power switch.

[0079] Based on the virtual gate circuit model shown in Figure 2, circuit simulation was performed using LTspice (Analog Devices) to verify the above description and... Figure 4 , Figure 5 The performance and advantages of the embodiments shown are illustrated. Simulation results are as follows: Figure 6A and 6B As shown, and presented alongside the results of the traditional schemes in Figures 2 and 3 above: where Vsub=0 corresponds to the scheme in Figure 2, Vsub floating corresponds to the scheme in Figure 3, and Vsub s-switch corresponds to... Figure 4 Solution, Vsub g-switch corresponding Figure 5 plan. Figure 6A It shows the full range of the voltage waveform at the virtual gate. Figure 6B This shows the voltage waveform at that point is close to zero. Simulation results show that in the traditional scheme, the trap-related capacitor Ctrap is fully charged under high Vds conditions when the main GaNFET is off; however, it discharges when the main GaNFET is on, resulting in a negative bias on the virtual gate. Since the on-state of the main GaNFET is highly sensitive to the negative virtual gate bias, this hinders its full conduction, thus leading to the dynamic R in the traditional scheme shown in Figure 3. DSON The value is relatively high. Figure 6A and 6B Simulation data also shows that for both implementation methods ( Figure 4 and Figure 5 The positive bias voltage generated by the substrate potential (labeled as Vsub s-switch and Vsub g-switch, respectively) is higher than that of the traditional schemes in Figures 2 and 3, and can achieve better conduction characteristics.

[0080] Figure 7A An embodiment at the leadframe package level is illustrated, wherein a metal plate or metal insert 708 is bonded to a silicon substrate 706 via conductive adhesive 720, and an insulating adhesive 722 is used to isolate the metal plate 708 from the bottom leadframe metal part 710. A high-voltage small-size GaNFET and a main GaNFET are grown on an AlGaN layer and two-dimensional gallium nitride layers 702 and 704 on the silicon substrate 706, respectively. The high-voltage small-size GaNFET has three electrodes, D2, G2, and S2, located near the edge of the finger array and configured with an independent drain pad D2, which is connected to the bottom metal plate 708 via wire bonding 726. Figure 7A The main GaNFET electrodes D1 and G1 are shown, designed with a gate-around-source layout. To facilitate wire bonding, the bottom metal plate can be slightly larger than the die size of the gallium nitride chip or integrated circuit, but small enough to fit the package lead frame. Figure 7A The configuration in the illustrated embodiment can be applied to Figure 4 or Figure 5 The circuit scheme shown is illustrated. Figure 7A In Chinese, "periodicity" refers to the repetitive arrangement of elements laid out across the entire chip or wafer.

[0081] Figure 7B This is a schematic diagram illustrating a possible layout of a gallium nitride chip according to one embodiment: in which a portion of the gate finger structure is divided into two active regions, while the middle drain finger structure is connected to the top open pad through a metal via, and can then be wire-bonded to the bottom metal plate.

[0082] Figure 7C This is a schematic diagram illustrating a possible structure in which a smaller GaNFET used in the control circuit (i.e., the substrate switching device) is isolated from the main GaNFET in one embodiment: the source (S) and gate (G) terminals of this smaller GaNFET are connected through metal vias, and the PWM-in electrode is connected to the source terminal; its drain is connected to an open pad and can be connected to the bottom metal plate via wire bonding, with a similar structure. Figure 7B As shown.

[0083] This embodiment can also be applied to gallium nitride / sapphire technology, where the substrate is sapphire—a natural insulating material that maintains the floating state of the gallium nitride channel. For example... Figure 8Example of the illustrated embodiment: An AlGaN layer and 2-DEG gallium nitride layers 802 and 804 are grown on a sapphire substrate 807, respectively. A small high-voltage gallium nitride field-effect transistor (GaNFET) with electrodes D2, G2, and S2 is formed on these layers, along with a main GaNFET with electrodes D1 and G1, an S-shaped structure, and surrounded by a G layer. A metal thin film, metal pattern, or metal mesh can be formed below the gallium nitride channel 804 and above the sapphire substrate 807 as a bottom metal layer 820 to control the substrate potential: in a first mode, the bottom metal is in a floating state; in a second mode, the bottom metal potential is the same as the source potential, or equal to, proportional to, or monotonic with the gate potential. Vias with a metal-filled layer 830 can also be formed to connect the small GaNFET to the bottom metal layer 820. The sapphire substrate can be fixed to the lead frame metal part 810 of the package using an insulating or non-insulating adhesive 822.

[0084] Reference Figure 4 and Figure 5 The illustrated embodiment is on a sapphire substrate (such as...) Figure 8 As shown, in this implementation, the resistance value Rs is relatively large while the capacitance value Cs is relatively small, resulting in poor electrical control of the virtual gate from below the sapphire. Therefore, the control point should be set between Cs and Rs. The core objective is still to control the substrate potential, but in this case, the control source is located on the sapphire surface, rather than being controlled from the bottom as in the case of a silicon substrate.

[0085] Figure 9A The illustration shows two gallium nitride field-effect transistor (GaNFET) chips: the larger chip 901 acts as the main power switch, while the smaller chip 902 acts as the control FET (i.e., a substrate switching device used to control the substrate potential). In this embodiment, the two GaNFETs are discretely designed and integrated within the same package; conductive adhesive 920 can be used to secure the chips to the bottom metal layer (not shown). In this configuration, the main GaNFET and the input voltage regulator are integrated between the main drive voltage input (PWM-in) and the main GaNFET gate G. In other embodiments, the two GaNFETs can also be integrated as an integrated circuit on the same chip.

[0086] Figure 9B Demonstrated the use of Figure 9AThe two chips shown are in one embodiment of a TO247-4 co-package leadframe structure: the source (S) and gate (G) terminals of the control GaNFET 902 are shorted and connected to the PWM-in input of the main power switch 901. The two GaNFET chips are fixed to a bottom metal layer 908 (e.g., an aluminum layer) with conductive adhesive, which in turn is connected to the leadframe package metal 910 via insulating adhesive 922. The source of the main power switch 901 is connected to the leadframe package metal 910 (labeled source S) and simultaneously to the Kelvin source KS terminal—which serves as an auxiliary source dedicated to the gate drive circuit. Figure 9C This demonstrates another implementation: using Figure 9B The aforementioned TO247-4 co-package structure and Figure 9A The two chips share a common source and gate connection, with the source and gate of the substrate switching device 902 shorted and connected to the PWM-in input of the main GaNFET 901.

[0087] Figure 10A The diagram illustrates one implementation of a GaNFET main power switch chip 1001: the chip is fixed to a bottom metal layer 1008 (e.g., aluminum) by conductive adhesive 1020, and the bottom metal layer 1008 is fixed to a lead frame package metal (not shown) by insulating adhesive 1022. In this embodiment, the control circuitry is implemented using a diode 1040 made of a different material than gallium nitride (e.g., silicon or silicon carbide). The anode of this diode is connected to the PWM-in input of the main GaNFET 1001, and the cathode is connected to the bottom metal layer 1008. This connection method ensures that when the PWM-in input is positive, the diode controls the bottom metal potential to be close to the PWM-in potential; when the PWM-in input is zero or negative, the bottom metal potential is in a floating state. Figure 10B A cross-sectional view of a space-saving implementation: The bare die of diode 1040 is stacked on the PWM-in input (or Vin) / gate of the main switching device via conductive adhesive 1020, thereby forming an electrical connection with the diode anode. A dielectric material 1044 (e.g., SiN or silicon dioxide) may be disposed between the gate, drain, and source. This implementation is suitable for a leadframe metal package structure: a metal plate or insert 1008 is bonded to a silicon substrate 1006 via conductive adhesive 1020, and an insulating adhesive 1022 is used to isolate the metal plate 1008 from the bottom leadframe metal component 1010. The main GaNFET is grown on an AlGaN layer and 2-DEG gallium nitride layers 1002 and 1004 on the silicon substrate 1006, respectively. The cathode of diode 1040 is connected to the bottom metal layer 1008 via wire bonding 1026.

[0088] Figure 11AA schematic diagram of an embodiment employing a bidirectional switching structure is shown, which integrates two power switching GaNFETs, M11 and M22, on a single chip 1101. Chip 1101 is bonded to a bottom metal layer 1108 (e.g., an aluminum plate) via conductive adhesive 1120, and the bottom metal layer is connected to a lead frame package metal (not shown) via insulating adhesive 1122. Both GaNFETs M11 and M22 are equipped with diodes 1141 and 1142: these two diodes are connected from the gate G11 of M11 and the gate G22 of M22, respectively, to the bottom metal layer 1108 (i.e., forming the shared sources S11 and S22 of M11 and M22). For M11 and M22, the cathodes of the corresponding diodes 1141 and 1142 are connected to the gates, and the anodes are connected to the bottom metal layer. In this embodiment, the circuit design of S11-G11-S22-S22 allows S11 and S22 to alternately act as the drain of another source depending on the direction of the high voltage bias (HV).

[0089] Figure 11B Showing with Figure 11A The illustrated embodiment shows another bidirectional switch structure similar to the one shown, but in this embodiment, the control circuit proportionally controls the substrate potential. Resistors 1161 and 1162 have resistance values ​​ranging from approximately 10 MΩ to 500 MΩ and are connected from gates G11 and G22 to the bottom metal layer 1108, respectively.

[0090] Figure 11C Showing with Figure 11A The illustrated embodiment shows another bidirectional switch structure similar to the one shown, but in this embodiment, the control circuit proportionally controls the substrate potential. Smaller GaNFETs 1151 and 1152 are connected to the gates G11 and G22 of the corresponding power GaNFETs M11 and M22, respectively; resistors 1161 and 1162 (with resistance values ​​ranging from approximately 10 MΩ to 500 MΩ) are connected from the gates G11 and G22 to the bottom metal layer 1108, respectively.

[0091] All cited references are included in this paper in their full text via reference.

[0092] equivalent Although the present invention has been described in conjunction with its exemplary embodiments, it should be understood that various modifications can be made to these embodiments without departing from the scope of the invention. Therefore, the embodiments described are merely illustrative and should not be construed as limiting the invention thereto.

Claims

1. A field-effect transistor (FET) power switch; comprising: Substrate and metal layer; Two or more layers containing gallium-based material; Source, gate, and drain; as well as A control circuit that controls the metal layer potential based on the gate potential of a field-effect transistor power switch.

2. The field-effect transistor power switch as described in claim 1, wherein: The substrate includes a semiconductor material; The metal layer is disposed below the substrate and is electrically connected to the substrate; The two or more layers comprising gallium-based material are disposed above the substrate.

3. The field-effect transistor power switch as described in claim 1, wherein: The substrate comprises a non-conductive material; The metal layer is disposed above the substrate; The two or more layers containing gallium-based material are disposed above the metal layer.

4. The field-effect transistor power switch of claim 1, wherein the control circuit controls the potential of the metal layer according to at least a first mode and a second mode; The first mode is determined by the off state of the field-effect transistor power switch, and the second mode is determined by the on state of the field-effect transistor power switch.

5. The field-effect transistor power switch of claim 4, wherein the potential of the metal layer is in a floating state in the first mode.

6. The field-effect transistor power switch of claim 4, wherein in the second mode, the potential of the metal layer is the same as the potential of the source.

7. The field-effect transistor power switch of claim 4, wherein in the second mode, the potential of the metal layer is the same as the potential of the gate.

8. The field-effect transistor power switch of claim 4, wherein in the second mode, the potential of the metal layer is proportional to the potential of the gate.

9. The field-effect transistor power switch of claim 4, wherein in the second mode, the potential of the metal layer is a monotonic function of the gate potential.

10. The field-effect transistor power switch of claim 1, wherein the control circuit comprises a smaller field-effect transistor having a source, a gate, and a drain; The source and gate of the smaller field-effect transistor are respectively connected to the source and gate of the field-effect transistor power switch; The drain of a smaller field-effect transistor is connected to a metal layer.

11. The field-effect transistor power switch of claim 1, wherein the control circuit comprises a smaller field-effect transistor having a source, a gate, and a drain; The smaller field-effect transistors have their source and gate interconnected, and are both connected to the gate of the field-effect transistor power switch. The drain of the smaller field-effect transistor is connected to the metal layer.

12. The field-effect transistor power switch of claim 1, wherein the control circuit includes a diode; in, The anode of the diode is connected to the gate of the field-effect transistor power switch, while the cathode of the diode is connected to the metal layer.

13. A bidirectional switch comprising two field-effect transistor power switches as described in claim 1.

14. A method for controlling a gallium-based field-effect transistor (FET) power switch, comprising: The substrate and metal layer are disposed together with the power switch of the field-effect transistor; The potential of the metal layer is controlled by a control circuit based on the potential of the gate of the power switch of the field-effect transistor.

15. The method of claim 14, wherein: The substrate includes a semiconductor material, and a metal layer is disposed below the substrate and electrically connected to the substrate; The field-effect transistor power switch is positioned above the substrate.

16. The method of claim 14, wherein: The substrate comprises a non-conductive material, and a metal layer is disposed on the substrate; The power switch of the field-effect transistor is located above the metal layer.

17. The method of claim 14, wherein the control circuit controls the potential of the metal layer according to at least a first mode and a second mode; The first mode is determined by the off state of the field-effect transistor power switch, and the second mode is determined by the on state of the field-effect transistor power switch.

18. The method of claim 17, wherein in the first mode, the potential of the metal layer is in a floating state.

19. The method of claim 17, wherein in the second mode, the potential of the metal layer is the same as the potential of the source of the field-effect transistor power switch.

20. The method of claim 17, wherein in the second mode, the potential of the metal layer is the same as the potential of the gate of the field-effect transistor power switch.

21. The method of claim 17, wherein in the second mode, the potential of the metal layer is proportional to the potential of the gate of the field-effect transistor power switch.

22. The method of claim 17, wherein in the second mode, the potential of the metal layer is a monotonic function of the gate potential of the power switch of the field-effect transistor.

23. The method of claim 14, wherein the control circuitry comprises a small field-effect transistor having a source, a gate, and a drain; The smaller field-effect transistor's source and gate are connected to the source and gate of the field-effect transistor power switch, respectively. The drain of the smaller field-effect transistor is connected to the metal layer.

24. The method of claim 14, wherein the control circuitry comprises a small field-effect transistor having a source, a gate, and a drain; The smaller field-effect transistors have their source and gate interconnected, and are both connected to the gate of the field-effect transistor power switch. The drain of the smaller field-effect transistor is connected to the metal layer.

25. The method of claim 14, wherein the control circuit comprises a diode; in, The anode of the diode is connected to the gate of the field-effect transistor power switch, while the cathode of the diode is connected to the metal layer.

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