Array substrate, display panel and display method

Abstract

An array substrate (10) includes: an array substrate (BP1); a pixel circuit layer including a pixel circuit, a photosensitive circuit, and a photosensitive element (SM3), wherein the photosensitive circuit and the photosensitive element (SM3) are connected; and a reflective layer (BM) having a light-transmitting area (ANO1), wherein the orthogonal projection of the light-transmitting area (ANO1) on the pixel circuit layer overlaps with a photoelectric conversion unit (PIN1), and the reflective layer (BM) includes a pixel electrode (ANO) connected to the pixel circuit. The light control characteristics of the array substrate (10) are achieved through the arrangement of the photosensitive circuit and the photosensitive element (SM3); and for a display panel (100) including the array substrate (10), an auxiliary light-emitting device can be used to achieve air-to-ground or press-to-grip interaction with the display panel (100), thereby improving the operability of the display panel (100).

Description

Array substrate, display panel and display method Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to an array substrate, a display panel, and a display method. Background Technology

[0002] Total internal reflection (TIR) ​​panels are display panels that display images by reflecting ambient light. This eliminates the need for a backlight and reduces power consumption, leading to their widespread use. However, in these technologies, displaying the next frame requires the user to walk in front of the TIR panel for touch control, increasing the complexity of user interaction.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide an array substrate, a display panel, and a display method.

[0005] According to one aspect of this disclosure, an array substrate is provided, comprising:

[0006] Array substrate;

[0007] A pixel circuit layer is located on one side of the array substrate and includes a pixel circuit, a photosensitive circuit, and a photosensitive element. The photosensitive element includes a photoelectric conversion unit, and the photosensitive circuit is connected to the photosensitive element.

[0008] A reflective layer is located on the side of the pixel circuit layer opposite to the array substrate and has a light-transmitting area. The orthogonal projection of the light-transmitting area on the pixel circuit layer overlaps with the photoelectric conversion unit. The reflective layer includes a pixel electrode, which is connected to the pixel circuit.

[0009] According to any of the array substrates described in this disclosure, the pixel circuit layer includes a planarization layer covering the photosensitive element;

[0010] The planarization layer has a light-transmitting hole, and the light-transmitting area, the light-transmitting hole, and the photoelectric conversion unit have an overlapping region on the array substrate.

[0011] According to any of the array substrates described in this disclosure, the reflective layer includes voltage signal lines connected to the photosensitive element.

[0012] According to any of the array substrates described in this disclosure, the light-transmitting area is a light-transmitting notch on the pixel electrode.

[0013] According to any of the array substrates described in this disclosure, the orthographic projection of the photoelectric conversion unit on the array substrate and the orthographic projection of the plurality of pixel electrodes on the array substrate both have overlapping areas.

[0014] According to any of the array substrates described in this disclosure, at least one of the pixel electrodes has a light-transmitting notch.

[0015] According to any of the array substrates described in this disclosure, the array substrate includes a display area and a peripheral area located outside the display area;

[0016] The pixel circuit, the photosensitive circuit, and the photosensitive element are all located in the display area. The pixel circuit layer also includes driving data lines, driving scan lines, photosensitive data lines, and photosensitive scan lines extending to the peripheral area.

[0017] In the peripheral area, the driving scan line and the photosensitive scan line are located on both sides of the display area along the row direction, and the driving data line and the photosensitive data line are located on the same side of the display area along the column direction, and are located in different film layers.

[0018] According to any of the array substrates described in this disclosure, the pixel circuit layer includes a photosensitive layer, and the photosensitive layer includes a first conductive layer, a photoelectric conversion layer and a second conductive layer sequentially stacked in a direction away from the array substrate.

[0019] The first conductive layer includes a first electrode, the second conductive layer includes a second electrode, the photoelectric conversion layer includes the photoelectric conversion unit, the first electrode, the second electrode, and the photoelectric conversion unit constitute a photosensitive element, and the first electrode is connected to the photosensitive circuit. The second conductive layer is a light-transmitting layer, and the photoelectric conversion unit and the light-transmitting area have an overlapping region on the array substrate.

[0020] According to any of the array substrates described in this disclosure, the pixel circuit includes a driving transistor, the pixel circuit layer includes a driving layer located between the photosensitive layer and the array substrate, and the driving layer includes:

[0021] A gate metal layer is located on one side of the array substrate and includes a first conductive portion;

[0022] A gate insulating layer is located on the side of the gate metal layer opposite to the array substrate, and at least covers the first conductive portion;

[0023] An active layer is located on the side of the gate insulating layer away from the array substrate, and includes a first active portion, the first active portion including a first channel region and a first connection portion and a second connection portion located on both sides of the first channel region;

[0024] A source / drain metal layer is located on the side of the active layer away from the array substrate, and includes a first connection line, the two ends of which are electrically connected to the first connection portion and the pixel electrode, respectively.

[0025] The first connecting portion and the second connecting portion respectively form the first electrode and the second electrode of the driving transistor. The second electrode of the driving transistor is used to load a data signal. The area on the first conductive portion that overlaps with the first channel region forms the control electrode of the driving transistor. The control electrode of the driving transistor is used to load a scan signal.

[0026] According to any of the array substrates described in this disclosure, the first conductive layer further includes a first light-shielding portion, the orthogonal projection of the first light-shielding portion onto the active layer at least covering the first channel region.

[0027] According to any of the array substrates described in this disclosure, the gate metal layer further includes a first auxiliary electrode, and the source / drain metal layer further includes a second auxiliary electrode;

[0028] The gate insulating layer covers the first auxiliary electrode, the second auxiliary electrode is connected to the first connection line, and the orthogonal projections of the first auxiliary electrode and the second auxiliary electrode on the array substrate have an overlapping area.

[0029] According to any of the array substrates described in this disclosure, the spacing between the first auxiliary electrode and the second auxiliary electrode is greater than or equal to 3500 angstroms and less than or equal to 4500 angstroms.

[0030] According to any of the array substrates described in this disclosure, the first conductive layer further includes a third auxiliary electrode;

[0031] The third auxiliary electrode is connected to the first auxiliary electrode through a via, and the third auxiliary electrode and the second auxiliary electrode have overlapping regions in their orthogonal projections on the array substrate.

[0032] According to any of the array substrates described in this disclosure, the distance between the first auxiliary electrode and the second auxiliary electrode is greater than or equal to 3500 angstroms and less than or equal to 4500 angstroms, and the distance between the second auxiliary electrode and the third auxiliary electrode is greater than or equal to 2500 angstroms and less than or equal to 3500 angstroms.

[0033] According to one aspect of this disclosure, a display panel is provided, including a color filter substrate and an array substrate as described in the above aspect disposed opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate.

[0034] According to any of the display panels described in this disclosure, a spacer is provided between the array substrate and the color filter substrate, and the spacer is spherical.

[0035] According to one aspect of this disclosure, a display method for a display panel is provided, the display method being applied to the display panel described in the above aspect, wherein the pixel circuit includes a driving transistor, the photosensitive circuit includes a photosensitive transistor, the control electrode of the photosensitive transistor is used to load a first level signal, the first electrode of the photosensitive transistor is used to load a second level signal, the second electrode of the photosensitive transistor is connected to a first electrode of a photosensitive element, and the second electrode of the photosensitive element is used to load a third level signal.

[0036] The display panel includes a display phase and a blanking phase, the blanking phase including an illumination phase, a reading phase, and a feedback phase, and the display method includes:

[0037] During the display phase, data signals and scan signals are transmitted to the driving transistor based on the image information of the current frame, so that the display panel displays the image of the current frame;

[0038] During the illumination phase, a low-level first-level signal is input to the control electrode of the phototransistor to turn the phototransistor off; simultaneously, the photosensitive element performs photoelectric conversion on the received light beam.

[0039] During the reading phase, a high-level first-level signal is input to the control electrode of the phototransistor to turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element, so as to obtain the actual charge amount of the second-level signal after the charge in the photosensitive element flows to the first electrode of the phototransistor.

[0040] During the feedback phase, the target photosensitive element is determined based on the actual charge amount, and the display information of the next frame is determined based on the position information of the target photosensitive element, and then the process returns to the display phase.

[0041] According to any of the display methods described in this disclosure, the display method further includes:

[0042] During the display phase, a high-level first-level signal is periodically input to the control electrode of the phototransistor to periodically turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element to correct the amount of charge in the photosensitive element.

[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0044] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0045] Figure 1 is a cross-sectional structural diagram of a display panel provided in an embodiment of this disclosure.

[0046] Figure 2 is a cross-sectional structural diagram of another display panel provided in an embodiment of this disclosure.

[0047] Figure 3 is a schematic diagram of the membrane structure of a driving layer provided in an embodiment of this disclosure.

[0048] Figure 4 is a schematic diagram of a driving circuit and a photosensitive circuit provided in an embodiment of this disclosure.

[0049] Figure 5 is a schematic diagram of the film structure of a photosensitive layer provided in an embodiment of this disclosure.

[0050] Figure 6 is a schematic diagram of the film structure of a pixel circuit layer provided in an embodiment of this disclosure.

[0051] Figure 7 is a schematic diagram of another pixel circuit layer film structure provided in the embodiments of this disclosure.

[0052] Figure 8 is a cross-sectional view of the display panel corresponding to Figure 7.

[0053] Figure 9 is a schematic diagram of another driving layer structure provided in this embodiment.

[0054] Figure 10 is a cross-sectional view of the display panel corresponding to Figure 9.

[0055] Figure 11 is a schematic diagram of another driving layer provided in the embodiments of this disclosure.

[0056] Figure 12 is a cross-sectional view of the display panel corresponding to Figure 11.

[0057] Figure 13 is a top view of an array substrate provided in an embodiment of this disclosure.

[0058] Figure 14 is a schematic diagram of the array distribution of a pixel circuit provided in an embodiment of this disclosure.

[0059] Figure 15 is a schematic diagram of the display timing of a display screen provided in an embodiment of this disclosure.

[0060] Figure 16 is a schematic diagram of the display process of a display screen provided in an embodiment of this disclosure.

[0061] Reference numerals: 100, Display panel; AA, Display area; BB, Peripheral area; B1, Driving module; B2, Photosensitive module; 10, Array substrate; 20, Color filter substrate; 30, Liquid crystal layer; 40, Spacer; BP1, Array substrate; DR, Driving layer; SM, Photosensitive layer; BM, Reflective layer; PVX1, First passivation layer; PLN, Planarization layer; PVX2, Second passivation layer; Buff, Buffer layer; ST1, Driving transistor; ST2, Photosensitive transistor; Ga, Gate metal layer; GI, Gate insulating layer; ACT, Active layer; SD, Source / drain metal layer; G1, First conductive part; G2, Second conductive part; G3, First auxiliary electrode; DG, Driving scan line; MG, Photosensitive scan line; P1, First active part; P11, First channel region; P12, First connecting part; P13, Second connecting part; P2, Second active part; P21, Second channel region; P22, Third connecting part; P23, Fourth connecting part; SD1, First connecting line; SD2, Second connecting line; SD3, Third connecting line; SD4, Fourth connecting line; SD5, Second auxiliary electrode; DD, Drive data line; MD, Photosensitive data line; SM1, First conductive layer; PIN, Photoelectric conversion layer; SM2, Second conductive layer; SM3, Photosensitive element; SM11, First electrode; SM12, Third auxiliary electrode; SM13, First light-shielding part; SM14, Second light-shielding part; PIN1, Photoelectric conversion unit; SM21, Second electrode; ANO, Pixel electrode; ANO1, Light-transmitting area; VDD, Voltage signal line; PLN1, Light-transmitting hole; BP2, Color filter substrate; COM, Common electrode layer. Detailed Implementation

[0062] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0063] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0064] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0065] A transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain electrode) and the source electrode (source terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. The channel region is the area through which the current primarily flows.

[0066] The first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0067] Figure 1 illustrates a cross-sectional structural schematic diagram of a display panel 100 provided in this embodiment of the present disclosure. As shown in Figure 1, the display panel 100 includes: an array substrate 10 and a color filter substrate 20 disposed opposite to each other, and a liquid crystal layer 30 located between the array substrate 10 and the color filter substrate 20.

[0068] A spacer 40 is provided between the array substrate 10 and the color filter substrate 20 to ensure the cell thickness of the display panel 100, thereby ensuring the thickness of the liquid crystal layer 30. The spacer 40 can be a right prism structure, for example, as shown in Figure 1, the cross-section of the spacer 40 is an inverted trapezoidal structure; of course, the spacer 40 can also have other structures, for example, the spacer 40 is spherical, that is, as shown in Figure 2, the cross-section of the spacer 40 is circular. When the spacer 40 is spherical, it is easier to simplify the manufacturing process of the color filter substrate 20, thereby reducing development and manufacturing costs.

[0069] In addition, a frame is provided between the array substrate 10 and the color filter substrate 20, and the spacer 40 is located in the area enclosed by the frame. The frame is used to bond and fix the array substrate 10 and the color filter substrate 20, and at the same time, it isolates the liquid crystal layer 30 from the outside world to prevent moisture and other substances from entering.

[0070] It should be noted that the display panel 100 can be a backlight-free structure to achieve a low-power design. In this case, the color filter substrate 20 is a light-transmitting design, and the array substrate 10 has a reflective layer BM close to the color filter substrate 20 to reflect the natural light passing through the color filter substrate 20, thereby displaying the image on the display panel 100.

[0071] In some embodiments, as shown in FIG1 or FIG2, the color filter substrate 20 includes a color filter substrate BP2, and a common electrode layer COM and a first alignment layer (not shown in the figure) sequentially stacked on the side of the color filter substrate BP2 near the array substrate 10.

[0072] Taking the display panel 100 as an example of a backlight structure, the color filter substrate BP2, the common electrode layer COM, and the first alignment layer are all designed to be transparent.

[0073] The color filter substrate BP2 can be a single-layer transparent structure such as a glass substrate, quartz substrate, or plastic substrate. Alternatively, the color filter substrate BP2 can be a multi-layer transparent structure. For example, the color filter substrate BP2 includes a first polyimide layer, a first protective layer, a second polyimide layer, and a second protective layer stacked sequentially. The two protective layers protect the polyimide layers and prevent damage from subsequent processes. The common electrode layer COM can be a transparent conductive layer, such as an indium tin oxide layer.

[0074] It should be noted that the color filter substrate 20 with the above-mentioned film structure can realize the display of black and white images. Furthermore, a filter layer (for example, located between the color filter substrate 20 and the common electrode layer COM) can be provided in the color filter substrate 20 to realize the display of full-color images, thereby improving the display effect of the display panel 100. In addition, the common electrode layer COM included in the color filter substrate 20 can also be provided in the array substrate 10, that is, the color filter substrate 20 used for displaying black and white images only includes the color filter substrate BP2 and the first alignment layer.

[0075] In some embodiments, as shown in FIG1 or FIG2, the array substrate 10 includes an array substrate BP1, and a pixel circuit layer (not shown in the figure), a reflective layer BM, and a second alignment layer (not shown in the figure) sequentially stacked on the side of the array substrate BP1 near the color filter substrate 20.

[0076] The pixel circuit layer includes an array of pixel circuits (shown as driving transistor ST1 in the figure), and the reflective layer BM includes an array of pixel electrodes ANO. One pixel circuit is connected to one pixel electrode ANO, so that the pixel circuit applies a voltage to the connected pixel electrode ANO, and then the electric field formed with the common electrode layer COM on the color filter substrate 20 causes the liquid crystal molecules of the liquid crystal layer 30 to deflect, thereby realizing the display of the image. After the pixel circuit stops applying voltage to the pixel electrode ANO, the display of the image can continue to be maintained based on the parallel capacitance C1 formed by the pixel electrode ANO and the common electrode layer COM.

[0077] It should be noted that, in conjunction with the color filter substrate 20 described above, when the color filter substrate 20 does not include the common electrode layer COM, the common electrode layer COM can be located between the reflective layer BM and the second alignment layer of the array substrate 10, and an insulating layer (such as a passivation layer) is provided between the reflective layer BM and the common electrode layer COM to ensure the insulation between the pixel electrode ANO and the common electrode layer COM.

[0078] In some embodiments, as shown in Figures 1 and 2, the pixel circuit layer includes a driving layer DR located between the array substrate BP1 and the reflective layer BM. Specifically, as shown in Figure 1 or Figure 2 and Figure 3, the driving layer DR includes a gate metal layer Ga, a gate insulating layer GI, an active layer ACT, and a source / drain metal layer SD that are sequentially stacked on the array substrate BP1.

[0079] The array substrate BP1 can be a glass substrate, quartz substrate, plastic substrate or other transparent substrate; or the array substrate BP1 is a multilayer structure. For example, the array substrate BP1 includes a first polyimide layer, a first protective layer, a second polyimide layer and a second protective layer stacked in sequence. The two protective layers are used to protect the polyimide layer and prevent subsequent processes from damaging the polyimide layer.

[0080] In this design, the gate metal layer Ga can be a single-layer or multi-layer structure. The gate metal layer Ga is used to form the conductive portion of the transistor (i.e., the control electrode of the transistor) in the pixel circuit, as well as traces such as scan lines. The active layer ACT can be a single-layer or multi-layer structure. The active layer ACT is used to form the active portion of the transistor in the pixel circuit, including the channel region and two connection portions located on either side of the channel region (i.e., the source and drain of the transistor). The source / drain metal layer SD can be a single-layer or multi-layer structure, etc. The source / drain metal layer SD is used to form data lines, connection lines, and other traces.

[0081] In addition, as shown in Figure 1 or Figure 2, the driving layer DR also includes a first passivation layer PVX1 located on the side of the source / drain metal layer SD away from the array substrate BP1, so as to protect the source / drain metal layer SD through the first passivation layer PVX1 and extend the lifetime of the source / drain metal layer SD.

[0082] Taking the pixel circuit shown in Figure 4, which includes a driving transistor ST1, as an example, as shown in Figure 3, the gate metal layer Ga includes a first conductive portion G1; the gate insulating layer GI at least covers the first conductive portion G1; the active layer ACT includes a first active portion P1, which includes a first channel region P11 and a first connection portion P12 and a second connection portion P13 located on both sides of the first channel region P11.

[0083] Thus, the first and second electrodes of the driving transistor ST1 can be formed by the first connecting portion P12 and the second connecting portion P13 respectively, and the control electrode of the driving transistor ST1 can be formed by the area on the first conductive portion G1 that overlaps with the first channel region P11.

[0084] Additionally, as shown in Figures 3 and 4, the gate metal layer Ga typically includes a drive scan line DG, and the source / drain metal layer SD includes a first connection line SD1, a second connection line SD2, and a drive data line DD. The drive scan line DG is connected to the first conductive part G1 (or is an integral design) to load a scan signal onto the first conductive part G1 (i.e., the control electrode of the drive transistor ST1), thereby controlling the conduction or disconnection of the drive transistor ST1. One end of the first connection line SD1 is connected to the first connection part P12 (the first electrode of the drive transistor ST1) (e.g., directly covering the first connection part P12), and the other end is connected to the pixel electrode ANO through a via. One end of the second connection line SD2 is connected to the drive data line DD (or is an integral design), and the other end is connected to the second connection part P13 (the second electrode of the drive transistor ST1) (e.g., directly covering the second connection part P13), so that a data signal is loaded onto the second conductive part G2 (i.e., the second electrode of the drive transistor ST1) through the drive data line DD, thereby loading a voltage onto the pixel electrode ANO when the drive transistor ST1 is turned on.

[0085] In some embodiments, as shown in FIG1 or FIG2, the pixel circuit layer of the array substrate 10 further includes a photosensitive circuit (shown as photosensitive transistor ST2 in the figure) and a photosensitive element SM3. The photosensitive element SM3 includes a photoelectric conversion unit PIN1, and the photosensitive circuit is connected to the photosensitive element SM3. The reflective layer BM has a light-transmitting area ANO1, and the orthographic projection of the light-transmitting area ANO1 on the pixel circuit layer overlaps with the photoelectric conversion unit PIN1.

[0086] Thus, by setting up the photosensitive circuit and photosensitive element SM3 in the pixel circuit layer, the light control characteristics of the array substrate 10 are realized, and the array substrate 10 can be controlled by auxiliary light-emitting devices such as button laser pointers or press-type laser pointers; and for the display panel 100 including the array substrate 10, the effect of air-to-air interaction or press-type interaction with the display panel 100 can be realized by auxiliary light-emitting devices, thereby improving the operability and user stickiness of the display panel 100.

[0087] In conjunction with the film structure of the pixel circuit layer described above, taking the photosensitive circuit including the photosensitive transistor ST2 as shown in Figure 4 as an example, as shown in Figures 3 and 4, the gate metal layer Ga also includes a second conductive part G2; the gate insulating layer GI also covers the second conductive part G2; the active layer ACT includes a second active part P2, the second active part P2 includes a second channel region P21 and a third connection part P22 and a fourth connection part P23 located on both sides of the second channel region P21.

[0088] Thus, the first and second electrodes of the photosensitive transistor ST2 can be formed by the third connecting part P22 and the fourth connecting part P23 respectively, and the control electrode of the photosensitive transistor ST2 can be formed by the area on the second conductive part G2 that overlaps with the second channel region P21.

[0089] Additionally, as shown in Figures 1, 3, and 4, the photosensitive element SM3 includes a photoelectric conversion unit PIN1 and a first electrode SM11 and a second electrode SM21 located on both sides of the photoelectric conversion unit. The gate metal layer Ga also includes a photosensitive scan line MG, and the source / drain metal layer SD includes a third connection line SD3, a fourth connection line SD4, and a photosensitive data line MD. The photosensitive scan line MG is connected to the second conductive part G2 (or is an integral design) to load a first level signal onto the second conductive part G2 (i.e., the control electrode of the photosensitive transistor ST2) through the photosensitive scan line MG. One end of the four connecting lines SD4 is connected to the fourth connecting portion P23 (i.e., the second electrode of the photosensitive transistor ST2) (e.g., directly covering the fourth connecting portion P23), and the other end is connected to the photosensitive element SM3 (first electrode SM11) through a via. One end of the third connecting line SD3 is connected to the photosensitive data line MD (or is an integral design), and the other end is connected to the third connecting portion P22 (i.e., the first electrode of the photosensitive transistor ST2) (e.g., directly covering the third connecting portion P22), so that a second level signal is loaded on the third connecting portion P22 through the photosensitive data line MD. In addition, as shown in Figure 1 or Figure 2, the array substrate 10 also includes a voltage signal line VDD, which is connected to the photosensitive element SM3 and is used to load the third level signal.

[0090] In this way, a high-level first-level signal can be applied to the second conductive part G2 (i.e., the control electrode of the phototransistor) via the photosensitive scan line MG to control the phototransistor ST2 to conduct. Simultaneously, a second-level signal is applied to the third connecting part P22 (i.e., the first electrode of the phototransistor ST2) via the photosensitive data line MD, and a third-level signal is applied to the photosensitive element SM3 via the voltage signal line VDD. It is ensured that the second-level signal and the third-level signal are different, so that the charge obtained from photoelectric conversion by the photosensitive element SM3 flows towards the high-level direction (e.g., the photosensitive data line MD), and the electrons flow towards the low-level direction (e.g., the voltage signal line VDD). Furthermore, when a change in current (change in charge or electron quantity) is detected in either the second-level or third-level signal, a corresponding control command is determined based on the position information of the photosensitive element SM3, thereby controlling the displayed image.

[0091] The voltage signal line VDD included in the array substrate 10 can be located in the pixel circuit layer or the reflective layer BM, i.e., it is disposed in the same layer as the pixel electrode ANO. When the voltage signal line VDD is located in the pixel circuit layer, the orthogonal projection of the pixel electrode ANO on the array substrate BP1 can be configured to completely cover the orthogonal projection of the photosensitive element SM3 on the array substrate BP1, so as to ensure the pixel aperture ratio on the array substrate 10. As shown in Figure 5, when the voltage signal line VDD is located in the reflective layer BM, since the voltage signal line VDD is a narrow signal trace, the influence of the voltage signal line VDD on the pixel aperture ratio can be ignored, i.e., the pixel aperture ratio on the array substrate 10 is guaranteed.

[0092] It should be noted that when the voltage signal line VDD is located in the reflective layer BM, in order to avoid the electric field formed by the voltage signal line VDD and the common electrode layer COM of the color filter substrate 20 affecting the deflection of the liquid crystal molecules, the third level signal loaded on the voltage signal line VDD can be low level (i.e., the voltage loaded on the voltage signal line VDD is basically equal to the voltage loaded on the common electrode layer COM), and the second level signal loaded on the corresponding photosensitive data line MD is high level. At this time, when the photosensitive transistor ST2 is turned on, the charge obtained by the photoelectric conversion of the photosensitive unit flows to the photosensitive data line MD, and the electrons flow to the voltage signal line VDD.

[0093] In some embodiments, as shown in Figure 5, the pixel electrode ANO has a light-transmitting notch, which constitutes the light-transmitting region ANO1 of the reflective layer BM. This facilitates reducing the impact of the light-transmitting region ANO1 on the pixel aperture ratio.

[0094] Alternatively, the light-transmitting region ANO1 can be located outside the pixel electrode ANO, meaning that at least a portion of the orthogonal projection of the photoelectric conversion unit PIN1 onto the array substrate BP1 extends beyond the orthogonal projection of the pixel electrode ANO onto the array substrate BP1. In this way, the light-transmitting region ANO1 on the reflective layer BM will not interfere with the pixel electrode ANO, thereby simplifying the fabrication of the pixel electrode ANO on the reflective layer BM.

[0095] Specifically, for the photosensitive element SM3 and pixel electrode ANO included in the pixel circuit layer, one photosensitive element SM3 can correspond to one pixel electrode ANO, that is, the orthogonal projection of the photoelectric conversion unit PIN1 of one photosensitive element SM3 on the array substrate BP1 only overlaps with the orthogonal projection of one pixel electrode ANO on the array substrate BP1; or one photosensitive element SM3 can correspond to multiple pixel electrodes ANO, that is, the orthogonal projection of the photoelectric conversion unit PIN1 of one photosensitive element SM3 on the array substrate BP1 overlaps with the orthogonal projection of multiple pixel electrodes ANO on the array substrate BP1.

[0096] In conjunction with the above-mentioned case where the pixel electrode ANO has a light-transmitting notch, when one photosensitive element SM3 corresponds to multiple pixel electrodes ANO, at least one pixel electrode ANO has a light-transmitting notch. That is, one pixel electrode ANO may have a light-transmitting notch, or multiple pixel electrodes ANO may have light-transmitting notches. Thus, the photoelectric conversion unit PIN1 can receive the light beam through multiple light-transmitting notches.

[0097] In some embodiments, as shown in FIG1 or FIG2 and FIG6, the pixel circuit layer includes a photosensitive layer SM, which includes a first conductive layer SM1, a photoelectric conversion layer PIN, and a second conductive layer SM2 stacked sequentially in a direction away from the array substrate BP1; the first conductive layer SM1 includes a first electrode SM11, the photoelectric conversion layer PIN includes a photoelectric conversion unit PIN1, and the second conductive layer SM2 includes a second electrode SM21. The first electrode SM11, the second electrode SM21, and the photoelectric conversion unit PIN1 constitute a photosensitive element SM3.

[0098] In this configuration, the orthographic projections of the first electrode SM11 and the second electrode SM21 onto the array substrate BP1 overlap with the orthographic projection of the photoelectric conversion unit PIN1 onto the array substrate BP1. The first electrode SM11 is connected to the photosensitive circuit, and the second electrode SM21 is connected to the voltage signal line VDD. This ensures that the charge and electrons generated after photoelectric conversion by the photoelectric conversion unit PIN1 can flow to the photosensitive circuit and the voltage signal line VDD, respectively. Furthermore, considering the aforementioned scenario where the voltage signal line VDD is located on the pixel circuit layer, it can be that the voltage signal line VDD and the second electrode are located on the same layer.

[0099] The first conductive layer SM1 can be a metal layer, such as the same material as the source / drain metal layer SD; the second conductive layer SM2 includes a second electrode SM21 that only covers a part of the photoelectric conversion unit PIN1, or the second conductive layer SM2 is a light-transmitting layer (such as an indium tin oxide layer) to ensure that the light beam emitted by the auxiliary light-emitting device can directly illuminate the photoelectric conversion unit PIN1; in addition, in conjunction with the driving layer DR mentioned above, the photosensitive layer SM is located on the side of the driving layer DR away from the array substrate BP1 to reduce the reflection and scattering of the light beam by the film layer, thereby ensuring that the photosensitive element SM3 can absorb enough light beam and then convert it into enough charge and electrons.

[0100] It should be noted that the photosensitive layer SM can be, in addition to the film structure described above, also include only the photoelectric conversion layer and the second conductive layer SM2. When the photosensitive layer SM does not include the first conductive layer SM1, in combination with the film structure of the driving layer DR described above, the source / drain metal layer SD can include the first electrode SM11, so as to simplify the film structure of the array substrate 10 by reusing the source / drain metal layer SD.

[0101] In some embodiments, in conjunction with the active layer ACT described above having a first active portion P1, as shown in FIG7 or FIG8, the first conductive layer SM1 further includes a first light-shielding portion SM13, the orthographic projection of the first light-shielding portion SM13 on the active layer ACT at least covers the first channel region P11.

[0102] In this way, the first light-shielding part SM13 can block the first channel region P11, reducing or even avoiding the illumination of the first channel region P11, thereby preventing the leakage current of the driving transistor ST1 from increasing, and thus ensuring the performance of the driving transistor ST1.

[0103] In conjunction with the above-described case where the active layer ACT has a second active portion P2, as shown in Figure 7 or Figure 8, the first conductive layer SM1 further includes a second light-shielding portion SM14, the orthographic projection of the second light-shielding portion SM14 on the active layer ACT at least covers the second channel region P21.

[0104] In this way, the second light-shielding part SM14 can block the second channel region P21, reducing or even avoiding the illumination of the second channel region P21, thereby preventing the leakage current of the phototransistor ST2 from increasing, and thus ensuring the performance of the phototransistor ST2.

[0105] In this embodiment of the disclosure, in conjunction with the above description, after the pixel circuit stops applying voltage to the pixel electrode ANO, the display image can continue to be maintained based on the parallel capacitor C1 formed by the pixel electrode ANO and the common electrode layer COM. Regarding the parallel capacitor C1 formed by the pixel electrode ANO and the common electrode layer COM, the smaller the capacitance value of the parallel capacitor C1, the easier it is for crosstalk to occur, causing screen flickering; the larger the capacitance value of the parallel capacitor C1, the less likely crosstalk will occur, and the more stable the display image will be.

[0106] In some embodiments, as shown in FIG9 or FIG10, the gate metal layer Ga further includes a first auxiliary electrode G3, and the source drain metal layer SD further includes a second auxiliary electrode SD5; the gate insulating layer GI covers the first auxiliary electrode G3, the second auxiliary electrode SD5 is connected to the first connection line SD1, and the orthogonal projections of the first auxiliary electrode G3 and the second auxiliary electrode SD5 on the array substrate BP1 have overlapping areas.

[0107] In this process, the first auxiliary electrode G3 of the gate metal layer Ga is connected to the common electrode layer COM of the color filter substrate 20, and the second auxiliary electrode SD5 of the source-drain metal layer SD is connected to the pixel electrode ANO. At this time, the first auxiliary electrode G3 and the second auxiliary electrode SD5 can form a first auxiliary capacitor C2 connected in parallel with the parallel capacitor C1, thereby increasing the capacitance value between the pixel electrode ANO and the common electrode layer COM and ensuring the stability of the displayed image.

[0108] Optionally, the distance between the first auxiliary electrode G3 and the second auxiliary electrode SD5 is greater than or equal to 3500 angstroms and less than or equal to 4500 angstroms. For example, the distance between the first auxiliary electrode G3 and the second auxiliary electrode SD5 can be 3500 angstroms, 3600 angstroms, 3700 angstroms, 3800 angstroms, 3900 angstroms, 4000 angstroms, 4100 angstroms, 4200 angstroms, 4300 angstroms, 4400 angstroms, 4500 angstroms, etc. Of course, the distance between the first auxiliary electrode G3 and the second auxiliary electrode SD5 can also be less than 3500 angstroms or greater than 4500 angstroms, as long as the capacitance value between the pixel electrode ANO and the common electrode layer COM can be increased based on the first auxiliary capacitance C2 formed by the first auxiliary electrode G3 and the second auxiliary electrode SD5.

[0109] In some embodiments, as shown in FIG11 or FIG12, the first conductive layer SM1 further includes a third auxiliary electrode SM12, which is connected to the first auxiliary electrode G3 through a via, and the third auxiliary electrode SM12 and the second auxiliary electrode SD5 have overlapping regions on the array substrate BP1.

[0110] In this configuration, the third auxiliary electrode SM12 of the first conductive layer SM1 and the first auxiliary electrode G3 of the gate metal layer Ga are connected to the common electrode layer COM of the color filter substrate 20. The second auxiliary electrode SD5 of the source / drain metal layer SD is connected to the pixel electrode ANO. At this time, the first auxiliary electrode G3 and the second auxiliary electrode SD5 can form a first auxiliary capacitor connected in parallel with the parallel capacitor, and the third auxiliary electrode SM12 and the second auxiliary electrode SD5 can form a second auxiliary capacitor connected in parallel with the parallel capacitor, thereby increasing the capacitance value between the pixel electrode ANO and the common electrode layer COM and ensuring the stability of the displayed image.

[0111] Optionally, the distance between the first auxiliary electrode G3 and the second auxiliary electrode SD5 is greater than or equal to 3500 angstroms and less than or equal to 4500 angstroms, and the distance between the second auxiliary electrode SD5 and the third auxiliary electrode SM12 is greater than or equal to 2500 angstroms and less than or equal to 3500 angstroms.

[0112] For example, the spacing between the first auxiliary electrode G3 and the second auxiliary electrode SD5 is 3500 Å, 3600 Å, 3700 Å, 3800 Å, 3900 Å, 4000 Å, 4100 Å, 4200 Å, 4300 Å, 4400 Å, 4500 Å, etc. The spacing between the second auxiliary electrode SD5 and the third auxiliary electrode SM12 is 2500 Å, 2600 Å, 2700 Å, 2800 Å, 2900 Å, 3000 Å, 3100 Å, 3200 Å, 3300 Å, 3400 Å, 3500 Å, etc. Of course, the distance between the first auxiliary electrode G3 and the second auxiliary electrode SD5 can be less than 3500 angstroms or greater than 4500 angstroms, and the distance between the second auxiliary electrode SD5 and the third auxiliary electrode SM12 can be less than 2500 angstroms or greater than 3500 angstroms, as long as the capacitance value between the pixel electrode ANO and the common electrode layer COM can be increased based on the first auxiliary capacitor formed by the first auxiliary electrode G3 and the second auxiliary electrode SD5, and the second auxiliary capacitor formed by the second auxiliary electrode SD5 and the third auxiliary electrode SM12.

[0113] In some embodiments, as shown in FIG1 or FIG2, the pixel circuit layer includes a planarization layer PLN covering the photosensitive element SM3, so as to ensure the planarity of the array substrate 10 by the arrangement of the planarization layer PLN.

[0114] In this configuration, the planarization layer PLN is located on the side of the second conductive layer SM2 away from the array substrate BP1, in conjunction with the aforementioned driving layer DR and photosensitive layer SM, so that the planarization layer PLN can directly cover the exposed surfaces of the first passivation layer PVX1, the first conductive layer SM1, and the second conductive layer SM2.

[0115] Furthermore, as shown in Figure 1 or Figure 2, the pixel circuit layer also includes a buffer layer Buff located on the side of the planarization layer PLN near the array substrate BP1. That is, the pixel circuit layer also includes a buffer layer Buff located between the planarization layer PLN and the first conductive layer SM1 and the second conductive layer SM2. In this way, the bonding strength between the planarization layer PLN and the first conductive layer SM1 and the second conductive layer SM2 can be achieved by setting the buffer layer Buff.

[0116] Furthermore, as shown in Figure 1 or Figure 2, the pixel circuit layer also includes a second passivation layer PVX2 located on the side of the planarization layer PLN away from the array substrate BP1, so as to realize the spacing between the planarization layer PLN and the reflective layer BM (pixel electrode ANO) through the second passivation layer PVX2, thereby protecting the pixel electrode ANO and extending the life of the pixel electrode ANO.

[0117] In some implementations, the planarization layer PLN is a diffuse reflection layer. For example, the surface of the planarization layer PLN has an uneven microstructure to achieve diffuse reflection of ambient light, thereby ensuring the uniformity of brightness when the display panel 100 displays an image.

[0118] As shown in Figure 1 or Figure 2, the planarization layer PLN has a light-transmitting aperture PLN1. The light-transmitting area ANO1, the light-transmitting aperture PLN1, and the photoelectric conversion unit PIN1 have overlapping projections on the array substrate BP1. Thus, the light-transmitting aperture PLN1 on the planarization layer PLN ensures that the light beam emitted from the auxiliary light-emitting device can sequentially pass through the light-transmitting area ANO1 of the reflective layer BM and the light-transmitting aperture PLN1 of the planarization layer PLN to illuminate the photoelectric conversion unit PIN1. Furthermore, as shown in Figure 1 or Figure 2, the second passivation layer PVX2 has a light-transmitting aperture overlapping the area on the planarization layer PLN to further ensure the reliability of the photosensitive element SM3 in receiving light.

[0119] In this embodiment of the disclosure, as shown in FIG13, the array substrate 10 includes a display area AA and a peripheral area BB located outside the display area AA. In conjunction with the above description, the pixel circuit layer includes a pixel circuit, a photosensitive circuit, and a photosensitive element SM3 located in the display area AA, as well as a driving data line DD and a driving scan line DG connected to the pixel circuit, and a photosensitive data line MD and a photosensitive scan line MG connected to the photosensitive circuit. To enable normal driving of the pixel circuit and the photosensitive circuit, the driving data line DD and the driving scan line DG, as well as the photosensitive data line MD and the photosensitive scan line MG, all extend to the peripheral area BB. That is, as shown in FIG13, the pixel circuit layer includes a driving data line DD, a driving scan line DG, a photosensitive data line MD, and a photosensitive scan line MG extending to the peripheral area BB.

[0120] In some implementations, as shown in FIG14, taking the scan lines (driving scan lines DG and photosensitive scan lines MG) of the display area AA extending along the row direction X and the data lines (driving data lines DD and photosensitive data lines MD) of the display area AA extending along the column direction Y as an example, as shown in FIG13, the driving scan lines DG and photosensitive scan lines MG of the peripheral area BB are located on both sides of the display area AA along the row direction, and the driving data lines DD and photosensitive data lines MD of the peripheral area BB are located on the same side of the display area AA along the column direction.

[0121] In this design, the driving scan line DG and photosensitive scan line MG of the peripheral area BB are respectively positioned on both sides of the display area AA along the row direction to reduce crosstalk between them. Additionally, the peripheral area BB houses a driving module B1 and a photosensitive module B2, both located on one side of the display area AA along the column direction, and on the same side as the driving data line DD and photosensitive data line MD. Thus, normal driving of the pixel circuit and photosensitive circuit can be achieved through the connection of the driving scan line DG and driving data line DD to the driving module B1, and through the connection of the photosensitive scan line MG and photosensitive data line MD to the photosensitive module B2.

[0122] In the display area AA, the driving data line DD and the photosensitive data line MD are both located on the source / drain metal layer SD of the driving layer DR. At this time, the driving data line DD and the photosensitive data line MD can be layered in the outer area BB (for example, one is located on the source / drain metal layer SD in the outer area BB, and the other is located on the second conductive layer SM2 in the outer area BB, etc.) to avoid interference caused when the driving data line DD and the photosensitive data line MD in the outer area BB are located on the same side of the display area AA. This makes it easier to realize the miniaturization design of the outer area BB, that is, to realize the narrow bezel design of the display panel 100.

[0123] This disclosure also provides a display method for a display panel, which is applied to the display panel described in the above embodiments.

[0124] The display panel includes a display phase for displaying each frame and a blanking phase between two adjacent frames. The blanking phase includes an illumination phase where the photosensitive unit performs light conversion, a reading phase for reading changes in charge after photoelectric conversion, and a feedback phase for feeding back information about the next frame based on changes in charge. As shown in Figures 15 and 16, the display method includes steps S110-S140.

[0125] Step S110: In the display stage, data signals and scan signals are transmitted to the driving transistor based on the image information of the current frame, so that the display panel displays the image of the current frame.

[0126] Step S120: During the illumination stage, a low-level first-level signal is input to the control electrode of the phototransistor to turn off the phototransistor; at the same time, the photosensitive element performs photoelectric conversion on the received light beam.

[0127] Step S130: During the reading stage, a high-level first-level signal is input to the control electrode of the phototransistor to turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element, so as to obtain the actual charge amount of the second-level signal after the charge in the photosensitive element flows to the first electrode of the phototransistor.

[0128] Step S140: In the feedback stage, the target photosensitive element is determined based on the actual charge amount, and the display information of the next frame is determined based on the position information of the target photosensitive element, and then the process returns to the display stage.

[0129] In this embodiment of the disclosure, after the display panel displays the current frame normally, the display of the next frame can be realized based on the cooperation of the photosensitive transistor and the photosensitive element, thereby realizing the control mode of air touch or press touch on the display panel, improving the convenience of display panel operation and increasing user stickiness.

[0130] In step S110 above, in addition to displaying the current frame, since there may be charge in the photosensitive element that has not flowed to the first electrode of the photosensitive transistor during the display of the previous frame, and / or the photosensitive element will be irradiated by the light beam during the display process, so that the photosensitive element has a certain amount of charge, the amount of charge in the photosensitive element can be corrected to ensure the accuracy of subsequent light control.

[0131] Specifically, a high-level first-level signal can be periodically input to the control electrode of the phototransistor to make the phototransistor periodically turn on, while a high-level second-level signal is input to the first electrode of the phototransistor and a low-level third-level signal is input to the second electrode of the photosensitive element to correct the amount of charge in the photosensitive element.

[0132] In this way, by turning on the phototransistor, the charge in the photosensitive element can flow periodically to the first electrode of the phototransistor and be released along the photosensitive data line. This ensures that the amount of charge in the photosensitive element remains constant during the display of the current frame, thus avoiding any impact on the accuracy of the display panel control. Furthermore, the periodic turning on of the phototransistor facilitates the matching of the scanning signal applied to the driving transistor, thereby preventing the level signal applied to the photosensitive transistor from affecting the driving transistor.

[0133] In step S120 above, a low-level first-level signal can be input to the control electrode of the photosensitive transistor through the photosensitive scan line to turn off the photosensitive transistor.

[0134] In step S130 above, a high-level first-level signal can be input to the control electrode of the photosensitive transistor via the photosensitive scan line to turn on the photosensitive transistor; a high-level second-level signal can be input to the first electrode of the photosensitive transistor via the photosensitive data line, and a low-level third-level signal can be input to the second electrode of the photosensitive element via the voltage signal line to make the charge in the photosensitive element flow to the first electrode of the photosensitive transistor; since the first electrode of the photosensitive transistor is connected to the photosensitive data line, the actual charge amount of the second-level signal can be obtained by detecting the current on the photosensitive data line.

[0135] In step S140 above, it can be determined whether the charge of the second level signal has changed based on the reference charge and the actual charge of the second level signal. When the charge of the second level signal has not changed, it can be confirmed that the corresponding photosensitive element has not received the illumination of the light beam. When the charge of the second level signal changes, it can be confirmed that the corresponding photosensitive element has received the illumination of the light beam. At this time, the photosensitive element can be identified as the target photosensitive element.

[0136] In addition, since the distribution of photosensitive elements on the array substrate is pre-designed, the position information of the target photosensitive element can be obtained after the target photosensitive element is determined. Then, based on the position information of the target photosensitive element, the control command (such as the "next page" command) in the area can be determined, and the image information of the next page can be used as the display information of the next frame.

[0137] It should be noted that although the steps of the methods shown in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0138] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. An array substrate, wherein, include: Array substrate; A pixel circuit layer is located on one side of the array substrate and includes a pixel circuit, a photosensitive circuit, and a photosensitive element. The photosensitive element includes a photoelectric conversion unit, and the photosensitive circuit is connected to the photosensitive element. A reflective layer is located on the side of the pixel circuit layer opposite to the array substrate and has a light-transmitting area. The orthogonal projection of the light-transmitting area on the pixel circuit layer overlaps with the photoelectric conversion unit. The reflective layer includes a pixel electrode, which is connected to the pixel circuit.

2. The array substrate as claimed in claim 1, wherein, The pixel circuit layer includes a planar layer covering the photosensitive element; The planarization layer has a light-transmitting hole, and the light-transmitting area, the light-transmitting hole, and the photoelectric conversion unit have an overlapping region on the array substrate.

3. The array substrate as claimed in claim 1, wherein, The reflective layer includes voltage signal lines, which are connected to the photosensitive element.

4. The array substrate as claimed in claim 1, wherein, The light-transmitting area is the light-transmitting notch on the pixel electrode.

5. The array substrate as claimed in claim 4, wherein, The orthographic projection of the photoelectric conversion unit on the array substrate and the orthographic projection of the multiple pixel electrodes on the array substrate both have overlapping areas.

6. The array substrate as claimed in claim 5, wherein, At least one of the pixel electrodes has a light-transmitting notch.

7. The array substrate as claimed in claim 1, wherein, The array substrate includes a display area and a peripheral area located outside the display area; The pixel circuit, the photosensitive circuit, and the photosensitive element are all located in the display area. The pixel circuit layer also includes driving data lines, driving scan lines, photosensitive data lines, and photosensitive scan lines extending to the peripheral area. In the peripheral area, the driving scan line and the photosensitive scan line are located on both sides of the display area along the row direction, and the driving data line and the photosensitive data line are located on the same side of the display area along the column direction, and are located in different film layers.

8. The array substrate as described in any one of claims 1-7, wherein, The pixel circuit layer includes a photosensitive layer, which includes a first conductive layer, a photoelectric conversion layer and a second conductive layer stacked sequentially in a direction away from the array substrate. The first conductive layer includes a first electrode, the second conductive layer includes a second electrode, the photoelectric conversion layer includes the photoelectric conversion unit, the first electrode, the second electrode, and the photoelectric conversion unit constitute a photosensitive element, and the first electrode is connected to the photosensitive circuit. The second conductive layer is a light-transmitting layer, and the photoelectric conversion unit and the light-transmitting area have an overlapping region on the array substrate.

9. The array substrate as claimed in claim 8, wherein, The pixel circuit includes a driving transistor, the pixel circuit layer includes a driving layer located between the photosensitive layer and the array substrate, and the driving layer includes: A gate metal layer is located on one side of the array substrate and includes a first conductive portion; A gate insulating layer is located on the side of the gate metal layer opposite to the array substrate, and at least covers the first conductive portion; An active layer is located on the side of the gate insulating layer away from the array substrate, and includes a first active portion, the first active portion including a first channel region and a first connection portion and a second connection portion located on both sides of the first channel region; A source / drain metal layer is located on the side of the active layer away from the array substrate, and includes a first connection line, the two ends of which are electrically connected to the first connection portion and the pixel electrode, respectively. The first connecting portion and the second connecting portion respectively form the first electrode and the second electrode of the driving transistor. The second electrode of the driving transistor is used to load a data signal. The area on the first conductive portion that overlaps with the first channel region forms the control electrode of the driving transistor. The control electrode of the driving transistor is used to load a scan signal.

10. The array substrate as claimed in claim 9, wherein, The first conductive layer further includes a first light-shielding portion, the orthogonal projection of which on the active layer at least covers the first channel region.

11. The array substrate as claimed in claim 9, wherein, The gate metal layer further includes a first auxiliary electrode, and the source / drain metal layer further includes a second auxiliary electrode; The gate insulating layer covers the first auxiliary electrode, the second auxiliary electrode is connected to the first connection line, and the orthogonal projections of the first auxiliary electrode and the second auxiliary electrode on the array substrate have an overlapping area.

12. The array substrate as claimed in claim 11, wherein, The distance between the first auxiliary electrode and the second auxiliary electrode is greater than or equal to 3500 angstroms and less than or equal to 4500 angstroms.

13. The array substrate as claimed in claim 11, wherein, The first conductive layer further includes a third auxiliary electrode; The third auxiliary electrode is connected to the first auxiliary electrode through a via, and the orthographic projections of the third auxiliary electrode and the second auxiliary electrode on the array substrate overlap in an area.

14. The array substrate as claimed in claim 13, wherein, The distance between the first auxiliary electrode and the second auxiliary electrode is greater than or equal to 3500 angstroms and less than or equal to 4500 angstroms, and the distance between the second auxiliary electrode and the third auxiliary electrode is greater than or equal to 2500 angstroms and less than or equal to 3500 angstroms.

15. A display panel, wherein, It includes a color filter substrate and an array substrate as described in any one of claims 1-14, which are disposed opposite to each other, and a liquid crystal layer located between the array substrate and the color filter substrate.

16. The display panel as claimed in claim 15, wherein, A spacer is provided between the array substrate and the color filter substrate, and the spacer is spherical.

17. A method for displaying a display panel, wherein, The display method is applied to the display panel of claim 15 or 16, wherein the pixel circuit includes a driving transistor, the photosensitive circuit includes a photosensitive transistor, the control electrode of the photosensitive transistor is used to load a first level signal, the first electrode of the photosensitive transistor is used to load a second level signal, and the second electrode of the photosensitive transistor is connected to the first electrode of the photosensitive element, wherein the second electrode of the photosensitive element is used to load a third level signal. The display panel includes a display phase and a blanking phase, the blanking phase including an illumination phase, a reading phase, and a feedback phase, and the display method includes: During the display phase, data signals and scan signals are transmitted to the driving transistor based on the image information of the current frame, so that the display panel displays the image of the current frame; During the illumination phase, a low-level first-level signal is input to the control electrode of the phototransistor to turn the phototransistor off; simultaneously, the photosensitive element performs photoelectric conversion on the received light beam. During the reading phase, a high-level first-level signal is input to the control electrode of the phototransistor to turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element, so as to obtain the actual charge amount of the second-level signal after the charge in the photosensitive element flows to the first electrode of the phototransistor. During the feedback phase, the target photosensitive element is determined based on the actual charge amount, and the display information of the next frame is determined based on the position information of the target photosensitive element, and then the process returns to the display phase.

18. The display method as described in claim 17, wherein, The display method further includes: During the display phase, a high-level first-level signal is periodically input to the control electrode of the phototransistor to periodically turn on the phototransistor. At the same time, a high-level second-level signal is input to the first electrode of the phototransistor, and a low-level third-level signal is input to the second electrode of the photosensitive element to correct the amount of charge in the photosensitive element.

Images