Display substrate and display device

Abstract

Display substrate and display device, relating to the field of display technology, the display substrate includes a display area and a non-display area, the display area includes a plurality of sub-pixels, the sub-pixels include thin film transistors and pixel electrodes, the display substrate further includes: a substrate; a driving circuit structure layer located on one side of the substrate, including the pixel electrodes and the source connection region, channel region, drain connection region and gate of the thin film transistors, the pixel electrodes being electrically connected to the drain connection region; a piezoelectric layer located on the side of the driving circuit structure layer opposite to the substrate, the piezoelectric layer including piezoelectric patterns located on different sub-pixels, the piezoelectric patterns at least partially overlapping the orthographic projection of the pixel electrodes on the substrate; wherein, the piezoelectric patterns are configured to deform in the thickness direction of the substrate based on a voltage applied to the pixel electrodes.

Description

Display substrate and display device

[0001] This disclosure claims priority to Chinese Patent Application No. 2024117467541, filed on November 29, 2024, entitled “Display Substrate and Display Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of electrophoretic display technology, and in particular to a display substrate and display device. Background Technology

[0003] Electronic paper primarily uses electrophoresis display (EPD) technology as its display panel. Electronic paper displays not only offer advantages similar to paper, such as comfortable reading, ultra-thin and lightweight design, and flexibility, but also allow for content refresh and consume less power than LCD displays.

[0004] Overview

[0005] This disclosure provides a display substrate, comprising a display area and a non-display area. The display area includes a plurality of sub-pixels, each sub-pixel including a thin-film transistor and a pixel electrode. The display substrate further includes:

[0006] Substrate;

[0007] A driving circuit structure layer is located on one side of the substrate, including the pixel electrode and the source connection region, channel region, drain connection region and gate of the thin film transistor, wherein the pixel electrode is electrically connected to the drain connection region;

[0008] A piezoelectric layer is located on the side of the driving circuit structure layer opposite to the substrate. The piezoelectric layer includes piezoelectric patterns located on different sub-pixels. The piezoelectric patterns at least partially overlap with the orthographic projection of the pixel electrode on the substrate.

[0009] The piezoelectric pattern is configured to deform in the thickness direction of the substrate based on the voltage applied to the pixel electrode.

[0010] For example, the piezoelectric layer further includes a barrier pattern, the barrier pattern including a plurality of openings, wherein the pixel electrodes of different sub-pixels and the orthographic projections of the piezoelectric pattern on the substrate are located within the orthographic projections of different openings on the substrate;

[0011] In the thickness direction of the substrate, the size of the barrier pattern is larger than the size of the piezoelectric pattern.

[0012] For example, the barrier pattern includes a first portion located on the side of the piezoelectric pattern away from the substrate and a second portion located on the side of the piezoelectric pattern closer to the substrate;

[0013] In the thickness direction of the substrate, the size of the second portion is smaller than the size of the first portion, and the size of the first portion is larger than the size of the piezoelectric pattern.

[0014] For example, the pixel electrodes located in different sub-pixels are isolated by the second portion.

[0015] For example, the sidewall of the second portion is in direct contact with the sidewall of the pixel electrode.

[0016] For example, the size of the barrier pattern in the planar direction of the substrate is larger than the size of the piezoelectric pattern in the thickness direction of the substrate.

[0017] For example, the driving circuit structure layer further includes scan lines and data lines, the scan lines intersect the data lines, and the sub-pixel is located in the area defined by the intersection of the scan lines and the data lines;

[0018] The barrier pattern includes a first barrier parallel to the scan line and a second barrier parallel to the data line.

[0019] Wherein, the orthographic projection of the first barrier on the substrate at least partially overlaps with the orthographic projection of the scan line on the substrate, and the orthographic projection of the second barrier on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

[0020] For example, the pixel electrode includes a second pixel electrode, and in the thickness direction of the substrate, the distance between the second pixel electrode and the piezoelectric pattern is smaller than the distance between the film layer in the driving circuit structure layer other than the film layer where the second pixel electrode is located and the piezoelectric pattern.

[0021] Wherein, the edge of the first barrier near the second pixel electrode coincides with the orthographic projection of the edge of the second pixel electrode near the scan line onto the substrate; and / or,

[0022] The edge of the second barrier near the second pixel electrode and the edge of the second pixel electrode near the data line have their orthogonal projections on the substrate.

[0023] For example, the width of the first barrier along the data line direction is less than or equal to the spacing between the pixel electrodes of two adjacent sub-pixels along the data line direction;

[0024] And / or, the width of the second barrier along the scan line direction is greater than or equal to the spacing between the pixel electrodes of two adjacent sub-pixels along the scan line direction.

[0025] For example, the pixel electrode includes a second pixel electrode, and in the thickness direction of the substrate, the distance between the second pixel electrode and the piezoelectric pattern is smaller than the distance between the film layer in the driving circuit structure layer other than the film layer where the second pixel electrode is located and the piezoelectric pattern.

[0026] The piezoelectric pattern is in direct contact with the second pixel electrode on the side closest to the substrate.

[0027] Exemplarily, the display substrate further includes:

[0028] The third common electrode is located on the side of the piezoelectric layer away from the substrate, and the orthographic projection of the third common electrode on the substrate at least partially overlaps with the orthographic projection of the piezoelectric pattern on the substrate.

[0029] For example, the third common electrode is in direct contact with the surface of the piezoelectric pattern on the side opposite to the substrate.

[0030] For example, the driving circuit structure layer includes: a first conductive layer, a semiconductor layer, a first insulating layer, and a second conductive layer sequentially stacked on one side of the substrate, wherein the first conductive layer is disposed close to the substrate; wherein,

[0031] The first conductive layer includes data lines;

[0032] The semiconductor layer includes multiple semiconductor patterns located in different sub-pixels. The semiconductor patterns include the source connection region, the first conductor region, and the channel region. The source connection region, the first conductor region, and the channel region are arranged along a first direction and connected sequentially.

[0033] The second conductive layer includes a first transition pattern, a scan line, and the gate;

[0034] The first insulating layer has a first via, which exposes a portion of the data line, the source connection region, and the first conductor region. The data line and the source connection region are respectively connected to the first transition pattern through the first via. The first transition pattern and the orthographic projection of the first conductor region on the substrate do not overlap.

[0035] For example, the pixel electrode includes a first pixel electrode and a second pixel electrode; the first pixel electrode is located in the semiconductor layer or the second conductive layer, and the display substrate further includes:

[0036] A third conductive layer is disposed on the side of the second conductive layer opposite to the substrate; and

[0037] A transparent conductive layer is disposed on the side of the third conductive layer opposite to the substrate, including a second pixel electrode. The second pixel electrode is connected to the first pixel electrode through a via, and the first pixel electrode is also connected to the drain connection region of the thin film transistor.

[0038] In this case, the orthographic projection of the first pixel electrode on the substrate overlaps with the orthographic projection of the second pixel electrode on the substrate, and the orthographic projection of the piezoelectric pattern on the substrate overlaps with the orthographic projections of both the first pixel electrode and the second pixel electrode on the substrate.

[0039] For example, the first pixel electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode connected in sequence. The first sub-electrode is connected to the drain connection region of the thin-film transistor and is located on the side of the drain connection region away from the channel region. Along the second direction and away from the channel region, the widths of the first sub-electrode, the second sub-electrode, and the third sub-electrode increase sequentially along the first direction. The second direction intersects the first direction.

[0040] The piezoelectric pattern includes a first pattern area and a second pattern area. The first pattern area overlaps with the orthographic projection of the first sub-electrode on the substrate, and the second pattern area overlaps with the orthographic projections of the second sub-electrode and the third sub-electrode on the substrate.

[0041] Wherein, the width of the first pattern area along the first direction is less than the width of the second pattern area along the first direction, the orthographic projection of the edge of the second pattern area near the scan line on the substrate coincides with the orthographic projection of the edge of the second sub-electrode near the scan line on the substrate, the width of the second pattern area along the first direction is greater than the width of the second sub-electrode along the first direction, and is greater than or equal to the width of the third sub-electrode along the first direction.

[0042] For example, the sub-pixel further includes a first common electrode and a second common electrode; wherein the first common electrode and the first pixel electrode are disposed in different layers and overlap in their orthogonal projection on the substrate, the first common electrode is located in the first conductive layer, and the second common electrode is located in the third conductive layer;

[0043] The second conductive layer further includes a third transition pattern, which is located on the side of the first transition pattern and the gate away from the scan line. The second common electrode and the first common electrode are respectively connected to the third transition pattern through vias. The third transition pattern does not overlap with the orthographic projection of the first pixel electrode on the substrate.

[0044] Wherein, the orthographic projection of the second patterned area on the substrate overlaps the orthographic projection of the third transition pattern on the substrate.

[0045] For example, the semiconductor pattern further includes a third conductive region and a fourth conductive region, and the channel region, the fourth conductive region, the third conductive region and the drain connection region are arranged along the first direction and connected in sequence;

[0046] The second conductive layer further includes a second transition pattern located on the side of the gate away from the first transition pattern. A second via is also provided on the first insulating layer, the second via exposing the drain connection region and the third conductive region. The second transition pattern overlaps with the drain connection region through the second via.

[0047] Wherein, the orthographic projection of the first patterned area on the substrate covers the orthographic projection of the second via on the substrate.

[0048] For example, the first pixel electrode is located in the semiconductor layer, and the first pixel electrode includes a fourth sub-electrode and a fifth sub-electrode connected in sequence; the fourth sub-electrode is connected to the drain connection region of the thin film transistor and is located on the side of the drain connection region away from the channel region; the width of the fourth sub-electrode along the first direction is smaller than the width of the fifth sub-electrode along the first direction.

[0049] The piezoelectric pattern includes a first pattern area and a second pattern area, wherein the first pattern area overlaps with the orthographic projection of the fourth sub-electrode on the substrate, and the second pattern area overlaps with the orthographic projection of the fifth sub-electrode on the substrate;

[0050] Wherein, the width of the first pattern area along the first direction is less than the width of the second pattern area along the first direction, the orthographic projection of the edge of the second pattern area near the scan line on the substrate coincides with the orthographic projection of the edge of the fifth sub-electrode near the scan line on the substrate, and the width of the second pattern area along the first direction is greater than or equal to the width of the fifth sub-electrode along the first direction.

[0051] For example, the sub-pixel further includes a first common electrode and a second common electrode;

[0052] Wherein, the first common electrode and the first pixel electrode are disposed in different layers and their orthogonal projections on the substrate overlap, the first common electrode and the second common electrode are disposed in different layers, and the second common electrode is located in the third conductive layer;

[0053] The orthographic projection of the piezoelectric pattern on the substrate covers the orthographic projection of the first common electrode on the substrate and at least partially overlaps with the orthographic projection of the second common electrode on the substrate.

[0054] For example, the orthographic projection of the second pixel electrode on the substrate covers the orthographic projection of the first pixel electrode on the substrate, and the orthographic projections of both the first and second pixel electrodes on the substrate do not overlap with the orthographic projection of the scan line on the substrate; the orthographic projection of the first pixel electrode on the substrate does not overlap with the orthographic projection of the data line on the substrate, and the second pixel electrode at least partially covers the data line;

[0055] The piezoelectric layer further includes a barrier pattern, which isolates the piezoelectric patterns located in different sub-pixels;

[0056] Wherein, the orthographic projection of the edge of the barrier pattern along the scan line direction on the substrate coincides with the orthographic projection of the edge of the second pixel electrode along the scan line direction on the substrate; the orthographic projection of the portion of the barrier pattern parallel to the data line on the substrate covers the orthographic projection of the data line on the substrate and does not overlap with the first pixel electrode.

[0057] For example, the driving circuit structure layer includes: a first conductive layer, a semiconductor layer, a second conductive layer, and a transparent conductive layer sequentially stacked on one side of the substrate, wherein the first conductive layer is close to the substrate; wherein,

[0058] The first conductive layer includes a gate;

[0059] The semiconductor layer includes the source connection region, the channel region, and the drain connection region;

[0060] The second conductive layer includes a fifth transition pattern, and the transparent conductive layer includes a second pixel electrode, which is electrically connected to the drain connection region through the fifth transition pattern.

[0061] For example, the driving circuit structure includes: a semiconductor layer, a second conductive layer, a third conductive layer and a transparent conductive layer sequentially stacked on one side of the substrate, wherein the semiconductor layer is disposed close to the substrate;

[0062] The semiconductor layer includes the source connection region, the channel region, and the drain connection region; the second conductive layer includes the gate; the second conductive layer includes a sixth transition pattern; and the transparent conductive layer includes a second pixel electrode.

[0063] The second pixel electrode is connected to the drain connection area through the sixth transition pattern.

[0064] A display device disclosed herein includes: a counter substrate, an electrophoretic solution, and a display substrate as described in any of the above embodiments, wherein the electrophoretic solution is located between the counter substrate and the display substrate.

[0065] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below.

[0066] Brief description of the attached diagram

[0067] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0068] Figure 1A shows a cross-sectional structural diagram of the first type of display substrate in this embodiment, state 1;

[0069] Figure 1B shows a cross-sectional structural diagram of the first type of display substrate in state 2 of this embodiment;

[0070] Figure 1C shows a planar schematic diagram of the second pixel electrode, piezoelectric layer, and third common electrode during the fabrication process of the first type of display substrate;

[0071] Figure 2 shows a cross-sectional view of the second type of display substrate in this embodiment;

[0072] Figures 3 and 6 show cross-sectional structural schematic diagrams of another display substrate in this embodiment;

[0073] Figure 4 shows a schematic diagram of a fabrication process for forming the piezoelectric layer shown in Figure 3;

[0074] Figure 5 shows a schematic diagram of another fabrication process for forming the piezoelectric layer shown in Figure 3;

[0075] Figure 7 shows a schematic cross-sectional structure of the piezoelectric layer shown in Figure 6;

[0076] Figure 8 shows a schematic diagram of a stack-up between a piezoelectric layer, data lines, and scan lines;

[0077] Figure 9 shows a schematic diagram of the structure of the first example of the third type of display substrate;

[0078] Figure 10 shows a schematic diagram of the display substrate structure after the first conductive layer has been fabricated in the first example;

[0079] Figure 11 shows a schematic diagram of the display substrate structure after the semiconductor layer fabrication is completed in the first example;

[0080] Figure 12 shows a schematic diagram of the display substrate structure after the first insulating layer has been fabricated in the first example;

[0081] Figure 13 shows a schematic diagram of the display substrate structure after the second conductive layer has been fabricated in the first example;

[0082] Figure 14 shows a schematic diagram of the display substrate structure after the organic insulating layer has been fabricated in the first example;

[0083] Figure 15 shows a schematic diagram of the display substrate structure after the second insulating layer has been fabricated in the first example;

[0084] Figure 16 shows a schematic diagram of the display substrate structure after the third conductive layer has been fabricated in the first example;

[0085] Figure 17 shows a schematic diagram of the display substrate structure after the third insulating layer has been fabricated in the first example;

[0086] Figure 18 shows a schematic diagram of the display substrate structure after the transparent conductive layer is fabricated in the first example;

[0087] Figure 19 shows a structural schematic diagram of an example of the second display substrate in the third type of display substrate;

[0088] Figure 20 shows a schematic diagram of the display substrate structure after the first conductive layer has been fabricated in the second example;

[0089] Figure 21 shows a schematic diagram of the display substrate structure after the semiconductor layer fabrication is completed in the second example;

[0090] Figure 22 shows a schematic diagram of the display substrate structure after the first insulating layer has been fabricated in the second example;

[0091] Figure 23 shows a schematic diagram of the display substrate structure after the second conductive layer has been fabricated in the second example;

[0092] Figure 24 shows a schematic diagram of the display substrate structure after the organic insulating layer has been fabricated in the second example;

[0093] Figure 25 shows a schematic diagram of the display substrate structure after the second insulating layer has been fabricated in the second example;

[0094] Figure 26 shows a schematic diagram of the display substrate structure after the third conductive layer has been fabricated in the second example;

[0095] Figure 27 shows a schematic diagram of the display substrate structure after the third insulating layer has been fabricated in the second example;

[0096] Figure 28 shows a schematic diagram of the display substrate structure after the transparent conductive layer is fabricated in the second example;

[0097] Figure 29 shows a schematic diagram of the structure of an example of the third type of display substrate;

[0098] Figure 30 shows a schematic diagram of the display substrate structure after the first conductive layer has been fabricated in the third example;

[0099] Figure 31 shows a schematic diagram of the display substrate structure after the semiconductor layer fabrication is completed in the third example;

[0100] Figure 32 shows a schematic diagram of the display substrate structure after the first insulating layer has been fabricated in the third example;

[0101] Figure 33 shows a schematic diagram of the display substrate structure after the second conductive layer has been fabricated in the third example;

[0102] Figure 34 shows a schematic diagram of the display substrate structure after the organic insulating layer has been fabricated in the third example;

[0103] Figure 35 shows a schematic diagram of the display substrate structure after the third conductive layer has been fabricated in the third example;

[0104] Figure 36 shows a schematic diagram of the display substrate structure after the third insulating layer has been fabricated in the third example;

[0105] Figure 37 shows a schematic diagram of the display substrate structure after the transparent conductive layer is fabricated in the third example;

[0106] Figures 38-40 show schematic diagrams of several overlapping film layers, including the barrier pattern, scan lines, data lines, first pixel electrode, and second pixel electrode.

[0107] Figures 41-43 show schematic diagrams of several overlapping film layers between piezoelectric patterns, scan lines, data lines, first pixel electrodes, and second pixel electrodes, respectively.

[0108] Figures 44 and 45 show schematic diagrams of the overlapping of two types of film layers, namely piezoelectric pattern, scan line, data line, first common electrode and second common electrode;

[0109] Figure 46 shows a bar chart of the electric field strength in the channel region as a function of the doping concentration in the first conductor region;

[0110] Figure 47 illustrates a schematic cross-sectional structure of a display device;

[0111] Figure 48 illustrates a schematic diagram of the connection structure of a display device.

[0112] Detailed description

[0113] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0114] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0115] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0116] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and encompassing, that is, "including, but not limited to".

[0117] In this application, "same layer" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). "Same layer" here does not always mean that multiple film layers have the same thickness or the same height in a cross-sectional view. The polygons used in this specification are not strictly defined; they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances.

[0118] In related technologies, electronic paper mainly uses the following two methods to achieve full-color display: The first is color printing electronic paper technology, which uses electronic paper with color filters and the principle of color mixing to convert black and white electronic paper into full-color electronic paper; the second is color electronic paper technology, which is composed of ink particles of four colors (such as yellow, cyan, magenta and white). By applying an electric field and using the principle of attraction between positive and negative, the ink particles of the corresponding colors are pushed to the display side. After the particles of different colors are mixed, a variety of colors are presented.

[0119] To drive electronic paper for full-color display, higher driving voltages are required, such as VGH ≥ 28V and VGL ≤ -28V. However, high driving voltages can cause TFT failure in the GOA (Gate Driver on Array) region; for example, high voltage can burn out the TFTs in the GOA region.

[0120] In view of the above, this disclosure provides a display substrate, which may include a display area and a non-display area. The display area includes a plurality of sub-pixels, and each sub-pixel includes a thin-film transistor and a pixel electrode. The display substrate further includes a substrate, a driving circuit structure layer, and a piezoelectric layer. The driving circuit structure layer includes a source connection region, a channel region, a drain connection region, and a gate of the thin-film transistor. The pixel electrode is electrically connected to the drain connection region. The piezoelectric layer includes piezoelectric patterns located in different sub-pixels. The piezoelectric patterns at least partially overlap with the orthographic projection of the pixel electrode on the substrate. The piezoelectric patterns are configured to deform in the thickness direction of the substrate based on the voltage applied to the pixel electrode.

[0121] The display substrate of this embodiment, by having a piezoelectric pattern overlapping the pixel electrode in each sub-pixel, can utilize the inverse piezoelectric effect to deform the piezoelectric pattern along the thickness direction of the substrate. Thus, when the display substrate is applied to electronic paper displays, the deformed piezoelectric pattern can drive ink particles to the display side. Since the driving voltage required for the piezoelectric pattern is generally low, a high refresh rate can be achieved at a low voltage, achieving the effect of high-voltage driving. This reduces the driving voltage of the electronic paper and avoids the problem of TFTs in the GOA region being burned out.

[0122] The display substrate proposed in this disclosure will now be described by way of example with reference to the accompanying drawings.

[0123] First, referring to Figures 1A-9, the display substrate of this embodiment may include a display area AA and a non-display area NA. The display area AA may include multiple sub-pixels PX, and each sub-pixel PX may include a thin-film transistor and a pixel electrode (first pixel electrode EP1 / second pixel electrode EP2). The display substrate may also include:

[0124] Substrate 10;

[0125] The driving circuit structure layer is located on one side of the substrate 10, including the pixel electrode and the source connection region S, channel region CH, drain connection region D and gate G of the thin film transistor. The pixel electrode is electrically connected to the drain connection region D.

[0126] The piezoelectric layer 20 is located on the side of the driving circuit structure layer away from the substrate 10. The piezoelectric layer 20 includes piezoelectric patterns 21 located in different sub-pixels PX. The piezoelectric patterns 21 at least partially overlap with the orthographic projection of the pixel electrode on the substrate 10.

[0127] The piezoelectric pattern 21 is configured to deform in the thickness direction Z of the substrate 10 based on the voltage applied to the pixel electrode.

[0128] In this embodiment, the non-display area NA may surround the display area AA, or partially surround the display area AA.

[0129] In this embodiment, as shown in Figures 6-9, the display substrate may include multiple scan lines GL and multiple data lines DL. The multiple scan lines GL and multiple data lines DL are intersected to define multiple sub-pixel areas. In this way, the display area AA can be divided into multiple sub-pixel areas.

[0130] In this embodiment, the thin-film transistors, pixel electrodes, and film layers connecting the thin-film transistors and pixel electrodes included in each sub-pixel region of the display substrate can be collectively referred to as sub-pixels (PX). That is, the sub-pixel PX in this embodiment can be understood as the structures included in the sub-pixel region.

[0131] As shown in Figures 1A-2, the driving circuit structure layer can be located on one side of the substrate 10. The driving circuit structure layer is provided with a driving circuit that connects the pixel electrode of each sub-pixel PX. The driving circuit includes a thin film transistor and a storage capacitor. The number of thin film transistors can be one or more, and the number of storage capacitors can be one or more.

[0132] The pixel electrodes can be located in the driving circuit structure layer.

[0133] In this embodiment, the driving circuit structure layer may include multiple conductive layers (as shown in Figures 1A, 2 and 9, including a first conductive layer M1, a second conductive layer M2, a third conductive layer M3 and a transparent conductive layer TD).

[0134] The source connection region S, channel region CH, drain connection region D, and gate G of the thin-film transistor, the storage capacitor in the driving circuit, and the scan line GL and data line DL can be distributed in multiple conductive layers.

[0135] As shown in Figures 1A-2, the source connection region S, channel region CH, and drain connection region D of a thin-film transistor can be disposed in the same layer. The source connection region S, channel region CH, and drain connection region D can constitute the active layer of the thin-film transistor. The active layer can be disposed in a different layer from the gate G. An insulating material layer can be used to isolate the active layer from the gate G. This insulating material layer can be called the first insulating layer GI.

[0136] In this embodiment, the scan line GL can be disposed on the same layer as the gate G and connected to the gate G; the data line DL can be disposed on a different layer from the scan line GL and electrically connected to the source connection region S.

[0137] For example, as shown in FIG1A, the driving circuit structure layer may include multiple conductive layers, which may include a first conductive layer M1, a semiconductor layer ACT, a second conductive layer M2, and a transparent conductive layer TD arranged along the thickness direction Z of the substrate 10; the first conductive layer M1 is disposed closer to the substrate 10. The first conductive layer M1 includes the gate G and scan line GL of the thin-film transistor (not shown in FIG1A), the semiconductor layer ACT includes the source connection region S, the channel region CH, and the drain connection region D of the thin-film transistor; the second conductive layer M2 includes a fifth transition pattern ZJ5 electrically connecting the pixel electrode to the drain connection region D of the thin-film transistor, and the transparent conductive layer TD includes a pixel electrode (second pixel electrode EP2) electrically connected to the fifth transition pattern ZJ5.

[0138] In Figure 1A, the gate G of the thin-film transistor is located on the side of the active layer close to the substrate 10. This thin-film transistor can also be called a bottom-gate thin-film transistor. The display substrate in this example is called the first type of display substrate.

[0139] For example, in some other embodiments, as shown in FIG2, the multiple conductive layers of the driving circuit structure layer may include: a semiconductor layer ACT, a second conductive layer M2, a third conductive layer M3, and a transparent conductive layer TD arranged along the thickness direction Z of the substrate 10; wherein, the semiconductor layer ACT is disposed close to the substrate 10, and the semiconductor layer ACT includes the source connection region S, the channel region CH, and the drain connection region D of the thin film transistor; the second conductive layer M2 includes the gate G and the scan line GL (not shown in FIG2); the third conductive layer M3 includes a sixth transition pattern ZJ6ZJ6 overlapping with the pixel electrode and the drain connection region D of the thin film transistor; and the transparent conductive layer TD may include the second pixel electrode EP2.

[0140] In Figure 2, the gate G of the thin-film transistor is located on the side of the active layer away from the substrate 10. This thin-film transistor can also be called a top-gate thin-film transistor. The display substrate in this example is called the second type of display substrate.

[0141] As further exemplarily, as shown in Figures 9-37, the multiple conductive layers of the driving circuit structure layer may include a first conductive layer M1, a semiconductor layer ACT, a second conductive layer M2, a third conductive layer M3, and a transparent conductive layer arranged along the thickness direction Z of the substrate 10. The first conductive layer M1 includes a data line DL; the semiconductor layer ACT includes the source connection region S, the channel region CH, and the drain connection region D of a thin-film transistor; the second conductive layer M2 includes the gate G of a thin-film transistor; the third conductive layer M3 may include one electrode of a storage capacitor in the driving circuit (such as a second common electrode EC2); and the transparent conductive layer may include a pixel electrode (referred to as a second pixel electrode EP2). The display substrate in this example is referred to as a third type of display substrate.

[0142] As shown in Figures 1A, 2 and 9, the pixel electrode can be included in one conductive layer of the driving circuit structure layer, or the pixel electrode can be set in multiple conductive layers. In the case where the pixel electrode is included in multiple conductive layers, the multiple pixel electrodes can be electrically connected through a transition pattern.

[0143] For example, as shown in FIG9, the second conductive layer M2 may include a first pixel electrode EP1, and the transparent conductive layer may include a second pixel electrode EP2, wherein the orthogonal projection portions of the first pixel electrode EP1 and the second pixel electrode EP2 on the substrate 10 overlap.

[0144] In this embodiment, a piezoelectric layer 20 is included on the side of the driving circuit structure layer away from the substrate 10. The piezoelectric layer 20 includes piezoelectric patterns 21 located in different sub-pixels PX. As shown in Figure 1C (2), the multiple piezoelectric patterns 21 can be independent of each other, so that the piezoelectric patterns 21 in adjacent sub-pixels PX are not connected to each other.

[0145] For example, as shown in Figures 1A-2, a barrier PS can be used to disconnect the piezoelectric pattern 21 and pixel electrode (EP1 / EP2) in different sub-pixels PX.

[0146] As shown in Figures 1A-2, the orthographic projection of the piezoelectric pattern 21 on the substrate 10 can at least partially overlap with the orthographic projection of the pixel electrodes (EP1 / EP2) on the substrate 10. In some examples, the orthographic projection of the piezoelectric pattern 21 on the substrate 10 can be located within the orthographic projection of the pixel electrodes (EP1 / EP2) on the substrate 10; in other examples, the orthographic projection of the piezoelectric pattern 21 on the substrate 10 can cover the orthographic projection of the pixel electrodes (EP1 / EP2) on the substrate 10; in still other examples, the orthographic projection of the piezoelectric pattern 21 on the substrate 10 can partially overlap with the orthographic projection of the pixel electrodes (EP1 / EP2) on the substrate 10.

[0147] In some other examples, as shown in Figure 1C(2), the orthographic projection of the piezoelectric pattern 21 onto the substrate 10 can coincide with the orthographic projection of the pixel electrodes (EP1 / EP2) onto the substrate 10. In this way, the patterns of the piezoelectric pattern 21 and the pixel electrodes (EP1 / EP2) can be the same, thus sharing the same mask and saving manufacturing processes.

[0148] In conjunction with the above embodiments, pixel electrodes may be included in one or more conductive layers of the driving circuit structure layer. In cases where pixel electrodes are included in multiple conductive layers, in some examples, as shown in FIG41, the piezoelectric pattern 21 may at least partially overlap with the orthographic projection of the pixel electrode in each layer onto the substrate 10.

[0149] For example, as shown in FIG41, the piezoelectric pattern 21 overlaps with the orthographic projection of the first pixel electrode EP1 in the second conductive layer M2 onto the substrate 10, and also overlaps with the orthographic projection of the second pixel electrode EP2 in the transparent conductive layer onto the substrate 10.

[0150] In this embodiment, the piezoelectric layer 20 can be formed using a piezoelectric material. For example, the material of the piezoelectric layer 20 can be polyvinylidene fluoride, such as polyvinylidene fluoride.

[0151] In some examples, the piezoelectric coefficient of the piezoelectric pattern 21 can be 26-30 pC / N. For example, it can be 26 pC / N, 27 pC / N, 28 pC / N, 29 pC / N, or 30 pC / N.

[0152] In some examples, the piezoelectric pattern 21 can be a transparent pattern.

[0153] In this embodiment, the scanning signal transmitted on the scanning line GL and the data signal input on the data line DL can be used to turn on the thin film transistor. The pixel electrode of the sub-pixel PX obtains the voltage required to display the image. The piezoelectric pattern 21 in the piezoelectric layer 20 deforms in the thickness direction Z of the substrate 10 under the action of the voltage, thereby driving the ink particles located on the display substrate to move in the thickness direction Z of the substrate 10.

[0154] The driving voltage that drives the piezoelectric pattern 21 to deform is generally 18V, which is less than the driving voltage required for full-color display (VGH≥28V, VGL≤-28V).

[0155] For example, taking Figure 1A as an example, in state 1, no voltage is applied to the pixel electrode and the piezoelectric pattern 21 does not deform; as shown in Figure 1B, in state 2, a voltage is applied to the pixel electrode and the piezoelectric pattern 21 deforms. Since its deformation is located in the thickness direction Z of the substrate 10, the ink particles located on the side of the piezoelectric pattern 21 away from the substrate 10 can be driven to move in a direction away from the substrate 10 (display side), thereby realizing the display of the image.

[0156] The display substrate of this embodiment requires a smaller driving voltage to generate the deformation of the piezoelectric pattern 21, thereby reducing the driving voltage and achieving a high refresh rate at a low voltage, achieving the effect of high-voltage driving. This avoids the problem of TFTs in the GOA region being burned out.

[0157] In some exemplary embodiments, the size of the piezoelectric pattern 21 in the thickness direction Z of the substrate 10 is 5-10 μm.

[0158] In this example, the size of the piezoelectric pattern 21 in the thickness direction Z of the substrate 10 can be understood as the thickness of the piezoelectric pattern 21. The thickness of the piezoelectric pattern 21 can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm.

[0159] In one alternative embodiment of this example, the thickness of the piezoelectric pattern 21 may be related to the structure type of the thin-film transistor in the drive circuit structure layer.

[0160] For example, as shown in Figures 1A and 1B, the gate G of the thin-film transistor is located in the first conductive layer M1. The thin-film transistor is a bottom-gate structure, in which the thin-film transistor has a weaker ability to withstand high voltages. Therefore, the thickness of the piezoelectric pattern 21 can be relatively small. In this example, the thickness of the piezoelectric pattern 21 can be referred to as the first thickness.

[0161] As an example, as shown in FIG2, the gate G of the thin film transistor is located on the second conductive layer M2, and the data line DL is located on the side of the semiconductor layer ACT away from the substrate 10. The thin film transistor is of the top gate structure type. In this example, the thickness of the piezoelectric pattern 21 can be referred to as the second thickness, and the second thickness can also be smaller.

[0162] As an example, as shown in Figures 9-37, the gate G of the thin-film transistor is located in the second conductive layer M2, and the data line DL is located in the first conductive layer M1. In this example, the thin-film transistor has a stronger ability to withstand high voltages; that is, the voltage withstand capability of the thin-film transistor in this example is higher than that shown in Figures 1A and 2. Therefore, the thickness of the piezoelectric pattern 21 can be larger. In this example, the thickness of the piezoelectric pattern 21 can be referred to as the third thickness.

[0163] The first and second thicknesses can be less than the third thickness.

[0164] For example, the third thickness can be 7μm-10μm; the first and second thicknesses can be 5μm-8μm.

[0165] Referring to Figures 1A-2, the pixel electrode may include a second pixel electrode EP2, which may be the pixel electrode closest to the piezoelectric pattern 21 in the driving circuit structure layer. For example, in the thickness direction Z of the substrate 10, the distance between the second pixel electrode EP2 and the piezoelectric pattern 21 is smaller than the distance between other conductive layers in the driving circuit structure layer and the piezoelectric pattern 21.

[0166] In some embodiments, an isolation layer may be spaced between the pixel electrode and the piezoelectric pattern 21 in the thickness direction Z of the substrate 10. This isolation layer may be an inorganic layer or an organic layer, used to protect the pixel electrode.

[0167] In some other embodiments, as shown in Figures 1A-2, the second pixel electrode EP2 can be in direct contact with the surface of the piezoelectric pattern 21 on the side near the substrate 10.

[0168] When the second pixel electrode EP2 is in direct contact with the piezoelectric pattern 21, the piezoelectric pattern 21 can deform when a lower driving voltage is applied to the second pixel electrode EP2, thereby further reducing the driving voltage.

[0169] In practice, the electric field formed on the opposite sides of the piezoelectric pattern 21 in the thickness direction Z of the substrate 10 can drive the piezoelectric pattern 21 to deform in the thickness direction Z of the substrate 10. The opposite sides of the piezoelectric pattern 21 in the thickness direction Z of the substrate 10 can include a pixel electrode and a common electrode (referred to as the third common electrode 30).

[0170] The third common electrode 30 can be disposed on the display substrate. As shown in Figures 1A, 2, and 6, the piezoelectric pattern 21 may include pixel electrodes and the third common electrode 30 on opposite sides of the substrate 10 in the thickness direction Z. The third common electrode 30 may be located on the side of the piezoelectric layer 20 away from the substrate 10, and the orthographic projection of the third common electrode 30 on the substrate 10 at least partially overlaps with the orthographic projection of the piezoelectric pattern 21 on the substrate 10.

[0171] In one example, the orthogonal projection of the third common electrode 30 onto the substrate 10 overlaps the orthogonal projection of the piezoelectric pattern 21 onto the substrate 10.

[0172] In another example, the orthographic projection of the third common electrode 30 onto the substrate 10 may coincide with the orthographic projection of the piezoelectric pattern 21 onto the substrate 10.

[0173] In one example, the third common electrode 30 can be disposed on the entire surface. For example, the orthogonal projection of the third common electrode 30 on the substrate 10 can cover the orthogonal projection of the piezoelectric pattern 21 located on the substrate 10 of the multiple sub-pixels PX.

[0174] In another example, as shown in Figure 1C (3), the third common electrode 30 of different sub-pixels PX can be independent of each other, and multiple third common electrodes 30 can be connected in parallel or in series.

[0175] "Independent" means that the orthogonal projections of the third common electrode 30 of different sub-pixels PX on the substrate 10 do not overlap.

[0176] In this embodiment, the piezoelectric pattern 21 can be deformed under the action of the electric field formed between the pixel electrode EP2 and the third common electrode 30.

[0177] In this embodiment, since the third common electrode 30 is directly disposed on the display substrate, the distance between the third common electrode 30 and the piezoelectric layer 20 in the thickness direction Z of the substrate 10 can be reduced, thereby forming a stronger electric field under the same driving voltage, which can further reduce the driving voltage, accommodate the thin film transistors described in FIG1A and FIG2, and also reduce power consumption.

[0178] In this embodiment, the third common electrode 30 can be formed of a transparent conductive material, such as indium tin oxide.

[0179] In another embodiment, the third common electrode 30 can be formed of a flexible conductive material. In this way, when the piezoelectric pattern 21 deforms in the thickness direction Z of the substrate 10, the flexible third common electrode 30 can match the deformation of the piezoelectric pattern 21, thereby ensuring that the ink particles are driven by the piezoelectric pattern 21.

[0180] In one implementation of this embodiment, an insulating layer may be included between the piezoelectric pattern 21 and the third common electrode 30 to protect the piezoelectric layer 20. Similarly, this insulating layer may be formed of a flexible material.

[0181] In another implementation of this embodiment, the piezoelectric pattern 21 can be in direct contact with the third common electrode 30. For example, as shown in Figures 1A, 2, and 6, the surface of the piezoelectric pattern 21 facing away from the substrate 10 can be in direct contact with the third common electrode 30. This reduces the distance between the third common electrode 30 and the piezoelectric pattern 21 in the thickness direction Z of the substrate 10, thereby achieving a higher electric field strength at the same driving voltage, which helps to reduce the driving voltage.

[0182] In this embodiment, when the third common electrode 30 is included on the display substrate, as shown in FIG47, since the opposing substrate 1711 of the display substrate includes an opposing electrode 1712 for driving ink particles, the opposing electrode 1712 can form an electric field with the pixel electrode and an electric field with the third common electrode. Thus, two electric fields along the thickness direction of the substrate 10 can be formed in the sub-pixel. The two electric fields are superimposed, which is beneficial to the movement of ink particles and further improves the response speed.

[0183] Of course, when the third common electrode 30 is not provided on the display substrate, an electric field can be formed between the counter electrode 1712 and the pixel electrode. This electric field can simultaneously drive the movement of ink particles and cause the piezoelectric layer to deform, thereby saving the material used for the third common electrode, increasing the space for ink particles, accommodating more ink particles, and thus improving the display effect.

[0184] In some embodiments, as shown in FIG3, the piezoelectric layer 20 may further include a barrier pattern 22, which may include a plurality of openings, wherein the orthogonal projections of the pixel electrodes EP1 / EP2 of different sub-pixels PX and the piezoelectric pattern 21 on the substrate 10 are located within the orthogonal projections of different openings on the substrate 10.

[0185] In this embodiment, the size of the barrier pattern 22 is larger than the size of the piezoelectric pattern 21 in the thickness direction Z of the substrate 10.

[0186] As shown in Figures 3 and 8, Figure 8 illustrates a schematic diagram of the planar structure of the piezoelectric layer 20. As shown in Figures 3-8, the piezoelectric layer 20 may include a piezoelectric pattern 21 and a barrier pattern 22. The barrier pattern 22 may include an opening, and the piezoelectric pattern 21 may be located within the opening. In this way, the barrier pattern 22 can isolate the piezoelectric patterns 21 of different sub-pixels PX.

[0187] As shown in Figures 3 and 4, the orthographic projection of the pixel electrode on the substrate 10 can be located within the orthographic projection of the opening of the barrier pattern 22 on the substrate 10.

[0188] In some examples, as shown in Figure 3, the barrier pattern 22 can be directly connected to the piezoelectric pattern 21, so that the barrier pattern 22 and the piezoelectric pattern 21 form a whole.

[0189] The size of the barrier pattern 22 in the thickness direction Z of the substrate 10 can be larger than the size of the piezoelectric pattern 21 in the thickness direction Z of the substrate 10. In this way, the barrier pattern 22 can serve as an isolation pillar for the display substrate and can be used to support the opposing substrate 171 and the display substrate 173 when they are aligned with the opposing substrate 171.

[0190] In some examples, the size of the barrier pattern 22 in the planar direction X of the substrate 10 can be smaller than the size of the piezoelectric pattern 21 in the planar direction X of the substrate 10. This reduces the spacing between sub-pixels PX, thereby increasing the sub-pixel PX arrangement density and thus improving the resolution of the display substrate.

[0191] In some examples, the barrier pattern 22 and the piezoelectric pattern 21 can be formed from the same material, thus the barrier pattern 22 and the piezoelectric pattern 21 can be formed in the same process.

[0192] In some examples, as shown in Figure 4, which shows a cross-sectional view of the piezoelectric layer 20, the barrier pattern 22 may include a first piezoelectric layer 2231 and a second piezoelectric layer 2232. The first piezoelectric layer 2231 may be disposed in the same layer as the piezoelectric pattern 21, and the second piezoelectric layer 2232 is located on the side of the first piezoelectric layer 2231 that is away from the substrate 10.

[0193] In this embodiment, the first piezoelectric layer 2231 and the piezoelectric pattern 21 are disposed on the same layer, so the first piezoelectric layer 2231 and the piezoelectric pattern 21 can be formed in the same patterning process. The first piezoelectric layer 2231 and the piezoelectric pattern 21 have the same thickness.

[0194] The piezoelectric material used in the second piezoelectric layer 2232 may be the same as or different from the piezoelectric material used in the first piezoelectric layer 2231.

[0195] In one example, the thickness of the second piezoelectric layer 2232 may be greater than the thickness of the first piezoelectric layer 2231.

[0196] As shown in Figure 4(1), when forming the piezoelectric layer 20 of this embodiment, the first piezoelectric layer 2231 and the piezoelectric pattern 21 can be formed in a single patterning process; then, as shown in Figure 4(2), piezoelectric material is grown on the side of the first piezoelectric layer 2231 away from the substrate 10 to form the second piezoelectric layer 2232.

[0197] The piezoelectric layer 20 structure of this embodiment can simplify the manufacturing process, improve production efficiency, and reduce production costs.

[0198] In one embodiment of this invention, as shown in FIG3, a pixel defining layer (PDL) may be further included. The PDL includes multiple opening regions (not shown in the figure), and the pixel electrode is located in the opening region. The pixel electrode and the PDL may be disposed in the same layer, or the PDL may be located on the side of the pixel electrode facing away from the substrate 10, and the piezoelectric layer 20 may be located on the side of the PDL facing away from the substrate 10. In this way, the pixel electrodes located in different sub-pixels PX can be isolated by the PDL.

[0199] In some other embodiments, as shown in FIG5, FIG5(1) and (2) show a schematic diagram of the process of forming piezoelectric layer 20. As shown in FIG5(1), piezoelectric layer 20' can be formed on the entire surface. Then, as shown in FIG5(2), the portion of piezoelectric layer 20' located in the sub-pixel PX region is etched to obtain piezoelectric pattern 21 and barrier pattern 22.

[0200] The etching depth is less than the thickness of the piezoelectric layer 20.

[0201] The piezoelectric layer 20 structure of this embodiment can improve the film layer coherence between the barrier pattern 22 and the piezoelectric pattern 21 in the piezoelectric layer 20. The opening formed in this way has no gap between the sidewall and bottom wall, thereby avoiding cross-current between the electrophoretic liquid located in different sub-pixels PX, thus improving the display quality.

[0202] In some embodiments, the size of the barrier pattern 22 in the planar direction X of the substrate 10 is greater than the size of the piezoelectric pattern 21 in the thickness direction Z of the substrate 10.

[0203] As shown in Figures 3 and 4, the size of the barrier pattern 22 in the planar direction X of the substrate 10 can affect the spacing between sub-pixels PX. When the size of the barrier pattern 22 in the planar direction X of the substrate 10 is larger than the size of the piezoelectric pattern 21 in the thickness direction Z of the substrate 10, the thickness of the barrier pattern 22 can be made larger, thereby preventing the barrier pattern 22 from deforming and thus preventing the aperture ratio of the sub-pixels PX from changing.

[0204] For example, the size of the piezoelectric pattern 21 in the thickness direction Z of the substrate 10 can be 5μm-10μm, and the size of the barrier pattern 22 in the planar direction X of the substrate 10 can be 8μm-12μm.

[0205] In this embodiment, the piezoelectric pattern 21, under the influence of the voltage from the pixel electrode, can deform in the thickness direction Z of the substrate 10. This may cause the barrier pattern 22 to deform in the planar direction X of the substrate 10. In this embodiment, the dimension of the barrier pattern 22 in the planar direction X of the substrate 10 is larger than the thickness of the piezoelectric pattern 21, and the dimension of the barrier pattern 22 in the thickness direction Z of the substrate 10 is also larger than the thickness of the piezoelectric pattern 21. This allows the barrier pattern 22 to resist the deformation pull from the piezoelectric pattern 21, thereby preventing the barrier pattern 22 from deforming in the planar direction X of the substrate 10, ensuring that the aperture ratio of the sub-pixel PX remains consistent throughout the display process.

[0206] Referring to Figure 6, in some embodiments, the barrier pattern 22 may include a first portion 223 located on the side of the piezoelectric pattern 21 away from the substrate 10, and a second portion 224 located on the side of the piezoelectric pattern 21 close to the substrate 10.

[0207] In the thickness direction Z of the substrate 10, the size of the second part 224 is smaller than the size of the first part 223, and the size of the first part 223 is larger than the size of the piezoelectric pattern 21.

[0208] As shown in Figure 6, along the thickness direction Z of the substrate 10, the barrier pattern 22 sequentially includes a second part 224 and a first part 223.

[0209] The second part 224 can isolate the pixel electrodes of different sub-pixels PX, so the barrier pattern 22 can also isolate the pixel electrodes of different sub-pixels PX.

[0210] Both the first part 223 and the second part 224 can isolate the piezoelectric patterns 21 of different sub-pixels PX. The second part 224 can be used to support the first part 223.

[0211] The thickness of the second part 224 is less than the thickness of the first part 223. This thickness refers to the dimension in the thickness direction Z of the substrate 10.

[0212] In some examples, as shown in Figure 6, the dimension of the second portion 224 in the planar direction X of the substrate 10 is equal to the dimension of the first portion 223 in the planar direction X of the substrate 10.

[0213] In some other examples, the size of the second portion 224 in the planar direction X of the substrate 10 may also be larger than the size of the first portion 223 in the planar direction X of the substrate 10. In this case, the orthographic projection of the second portion 224 on the substrate 10 may overlap with the orthographic projection of the piezoelectric pattern 21 on the substrate 10, thereby increasing the support force on the first portion 223 through the second portion 224.

[0214] In this embodiment, as shown in FIG7, FIG7 shows a cross-sectional structural schematic diagram of a piezoelectric layer 20 in this embodiment. As shown in FIG7, the first part 223 may include a first piezoelectric layer 2231 and a second piezoelectric layer 2232. The second piezoelectric layer 2232 is located on the side of the first piezoelectric layer 2231 away from the substrate 10, and the first piezoelectric layer 2231 is located on the side of the second part 224 away from the substrate 10.

[0215] The first piezoelectric layer 2231 can be disposed on the same layer as the piezoelectric pattern 21.

[0216] The thickness of the second piezoelectric layer 2232 can be greater than the thickness of the first piezoelectric layer 2231.

[0217] The material of the second piezoelectric layer 2232 may be the same as or different from the material of the first piezoelectric layer 2231.

[0218] When forming the piezoelectric layer 20 shown in FIG7, a first patterning process can be performed to form a second portion 224. Then, a piezoelectric pattern 21 and a first piezoelectric layer 2231 are formed on the side of the second portion 224 away from the substrate 10. Then, piezoelectric material is grown on the side of the first piezoelectric layer 2231 away from the substrate 10 to obtain a second piezoelectric layer 2232.

[0219] Of course, in another example of forming the piezoelectric layer 20 shown in FIG6, a first patterning process can be performed first to form the second part 224, and then a full-surface piezoelectric material layer can be formed on the side of the second part 224 away from the substrate 10. The thickness of the piezoelectric material layer is equal to the thickness of the first part 223. Then, the area in the piezoelectric layer 20 where the sub-pixel PX is located is etched to form the piezoelectric pattern 21 and the first part 223. The etching depth is less than the thickness of the piezoelectric material layer.

[0220] In this embodiment, the second part 224 can be set in the same layer as the pixel electrode or in a different layer.

[0221] As shown in Figure 6, in one implementation of this embodiment, the second part 224 can be disposed on the same layer as the second pixel electrode EP2, and the second pixel electrode EP2 located in different sub-pixels PX can be isolated by the second part 224.

[0222] The thickness of the second part 224 can be the same as the thickness of the second pixel electrode EP2, and this thickness refers to the dimension in the thickness direction Z of the substrate 10.

[0223] In this embodiment, the piezoelectric layer 20 can be used because the second part 224 in the barrier pattern 22 can isolate the second pixel electrode EP2 of different sub-pixels PX, thereby allowing the piezoelectric pattern 21 to act as the pixel delimiting layer PDL between sub-pixels PX, which can save process steps.

[0224] In one example of this embodiment, the second portion 224 can be in direct contact with the pixel electrode, such as the sidewall of the second portion 224 being in direct contact with the sidewall of the pixel electrode. Thus, the second portion 224 has second pixel electrodes EP2 on opposite sides in the planar direction X of the substrate 10. When there is a voltage difference between the voltages applied to the two second pixel electrodes EP2, an electric field (hereinafter referred to as a lateral electric field) parallel to the planar direction X of the substrate 10 can be formed at the second portion 224.

[0225] In this example, to prevent the second portion 224 from deforming under the influence of the lateral electric field, the size of the second portion 224 in the planar direction X of the substrate 10 can be larger than the size of the piezoelectric pattern 21 in the thickness direction Z of the substrate 10. Therefore, the voltage on the second pixel electrode EP2 is sufficient to drive the piezoelectric pattern 21 to deform only in the thickness direction Z of the substrate 10, but not enough to cause deformation of the second portion 224 in the planar direction X of the substrate 10. This prevents changes in the aperture ratio of the sub-pixel PX.

[0226] In one embodiment of this invention, as shown in FIG8, the driving circuit structure layer further includes a scan line GL and a data line DL, the scan line GL intersects the data line DL, and the sub-pixel PX is located in the area defined by the intersection of the scan line GL and the data line DL; wherein, the barrier pattern 22 includes a first barrier 221 parallel to the scan line GL and a second barrier 222 parallel to the data line DL; wherein, the orthographic projection of the first barrier 221 on the substrate 10 at least partially overlaps with the orthographic projection of the scan line GL on the substrate 10, and the orthographic projection of the second barrier 222 on the substrate 10 at least partially overlaps with the orthographic projection of the data line DL on the substrate 10.

[0227] Please refer to Figures 38-40, which respectively show several overlapping film layers of the barrier pattern 22, scan line GL, data line DL, first pixel electrode EP1 and second pixel electrode EP2. Figures 38, 39 and 40 correspond to Figure 9.

[0228] The first barrier wall 221 and the second barrier wall 222 define the opening, and the piezoelectric pattern 21 is located within the space enclosed by the first barrier wall 221 and the second barrier wall 222.

[0229] In this case, the orthographic projection of the first barrier 221 of the barrier pattern 22 on the substrate 10 is parallel to the scan line GL and at least partially overlaps with the orthographic projection of the scan line GL on the substrate 10. For example, as shown in Figures 38-40, the orthographic projection of the first barrier 221 on the substrate 10 can cover the orthographic projection of the scan line GL on the substrate 10.

[0230] In some other examples, the orthographic projection of the first barrier 221 onto the substrate 10 may also fall within the orthographic projection of the scan line GL onto the substrate 10. In still some other examples, the orthographic projection of the first barrier 221 onto the substrate 10 may also coincide with the orthographic projection of the scan line GL onto the substrate 10.

[0231] In some examples, the width of the first barrier 221 along the data line DL direction is greater than the width of the scan line GL along the data line DL direction. This prevents the voltage on the pixel electrodes on both sides of the first barrier 221 from causing deformation of the piezoelectric pattern 21 when the first barrier 221 separates the pixel electrodes of each sub-pixel PX.

[0232] In this design, the orthographic projection of the second barrier 222 of the barrier pattern 22 onto the substrate 10 is parallel to the data line DL and at least partially overlaps with the orthographic projection of the data line DL onto the substrate 10. For example, as shown in Figures 38-40, the orthographic projection of the first barrier 221 onto the substrate 10 can cover the orthographic projection of the data line DL onto the substrate 10.

[0233] In some other examples, the orthographic projection of the second barrier 222 onto the substrate 10 may also fall within the orthographic projection of the data line DL onto the substrate 10. In still some other examples, the orthographic projection of the second barrier 222 onto the substrate 10 may coincide with the orthographic projection of the data line DL onto the substrate 10.

[0234] In some examples, the width of the second barrier 222 along the scan line GL is greater than the width of the data line DL along the scan line GL. This prevents the voltage on the pixel electrodes on both sides of the second barrier 222 from driving the piezoelectric pattern 21 to deform when the second barrier 222 separates the pixel electrodes of each sub-pixel PX.

[0235] In some embodiments, the pixel electrode may include a second pixel electrode EP2. In the thickness direction Z of the substrate 10, the distance between the second pixel electrode EP2 and the piezoelectric pattern 21 is smaller than the distance between the conductive layer in the driving circuit structure layer other than the conductive layer where the second pixel electrode EP2 is located and the piezoelectric pattern 21.

[0236] Wherein, the edge of the first barrier 221 near the second pixel electrode EP2 coincides with the orthographic projection of the edge of the second pixel electrode EP2 near the scan line GL onto the substrate 10; and / or,

[0237] The edge of the second barrier 222 near the second pixel electrode EP2 coincides with the orthographic projection of the edge of the second pixel electrode EP2 near the data line DL on the substrate 10.

[0238] As shown in Figure 1C, the orthographic projection of the second pixel electrode EP2 onto the substrate 10 can fall within the area defined by the intersection of the scan line GL and the data line DL. Thus, in the orthographic projection onto the substrate 10, the second pixel electrode EP2 does not overlap with either the scan line GL or the data line DL. As shown in Figure 9, the orthographic projection of the second pixel electrode EP2 onto the substrate 10 does not overlap with the scan line GL, but partially overlaps with the data line DL.

[0239] For example, as shown in FIG8, the edge of the first barrier 221 near the second pixel electrode EP2 can coincide with the orthographic projection of the edge of the second pixel electrode EP2 near the scan line GL on the substrate 10. This results in a larger width of the first barrier 221 along the data line DL direction, preventing deformation of the first barrier 221.

[0240] For example, as shown in FIG8, the edge of the second barrier 222 near the second pixel electrode EP2 can coincide with the orthographic projection of the edge of the second pixel electrode EP2 near the data line DL on the substrate 10. This results in a larger width of the second barrier 222 in the scan line GL direction, preventing deformation of the second barrier 222.

[0241] Since the piezoelectric pattern 21 is located within the space enclosed by the first barrier 221 and the second barrier 222, the piezoelectric pattern 21 can coincide with the orthographic projection of the second pixel electrode EP2 on the substrate 10 when the first barrier 221 and the second barrier 222 are flush with the edge of the second pixel electrode EP2, respectively.

[0242] Thus, as shown in Figure 8, the width of the first barrier 221 along the data line DL direction can be equal to the gap between the second pixel electrodes in two adjacent sub-pixels PX along the data line DL direction. Similarly, the width of the second barrier 221 along the scan line GL direction can be equal to the gap between the second pixel electrodes in two adjacent sub-pixels PX along the scan line GL direction.

[0243] Of course, when one of the first barrier 221 and the second barrier 222 is flush with the edge of the second pixel electrode EP2, the aperture ratio of the sub-pixel PX can be increased.

[0244] In some other examples, as shown in Figures 38-40, the orthogonal projection of the second pixel electrode EP2 onto the substrate 10 may overlap with the data line DL portion but not with the scan line GL.

[0245] As shown in Figure 38, the orthographic projection of the first barrier 221 on the substrate 10 covers the orthographic projection of the scan line GL on the substrate 10, and coincides with the orthographic projection of the second pixel electrode EP2 near the scan line GL on the first barrier 221.

[0246] As shown in Figure 39, the orthographic projection of the first barrier 221 on the substrate 10 covers the orthographic projection of the scan line GL on the substrate 10 and overlaps with the second pixel electrode EP2. The edge of the second pixel electrode EP2 near the scan line GL is located within the orthographic projection of the first barrier 221.

[0247] As shown in Figure 40, the orthogonal projection of the first barrier 221 on the substrate 10 covers the orthogonal projection of the scan line GL on the substrate 10 and does not overlap with the second pixel electrode EP2.

[0248] As shown in Figures 38-40, the orthographic projection of the first barrier 221 on the substrate 10 covers the orthographic projection of the data line DL on the substrate 10 and overlaps with the orthographic projection of the second pixel electrode EP2 on the substrate 10.

[0249] Referring to Figures 3-7, the display substrate includes a third common electrode 30. When the piezoelectric layer 20 includes a barrier pattern 22, the barrier pattern 22 and the third common electrode 30 can be configured in the following ways:

[0250] In one example, as shown in Figure 3, the barrier pattern 22 can isolate the third common electrode 30 located in different sub-pixels PX. In this way, the orthographic projection of the third common electrode 30 on the substrate 10 is located within the opening of the barrier pattern 22.

[0251] In this example, a first piezoelectric layer 2231 with piezoelectric pattern 21 and barrier pattern 22 can be formed first. Then, a third common electrode 30 is formed on the side of piezoelectric pattern 21 away from substrate 10. The orthographic projection of the third common electrode 30 on substrate 10 does not overlap with the orthographic projection of the first piezoelectric layer 2231 on substrate 10. Then, a second piezoelectric layer 2232 is formed on the side of the first piezoelectric layer 2231 away from substrate 10.

[0252] In another example, the orthographic projection of the third common electrode 30 on the substrate 10 is located within the opening of the barrier pattern 22, and a fourth electrode (not shown) may be included on the side of the barrier pattern 22 facing away from the substrate 10, the orthographic projection of the fourth electrode on the substrate 10 being non-overlapping with the orthographic projection of the third common electrode 30 on the substrate 10.

[0253] When forming the display substrate of this embodiment, a first piezoelectric layer 2231 with piezoelectric pattern 21 and barrier pattern 22 can be formed first. Then, a second piezoelectric layer 2232 can be formed on the side of the first piezoelectric layer 2231 away from the substrate 10. After that, a third common electrode 30 can be formed on the entire surface. When forming the third common electrode 30, a chemical deposition method can be used. The formed common electrode layer can be isolated at the barrier pattern 22, resulting in the third common electrode 30 located in the sub-pixel region and a fourth electrode located on the side of the barrier pattern 22 away from the substrate 10.

[0254] The fourth electrode can be insulated from the third common electrode 30. The fourth electrode can be regarded as a residual layer left on the barrier pattern 22 when the third common electrode 30 is formed.

[0255] Among them, the residual layer on the retaining wall pattern 22 can be removed to form the structure shown in Figure 3 and Figure 6.

[0256] In this embodiment, since a piezoelectric pattern 21 is provided in the sub-pixel PX, the piezoelectric pattern 21 can be deformed in the thickness direction Z of the substrate 10 under the influence of the driving voltage when a driving voltage is applied to the pixel electrode. This can drive the ink particles to move in the direction away from the substrate 10, thereby improving the response speed of the ink particles and effectively reducing the driving voltage. This reduces the requirement for high voltage driving of the thin film transistor, that is, a thin film transistor with lower high voltage resistance can be used.

[0257] In conjunction with the above embodiments, as shown in Figure 1A, the thin film transistor can be a bottom-gate thin film transistor, as shown in Figure 2, the thin film transistor can be a top-gate thin film transistor, as shown in Figures 9-37, the gate G of the thin film transistor is located on the side of the active layer away from the substrate 10, and the data line DL is located on the side of the active layer close to the substrate 10.

[0258] In the display substrate shown in Figure 9, Figure 19 or Figure 37, the voltage withstand capability of the thin film transistor is higher than that of the thin film transistor shown in Figure 1A and Figure 2. Thus, when using the display substrate shown in Figure 9, Figure 19 or Figure 37, the high voltage withstand capability of the driving circuit can be further improved, and a higher driving voltage can be achieved. Combined with the piezoelectric pattern 21, the response speed of the ink particles can be greatly improved.

[0259] The display substrate shown in Figures 9-37 will now be described.

[0260] In Figures 9 to 37, Figure a exemplarily shows a planar structural schematic of a single sub-pixel PX in the display substrate; Figure b exemplarily shows a cross-sectional structural schematic along position AA' in Figure a; and Figure c exemplarily shows a cross-sectional structural schematic along positions BB' and CC' in Figure a. In Figures 9 to 18, Figure d exemplarily shows a planar structural schematic of four sub-pixels PX in the display substrate.

[0261] As shown in Figures 9, 19, or 37, the driving circuit structure layer of the display substrate is called the third driving circuit structure layer. It includes a first conductive layer M1, a semiconductor layer ACT, a first insulating layer GI, and a second conductive layer M2, which are sequentially stacked on one side of the substrate 10. The first conductive layer M1 is disposed close to the substrate 10 and includes a data line DL. The semiconductor layer ACT includes multiple semiconductor patterns located in different sub-pixels PX. The semiconductor patterns include the source connection region S, the first conductive region DT1, and the channel region CH of the thin film transistor. The source connection region S, the first conductive region DT1, and the channel region CH are arranged along the first direction f1 and connected sequentially. The second conductive layer M2 includes a first transition pattern ZJ1, a scan line GL, and the gate G of the thin film transistor.

[0262] The first insulating layer GI includes a first via H1, which exposes a portion of the data line DL, the source connection region S, and the first conductor region DT1. The data line DL and the source connection region S are respectively connected to the first transition pattern ZJ1 through the first via H1. The orthographic projections of the first transition pattern ZJ1 and the first conductor region DT1 on the substrate 10 do not overlap.

[0263] In this embodiment, the first conductive region DT1 is exposed at the location of the first via H1, and the first transition pattern ZJ1 and the orthographic projection of the first conductive region DT1 on the substrate 10 do not overlap, that is, the first transition pattern ZJ1 does not cover the first conductive region DT1. In other words, the first transition pattern ZJ1 achieves the connection between the data line DL and the source connection region S by partially covering or partially overlapping the first via H1. By adjusting the doping concentration of the first conductive region DT1 exposed by the first via H1, the resistance of the first via H1 can be adjusted, thereby adjusting the voltage division magnitude of the first via H1, which is beneficial to improving the voltage withstand capability of the thin film transistor.

[0264] Referring to Figure 46, a bar graph showing the change in the channel region CH electric field intensity with the doping concentration of the first conductive region DT1 is shown. As shown in Figure 46, the channel region CH electric field intensity decreases as the doping concentration of the first conductive region DT1 decreases. This is because as the doping concentration of the first conductive region DT1 decreases, the resistance and voltage division of the first via H1 increase, thus reducing the channel region CH electric field intensity and consequently improving the breakdown voltage capability of the thin-film transistor. With the improved breakdown voltage capability of the thin-film transistor, the driving voltage applied to the pixel electrode can be increased. With an increased driving voltage, the degree of deformation of the piezoelectric pattern 21 can be increased, thereby improving the response speed of the ink particles.

[0265] In this embodiment, a thin-film transistor (TFT) refers to a device that includes at least three terminals: a gate (G), a drain (G), and a source (S). A TFT has a channel region (CH) between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel region (CH), and the source. In this embodiment, the channel region (CH) refers to the region through which the current primarily flows.

[0266] In embodiments, when using thin-film transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this disclosure, the "source" and "drain" can be interchanged.

[0267] For example, the material of the active layer 12 includes oxide semiconductor materials such as IGZO, and may also include materials such as amorphous silicon or low-temperature polycrystalline silicon, which are not limited in this disclosure.

[0268] In some embodiments, the channel region CH of the thin-film transistor comprises a semiconductor material M1OaNb, where M1 is a single metal or a combination of multiple metals, a > 0, and b ≥ 0, O represents oxygen, and N represents nitrogen. That is, the semiconductor material is a metal oxide material or a metal oxide-nitrogen material. Suitable metal oxide materials include, but are not limited to, one or more of the following: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth-doped oxides (Ln-OS, such as rare earth element-doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O. The material of the channel CH can be amorphous, partially crystalline, single crystal or polycrystalline, and can also be a single layer or multilayer structure.

[0269] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the material of the channel region CH includes indium gallium zinc oxide (IGZO).

[0270] For example, referring to Figures 2, 20, or 30, the data line DL includes a first segment XD1 extending along a second direction f2 and a second segment XD2 extending along a first direction f1. As shown in Figures 9, 19, or 37, the second segment XD2 is connected to the side of the first segment XD1 near the channel region CH. The second segment XD2 is exposed at the first via H1. The second segment XD2 overlaps with the orthographic projection of the source connection region S on the substrate 10. The first transition pattern ZJ1 connects the second segment XD2 to the source connection region S by partially overlapping the first via H1. The source connection region S is located near the intersection of the first segment XD1 and the scan line GL.

[0271] For example, the first direction f1 is parallel to the extension direction of the scan line GL.

[0272] For example, as shown in Figures 9, 19, or 37, the sub-pixel PX further includes pixel electrodes EP1 / EP2, the gate G of the thin-film transistor is connected to the scan line GL, the source connection region S is connected to the data line DL through the first transition pattern ZJ1, and the drain connection region D is connected to the pixel electrodes EP1 / EP2. The pixel electrodes EP1 / EP2 are used to drive the movement of ink particles. The ink particles can be electrophoretic particles, such as two-color, three-color, or four-color particles; or they can be liquid crystal molecules.

[0273] In this embodiment, the movement of the target particle can refer to the up-and-down movement of the target particle between two substrates or plates (such as moving in a direction perpendicular to the substrate 10).

[0274] Because the process of forming the first via H1 will cause over-etching of the source connection region S and the first conductor region DT1, as shown in Figure 9, Figure 19 or Figure 37, the thickness of the source connection region S and the first conductor region DT1 is less than the thickness of the channel region CH.

[0275] For example, as shown in FIG9, FIG19 or FIG37, the thickness of the first conductor region DT1 is less than or equal to the thickness of the source connection region S.

[0276] In some embodiments, as shown in FIG9, FIG19 or FIG37, the semiconductor pattern further includes: a second conductive region DT2 connected between the first conductive region DT1 and the channel region CH, wherein the thickness of the first conductive region DT1 is less than the thickness of the second conductive region DT2, and the thickness of the second conductive region DT2 is less than or equal to the thickness of the channel region CH.

[0277] In some embodiments, as shown in FIG9 or FIG37, the semiconductor pattern further includes: a drain connection region D, a third conductive region DT3, and a fourth conductive region DT4 of a thin-film transistor. The channel region CH, the fourth conductive region DT4, the third conductive region DT3, and the drain connection region D are arranged along a first direction f1 and connected sequentially. The thickness of the third conductive region DT3 is less than the thickness of the fourth conductive region DT4. The second conductive layer M2 further includes a second transition pattern ZJ2, which is located on the side of the gate G away from the first transition pattern ZJ1. The first insulating layer GI also includes a second via H2, which exposes the drain connection region D and the third conductive region DT3. The second transition pattern ZJ2 and the drain connection region D are connected through the second via H2. The orthographic projections of the second transition pattern ZJ2 and the third conductive region DT3 on the substrate 10 do not overlap.

[0278] In this embodiment, the third conductive region DT3 is exposed at the location of the second via H2, and the orthographic projection of the second transition pattern ZJ2 and the third conductive region DT3 on the substrate 10 does not overlap. That is, the second transition pattern ZJ2 does not cover the third conductive region DT3. In other words, the second transition pattern ZJ2 is connected to the drain connection region D by partially covering or partially overlapping the second via H2. By adjusting the doping concentration of the third conductive region DT3 exposed by the second via H2, the resistance of the second via H2 can be adjusted, thereby adjusting the voltage division magnitude of the second via H2, which can further improve the voltage withstand capability of the thin film transistor.

[0279] For example, the thickness of the third conductive region DT3 is less than or equal to the thickness of the drain connection region D. The thicknesses of both the drain connection region D and the third conductive region DT3 are less than the thickness of the channel region CH. The thickness of the fourth conductive region DT4 is less than or equal to the thickness of the channel region CH.

[0280] For example, the thickness of the drain connection region D is approximately equal to the thickness of the source connection region S, the thickness of the third conductor region DT3 is approximately equal to the thickness of the first conductor region DT1, and the thickness of the fourth conductor region DT4 is approximately equal to the thickness of the second conductor region DT2.

[0281] In practical implementation, after forming the second conductive layer M2, the first insulating layer GI can be etched a second time using the second conductive layer M2 as a mask. Then, using the second conductive layer M2 as a mask again, a self-aligned process is used to conduct the semiconductor material in the exposed areas of the semiconductor layer ACT (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3, and the fourth conductor region DT4). This conductor formation process can, for example, use dry etching equipment or ion implantation equipment to implant plasma (such as plasma containing at least one element selected from helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material, or use ion doping technology to dope any one or more of the above elements into the semiconductor material to achieve conductor formation. Among these methods, using dry etching equipment to conduct the semiconductor material can be performed simultaneously with the second etching process of the first insulating layer GI, thereby simplifying the process.

[0282] In specific implementation, after forming the second conductive layer M2, the first insulating layer GI may not be etched a second time. Instead, the second conductive layer M2 can be used as a mask to directly conduct the semiconductor material in the exposed areas of the semiconductor layer ACT (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3, and the fourth conductor region DT4) using a self-aligned process. This conductor formation process can be achieved by, for example, using a dry etching device or an ion implantation device to implant plasma (such as plasma containing at least one of the elements helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material, or by using an ion doping process to dope any one or more of the above elements into the semiconductor material to achieve conductor formation.

[0283] For example, when the first insulating layer GI is etched a second time, as shown in FIG9, FIG19, or FIG37, the second conductive region DT2 and the first insulating layer GI do not overlap when projected onto the substrate 10. The thickness of the first conductive region DT1 is less than the thickness of the source connection region S and the second conductive region DT2, and the thickness of the second conductive region DT2 is less than the thickness of the channel region CH. The fourth conductive region DT4 and the first insulating layer GI do not overlap when projected onto the substrate 10. The thickness of the third conductive region DT3 is less than the thickness of the drain connection region D and the fourth conductive region DT4, and the thickness of the fourth conductive region DT4 is less than the thickness of the channel region CH.

[0284] For example, without performing a secondary etching on the first insulating layer GI, the first insulating layer GI covers the second conductive region DT2 away from the surface of the substrate 10, the thickness of the second conductive region DT2 is approximately equal to the thickness of the channel region CH, and the thickness of the first conductive region DT1 is approximately equal to the thickness of the source connection region S. The first insulating layer GI covers the fourth conductive region DT4 away from the surface of the substrate 10, the thickness of the fourth conductive region DT4 is approximately equal to the thickness of the channel region CH, and the thickness of the third conductive region DT3 is approximately equal to the thickness of the drain connection region D.

[0285] For example, the pixel electrodes EP1 / EP2 of different sub-pixels PX are separated from each other. The pixel electrodes EP1 / EP2 may include a first pixel electrode EP1 and may also include a second pixel electrode EP2. The first pixel electrode EP1 and the second pixel electrode EP2 are, for example, disposed in different layers and connected through a via.

[0286] In the thickness direction Z of the substrate 10, the vertical distance between the second pixel electrode EP2 and the piezoelectric pattern 21 can be smaller than the vertical distance between the first pixel electrode EP1 and the piezoelectric pattern 21.

[0287] For example, a sub-pixel PX may further include a common electrode EC1 / EC2, the orthographic projections of which overlap with those of the pixel electrodes EP1 / EP2 on the substrate 10 to form a storage capacitor. The common electrodes EC1 / EC2 of different sub-pixels PX may be interconnected. The common electrode EC1 / EC2 may include a first common electrode EC1 and may also include a second common electrode EC2. The first common electrode EC1 and the second common electrode EC2 may be disposed on the same layer and interconnected, or they may be disposed on different layers and connected through vias.

[0288] In some embodiments, as shown in FIG9, the second transition pattern ZJ2 overlaps with the orthographic projection of the common electrode EC1 / EC2 on the substrate 10, and the second transition pattern ZJ2 constitutes the first pixel electrode EP1.

[0289] In some embodiments, as shown in FIG37, the second transition pattern ZJ2 does not overlap with the orthographic projection of the common electrodes EC1 / EC2 on the substrate 10. The semiconductor pattern further includes a fifth conductive region DT5, located on the side of the drain connection region D away from the channel region CH, connected to the drain connection region D. The fifth conductive region DT5 overlaps with the orthographic projection of the common electrodes EC1 / EC2 on the substrate 10, and the fifth conductive region DT5 constitutes the first pixel electrode EP1. The second transition pattern ZJ2 serves to connect the first pixel electrode EP1 and the second pixel electrode EP2.

[0290] In some embodiments, as shown in FIG9, FIG19 or FIG37, the sub-pixel PX further includes a first common electrode EC1, a first pixel electrode EP1, a second common electrode EC2 and a second pixel electrode EP2, wherein the first pixel electrode EP1 is located in the semiconductor layer ACT (as shown in FIG19 and FIG37) or the second conductive layer M2 (as shown in FIG9).

[0291] The first common electrode EC1 and the first pixel electrode EP1 are disposed in different layers and their orthogonal projections on the substrate 10 overlap to form the first storage capacitor Cst1. The second common electrode EC2 and the second pixel electrode EP2 are disposed in different layers and their orthogonal projections on the substrate 10 overlap to form the second storage capacitor Cst2.

[0292] As shown in Figure 9, the first pixel electrode EP1 is located in the second conductive layer M2. The first pixel electrode EP1 is the second transition pattern ZJ2 of the second conductive layer M2. The first pixel electrode EP1 is connected to the drain connection area D through the second via H2.

[0293] As shown in Figure 37, the first pixel electrode EP1 is located in the semiconductor layer ACT. The first pixel electrode EP1 is located in the fifth conductor region DT5 of the semiconductor layer ACT. The fifth conductor region DT5 is located on the side of the drain connection region D away from the channel region CH and is connected to the drain connection region D.

[0294] As shown in Figure 19, the first pixel electrode EP1 is located in the semiconductor layer ACT. The semiconductor pattern also includes a sixth conductive region DT6. The sixth conductive region DT6 is located on the side of the drain connection region D away from the channel region CH and is connected to the drain connection region D. The sixth conductive region DT6 constitutes the first pixel electrode EP1.

[0295] For example, as shown in FIG9, FIG19 or FIG37, the display substrate further includes: a third conductive layer M3 disposed on the side of the second conductive layer M2 away from the substrate 10, including a second common electrode EC2; and a transparent conductive layer TD disposed on the side of the third conductive layer M3 away from the substrate 10, including a second pixel electrode EP2, wherein the orthographic projections of the second pixel electrode EP2 and the second common electrode EC2 on the substrate 10 overlap, the second pixel electrode EP2 and the first pixel electrode EP1 are connected through a via, and the first pixel electrode EP1 is also connected to the drain connection region D of the thin film transistor.

[0296] For example, the first common electrode EC1 is located in the first conductive layer M1 (as shown in Figures 9 and 19) or the third conductive layer M3 (as shown in Figure 37).

[0297] In some embodiments, as shown in FIG9, FIG19 or FIG37, the first pixel electrode EP1 includes a plurality of sub-electrodes 11, the plurality of sub-electrodes 11 are arranged along the second direction f2 and connected in sequence, the second direction f2 intersects the first direction f1, and the width of different sub-electrodes 11 along the first direction f1 is different.

[0298] For example, the second direction f2 is parallel to the extension direction of the data line DL. The first direction f1 is, for example, perpendicular to the second direction f2.

[0299] For example, as shown in FIG9, FIG19 or FIG37, the width of the plurality of sub-electrodes 11 increases sequentially along the first direction f1 in the direction of the second direction f2 and away from the channel region CH.

[0300] For example, as shown in FIG9, FIG19 or FIG37, in the orthographic projection on the substrate 10, the edges of the plurality of sub-electrodes 11 away from the channel region CH or data line DL (the lower edge of the sub-electrodes 11 shown in the figure) are roughly aligned.

[0301] For example, as shown in Figures 9, 19 or 37, multiple sub-electrodes connected in sequence form a stepped structure.

[0302] For example, as shown in FIG9 or FIG19, a plurality of sub-electrodes 11 include a first sub-electrode 111, a second sub-electrode 112, and a third sub-electrode 113 connected in sequence. The first sub-electrode 111 is connected to the drain connection region D of the thin-film transistor and is located on the side of the drain connection region D away from the channel region CH. The first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 are arranged sequentially along the second direction f2 and away from the channel region CH. The widths of the first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 increase sequentially along the first direction f1. Furthermore, the edges of the first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 away from the channel region CH or the data line DL are approximately aligned, and the first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 form a three-level stepped structure.

[0303] For example, as shown in FIG37, the plurality of sub-electrodes 11 include a fourth sub-electrode 114 and a fifth sub-electrode 115 connected in sequence. The fourth sub-electrode 114 is connected to the drain connection region D of the thin-film transistor and is located on the side of the drain connection region D away from the channel region CH. The fourth sub-electrode 114 and the fifth sub-electrode 115 are arranged sequentially along the second direction f2 and away from the channel region CH, and the widths of the fourth sub-electrode 114 and the fifth sub-electrode 115 increase sequentially along the first direction f1. Furthermore, the edges of the fourth sub-electrode 114 and the fifth sub-electrode 115 away from the channel region CH or the data line DL are approximately aligned, and the fourth sub-electrode 114 and the fifth sub-electrode 115 form a two-stage stepped structure.

[0304] In some embodiments, as shown in FIG9 or FIG19, the first common electrode EC1 is located in the first conductive layer M1. The first common electrode EC1 is located, for example, between two adjacent data lines DL.

[0305] As shown in Figure 9, the first common electrode EC1 is located in the first conductive layer M1, and the first pixel electrode EP1 is located in the second conductive layer M2. That is, the two plates of the first storage capacitor Cst1 are located in the first conductive layer M1 and the second conductive layer M2, respectively.

[0306] As shown in Figure 19, the first common electrode EC1 is located in the first conductive layer M1, and the first pixel electrode EP1 is located in the semiconductor layer ACT. That is, the two plates of the first storage capacitor Cst1 are located in the first conductive layer M1 and the semiconductor layer ACT, respectively. Compared with Figure 9, the first insulating layer GI is reduced between the two plates of the first storage capacitor Cst1, which is beneficial to increasing the capacitance of the first storage capacitor Cst1 or reducing the area of ​​the first pixel electrode EP1 and the first common electrode EC1, thereby improving the pixel density.

[0307] For example, as shown in FIG9 or FIG19, the second conductive layer M2 further includes a third transition pattern ZJ3. The third transition pattern ZJ3 is located on the side of the first transition pattern ZJ1 and the gate G away from the scan line GL. The second common electrode EC2 and the first common electrode EC1 are respectively connected to the third transition pattern ZJ3 through vias. The third transition pattern ZJ3 and the first pixel electrode EP1 do not overlap on the orthographic projection on the substrate 10.

[0308] As shown in Figure 9 or Figure 19, the first common electrode EC1 is connected to the third transition pattern ZJ3 through via H3, and the second common electrode EC2 is connected to the third transition pattern ZJ3 through via RH1.

[0309] For example, as shown in FIG9 or FIG19, in the orthographic projection on the substrate 10, the second sub-electrode 112 and the third transition pattern ZJ3 are arranged along the first direction f1. The first common electrode EC1 overlaps with the second sub-electrode 112 and the third sub-electrode 113, respectively, but does not overlap with the first sub-electrode 111. The first common electrode EC1 is located on the side of the first transition pattern ZJ1 and the gate G away from the scan line GL.

[0310] For example, as shown in FIG9 or FIG19, in the orthographic projection on the substrate 10, the gate G and the third transition pattern ZJ3 are located on the same side of the second transition pattern ZJ2 (i.e., the first pixel electrode EP1), and the first transition pattern ZJ1 and the first sub-electrode 111 are located on opposite sides of the gate G in the first direction f1. The edge of the first transition pattern ZJ1 near the scan line GL is approximately aligned with the edge of the first sub-electrode 111 near the scan line GL, and the width of the first transition pattern ZJ1 in the second direction f2 is smaller than the width of the first sub-electrode 111 in the second direction f2.

[0311] For example, as shown in FIG9, in the orthographic projection on the substrate 10, the edge of the first transition pattern ZJ1 away from the scan line GL is aligned with the edge of the gate G away from the scan line GL. The edge of the third transition pattern ZJ3 near the second sub-electrode 112 is approximately aligned with the edge of the gate G near the first transition pattern ZJ1. The edge of the third transition pattern ZJ3 near the data line DL is aligned with the edge of the third sub-electrode 113 near the data line DL, and is located on the side of the first common electrode EC1 near the data line DL. The edge of the third transition pattern ZJ3 near the scan line GL is approximately aligned with the edge of the second sub-electrode 112 near the scan line GL, and is located on the side of the first common electrode EC1 near the scan line GL.

[0312] For example, as shown in FIG9 or FIG19, the width of the third transition pattern ZJ3 in the second direction f2 is smaller than the width of the second sub-electrode 112 in the second direction f2. The width of the second sub-electrode 112 in the second direction f2 is greater than the width of the first sub-electrode 111 and the third sub-electrode 113 in the second direction f2.

[0313] For example, as shown in FIG9 or FIG19, in the first direction f1, the width of the first common electrode EC1 is greater than the width of the second sub-electrode 112 and less than the width of the third sub-electrode 113. In the orthographic projection on the substrate 10, the third sub-electrode 113 covers the first common electrode EC1 in the first direction f1.

[0314] For example, as shown in FIG9 or FIG19, the third conductive layer M3 further includes: a fourth transition pattern ZJ4, the fourth transition pattern ZJ4 being disposed separately from the second common electrode EC2, the second sub-electrode 112 and the second pixel electrode EP2 being connected to the fourth transition pattern ZJ4 through vias, and the fourth transition pattern ZJ4 being located in the region of the second sub-electrode 112 in the orthogonal projection on the substrate 10.

[0315] As shown in Figure 9 or Figure 19, the second sub-electrode 112 is connected to the fourth transition pattern ZJ4 through via RH2, and the second pixel electrode EP2 is connected to the fourth transition pattern ZJ4 through via H4.

[0316] For example, as shown in FIG9, the edge of the fourth transition pattern ZJ4 away from the scan line GL is aligned with the edge of the third transition pattern ZJ3 away from the scan line GL. In the second direction f2, the width of the fourth transition pattern ZJ4 is smaller than the width of the third transition pattern ZJ3. The fourth transition pattern ZJ4 is located within the notch of the second common electrode EC2 away from the third transition pattern ZJ3. The second common electrode EC2 is disposed on three sides of the fourth transition pattern ZJ4, namely the left, right, and top sides as shown in FIG. The shape of the fourth transition pattern ZJ4 is, for example, a square. The width of the second common electrode EC2 in the first direction f1 is greater than the width of the first pixel electrode EP1 and the first common electrode EC1 in the first direction f1, and the second common electrode EC2 covers the first pixel electrode EP1 and the first common electrode EC1 in the first direction f1. In the orthographic projection on the substrate 10, the second common electrode EC2 is approximately aligned with the edges of the data line DL that are close to each other.

[0317] For example, as shown in FIG9, the gap between the fourth transition pattern ZJ4 and the second common electrode EC2 is approximately equal to the gap between the third transition pattern ZJ3 and the first pixel electrode EP1.

[0318] In some embodiments, as shown in FIG37, the first common electrode EC1 is located in the third conductive layer M3, and the first common electrode EC1 and the second common electrode EC2 share the same electrode EC. This embodiment can significantly reduce the number of vias, thereby increasing the facing area between electrodes, and thus increasing the storage capacitance, which is beneficial to improving pixel density and allows for more flexible adjustment of the storage capacitance size according to actual needs.

[0319] For example, as shown in FIG37, the second conductive layer M2 further includes a second transition pattern ZJ2. The second transition pattern ZJ2 is located on the side of the gate G away from the first transition pattern ZJ1. The second transition pattern ZJ2 is used to connect the first pixel electrode EP1 and the second pixel electrode EP2. In the orthographic projection on the substrate 10, the same electrode EC covers the first transition pattern ZJ1 and the gate G, and does not overlap with the second transition pattern ZJ2. The second transition pattern ZJ2 is located within the notch of the same electrode EC, and the same electrode EC is located on both sides of the second transition pattern ZJ2, as shown on the upper and right sides in FIG37.

[0320] As shown in Figure 37, the second transition pattern ZJ2 is connected to the first pixel electrode EP1 through the second via H2, and the second transition pattern ZJ2 is connected to the second pixel electrode EP2 through the via H5. The centers of the second via H2 and the via H5 do not coincide, and their orthogonal projections on the substrate 10 overlap.

[0321] For example, as shown in FIG37, the first pixel electrode EP1 is located in the semiconductor layer ACT.

[0322] For example, as shown in FIG37, in the orthographic projection on the substrate 10, the second transition pattern ZJ2 is located within the range of the fourth sub-electrode 114, and the same electrode EC overlaps with the edge of the fourth sub-electrode 114 near the channel region CH and the fifth sub-electrode 115, respectively.

[0323] For example, as shown in FIG37, the edge of the gate G away from the scan line GL is aligned with the edge of the second transition pattern ZJ2 away from the scan line GL. The edges of the same electrode EC and the data line DL are approximately aligned with each other.

[0324] For example, as shown in FIG35, the same electrode EC includes a first sub-common electrode EC11 and a second sub-common electrode EC12 arranged and connected sequentially along the second direction f2. In the first direction f1, the width of the first sub-common electrode EC11 is smaller than the width of the second sub-common electrode EC12. The boundary line between the first sub-common electrode EC11 and the second sub-common electrode EC12 is approximately aligned with the edge of the gate G away from the scan line GL. The first sub-common electrode EC11 is located on the side of the second transition pattern ZJ2 near the gate G.

[0325] For example, as shown in FIG37, the display substrate further includes: a second insulating layer PVX1 disposed between the second conductive layer M2 and the third conductive layer M3; and an organic insulating layer RS ​​disposed between the second insulating layer PVX1 and the third conductive layer M3, wherein the organic insulating layer RS ​​and the orthographic projection of the first pixel electrode EP1 on the substrate 10 do not overlap at least partially.

[0326] By removing the organic insulating layer RS ​​above the first pixel electrode EP1, the distance between the first pixel electrode EP1 and the first common electrode EC1 is reduced, thereby forming a first storage capacitor Cst1 with a larger capacitance or reducing the area of ​​the first pixel electrode EP1 and the first common electrode EC1, which is beneficial to improving pixel density.

[0327] In some embodiments, as shown in FIG9, FIG19 or FIG37, in the orthographic projection on the substrate 10, the first pixel electrode EP1 and the second pixel electrode EP2 do not overlap with the scan line GL, the first pixel electrode EP1 is located in the region of the second pixel electrode EP2, and the gap width w1 between the second pixel electrodes EP2 located in two adjacent sub-pixels PX is greater than or equal to 5 micrometers and less than or equal to 15 micrometers.

[0328] For example, as shown in FIG9, FIG19 or FIG37, in the orthographic projection on the substrate 10, the first pixel electrode EP1 does not overlap with the data line DL and the scan line GL, and in the first direction f1, the second pixel electrode EP2 at least partially covers the data line DL.

[0329] In some embodiments, as shown in FIG9, FIG19 or FIG37, in the orthographic projection on the substrate 10, the first common electrode EC1 and the second common electrode EC2 do not overlap with the data line DL, the second common electrode EC2 has an overlapping area with the scan line GL, and the width of the overlapping area along the first direction f1 is smaller than the width of the non-overlapping area along the first direction f1.

[0330] By reducing the width of the second common electrode EC2 in the overlapping region, the parasitic capacitance between the second common electrode EC2 and the scan line GL can be reduced, thereby improving signal stability.

[0331] For example, as shown in FIG9, FIG19 or FIG37, in the orthographic projection on the substrate 10, the first common electrode EC1 does not overlap with the scan line GL and the data line DL.

[0332] For example, as shown in FIG9, the width w2 of the overlapping region of the second common electrode EC2 and the scan line GL along the first direction f1 is greater than or equal to one times the linewidth of the scan line GL, and less than or equal to two times the linewidth of the scan line GL. The linewidth of the scan line GL is the width of the scan line GL along the second direction f2.

[0333] In the third embodiment of the display substrate described above, the gap width w1 between the second pixel electrodes EP2 of two adjacent sub-pixels PX is greater than or equal to 5 micrometers and less than or equal to 15 micrometers. As shown in Figures 41-43, the width of the barrier pattern 22 along the first direction f1 (scan line GL direction) can be greater than or equal to the gap width between the second pixel electrodes EP2 of two adjacent sub-pixels PX.

[0334] As shown in Figures 41-43, the orthographic projection of the piezoelectric pattern 21 on the substrate 10 overlaps with the orthographic projections of the first pixel electrode EP1 and the second pixel electrode EP2 on the substrate 10.

[0335] In this way, the voltages on the first pixel electrode EP1 and the second pixel electrode EP2 can be superimposed on the piezoelectric pattern 21. In some examples, as shown in Figures 41-43, the piezoelectric pattern 21 may not coincide with the outer contour of the orthographic projection of the first pixel electrode EP1 on the substrate 10, nor with the outer contour of the orthographic projection of the second pixel electrode EP2 on the substrate 10.

[0336] Combined with the third type of driving circuit structure layer, as shown in Figures 9, 38 and 40, the first pixel electrode EP1 does not overlap with the data line DL and the scan line GL. In the first direction f1, the second pixel electrode EP2 at least partially covers the data line DL. The orthogonal projection of the second pixel electrode EP2 on the substrate 10 can cover the orthogonal projection of the first pixel electrode EP1 on the substrate 10.

[0337] The piezoelectric layer 20 also includes a barrier pattern 22, which isolates the piezoelectric patterns 21 located in different sub-pixels PX.

[0338] The orthographic projection of the edge of the barrier pattern 22 along the scan line GL direction onto the substrate 10 coincides with the orthographic projection of the edge of the second pixel electrode EP2 along the scan line GL direction onto the substrate 10.

[0339] For example, as shown in FIG38, the barrier pattern 22 includes a first barrier 221 and a second barrier 222. The first barrier 221 is parallel to the scan line GL, and the second barrier 222 is parallel to the data line DL. The second pixel electrode EP2 and the orthographic projection of the scan line GL on the substrate 10 do not overlap. In the orthographic projection on the substrate 10, the edge of the first barrier 221 parallel to the scan line GL may coincide with the edge of the second pixel electrode EP2 parallel to the scan line GL. Therefore, the width of the barrier pattern 22 along the second direction f2 (data line DL direction) can be equal to the gap width of the second direction f2 between the second pixel electrodes EP2 of two adjacent sub-pixels PX.

[0340] In this case, the orthographic projection of the portion of the parallel data line DL in the barrier pattern 22 onto the substrate 10 covers the orthographic projection of the data line DL onto the substrate 10 and does not overlap with the first pixel electrode EP1.

[0341] For example, as shown in FIG38, the second barrier 222 can cover the data line DL. In the orthographic projection on the substrate 10, the edge of the second barrier 222 parallel to the data line DL is located between the first pixel electrode EP1 and the data line DL. Therefore, the width of the barrier pattern 22 along the first direction f1 can be greater than the gap width along the first direction f1 between the second pixel electrodes EP2 of two adjacent sub-pixels PX. This increases the coverage of the barrier pattern 22 on the scan line GL and the data line DL while ensuring the aperture ratio of the sub-pixels PX.

[0342] In some other examples, the width of the barrier pattern 22 along the second direction f2 (data line DL direction) can be smaller than the gap width of the second direction f2 between the second pixel electrodes EP2 of two adjacent sub-pixels PX, so that the edge of the barrier pattern 22 along the second direction f2 can not overlap with the second pixel electrode EP2.

[0343] As shown in Figures 41 and 9, the first pixel electrode EP1 includes a first sub-electrode 111, a second sub-electrode 112, and a third sub-electrode 113 connected in sequence. The first sub-electrode 111 is connected to the drain connection region D of the thin film transistor and is located on the side of the drain connection region D away from the channel region CH. Along the second direction f2 and away from the channel region CH, the widths of the first sub-electrode 111, the second sub-electrode 112, and the third sub-electrode 113 increase sequentially along the first direction f1.

[0344] The piezoelectric pattern 21 may include a first pattern region 211 and a second pattern region 212. The width of the first pattern region 211 along the first direction f1 is smaller than the width of the second pattern region 212 along the first direction f1. The orthographic projection of the edge of the second pattern region 212 near the scan line GL on the substrate 10 coincides with the orthographic projection of the edge of the second sub-electrode 112 near the scan line GL on the substrate 10. The width of the second pattern region 212 along the first direction f1 is greater than the width of the second sub-electrode 112 along the first direction f1, and is greater than or equal to the width of the third sub-electrode 113 along the first direction f1.

[0345] In this embodiment, as shown in Figures 41 and 42, the edges of the first pattern area 211 and the second pattern area 212 that are parallel to the data line DL and far from the source connection area S can be aligned.

[0346] The orthographic projection of the first pattern region 211 on the substrate 10 partially overlaps with the orthographic projection of the first sub-electrode 111 on the substrate 10. For example, the orthographic projection of the first pattern region 211 on the substrate 10 may cover the orthographic projection of the first sub-electrode 111 on the substrate 10. The width of the first pattern region 211 along the first direction f1 may be greater than the width of the first sub-electrode 111 along the first direction f1.

[0347] As shown in Figure 41, the orthographic projection of the second pattern region 212 on the substrate 10 overlaps with the orthographic projections of the second sub-electrode 112 and the third sub-electrode 113 on the substrate 10. The edge of the second pattern region 212 near the scan line GL coincides with the orthographic projection of the edge of the second sub-electrode 112 near the scan line GL on the substrate 10.

[0348] As shown in Figure 41, the width of the second pattern region 212 along the first direction f1 can be greater than the width of the second sub-electrode 112 along the first direction f1. Specifically, the orthogonal projection of the second pattern region 212 on the substrate 10 can cover the orthogonal projection of the second sub-electrode 112 on the substrate 10.

[0349] As shown in Figure 41, the width of the second pattern region 212 along the first direction f1 can be greater than or equal to the width of the third sub-electrode along the first direction f1. Specifically, the orthogonal projection of the second pattern region 212 on the substrate 10 can cover the orthogonal projection of the third sub-electrode on the substrate 10.

[0350] As shown in Figures 41 and 42, in the orthographic projection on the substrate 10, the edge of the second pattern region 212 that is parallel to the data line DL and located on one side of the source connection region S may overlap with the edge of the third sub-electrode 113 that is parallel to the data line DL and located on one side of the source connection region S.

[0351] In some embodiments, as shown in FIG41, when the semiconductor layer ACT includes the drain connection region D, the third conductor region DT3, and the fourth conductor region DT4 of the thin film transistor, the first insulating layer GI also includes a second via H2. The second via H2 exposes the drain connection region D and the third conductor region DT3. The second transition pattern ZJ2 overlaps with the drain connection region D through the second via H2. The orthographic projections of the second transition pattern ZJ2 and the third conductor region DT3 on the substrate 10 do not overlap.

[0352] The orthographic projection of the piezoelectric pattern 21 onto the substrate 10 can also cover the orthographic projection of the second via H2 onto the substrate 10. For example, the orthographic projection of the first pattern area onto the substrate 10 can cover the orthographic projection of the second via H2 onto the substrate 10. Thus, the piezoelectric pattern 21 can compensate for the unevenness of the film surface that may be caused by the second via H2, thereby allowing the ink particles between the two electrodes to be more evenly distributed.

[0353] In some other embodiments, as shown in FIG43, the first pixel electrode EP1 is located in the semiconductor layer ACT, and the first pixel electrode EP1 includes a fourth sub-electrode 114 and a fifth sub-electrode 115 connected in sequence; the fourth sub-electrode 114 is connected to the drain connection region D of the thin film transistor and is located on the side of the drain connection region D away from the channel region CH; the width of the fourth sub-electrode 114 along the first direction f1 is smaller than the width of the fifth sub-electrode 115 along the first direction f1.

[0354] The piezoelectric pattern 21 includes a first pattern region 211 and a second pattern region 212. The first pattern region 211 overlaps with the orthographic projection of the fourth sub-electrode 114 on the substrate 10, and the second pattern region 212 overlaps with the orthographic projection of the fifth sub-electrode 115 on the substrate 10.

[0355] Wherein, the width of the first pattern area 211 along the first direction f1 is less than the width of the second pattern area 212 along the first direction f2, the orthographic projection of the edge of the second pattern area 212 near the scan line GL on the substrate 10 coincides with the orthographic projection of the edge of the fifth sub-electrode 115 near the scan line GL on the substrate 10, and the width of the second pattern area 212 along the first direction f1 is greater than or equal to the width of the fifth sub-electrode 115 along the first direction f1.

[0356] For example, on the orthographic projection of the substrate 10, a portion of the first pattern region 211 along the first direction f1 covers a portion of the fourth sub-electrode 114 along the first direction f1.

[0357] For example, as shown in FIG43, the portion of the first pattern region 211 along the second direction f2 may overlap with the portion of the fourth sub-electrode 114 along the second direction f2.

[0358] In some other examples, if a portion of the first pattern region 211 along the second direction f2 covers a portion of the fourth sub-electrode along the second direction f2, then the width of the first pattern region 211 along the second direction f2 is greater than or equal to the width of the fourth sub-electrode 114 along the second direction f2. For example, on the orthographic projection of the substrate 10, the edge of the first pattern region 211 near the scan line GL may coincide with the edge of the second pixel electrode EP2 near the scan line GL.

[0359] For example, the orthographic projection of the second pattern region 212 onto the substrate 10 can cover the orthographic projection of the fifth sub-electrode 115 onto the substrate 10, such that the width of the second pattern region 212 along the first direction f1 is greater than the width of the fifth sub-electrode 115 along the first direction f1. For example, as shown in FIG43, on the orthographic projection of the substrate 10, the edge of the second pattern region 212 parallel to the data line DL can be located between the first pixel electrode EP1 and the data line DL.

[0360] In some other examples, the orthographic projection of the second pattern region 212 onto the substrate 10 may coincide with the orthographic projection of the fifth sub-electrode 115 onto the substrate 10. Thus, the width of the second pattern region 212 along the first direction f1 is equal to the width of the fifth sub-electrode 115 along the first direction f1. For example, on the orthographic projection onto the substrate 10, the edge of the second pattern region 212 parallel to the data line DL may coincide with the edge of the fifth sub-electrode 115 parallel to the data line DL.

[0361] Referring to Figures 41 and 42, in one implementation of this embodiment, the sub-pixel PX further includes a first common electrode EC1 and a second common electrode EC2; wherein, the first common electrode EC1 and the first pixel electrode EP1 are disposed in different layers and their orthogonal projections on the substrate 10 overlap, the first common electrode EC1 and the second common electrode EC2 are disposed in different layers, the first common electrode EC1 is located in the first conductive layer M1, the second common electrode EC2 is located in the third conductive layer M3, and the first common electrode EC1 is located between two adjacent data lines DL;

[0362] The second conductive layer M2 also includes a third transition pattern ZJ3. The third transition pattern ZJ3 is located on the side of the first transition pattern ZJ1 and the gate G away from the scan line GL. The second common electrode EC2 and the first common electrode EC1 are respectively connected to the third transition pattern ZJ3 through vias. The third transition pattern ZJ3 and the first pixel electrode EP1 do not overlap in their orthogonal projections on the substrate 10.

[0363] The orthographic projection of the second pattern area 212 on the substrate 10 covers the orthographic projection of the third transition pattern ZJ3 on the substrate 10.

[0364] In this embodiment, the second pattern area 212 covers the third transition pattern ZJ3. In this way, the piezoelectric pattern 21 can compensate for the unevenness of the film surface that may be caused by the third transition pattern ZJ3 at the third via H3, thereby making the ink particles between the two plates more evenly distributed and allowing the piezoelectric pattern 21 to cover as much of the area with conductive material as possible, thereby improving the deformation uniformity of the piezoelectric pattern 21 in the sub-pixel PX.

[0365] In some embodiments, please refer to FIG44, which shows an overlapping schematic diagram of the first common electrode, the second common electrode EC2, and the piezoelectric pattern 21 of two display substrates. FIG44 corresponds to FIG9 and FIG19. In this embodiment, the sub-pixel PX includes the first common electrode EC1 and the second common electrode EC2;

[0366] The first common electrode EC1 and the first pixel electrode EP1 are disposed in different layers and their orthogonal projections on the substrate 10 overlap. The first common electrode EC1 and the second common electrode EC2 are disposed in different layers, and the second common electrode EC2 is located in the third conductive layer M3.

[0367] The orthographic projection of the piezoelectric pattern 21 on the substrate 10 covers the orthographic projection of the first common electrode EC1 on the substrate 10 and at least partially overlaps with the orthographic projection of the second common electrode EC2 on the substrate 10.

[0368] As shown in Figure 44, the orthogonal projection of the piezoelectric pattern 21 on the substrate 10 covers the orthogonal projection of the first common electrode EC1 on the substrate 10. For example, the width of the piezoelectric pattern 21 along the first direction f1 is greater than the width of the first common electrode EC1 along the first direction f1, and the width of the piezoelectric pattern 21 along the second direction f2 is also greater than the width of the first common electrode EC1 along the second direction f2.

[0369] For example, the orthographic projection of the piezoelectric pattern 21 on the substrate 10 overlaps with the orthographic projection of the second common electrode EC2 on the substrate 10. Specifically, the width of the piezoelectric pattern 21 along the first direction f1 is greater than or equal to the width of the second common electrode EC2 along the first direction f1.

[0370] For example, in some embodiments, the width of the piezoelectric pattern 21 along the first direction f1 is equal to the width of the second common electrode EC2 along the first direction f1. However, in the orthographic projection of the substrate 10, the piezoelectric pattern 21 is parallel to the two opposite edges of the data line DL and does not coincide with the two opposite edges of the second common electrode EC2 parallel to the data line DL.

[0371] In this configuration, the orthographic projections of the second common electrode EC2 and the fourth transition pattern ZJ4 on the substrate 10 do not overlap, while the orthographic projection of the piezoelectric pattern 21 on the substrate 10 can cover the orthographic projection of the fourth transition pattern ZJ4 on the substrate 10. Thus, the piezoelectric pattern 21 and the second common electrode EC2 partially overlap.

[0372] In one embodiment of this example, as shown in FIG44, on the orthographic projection of the substrate 10, the edge of the piezoelectric pattern 21 parallel to the scan line GL can coincide with the edge of the second common electrode EC2 parallel to the scan line GL.

[0373] In another embodiment of this invention, as shown in FIG45, on the orthographic projection of the substrate 10, the edge of the piezoelectric pattern 21 parallel to the scan line GL can be located between the second common electrode EC2 and the scan line GL. For example, on the orthographic projection of the substrate 10, the edge of the piezoelectric pattern 21 near and parallel to the scan line GL can coincide with the edge of the second pixel electrode EP2 near the scan line GL, and the second pixel electrode EP2 covers the second common electrode EC2.

[0374] In one example of this embodiment, the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 are all metal layers.

[0375] In one example of this embodiment, the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 can each be independently made of any one or more of the following metal materials: copper, molybdenum, aluminum, titanium, silver, nickel, niobium, etc., and the structure of each conductive layer can be a single layer or a stack.

[0376] In some embodiments, the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3 may include at least one of copper or copper alloy, molybdenum-niobium alloy, molybdenum-nickel alloy, and molybdenum-nickel-titanium alloy, such as copper / molybdenum-niobium, molybdenum-niobium / copper, copper / molybdenum-nickel-titanium, molybdenum-nickel-titanium / copper, molybdenum-nickel / copper, copper / molybdenum-nickel, molybdenum-niobium / copper / molybdenum-nickel, molybdenum-niobium / copper / molybdenum-niobium, molybdenum-nickel ...nickel-titanium, etc.

[0377] For example, the transparent conductive layer TD can be made of transparent conductive materials, such as metal oxides like ITO, IZO, IGZO, IGO, and ZTO. Using metal oxides can improve the oxidation resistance of the transparent conductive layer TD.

[0378] To meet the driving requirements of color electronic paper, for example, in each sub-pixel PX, the storage capacitance formed by the common electrode EC1 / EC2 and the pixel electrode EP1 / EP2 is greater than or equal to 1.0pF and less than or equal to 2.0pF, such as 1.2pF.

[0379] For example, the storage capacitor includes a first storage capacitor Cst1 formed by a first common electrode EC1 and a first pixel electrode EP1, and a second storage capacitor Cst2 formed by a second common electrode EC2 and a second pixel electrode EP2. Since the first common electrode EC1 is connected to the second common electrode EC2 and the second pixel electrode EP2 is connected to the second pixel electrode EP2, the first storage capacitor Cst1 and the second storage capacitor Cst2 are connected in parallel. Therefore, in each sub-pixel PX, the storage capacitor formed by the common electrode EC1 / EC2 and the pixel electrode EP1 / EP2 is the sum of the capacitance values ​​of the first storage capacitor Cst1 and the second storage capacitor Cst2.

[0380] For example, as shown in Figure 9d, the data line DL extends along the row direction (i.e., the second direction f2), and the scan line GL extends along the column direction (i.e., the first direction f1). Sub-pixels PX located in the same column are connected to the same scan line GL. Adjacent sub-pixels PX in two columns are connected to different scan lines GL, and two columns of sub-pixels PX are arranged between two adjacent scan lines GL. Sub-pixels PX located in the same row are connected to two data lines DL, which are arranged on both sides of the sub-pixels PX in that row. Two adjacent sub-pixels PX in the same row are connected to different data lines DL.

[0381] The following describes several driving circuit structures provided in this embodiment with reference to Figures 9 to 37.

[0382] In a first exemplary embodiment, as shown in FIG9, the display substrate includes: a substrate 10, and a display area located on one side of the substrate 10. The display area includes a plurality of sub-pixels PX, each sub-pixel PX including a thin film transistor, a pixel electrode, and a piezoelectric pattern 21. The substrate 10 side of the display substrate includes a driving circuit structure layer, which includes a thin film transistor, a first pixel electrode EP1, and a second pixel electrode EP2. The piezoelectric pattern 21 is located on the side of the driving circuit structure layer opposite to the substrate 10 and overlaps with the orthographic projection of the first pixel electrode EP1 and the second pixel electrode EP2 on the substrate 10.

[0383] As shown in Figure 9, the driving circuit structure layer includes a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX1, an organic insulating layer RS, a third conductive layer M3, a third insulating layer PVX2, and a transparent conductive layer TD, which are stacked sequentially on one side of the substrate 10. The first conductive layer M1 is disposed close to the substrate 10.

[0384] As shown in Figure 9, the first conductive layer M1 includes a data line DL and a first common electrode EC1. The semiconductor layer ACT includes a semiconductor pattern, which includes a source connection region S, a first conductor region DT1, a second conductor region DT2, a channel region CH, a fourth conductor region DT4, a third conductor region DT3, and a drain connection region D arranged and connected sequentially along the first direction f1. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, a second transition pattern ZJ2, and a third transition pattern ZJ3. The third conductive layer M3 includes a second common electrode EC2 and a fourth transition pattern ZJ4. The transparent conductive layer TD includes a second pixel electrode EP2.

[0385] As shown in Figure 9, the first transition pattern ZJ1 connects the data line DL and the source connection area S through the first via H1, which is partially overlapped on the first insulating layer GI. The second transition pattern ZJ2 connects the drain connection area D through the second via H2, which is partially overlapped on the first insulating layer GI. The second transition pattern ZJ2 serves as the first pixel electrode EP1.

[0386] As shown in Figure 9, the first common electrode EC1 and the second common electrode EC2 are connected through the third transition pattern ZJ3. Specifically, the first common electrode EC1 and the third transition pattern ZJ3 are connected through vias provided on the first insulating layer GI and the buffer layer BF, and the second common electrode EC2 and the third transition pattern ZJ3 are connected through vias provided on the second insulating layer PVX1 and the organic insulating layer RS.

[0387] As shown in Figure 9, the first pixel electrode EP1 and the second pixel electrode EP2 are connected through the fourth transition pattern ZJ4. Specifically, the first pixel electrode EP1 and the fourth transition pattern ZJ4 are connected through vias provided on the second insulating layer PVX1 and the organic insulating layer RS, and the second pixel electrode EP2 and the fourth transition pattern ZJ4 are connected through vias provided on the third insulating layer PVX2.

[0388] As shown in Figure 9, the first common electrode EC1 and the first pixel electrode EP1 constitute the two plates of the first storage capacitor Cst1. The dielectric layer between the two plates includes a first insulating layer GI and a buffer layer BF. The second common electrode EC2 and the second pixel electrode EP2 constitute the two plates of the second storage capacitor Cst2. The dielectric layer between the two plates includes a third insulating layer PVX2. Testing showed that when the technical solution provided in this embodiment is applied to a 300 PPI display substrate, the storage capacitance of each sub-pixel PX can reach 1.2 pF.

[0389] Referring to Figures 2 to 18, the display substrate provided in this embodiment can be prepared by the following steps:

[0390] Step 11: Form a patterned first conductive layer M1 on the substrate 10, as shown in FIG2. The first conductive layer M1 includes a data line DL and a first common electrode EC1, and may also include a shielding pattern (not shown in the figure). The orthogonal projection of the shielding pattern on the substrate 10 covers the channel region CH.

[0391] Step 12: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 facing away from the substrate 10, as shown in Figure 11. The semiconductor layer ACT is a transparent material and includes semiconductor patterns located in different sub-pixels PX. The semiconductor patterns include a source connection region S, a first conductive region DT1, a second conductive region DT2, a channel region CH, a fourth conductive region DT4, a third conductive region DT3, and a drain connection region D arranged and connected sequentially along the first direction f1.

[0392] Step 13: A patterned first insulating layer GI is formed on the side of the semiconductor layer ACT facing away from the substrate 10, as shown in Figure 12. A first via H1, a second via H2 and a third via H3 are provided on the first insulating layer GI. In the orthographic projection on the substrate 10, the first via H1 and the second via H2 are located on both sides of the channel region CH. The first via H1 exposes a part of the data line DL, the source connection region S and the first conductor region DT1. The second via H2 exposes the drain connection region D and the third conductor region DT3. The third via H3 is located in the region of the first common electrode EC1.

[0393] Step 14: A patterned second conductive layer M2 is formed on the side of the first insulating layer GI away from the substrate 10, as shown in Figure 13. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, a second transition pattern ZJ2 (i.e., the first pixel electrode EP1), and a third transition pattern ZJ3. The gate G is connected to one side of the scan line GL and overlaps with the channel region CH. The first transition pattern ZJ1 partially covers the first via H1 and is connected to the data line DL and the source connection region S, respectively. The second transition pattern ZJ2 partially covers the second via H2 and is connected to the drain connection region D. The third transition pattern ZJ3 fully covers the third via H3 and is connected to the first common electrode EC1.

[0394] After forming the second conductive layer M2, the first insulating layer GI can be etched a second time using the second conductive layer M2 as a mask. Then, using the second conductive layer M2 as a mask again, a self-aligned process is used to conduct the semiconductor material in the exposed areas of the semiconductor layer ACT (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3, and the fourth conductor region DT4). This conductor formation process can, for example, use dry etching equipment or ion implantation equipment to implant plasma (such as plasma containing at least one element selected from helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material, or use ion doping technology to dope any one or more of the above elements into the semiconductor material to achieve conductor formation. Among these methods, using dry etching equipment to conduct the semiconductor material can be performed simultaneously with the second etching process of the first insulating layer GI, thereby simplifying the process.

[0395] Step 15: A second insulating material is sequentially deposited on the side of the second conductive layer M2 away from the substrate 10 to form a second insulating material layer. Then, an organic insulating material is coated to form an organic insulating material layer. Next, the organic insulating material layer is patterned to form an organic insulating layer RS, as shown in Figure 14. The organic insulating layer RS ​​includes two organic vias, namely a first organic via RH1 and a second organic via RH2. The first organic via RH1 is located within the region of the third transition pattern ZJ3. The first organic via RH1 and the third via H3 are arranged along the second direction f2. The second organic via RH2 is located within the region of the first pixel electrode EP1, such as the region of the second sub-electrode 112.

[0396] For example, as shown in FIG14, the third via H3 and the first organic via RH1 are arranged along the second direction f2, and the first organic via RH1 and the second organic via RH2 are arranged along the first direction f1. The first organic via RH1 and the second organic via RH2 have the same shape and the same size.

[0397] Step 16: Pattern the second insulating material layer to form the second insulating layer PVX1, as shown in Figure 15. The second insulating layer PVX1 includes two vias, namely via PH1 and via PH2. Via PH1 is located in the first organic via RH1, and via PH2 is located in the second organic via RH2.

[0398] For example, as shown in FIG15, via PH1 is centrally located within the first organic via RH1, and via PH2 is centrally located within the second organic via RH2. Vias PH1 and via PH2 are arranged along the first direction f1.

[0399] Step 17: A patterned third conductive layer M3 is formed on the side of the organic insulating layer RS ​​facing away from the substrate 10, as shown in Figure 16. The third conductive layer M3 includes a second common electrode EC2 and a fourth transition pattern ZJ4 separated from each other. The second common electrode EC2 covers the via RH1 on the third transition pattern ZJ3 and communicates with the third transition pattern ZJ3, and further communicates with the first common electrode EC1. The fourth transition pattern ZJ4 covers the via RH2 on the first pixel electrode EP1 and communicates with the first pixel electrode EP1.

[0400] Step 18: A patterned third insulating layer PVX2 is formed on the side of the third conductive layer M3 away from the substrate 10, as shown in FIG17. The third insulating layer PVX2 includes a via H4 located in the region of the second organic via RH2 for exposing the fourth transition pattern ZJ4.

[0401] Step 19: A patterned transparent conductive layer TD is formed on the side of the third insulating layer PVX2 away from the substrate 10, as shown in Figure 18. The transparent conductive layer TD includes a second pixel electrode EP2 located in different sub-pixels PX. The second pixel electrode EP2 covers the via H4 located on the fourth transition pattern ZJ4 and is connected to the fourth transition pattern ZJ4, and then connected to the first pixel electrode EP1.

[0402] Step 20: A patterned piezoelectric layer 20 is formed on the side of the transparent conductive layer TD2 away from the substrate 10, as shown in FIG6. The piezoelectric layer 20 includes a barrier pattern 22 and a piezoelectric pattern 21.

[0403] As shown in Figure 38, the barrier pattern 22 includes a first barrier 221 parallel to the scan line GL and a second barrier 222 parallel to the data line DL. The orthographic projection of the first barrier 221 onto the substrate 10 covers the scan line GL, and the orthographic projection of the second barrier 222 onto the substrate 10 covers the data line DL. Furthermore, on the orthographic projection onto the substrate 10, the edge of the first barrier 221 near the scan line GL coincides with the edge of the second pixel electrode EP2 near the scan line GL, and the edge of the second barrier 222 near the data line DL is located between the data line DL and the first pixel electrode EP1.

[0404] As shown in Figure 41, the piezoelectric pattern 21 includes a first pattern region 211 and a second pattern region 212. The width of the first pattern region 211 along the first direction f1 is smaller than the width of the second pattern region 212 along the first direction f1. The width of the first pattern region 211 along the first direction f1 is greater than the width of the first sub-electrode 111 along the first direction f1. The width of the second pattern region 212 along the first direction f1 is greater than the width of the second sub-electrode 112 along the first direction f1, and is greater than or equal to the width of the third sub-electrode 113 along the first direction f1.

[0405] As shown in Figure 41, on the orthographic projection of the substrate 10, the edge of the second pattern region 212 near the scan line GL can coincide with the edge of the second sub-electrode 112 near the scan line GL. Furthermore, the second pattern region 212 covers the third transition pattern ZJ3, and the first pattern region 211 covers the second via.

[0406] As shown in Figure 45, on the orthographic projection of the substrate 10, the edge of the piezoelectric pattern 21 near the scan line GL can partially coincide with the edge of the second pixel electrode EP2 near the scan line GL, and the edge of the piezoelectric pattern 21 near the data line DL can be located between the first pixel electrode EP1 and the data line DL. The orthographic projection of the piezoelectric pattern 21 on the substrate 10 can cover the first common electrode EC1 and partially overlap with the second common electrode EC2.

[0407] In the second exemplary embodiment, as shown in FIG19, the driving circuit structure layer includes a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX1, an organic insulating layer RS, a third conductive layer M3, a third insulating layer PVX2, and a transparent conductive layer TD, which are sequentially stacked on one side of the substrate 10. The first conductive layer M1 is disposed close to the substrate 10.

[0408] As shown in Figure 19, the first conductive layer M1 includes a data line DL and a first common electrode EC1. The semiconductor layer ACT includes a semiconductor pattern, which includes a source connection region S, a first conductor region DT1, a second conductor region DT2, a channel region CH, a drain connection region D, and a sixth conductor region DT6 (i.e., the first pixel electrode EP1) arranged and connected sequentially along the first direction f1. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, and a third transition pattern ZJ3. The third conductive layer M3 includes a second common electrode EC2 and a fourth transition pattern ZJ4. The transparent conductive layer TD includes a second pixel electrode EP2.

[0409] As shown in Figure 19, the first adapter pattern ZJ1 connects the data line DL and the source connection area S through the first via H1, which is partially overlapped on the first insulating layer GI.

[0410] As shown in Figure 19, the first common electrode EC1 and the second common electrode EC2 are connected through the third transition pattern ZJ3. Specifically, the first common electrode EC1 and the third transition pattern ZJ3 are connected through vias provided on the first insulating layer GI and the buffer layer BF, and the second common electrode EC2 and the third transition pattern ZJ3 are connected through vias provided on the second insulating layer PVX1 and the organic insulating layer RS.

[0411] As shown in Figure 19, the first pixel electrode EP1 and the second pixel electrode EP2 are connected through the fourth transition pattern ZJ4. Specifically, the first pixel electrode EP1 and the fourth transition pattern ZJ4 are connected through vias provided on the second insulating layer PVX1 and the organic insulating layer RS, and the second pixel electrode EP2 and the fourth transition pattern ZJ4 are connected through vias provided on the third insulating layer PVX2.

[0412] As shown in Figure 19, the first common electrode EC1 and the first pixel electrode EP1 constitute the two plates of the first storage capacitor Cst1, and the dielectric layer between the two plates includes a buffer layer BF. The second common electrode EC2 and the second pixel electrode EP2 constitute the two plates of the second storage capacitor Cst2, and the dielectric layer between the two plates includes a third insulating layer PVX2.

[0413] Referring to Figures 20 to 20, the display substrate provided in this embodiment can be prepared by the following steps:

[0414] Step 21: Form a patterned first conductive layer M1 on the substrate 10, as shown in FIG20. The first conductive layer M1 includes a data line DL and a first common electrode EC1, and may also include a masking pattern (not shown in the figure). The orthogonal projection of the masking pattern on the substrate 10 covers the channel region CH.

[0415] Step 22: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 facing away from the substrate 10, as shown in Figure 37. The semiconductor layer ACT is a transparent material and includes semiconductor patterns located in different sub-pixels PX. The semiconductor patterns overlap with the orthographic projection of the data line DL on the substrate 10. The semiconductor patterns include a source connection region S, a first conductive region DT1, a second conductive region DT2, a channel region CH, a drain connection region D, and a sixth conductive region DT6 arranged and connected sequentially along the first direction f1. The sixth conductive region DT6 constitutes the first pixel electrode EP1 and overlaps with the first common electrode EC1.

[0416] Step 23: A patterned first insulating layer GI is formed on the side of the semiconductor layer ACT away from the substrate 10, as shown in FIG30. The first insulating layer GI includes a first via H1 and a third via H3. The first via H1 exposes a portion of the data line DL, the source connection region S and the first conductor region DT1. The third via H3 is located in the region of the first common electrode EC1.

[0417] Step 24: A patterned second conductive layer M2 is formed on the side of the first insulating layer GI away from the substrate 10, as shown in Figure 31. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, and a third transition pattern ZJ3. The gate G is connected to one side of the scan line GL and overlaps with the channel region CH. The first transition pattern ZJ1 partially covers the first via H1 and is connected to the data line DL and the source connection region S, respectively. The third transition pattern ZJ3 fully covers the third via H3 and is connected to the first common electrode EC1.

[0418] After forming the second conductive layer M2, the first insulating layer GI can be etched a second time using the second conductive layer M2 as a mask. Then, using the second conductive layer M2 as a mask again, a self-aligned process is used to conduct the semiconductor material in the exposed areas of the semiconductor layer ACT (such as the first conductor region DT1, the second conductor region DT2, the region located between the channel region CH and the drain connection region D, and the sixth conductor region DT6). This conductor formation process can, for example, use dry etching equipment or ion implantation equipment to implant plasma (such as plasma containing at least one element selected from helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material, or use ion doping technology to dope any one or more of the above elements into the semiconductor material to achieve conductor formation. Among these methods, using dry etching equipment to conduct the semiconductor material can be performed simultaneously with the second etching process of the first insulating layer GI, thereby simplifying the process.

[0419] Step 25: A second insulating material is sequentially deposited on the side of the second conductive layer M2 away from the substrate 10 to form a second insulating material layer. Then, an organic insulating material is coated to form an organic insulating material layer. Next, the organic insulating material layer is patterned to form an organic insulating layer RS, as shown in Figure 32. The organic insulating layer RS ​​includes two organic vias, namely a first organic via RH1 and a second organic via RH2. The first organic via RH1 is located within the region of the third transition pattern ZJ3. The first organic via RH1 and the third via H3 are arranged along the second direction f2. The second organic via RH2 is located within the region of the first pixel electrode EP1, such as the region of the second sub-electrode 112.

[0420] Step 26: Pattern the second insulating material layer to form the second insulating layer PVX1, as shown in Figure 33. The second insulating layer PVX1 includes two vias, namely via PH1 and via PH2. Via PH1 is located in the first organic via RH1, and via PH2 is located in the second organic via RH2.

[0421] For example, as shown in FIG33, via PH1 is centrally located within the first organic via RH1, and via PH2 is centrally located within the second organic via RH2. Vias PH1 and via PH2 are arranged along the first direction f1.

[0422] Step 27: A patterned third conductive layer M3 is formed on the side of the organic insulating layer RS ​​facing away from the substrate 10, as shown in Figure 34. The third conductive layer M3 includes a second common electrode EC2 and a fourth transition pattern ZJ4 separated from each other. The second common electrode EC2 covers the via RH1 on the third transition pattern ZJ3 and communicates with the third transition pattern ZJ3, and further communicates with the first common electrode EC1. The fourth transition pattern ZJ4 covers the via RH2 on the first pixel electrode EP1 and communicates with the first pixel electrode EP1.

[0423] Step 28: A patterned third insulating layer PVX2 is formed on the side of the third conductive layer M3 away from the substrate 10, as shown in FIG35. The third insulating layer PVX2 includes a via H4 located in the region of the second organic via RH2 for exposing the fourth transition pattern ZJ4.

[0424] Step 29: A patterned transparent conductive layer TD is formed on the side of the third insulating layer PVX2 away from the substrate 10, as shown in Figure 20. The transparent conductive layer TD includes a second pixel electrode EP2 located in different sub-pixels PX. The second pixel electrode EP2 covers the via located on the fourth transition pattern ZJ4 and is connected to the fourth transition pattern ZJ4, and then connected to the first pixel electrode EP1.

[0425] Step 30: A patterned piezoelectric layer 20 is formed on the side of the transparent conductive layer TD facing away from the substrate 10. The piezoelectric layer 20 includes a piezoelectric pattern 21 and a barrier pattern 22.

[0426] In the third exemplary embodiment, as shown in FIG37, the driving circuit structure layer includes a first conductive layer M1, a buffer layer BF, a semiconductor layer ACT, a first insulating layer GI, a second conductive layer M2, a second insulating layer PVX1, an organic insulating layer RS, a third conductive layer M3, a third insulating layer PVX2, and a transparent conductive layer TD, which are sequentially stacked on one side of the substrate 10. The first conductive layer M1 is disposed close to the substrate 10.

[0427] As shown in Figure 37, the first conductive layer M1 includes a data line DL, the semiconductor layer ACT includes a semiconductor pattern, the semiconductor pattern includes a source connection region S, a first conductor region DT1, a second conductor region DT2, a channel region CH, a fourth conductor region DT4, a third conductor region DT3, a drain connection region D, and a fifth conductor region DT5 (i.e., the first pixel electrode EP1) arranged and connected in sequence along the first direction f1, the second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, and a second transition pattern ZJ2, the third conductive layer M3 includes a common electrode EC, i.e., a first common electrode EC1 and a second common electrode EC2, and the transparent conductive layer TD includes a second pixel electrode EP2.

[0428] As shown in Figure 37, the first adapter pattern ZJ1 connects the data line DL and the source connection area S through the first via H1, which is partially overlapped on the first insulating layer GI.

[0429] As shown in Figure 37, the first pixel electrode EP1 is disposed on the same layer as the drain connection region D and is connected to each other. The second pixel electrode EP2 is connected to the drain connection region D through the second transition pattern ZJ2. Specifically, the second transition pattern ZJ2 is connected to the drain connection region D through the second via H2 which is partially overlapped on the first insulating layer GI. The second pixel electrode EP2 and the second transition pattern ZJ2 are connected through vias disposed on the second insulating layer PVX1, the organic insulating layer RS ​​and the third insulating layer PVX2.

[0430] As shown in Figure 37, the first common electrode EC1 and the first pixel electrode EP1 constitute the two plates of the first storage capacitor Cst1. By removing the organic insulating layer RS ​​above the first pixel electrode EP1, the dielectric layer between the two plates is thinned to form the second insulating layer PVX1. The second common electrode EC2 and the second pixel electrode EP2 constitute the two plates of the second storage capacitor Cst2, and the dielectric layer between the two plates includes the third insulating layer PVX2.

[0431] Referring to Figures 30 to 37, the display substrate provided in this embodiment can be prepared by the following steps:

[0432] Step 31: Form a patterned first conductive layer M1 on the substrate 10, as shown in FIG30. The first conductive layer M1 includes data lines DL and may also include a masking pattern (not shown in the figure). The orthogonal projection of the masking pattern on the substrate 10 covers the channel region CH.

[0433] Step 32: A buffer layer BF and a patterned semiconductor layer ACT are sequentially formed on the side of the first conductive layer M1 away from the substrate 10, as shown in Figure 31. The semiconductor layer ACT is a transparent material and includes semiconductor patterns located in different sub-pixels PX. The semiconductor patterns overlap with the orthographic projection of the data line DL on the substrate 10. The semiconductor patterns include a source connection region S, a first conductive region DT1, a second conductive region DT2, a channel region CH, a fourth conductive region DT4, a third conductive region DT3, a drain connection region D, and a fifth conductive region DT5 (i.e., the first pixel electrode EP1) arranged and connected sequentially along the first direction f1. The fifth conductive region DT5 constitutes the first pixel electrode EP1 and overlaps with the first common electrode EC1.

[0434] Step 33: A patterned first insulating layer GI is formed on the side of the semiconductor layer ACT away from the substrate 10, as shown in Figure 32. The first insulating layer GI includes a first via H1 and a second via H2. The first via H1 and the second via H2 are located on both sides of the channel region CH. The first via H1 exposes a part of the data line DL, the source connection region S and the first conductor region DT1. The second via H2 exposes the drain connection region D.

[0435] Step 34: A patterned second conductive layer M2 is formed on the side of the first insulating layer GI away from the substrate 10, as shown in Figure 33. The second conductive layer M2 includes a scan line GL, a gate G, a first transition pattern ZJ1, and a second transition pattern ZJ2. The gate G is connected to one side of the scan line GL and overlaps with the channel region CH. The first transition pattern ZJ1 partially covers the first via H1 and is connected to the data line DL and the source connection region S, respectively. The second transition pattern ZJ2 partially covers the second via H2 and is connected to the drain connection region D.

[0436] After forming the second conductive layer M2, the first insulating layer GI can be etched a second time using the second conductive layer M2 as a mask. Then, using the second conductive layer M2 as a mask again, a self-aligned process is used to conduct the semiconductor material in the exposed areas of the semiconductor layer ACT (such as the first conductor region DT1, the second conductor region DT2, the third conductor region DT3, the fourth conductor region DT4, and the fifth conductor region DT5). This conductor formation process can, for example, use dry etching equipment or ion implantation equipment to implant plasma (such as plasma containing at least one element selected from helium, oxygen, nitrogen, chlorine, hydrogen, boron, and phosphorus) into the semiconductor material, or use ion doping technology to dope any one or more of the above elements into the semiconductor material to achieve conductor formation. Among these methods, using dry etching equipment to conduct the semiconductor material can be performed simultaneously with the second etching process of the first insulating layer GI, thereby simplifying the process.

[0437] Step 35: A second insulating material is sequentially deposited on the side of the second conductive layer M2 away from the substrate 10 to form a second insulating material layer. Then, an organic insulating material is coated to form an organic insulating material layer. Next, the organic insulating material layer is patterned to form an organic insulating layer RS, as shown in Figure 34. The organic insulating layer RS ​​includes an opening RH3, which exposes the first pixel electrode EP1 and the second transition pattern ZJ2 above it.

[0438] Step 36: A patterned third conductive layer M3 is formed on the side of the organic insulating layer RS ​​away from the substrate 10, as shown in FIG35. The third conductive layer M3 includes a common electrode EC of the first common electrode EC1 and the second common electrode EC2. The common electrode EC does not overlap with the second transition pattern ZJ2.

[0439] Step 37: A patterned third insulating layer PVX2 is formed on the side of the third conductive layer M3 away from the substrate 10, as shown in FIG36. The third insulating layer PVX2 includes a via H5 that penetrates the second insulating layer PVX1 to expose the second transition pattern ZJ2.

[0440] Step 38: A patterned transparent conductive layer TD is formed on the side of the third insulating layer PVX2 away from the substrate 10, as shown in FIG37. The transparent conductive layer TD includes a second pixel electrode EP2 located in different sub-pixels PX. The second pixel electrode EP2 covers the via located on the second transition pattern ZJ2 and communicates with the second transition pattern ZJ2, and then communicates with the first pixel electrode EP1.

[0441] Step 39: A patterned piezoelectric layer 20 is formed on the side of the transparent conductive layer TD facing away from the substrate 10. The piezoelectric layer 20 includes a piezoelectric pattern 21 and a barrier pattern 22.

[0442] In the three examples above, after forming the patterned piezoelectric layer 20, the following steps can be performed: a patterned third common electrode 30 is formed on the side of the piezoelectric layer 20 away from the substrate 10. The third common electrode 30 layer can be formed by chemical deposition with the barrier pattern 22 as a partition. The third common electrode 30 layer can be broken at the barrier pattern 22 to obtain the third common electrode 30 located in different sub-pixels PX.

[0443] The common electrode located on the retaining wall pattern 22 can be removed, or it can remain on the retaining wall pattern 22.

[0444] In one embodiment, the driving circuit structure layer of the first type of display substrate will be specifically described.

[0445] As shown in Figures 1A and 1B, the substrate 10 includes a first conductive layer M1, a semiconductor layer ACT, a second conductive layer M2, and a transparent conductive layer, which are sequentially stacked on one side of the substrate 10. The first conductive layer M1 is close to the substrate 10. The first conductive layer M1 includes a gate G, the semiconductor layer ACT includes a source connection region S, a channel region CH, and a drain connection region D, the second conductive layer M2 includes a fifth transition pattern ZJ5, and the transparent conductive layer includes a second pixel electrode EP2. The second pixel electrode EP2 is electrically connected to the drain connection region D through the fifth transition pattern ZJ5.

[0446] In this embodiment, a first insulating layer G1 is provided between the first conductive layer M1 and the semiconductor layer ACT. The scan line GL can be located in the first conductive layer M1 and electrically connected to the gate G.

[0447] As shown in Figure 1A, between the semiconductor layer ACT and the second conductive layer M2, there are also a second insulating layer PVX1, an organic insulating layer RS, and a fourth insulating layer PVX3. The second conductive layer M2 includes a fifth transition pattern ZJ5, which is connected to the drain connection region D through a sixth via H6. The second via H6 is located on the second insulating layer, the organic insulating layer, and the fourth insulating layer.

[0448] In some embodiments, the data line DL may be located in the second conductive layer M2 and overlap with the source connection region S.

[0449] In some embodiments, the transparent conductive layer is located on the side of the second conductive layer M2 away from the substrate 10, and overlaps with the fifth transition pattern ZJ5 through the seventh via H7, which is located on the third insulating layer PVX2 between the second conductive layer M2 and the transparent conductive layer TD.

[0450] The transparent conductive layer includes a second pixel electrode EP2, which does not overlap with the scan line GL or the data line DL.

[0451] In this embodiment, referring to FIG1C, the orthogonal projection of the piezoelectric region pattern on the substrate 10 can coincide with the orthogonal projection of the second pixel electrode EP2 on the substrate 10, and the orthogonal projection of the third common electrode 30 located in the sub-pixel PX on the substrate 10 can coincide with the orthogonal projection of the piezoelectric pattern 21 on the substrate 10.

[0452] In one embodiment, the driving circuit structure layer of the third type of display substrate can be as shown in FIG2, including a semiconductor layer ACT, a second conductive layer M2, a third conductive layer M3 and a transparent conductive layer sequentially stacked on one side of the substrate 10, with the semiconductor layer ACT disposed close to the substrate 10.

[0453] The semiconductor layer ACT includes a source connection region S, a channel region CH and a drain connection region D, the second conductive layer M2 includes a gate G, the second conductive layer M2 includes a sixth transition pattern ZJ6, and the transparent conductive layer includes a second pixel electrode EP2.

[0454] The second pixel electrode EP2 is connected to the drain connection region D through the sixth transition pattern ZJ6.

[0455] In this embodiment, the scan line GL can be located in the second conductive layer M2 and electrically connected to the gate G.

[0456] As shown in Figure 2, a first insulating layer GI is disposed between the semiconductor layer ACT and the second conductive layer M2, a second insulating layer PVX1 is disposed between the second conductive layer M2 and the third conductive layer M3, and an organic insulating layer RS ​​and a third insulating layer PVX2 are stacked between the third conductive layer M3 and the transparent conductive layer TD.

[0457] The second conductive layer M2 includes a sixth transition pattern ZJ6 and a data line DL. The data line DL is electrically connected to the source connection region S through a tenth via H10. The sixth transition pattern ZJ6 is electrically connected to the drain connection region D through an eighth via H8. The transparent conductive layer includes a second pixel electrode EP2. The second pixel electrode EP2 is electrically connected to the sixth transition pattern ZJ6 through a ninth via H9.

[0458] In this embodiment, referring to the plan view shown in FIG1C, the orthographic projection of the second pixel electrode EP2 on the substrate 10 does not overlap with the scan line GL and the data line DL.

[0459] The orthographic projection of the piezoelectric pattern 21 on the substrate 10 can coincide with the orthographic projection of the second pixel electrode EP2 on the substrate 10, and the orthographic projection of the third common electrode 30 located in the sub-pixel PX on the substrate 10 can partially coincide with the orthographic projection of the piezoelectric pattern 21 on the substrate 10.

[0460] This disclosure provides a display device, as shown in FIG46, which includes a counter substrate 171, an electrophoretic solution 172, and a display substrate 173 as provided in any embodiment. The electrophoretic solution 172 is located between the counter substrate 171 and the display substrate 173, and the pixel electrode is located on the side of the substrate 10 close to the electrophoretic solution.

[0461] The electrophoresis solution 172 includes target particles LZ. These target particles can be electrophoretic particles, such as two-color, three-color, or four-color particles; they can also be liquid crystal molecules.

[0462] Those skilled in the art will understand that the display device provided in this disclosure has the advantages of the display substrate 173 described above.

[0463] The display devices disclosed herein can be: electronic paper, electronic price tags, electronic name tags, display modules, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, in-vehicle display devices, smartwatches, fitness wristbands, personal digital assistants, and any other products or components with display functions.

[0464] For example, the counter substrate 171 includes: a counter substrate 1711, and a counter electrode 1712 disposed on the side of the counter substrate 1711 near the electrophoretic solution 172, wherein the counter electrode 1712 and the pixel electrode together form an electric field EP1 / EP2 to drive the target particle LZ to move.

[0465] In this way, the target particle in this embodiment can move under the electric field between the opposing substrate 171 and the display substrate, and can also move towards the display side driven by the piezoelectric pattern 21 when the piezoelectric pattern 21 deforms, thereby improving the response speed and reducing the driving voltage.

[0466] For example, the electrophoresis solution 172 can be an electronic paper membrane.

[0467] For example, the electrophoretic solution 172 can be a microcup structure, where the microcup structure in a single sub-pixel PX contains target particles of the same color, and the microcup structures in N adjacent sub-pixels PX contain target particles of different colors. For instance, four adjacent sub-pixels PX constitute a pixel containing four different colored target particles, such as white particles, yellow particles, magenta particles, and cyan particles. The combination of these four colored sub-pixels PX enables full-color display of the display device.

[0468] For example, as shown in FIG48, the display device may further include a driver chip IC bonded to the non-display area NA of the display substrate 173, and the driver chip IC is connected to the driver circuit board 182 via the flexible circuit board 181.

[0469] During the display process, the driver chip IC can be activated via the driver circuit board 182. The driver chip IC inputs the scan signal to the scan line GL and the data signal to the data line DL, turning on the thin film transistor. The pixel electrode of the sub-pixel PX obtains the voltage required for the image and forms a voltage difference with the upper opposing electrode 1712, thereby driving the movement of particles in the electrophoresis solution 172. The driver chip IC can also output voltage to the third common electrode 30, thereby forming an electric field between the pixel electrode and the third common electrode 30, which allows the piezoelectric pattern 21 to deform in the thickness direction Z of the display substrate. The piezoelectric pattern 21 responds to the electric field and deforms in the thickness direction Z, such as elongating in the thickness direction Z, thereby helping the particles move towards the display side. This improves the response speed of the particles and eliminates the need for high-voltage driving, thus reducing the driving voltage.

[0470] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0471] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0472] The above provides a detailed description of a display substrate and display device provided by this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0473] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0474] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

[0475] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this disclosure. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0476] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this disclosure may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0477] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This disclosure can be implemented by means of hardware comprising a plurality of different elements and by means of a suitably programmed computer. In a unit claim enumerating a plurality of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0478] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display substrate, wherein, The display substrate includes a display area and a non-display area. The display area includes multiple sub-pixels, each sub-pixel including a thin-film transistor and a pixel electrode. The display substrate also includes: Substrate; A driving circuit structure layer is located on one side of the substrate, including the pixel electrode and the source connection region, channel region, drain connection region and gate of the thin film transistor, wherein the pixel electrode is electrically connected to the drain connection region; A piezoelectric layer is located on the side of the driving circuit structure layer opposite to the substrate. The piezoelectric layer includes piezoelectric patterns located on different sub-pixels. The piezoelectric patterns at least partially overlap with the orthographic projection of the pixel electrode on the substrate. The piezoelectric pattern is configured to deform in the thickness direction of the substrate based on the voltage applied to the pixel electrode.

2. The display substrate according to claim 1, wherein, The piezoelectric layer further includes a barrier pattern, which includes multiple openings, and the pixel electrodes of different sub-pixels and the orthographic projections of the piezoelectric patterns on the substrate are located within the orthographic projections of the different openings on the substrate. In the thickness direction of the substrate, the size of the barrier pattern is larger than the size of the piezoelectric pattern.

3. The display substrate according to claim 2, wherein, The barrier pattern includes a first portion located on the side of the piezoelectric pattern away from the substrate, and a second portion located on the side of the piezoelectric pattern closer to the substrate; In the thickness direction of the substrate, the size of the second portion is smaller than the size of the first portion, and the size of the first portion is larger than the size of the piezoelectric pattern.

4. The display substrate according to claim 3, wherein, The pixel electrodes located in different sub-pixels are isolated by the second portion.

5. The display substrate according to claim 4, wherein, The sidewall of the second part is in direct contact with the sidewall of the pixel electrode.

6. The display substrate according to any one of claims 2-5, wherein, The size of the barrier pattern in the planar direction of the substrate is larger than the size of the piezoelectric pattern in the thickness direction of the substrate.

7. The display substrate according to any one of claims 2-5, wherein, The driving circuit structure layer also includes scan lines and data lines, the scan lines intersect the data lines, and the sub-pixel is located in the area defined by the intersection of the scan lines and the data lines; The barrier pattern includes a first barrier parallel to the scan line and a second barrier parallel to the data line. Wherein, the orthographic projection of the first barrier on the substrate at least partially overlaps with the orthographic projection of the scan line on the substrate, and the orthographic projection of the second barrier on the substrate at least partially overlaps with the orthographic projection of the data line on the substrate.

8. The display substrate according to claim 7, wherein, The pixel electrode includes a second pixel electrode, and in the thickness direction of the substrate, the distance between the second pixel electrode and the piezoelectric pattern is smaller than the distance between the film layer in the driving circuit structure layer other than the film layer where the second pixel electrode is located and the piezoelectric pattern. Wherein, the edge of the first barrier near the second pixel electrode coincides with the orthographic projection of the edge of the second pixel electrode near the scan line onto the substrate; and / or, The edge of the second barrier near the second pixel electrode and the edge of the second pixel electrode near the data line have their orthogonal projections on the substrate.

9. The display substrate according to claim 7, wherein, The width of the first barrier along the data line direction is less than or equal to the spacing between the pixel electrodes of two adjacent sub-pixels along the data line direction; And / or, the width of the second barrier along the scan line direction is greater than or equal to the spacing between the pixel electrodes of two adjacent sub-pixels along the scan line direction.

10. The display substrate according to claim 1, wherein, The pixel electrode includes a second pixel electrode, and in the thickness direction of the substrate, the distance between the second pixel electrode and the piezoelectric pattern is smaller than the distance between the film layer in the driving circuit structure layer other than the film layer where the second pixel electrode is located and the piezoelectric pattern. The piezoelectric pattern is in direct contact with the second pixel electrode on the side closest to the substrate.

11. The display substrate according to claim 1, wherein, The display substrate further includes: The third common electrode is located on the side of the piezoelectric layer away from the substrate, and the orthographic projection of the third common electrode on the substrate at least partially overlaps with the orthographic projection of the piezoelectric pattern on the substrate.

12. The display substrate according to claim 11, wherein, The third common electrode is in direct contact with the surface of the piezoelectric pattern on the side opposite to the substrate.

13. The display substrate according to claim 1, wherein, The driving circuit structure layer includes: a first conductive layer, a semiconductor layer, a first insulating layer, and a second conductive layer sequentially stacked on one side of the substrate, wherein the first conductive layer is disposed close to the substrate; wherein... The first conductive layer includes data lines; The semiconductor layer includes multiple semiconductor patterns located in different sub-pixels. The semiconductor patterns include the source connection region, the first conductor region, and the channel region. The source connection region, the first conductor region, and the channel region are arranged along a first direction and connected sequentially. The second conductive layer includes a first transition pattern, a scan line, and the gate; The first insulating layer has a first via, which exposes a portion of the data line, the source connection region, and the first conductor region. The data line and the source connection region are respectively connected to the first transition pattern through the first via. The first transition pattern and the orthographic projection of the first conductor region on the substrate do not overlap.

14. The display substrate according to claim 13, wherein, The pixel electrode includes a first pixel electrode and a second pixel electrode; The first pixel electrode is located in the semiconductor layer or the second conductive layer, and the display substrate further includes: A third conductive layer is disposed on the side of the second conductive layer opposite to the substrate; and A transparent conductive layer is disposed on the side of the third conductive layer opposite to the substrate, including a second pixel electrode. The second pixel electrode is connected to the first pixel electrode through a via, and the first pixel electrode is also connected to the drain connection region of the thin film transistor. In this case, the orthographic projection of the first pixel electrode on the substrate overlaps with the orthographic projection of the second pixel electrode on the substrate, and the orthographic projection of the piezoelectric pattern on the substrate overlaps with the orthographic projections of both the first pixel electrode and the second pixel electrode on the substrate.

15. The display substrate according to claim 14, wherein, The first pixel electrode includes a first sub-electrode, a second sub-electrode, and a third sub-electrode connected in sequence. The first sub-electrode is connected to the drain connection region of the thin film transistor and is located on the side of the drain connection region away from the channel region. Along the second direction and away from the channel region, the widths of the first sub-electrode, the second sub-electrode, and the third sub-electrode increase sequentially along the first direction; the second direction intersects the first direction. The piezoelectric pattern includes a first pattern area and a second pattern area. The first pattern area overlaps with the orthographic projection of the first sub-electrode on the substrate, and the second pattern area overlaps with the orthographic projections of the second sub-electrode and the third sub-electrode on the substrate. Wherein, the width of the first pattern area along the first direction is less than the width of the second pattern area along the first direction, the orthographic projection of the edge of the second pattern area near the scan line on the substrate coincides with the orthographic projection of the edge of the second sub-electrode near the scan line on the substrate, the width of the second pattern area along the first direction is greater than the width of the second sub-electrode along the first direction, and is greater than or equal to the width of the third sub-electrode along the first direction.

16. The display substrate according to claim 15, wherein, The sub-pixel further includes a first common electrode and a second common electrode; wherein the first common electrode and the first pixel electrode are disposed in different layers and overlap in their orthogonal projections on the substrate, the first common electrode is located in the first conductive layer, and the second common electrode is located in the third conductive layer. The second conductive layer further includes a third transition pattern, which is located on the side of the first transition pattern and the gate away from the scan line. The second common electrode and the first common electrode are respectively connected to the third transition pattern through vias. The third transition pattern does not overlap with the orthographic projection of the first pixel electrode on the substrate. Wherein, the orthographic projection of the second patterned area on the substrate overlaps the orthographic projection of the third transition pattern on the substrate.

17. The display substrate according to claim 16, wherein, The semiconductor pattern further includes a third conductive region and a fourth conductive region, wherein the channel region, the fourth conductive region, the third conductive region, and the drain connection region are arranged along the first direction and connected in sequence; The second conductive layer further includes a second transition pattern located on the side of the gate away from the first transition pattern. A second via is also provided on the first insulating layer, the second via exposing the drain connection region and the third conductive region. The second transition pattern overlaps with the drain connection region through the second via. Wherein, the orthographic projection of the first patterned area on the substrate covers the orthographic projection of the second via on the substrate.

18. The display substrate according to claim 14, wherein, The first pixel electrode is located in the semiconductor layer, and the first pixel electrode includes a fourth sub-electrode and a fifth sub-electrode connected in sequence; the fourth sub-electrode is connected to the drain connection region of the thin film transistor and is located on the side of the drain connection region away from the channel region; the width of the fourth sub-electrode along the first direction is smaller than the width of the fifth sub-electrode along the first direction. The piezoelectric pattern includes a first pattern area and a second pattern area, wherein the first pattern area overlaps with the orthographic projection of the fourth sub-electrode on the substrate, and the second pattern area overlaps with the orthographic projection of the fifth sub-electrode on the substrate; Wherein, the width of the first pattern area along the first direction is less than the width of the second pattern area along the first direction, the orthographic projection of the edge of the second pattern area near the scan line on the substrate coincides with the orthographic projection of the edge of the fifth sub-electrode near the scan line on the substrate, and the width of the second pattern area along the first direction is greater than or equal to the width of the fifth sub-electrode along the first direction.

19. The display substrate according to claim 14, wherein, The sub-pixel further includes a first common electrode and a second common electrode; Wherein, the first common electrode and the first pixel electrode are disposed in different layers and their orthogonal projections on the substrate overlap, the first common electrode and the second common electrode are disposed in different layers, and the second common electrode is located in the third conductive layer; The orthographic projection of the piezoelectric pattern on the substrate covers the orthographic projection of the first common electrode on the substrate and at least partially overlaps with the orthographic projection of the second common electrode on the substrate.

20. The display substrate according to claim 14, wherein, The orthographic projection of the second pixel electrode on the substrate covers the orthographic projection of the first pixel electrode on the substrate, and the orthographic projections of both the first pixel electrode and the second pixel electrode on the substrate do not overlap with the orthographic projection of the scan line on the substrate; The orthographic projection of the first pixel electrode on the substrate does not overlap with the orthographic projection of the data line on the substrate, and the second pixel electrode at least partially covers the data line; The piezoelectric layer further includes a barrier pattern, which isolates the piezoelectric patterns located in different sub-pixels; Wherein, the orthographic projection of the edge of the barrier pattern along the scan line direction on the substrate coincides with the orthographic projection of the edge of the second pixel electrode along the scan line direction on the substrate; the orthographic projection of the portion of the barrier pattern parallel to the data line on the substrate covers the orthographic projection of the data line on the substrate and does not overlap with the first pixel electrode.

21. The display substrate according to claim 1, wherein, The driving circuit structure layer includes: a first conductive layer, a semiconductor layer, a second conductive layer, and a transparent conductive layer sequentially stacked on one side of the substrate, with the first conductive layer close to the substrate; wherein... The first conductive layer includes a gate; The semiconductor layer includes the source connection region, the channel region, and the drain connection region; The second conductive layer includes a fifth transition pattern, and the transparent conductive layer includes a second pixel electrode, which is electrically connected to the drain connection region through the fifth transition pattern.

22. The display substrate according to claim 1, wherein, The driving circuit structure includes: a semiconductor layer, a second conductive layer, a third conductive layer and a transparent conductive layer sequentially stacked on one side of the substrate, wherein the semiconductor layer is disposed close to the substrate; The semiconductor layer includes the source connection region, the channel region, and the drain connection region; the second conductive layer includes the gate; the second conductive layer includes a sixth transition pattern; and the transparent conductive layer includes a second pixel electrode. The second pixel electrode is connected to the drain connection area through the sixth transition pattern.

23. A display device, comprising: The opposing substrate, the electrophoretic solution, and the display substrate as described in any one of claims 1 to 22, wherein the electrophoretic solution is located between the opposing substrate and the display substrate.

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