LED with transparent conductive structure
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2026-08-14
Smart Images
Figure CN122581003A_ABST
Abstract
Description
[0001] Cross-reference to related applications This application claims the benefit of priority to U.S. nonprovisional application No. 18 / 516,473, entitled “LED with transparent conductive structure,” filed November 21, 2023, which is incorporated herein by reference in its entirety. Technical Field
[0002] This invention relates generally to light-emitting devices, and in particular to LEDs having a segmented transparent conductive oxide structure. Background Technology
[0003] The automotive and general lighting industries have witnessed significant technological advancements, one of the breakthroughs being the invention of the light-emitting diode (LED). This innovation has transformed how we perceive and experience automotive and general lighting, offering increased efficiency, durability, and versatility. Developed in response to the limitations of traditional light sources, automotive LEDs have become a key feature of modern vehicles, providing enhanced safety, aesthetics, and functionality.
[0004] In the automotive and general lighting sectors, the pursuit of increased luminous flux has been a continuous effort. Luminous flux is a measure of the total amount of visible light emitted by a light source, and it directly impacts the practical applications of LEDs.
[0005] The reflectivity of an LED die is a function of many factors, including the size of the contact area between the bonding or conductive layer contacts on the n-side and p-side. The geometry of this die and the size of its openings affect the size of the reflective elements contained within it. Reducing the size of these openings or otherwise adjusting the geometry of the layers within the die can allow for an increase in the size of reflective elements and a reduction in the size of absorptive or less reflective elements. This adjustment can increase the overall reflectivity and optical efficiency of the system. Summary of the Invention
[0006] Embodiments of this invention introduce a novel method to increase the luminous flux of LEDs while remaining cost-effective in production. Compatible with chip-scale package (CSP) architectures, embodiments of this invention include a process for forming a die structure characterized by a segmented transparent conductive oxide (TCO) structure and / or a distributed Bragg reflector (DBR) mirror to increase the die's reflectivity while maintaining a low forward voltage V. f In other words, embodiments of the present invention include an improved workflow for manufacturing improved dies for LEDs. These dies can be used in automotive LEDs, general lighting LEDs, and any other LED applications that can utilize CSP dies.
[0007] These and other embodiments, features, and advantages of the invention will become more apparent to those skilled in the art when taken in conjunction with the accompanying drawings, which have been briefly described above, and in the following more detailed description of the invention. Attached Figure Description
[0008] Figure 1 A schematic cross-sectional view of an example pcLED is shown.
[0009] Figure 2A and Figure 2B The cross-sectional view and top view of the pcLED array are shown respectively. Figure 2C A schematic top view of an LED chip is shown, from which LEDs can be formed into various shapes. Figure 2A and Figure 2B The LED array shown is shown.
[0010] Figure 3A A schematic top view of an electronic board on which a pcLED array can be mounted is shown, and Figure 3B Similarly, installations are shown. Figure 3A pcLED array on an electronic board.
[0011] Figure 4A A schematic cross-sectional view of a pcLED array arranged relative to a waveguide and a projection lens is shown. Figure 4B It shows something similar to Figure 4A The arrangement is there, but there is no waveguide.
[0012] Figure 5 An example camera flash system is illustrated schematically.
[0013] Figure 6 An example display (e.g., AR / VR / MR) system is illustrated schematically.
[0014] Figure 7 A flowchart illustrating a process for manufacturing a die having a segmented transparent conductive oxide (TCO) structure according to an embodiment of the present invention is shown.
[0015] Figure 8 A cross-section of a die is shown, which has TCOs spaced apart from each other at the n-contact and p-contact.
[0016] Figure 9 A cross-section of a die is shown, which has TCOs spaced apart from each other at the n-contact and p-contact, as well as an extended metal reflector.
[0017] Figure 10 A cross-section of a die is shown, which has TCOs spaced apart from each other at the n-contact and p-contact, wherein two distributed Bragg reflectors (DBRs) are spaced apart from each other. Detailed Implementation
[0018] The following detailed description should be read with reference to the accompanying drawings, in which the same reference numerals refer to the same elements. The drawings, not necessarily drawn to scale, depict alternative embodiments and are not intended to limit the scope of the invention. The detailed description illustrates the principles of the invention by way of example rather than limitation. This description will clearly enable those skilled in the art to make and use the invention, and describes several embodiments, modifications, variations, substitutions, and uses of the invention.
[0019] As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” include plural indicators unless the context clearly indicates otherwise. Furthermore, the term “parallel” is intended to mean “substantially parallel” and includes minor deviations in parallel geometry. The term “perpendicular” refers to a direction parallel to Earth’s gravity. The term “horizontal” refers to a direction perpendicular to “perpendicular.” The term “on” means arranged to overlap (e.g., vertically) and / or in direct contact.
[0020] Figure 1 An example of a single pcLED 100 is shown, comprising a light-emitting semiconductor diode (LED) structure 102 disposed on a substrate 104 and a phosphor layer 106 disposed on the LED (also referred to in this text as a wavelength conversion structure). The light-emitting semiconductor diode structure 102 typically includes an active region disposed between n-type and p-type layers. Applying a suitable forward bias across the diode structure results in light emission from the active region. The wavelength of the emitted light is determined by the composition and structure of the active region.
[0021] For example, an LED can be a group III nitride LED that emits ultraviolet, blue, green, or red light. Alternatively, an LED formed from any other suitable material system and emitting light of any other suitable wavelength can be used. Other suitable material systems may include, for example, group III phosphide materials, group III arsenide materials, and group II-VI materials.
[0022] Depending on the required light output and the color specifications from the pcLED, any suitable phosphor material can be used. The phosphor layer may, for example, comprise phosphor particles dispersed in or bonded together with an adhesive material, or may comprise a sintered ceramic phosphor plate.
[0023] Figures 2A-2BCross-sectional and top views of an array 200 of pcLEDs 100, including a phosphor layer 106 disposed on a substrate 202, are shown respectively. Such an array can include any suitable number of pcLEDs arranged in any suitable manner. In the example shown, the array is described as being monolithically formed on a shared substrate; however, alternatively, the pcLED array can be formed from individual, mechanically separated pcLEDs disposed on the substrate. The substrate 202 may optionally include CMOS circuitry for driving the LEDs and can be formed from any suitable material.
[0024] although Figures 2A-2B A 3×3 array of 9 pcLEDs is shown, but such an array could include, for example, dozens, hundreds, or thousands of LEDs. The width (e.g., side length) of a single LED in the array plane could be, for example, less than or equal to 1 millimeter (mm), less than or equal to 500 micrometers, less than or equal to 100 micrometers, or less than or equal to 50 micrometers. LEDs in such an array could be separated from each other by streets or alleyways having widths in the array plane of, for example, several hundred micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, less than or equal to 10 micrometers, or less than or equal to 5 micrometers.
[0025] Figure 2C A schematic top view of a portion of an LED chip 210 is shown, from which forms such as Figure 2A and Figure 2B The LED array shown is shown. Figure 2C An enlarged 3×3 section of the wafer is also shown. In the example wafer, individual LEDs or pcLEDs 111 with side lengths (e.g., width) W1 are arranged in a square matrix, adjacent LEDs or pcLEDs having a center-to-center distance D1 and separated by aisles 113 of width W2. W1 can be, for example, less than or equal to 1 millimeter (mm), less than or equal to 500 micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, or less than or equal to 10 micrometers. W2 can be, for example, several hundred micrometers, less than or equal to 100 micrometers, less than or equal to 50 micrometers, less than or equal to 10 micrometers, or less than or equal to 5 micrometers. D1 = W1 + W2.
[0026] For example, the array can be formed by dicing the wafer 210 into individual LEDs or pcLEDs and arranging these dies on a substrate. Alternatively, the array can be formed from the entire wafer 210, or by dividing the wafer 210 into smaller arrays of LEDs or pcLEDs.
[0027] LEDs with dimensions (e.g., side length) less than or equal to about 50 micrometers in an array plane are generally referred to as microLEDs, and an array of such microLEDs can be called a microLED array.
[0028] Although the illustrated example shows rectangular LEDs or pcLEDs arranged in a symmetrical matrix, the LEDs or pcLEDs and the array can have any suitable shape or arrangement, and do not need to all have the same shape or size. For example, the LEDs or pcLEDs located in the center of the array may be larger than those located in the outermost parts of the array. Alternatively, the LEDs or pcLEDs located in the center of the array may be smaller than those located in the outermost parts of the array.
[0029] In a pcLED array, all pcLEDs can be configured to emit substantially the same spectrum. Alternatively, the pcLED array can be a multicolor array, where different pcLEDs in the array can be configured to emit different spectra (colors of light) by employing different phosphor compositions. Similarly, in an array of directly emitting LEDs (i.e., without wavelength conversion by phosphors), all LEDs in the array can be configured to emit substantially the same spectrum, or the array can be a multicolor array including LEDs configured to emit different colors of light.
[0030] Individual LEDs or pcLEDs in the array can be individually operable (addressable) and / or can operate as part of a group or subset of LEDs or pcLEDs in the array (e.g., adjacent).
[0031] An array of LEDs or pcLEDs, or a portion thereof, can be formed as a segmented monolithic structure, wherein the individual LEDs or pcLEDs are electrically isolated from each other by trenches and / or insulating materials, but the electrically isolated segments are physically connected to each other by portions of a semiconductor structure.
[0032] Therefore, an LED or pcLED array can be or include a monolithic multicolor matrix of individually operable LEDs or pcLED light emitters. The LEDs or pcLEDs in a monolithic array can be, for example, microLEDs as described above.
[0033] A single, individually operable LED or pcLED, or a group of adjacent such LEDs or pcLEDs, can correspond to a single pixel (image element) in a display. For example, a group of three individually operable adjacent LEDs or pcLEDs, including a red emitter, a blue emitter, and a green emitter, can correspond to a single color-tunable pixel in a display.
[0034] like Figures 3A-3BAs shown, the LED or pcLED array 200 can be mounted on an electronic board 300, which includes a power supply and control module 302, a sensor module 304, and an attachment area 306. The power supply and control module 302 can receive power and control signals from an external source and signals from the sensor module 304, based on which it controls the operation of the LED / pcLED. The sensor module 304 can receive signals from any suitable sensor (e.g., a temperature or light sensor). Alternatively, the array 200 can be mounted on a separate board (not shown) from the power supply and control module and the sensor module.
[0035] A single LED or pcLED can optionally be combined with a lens or other optical element, or arranged in combination with a lens or other optical element, which is adjacent to or disposed on the phosphor layer. Such an optical element, not shown in the figure, can be referred to as a "primary optical element." Furthermore, as... Figures 4A-4B As shown, array 200 (e.g., mounted on electronic board 300) can be arranged in conjunction with secondary optical elements such as waveguides, lenses, or both for the intended application. Figure 4A In this arrangement, the light emitted by pcLED 100 is collected by waveguide 402 and guided to projection lens 404. For example, projection lens 404 can be a Fresnel lens. This arrangement can be applied, for example, to automotive headlights. Figure 4B In this arrangement, the light emitted by pcLED 100 is directly collected by projection lens 404 without the use of an intermediate waveguide. This arrangement can be particularly suitable when LEDs or pcLEDs can be spaced close enough together, and can also be used in automotive headlights and camera flash applications. For example, microLED display applications can use similar... Figures 4A-4B The optical arrangement described in the text.
[0036] In another example arrangement, the central block of LEDs or pcLEDs in the array can be associated with a single common (shared) optics, and each of the edge LEDs or pcLEDs in the array located around the central block is associated with a corresponding individual optics.
[0037] Typically, depending on the desired application, any suitable arrangement of optical elements can be used in conjunction with the LED and pcLED arrays described herein.
[0038] The LED and pcLED arrays described herein can be used in applications that require or benefit from fine-grained intensity, spatial, and temporal control of light distribution. These applications can include, but are not limited to, precise, specific patterning of emitted light from a single LED or pcLED, or from a group of LEDs or pcLEDs (e.g., a block). Depending on the application, the emitted light can be spectrally diverse, time-adaptive, and / or environmentally responsive. Such arrays can provide pre-programmed light distributions in various intensity, spatial, or temporal patterns. The emitted light can be based at least in part on received sensor data and can be used for optical wireless communication. At the individual LED / pcLED, group, or device level, the associated electronics and optics may differ.
[0039] Arrays of independently operable LEDs or pcLEDs can be used in conjunction with lenses, lens systems, or other optics or optical systems (e.g., as described above) to provide illumination suitable for a specific purpose. For example, in operation, such adaptive lighting systems can provide illumination that varies with color and / or intensity on an illuminated scene or object, and / or aim in a desired direction. The focusing or manipulation of the light beam emitted by the LED or pcLED array can be electronically performed by activating LEDs or pcLEDs in groups or sequences of varying sizes, allowing for dynamic adjustment of the beam shape and / or direction without moving the optics or changing the focus of the lenses in the lighting device. A controller can be configured to receive data indicating the position and color characteristics of objects or people in a scene, and based on this information, control the LEDs or pcLEDs in the array to provide illumination suitable for the scene. This data can be provided by, for example, image sensors, or optical (e.g., laser scanning) or non-optical (e.g., millimeter-wave radar) sensors. Such adaptive lighting is increasingly important for automotive (e.g., adaptive headlights), mobile device cameras (e.g., adaptive flash), and VR and AR applications (such as those described below).
[0040] Figure 5 An example camera flash system 500 is schematically illustrated, comprising an LED or pcLED array and a lens system 502. This system may be, or include, the adaptive lighting system described above, wherein the LEDs or pcLEDs in the array may be individually operable. During operation of the camera flash system, illumination from some or all of the LEDs or pcLEDs in the array and lens system 502 can be adjusted—deactivated, operated at full intensity, or operated at intermediate intensity. As described above, the array may be a monolithic array, or may comprise one or more monolithic arrays. As described above, the array may be a microLED array.
[0041] The flash system 500 also includes an LED driver 506 controlled by a controller 504 (e.g., a microprocessor). The controller 504 may also be coupled to a camera 507 and a sensor 508, and operates according to instructions and profiles stored in a memory 510. The camera 507, along with the LED or pcLED array and lens system 502, may be controlled by the controller 504 to, for example, match the illumination provided by the system 502 (i.e., the field of view of the illumination system) to the field of view of the camera 507, or otherwise adapt the illumination provided by the system 502 to the scene observed by the camera, as described above. The sensor 508 may include, for example, a position sensor (e.g., a gyroscope and / or accelerometer) and / or other sensors that may be used to determine the position and orientation of the system 500.
[0042] Figure 6 An example display (e.g., AR / VR / MR) system 600 is schematically illustrated, comprising an array 610 of individually operable LEDs or pcLEDs, a display 620, a light-emitting array controller 630, a sensor system 640, and a system controller 650. As described above, array 610 may be a monolithic array or may comprise one or more monolithic arrays. The array may be monochromatic. Alternatively, as described above, the array may be a multicolor array, wherein different LEDs or pcLEDs in the array are configured to emit light of different colors. Thus, the array may be or comprise a monolithic multicolor matrix of individually operable LEDs or pcLED light emitters, which may be, for example, microLEDs as described above. A single individually operable LED or pcLED in the array, or a group of adjacent such LEDs or pcLEDs, may correspond to a single pixel (image element) in the display. For example, a group of three individually operable adjacent LEDs or pcLEDs, including a red emitter, a blue emitter, and a green emitter, may correspond to a single color-tunable pixel in the display. Array 610 can be used to project light onto graphic or object patterns supporting an AR / VR / MR system. Control inputs are provided to the sensor system 640, while power and user data inputs are provided to the system controller 650. In some embodiments, the modules included in the system 600 may be compactly arranged in a single structure, or one or more components may be mounted separately and connected via wireless or wired communication. For example, the array 610, display 620, and sensor system 640 may be mounted on a headset or glasses, while the light-emitting array controller and / or system controller 650 may be mounted separately.
[0043] System 600 can incorporate various optical devices (not shown) to couple the light emitted by array 610 to display 620. Any suitable optical device can be used for this purpose.
[0044] For example, sensor system 640 may include external sensors such as cameras, depth sensors, or audio sensors to monitor the environment, and internal sensors such as accelerometers or two-axis or three-axis gyroscopes to monitor the position of the AR / VR / MR headset. Other sensors may include, but are not limited to, barometric pressure, stress, temperature, or any other suitable sensors required for local or remote environmental monitoring. In some embodiments, control input may include detected touch or tap, gesture input, or control based on the position of the headset or display.
[0045] In response to data from sensor system 640, system controller 650 can send images or instructions to light-emitting array controller 630. Changes or modifications to images or instructions can also be made through user data input or automatic data input as needed. User data input can include, but is not limited to, data input provided by audio commands, haptic feedback, eye or pupil positioning, or connected keyboard, mouse, or game controller.
[0046] The flux, reflectivity, and optical efficiency of the LED die used in the above-mentioned LEDs depend on the geometry of the middle layers and components of the die. Improving the geometry of these components will improve the overall luminous efficiency of the LED.
[0047] Figure 7 A method for manufacturing a die used in a light-emitting device according to an embodiment of the present invention is shown.
[0048] At 700, a wafer is provided. The wafer may include a pGaN layer 810 on an nGaN layer 820. That is, the wafer may include a p-type doped semiconductor material stacked with an n-type doped semiconductor material.
[0049] At 710, the mesa is etched to expose the nGaN surface 822 (e.g., the surface of an n-type doped semiconductor) that will become part of the n-contact. Etching can include dry etching and / or wet etching. This can include removing portions of the pGaN layer to expose the nGaN surface of the nGaN layer, thereby enabling the establishment of electrical contacts on the horizontal, flat nGaN surface of the nGaN layer. A mesa is formed by cutting into the nGaN layer, with its top pGaN surface 812 being the pGaN layer, and the mesa sidewalls extending downwards to the nGaN surface. This mesa... Figure 8 As shown in the diagram. For example, etching can create a mesa with a (vertical) height of 0.5-2 micrometers (e.g., 0.5-1 micrometers) above the nGaN surface. The mesa can have vertical or non-vertical sidewalls. Once the etching is complete, the pGaN surface for forming p contacts (e.g., the surface of a p-type doped semiconductor) will be located on top of the mesa, and the nGaN surface for forming n contacts will be located below the mesa, adjacent to the mesa sidewalls.
[0050] At 720, the etched wafer surfaces are repaired, i.e., GaN repair is performed. Damage may occur on the pGaN and / or nGaN surfaces after mesa etching, especially if dry etching was used to etch the mesa. Damage may be present on the pGaN surface above the mesa, and also on the nGaN surface below the mesa. GaN repair is useful for ensuring the formation of good ohmic contacts with low resistivity at the p and n contacts. GaN repair may involve dry etching (which can be finely tuned than any dry etching used to form the mesa) to clean and / or polish the damaged pGaN / nGaN surfaces. Because this GaN repair is performed early in the process, and TCO is deposited in the next step, this allows the surfaces used to form ohmic contacts to be sealed with TCO early on, preventing subsequent steps from reacting with or further damaging these surfaces.
[0051] At 730, a TCO is deposited on the GaN surface and annealed to form an ohmic contact. The TCO can be deposited as a monolithic continuous layer or structure directly contacting the p-contact and n-contact regions (i.e., the pGaN surface on top of the mesa and the nGaN surface below and adjacent to the mesa). That is, the TCO contacting the p-contact and n-contact regions can be of the same material and thickness. For example, the material can be indium tin oxide (ITO), In₂O₃, ZnO, SnO₂, Ga₂O₃, CdO, or any other transparent conductive oxide. In this step, the TCO can be deposited over the entire surface of the etched wafer. The TCO can be a stepped structure extending down from the pGaN surface along the sidewalls of the mesa to the nGaN surface. Alternatively, the TCO may be planar on both the pGaN and nGaN surfaces. In this context, flatness may mean that the TCO has a maximum plane extending horizontally and / or parallel to the nGaN and / or pGaN surfaces; flatness may additionally or alternatively mean that the TCO has a maximum surface area away from the nGaN and / or pGaN surfaces, which does not include any steps or angular changes. After deposition, the TCO can be annealed in the p-contact and n-contact regions, thereby forming ohmic contacts in those respective regions. Simultaneous deposition and / or annealing of the TCO in the p-contact and n-contact regions can save production time and reduce the number of masks required to produce the die. Alternatively, the TCO in the p-contact and n-contact regions can be deposited in two steps instead of simultaneously in one step, and / or the TCO in the p-contact region can be or include a different material than the TCO in the n-contact region. However, even in this case, the TCO in both the p-contact and n-contact regions can be a flat layer as defined above.
[0052] At 740, the TCO can be patterned (by dry or wet etching), for example, to prevent the n-contact TCO from short-circuiting with the p-contact TCO. If the TCO is deposited as a monolithic, continuous stepped structure extending from the top to the bottom of the mesa, the TCO can be patterned by removing the stepped portion of the TCO that covers the edge of the mesa and the portion adjacent to the edge, including a portion of the pGaN surface closest to the edge, the entire sidewall of the mesa, and a portion of the nGaN surface. Once this stepped portion is removed, the p-side TCO 814 and the n-side TCO 824 are physically and electrically separated from each other. The corresponding TCOs can be planar, and the n-side TCO can be vertically positioned below the p-side TCO. The p-side TCO can extend throughout the entire p-contact region (i.e., as shown in the image). Figure 8 The metal reflector 838 shown directly contacts the p-side TCO, and the n-side TCO can extend through the entire n-contact area (i.e., as shown). Figure 8 The bonding layer 846 shown is in direct contact with the n-side TCO.
[0053] Additionally or alternatively, TCOs can be patterned so that they are removed in areas other than the aforementioned stepped portions. This patterning can be performed simultaneously with the removal of the stepped portions, thus saving production time and using fewer masks. For example, it is possible to remove what would otherwise be associated with the metal reflector 838 ( Figure 8 (As shown in the diagram) the portion of the p-side TCO in contact. When depositing the metal reflector later, it can be in direct contact with the pGaN surface, rather than having a p-side TCO in between. This improves the optical efficiency of the system while still maintaining the TCO in the surrounding area for current diffusion.
[0054] To facilitate TCO patterning, alignment marks indicating where the TCO will be patterned may have been placed during mesa etching step 710. Patterning the TCO reduces the amount of TCO in the system, improves the system's optical efficiency, and also results in lower current density near the less reflective die edges and / or n-contact areas.
[0055] At 750, a first dielectric structure 830 and a DBR are deposited. The first dielectric structure can be deposited to directly contact the TCO on the n-side and p-side, and / or to directly contact patterned openings of the TCO (e.g., exposed edges and bottoms of mesa, including portions of the pGaN and nGaN surfaces). The DBR 834 can be disposed on the first dielectric structure in a simultaneous deposition step with the first dielectric structure or in a separate deposition step. The first dielectric structure can include any dielectric, such as SiO2. x DBR can include multiple layers of dielectrics, each of which can be SiO2. x and / or TiO xThe first dielectric structure can be a thinner layer than the DBR, although this is not required. The first dielectric structure can be at least half the wavelength of light emitted by the semiconductor structure in thickness, and can be a low refractive index layer (e.g., compared to at least some layers of the DBR).
[0056] At 760, the first dielectric structure and the DBR are patterned such that the n-side TCO and p-side TCO are at least partially exposed. This patterning can be performed simultaneously in both the p-contact region and the n-contact region.
[0057] At 770, a metallic reflector 838 is deposited and stripped. The metallic reflector can be deposited in direct contact with the DBR and located in the opening created by the patterning of the first dielectric structure and the DBR, i.e., the n-contact and p-contact exposing the TCO. Once deposited, stripping can remove portions of the metallic reflector on the nGaN surface and portions of the metallic reflector on the pGaN surface, such as portions of the metallic reflector on the mesa edge and the region directly adjacent to the mesa edge. The metallic reflector can be or include one or more of silver, nickel, and palladium. For example, the metallic reflector can include one or more stacks of the aforementioned elements, such as a stack of Ag / Ni / Pd layered together. The metallic reflector can also include AlO x The layer, which is thinner than the metal in a metal reflector, is used for bonding purposes and, due to its thinness, has almost no effect on the electrical properties of the metal reflector.
[0058] At 780, a second dielectric structure 842 is deposited, and the structure is opened by removing portions of the second dielectric structure (e.g., by etching) to expose the material beneath the second dielectric structure. The second dielectric structure may be or may include pure SiO2. x Opening can be performed simultaneously on both the p-side (on the pGaN surface at the mesa) and the n-side (on the nGaN surface below the mesa), thus creating two spatially separated openings at the same time. On the n-side, this creates an opening through which the bonding layer can contact the n-side TCO, and on the p-side, this creates an opening through which the bonding layer can contact the metal reflector. Typically, opening both the p-side and n-side simultaneously can be difficult because opening both sides and the subsequent cleaning steps involved may react with the exposed material (e.g., with the nGaN surface if the TCO is absent). One solution is to open the p-side and n-side separately. This increases cost because it requires an additional masking, etching, and cleaning step. In embodiments of the invention, since the GaN repair step is completed early in the process and the repaired surface is sealed with TCO to prevent further impact, opening both the p-side and n-side simultaneously is possible, thereby reducing workflow costs.
[0059] At 790, a bonding layer 846 is deposited. The bonding layer may be a stepped structure extending downwards from the top of the second dielectric structure to the n-side TCO and may be in direct contact with the n-side TCO. The bonding layer may have two physically and electrically separated portions, one portion electrically connected to the n-side TCO and the other portion electrically connected to the p-side TCO (e.g., via a metal reflector 838). The bonding layer may be or include one or more of silver, nickel, titanium, and copper. For example, the bonding layer may include one or more stacks of the aforementioned elements, such as a stack of Ag / Ni / Ti / Cu / Ti layered together. In this case, the remainder of the process may follow a typical chip-scale package (CSP) type process.
[0060] Figure 8 A die according to an embodiment of the invention is shown. The n-side TCO 824 diffuses current at the n-contact, making it possible to have a smaller contact area of the contact metal stack (i.e., bonding layer 846). Additionally or alternatively, it is also possible to have a very thin dielectric material layer between the TCO and the bonding layer for adhesive purposes. In any case, a smaller contact area is advantageous because as the contact area decreases, it allows the DBR to have an increased area, which increases the reflectivity of the system.
[0061] The smaller size of the n-contact area also reduces the size occupied by the n-via / DBR opening, and thus reduces the gap required for the UBM, which in turn improves Rth, resulting in better LED performance at higher temperatures. Smaller n-vias enable new electrical layout designs. These new designs can increase current diffusion uniformity, which benefits LED efficiency, flux, and robustness.
[0062] Although the figure only shows one n-contact and p-contact region, the die according to embodiments of the present invention can of course have multiple n-contact and p-contact regions. For example, the die can have one or more n-side TCOs spaced apart from each other, one or more p-side TCOs spaced apart from each other, one or more bonding layers spaced apart from each other, and one or more metal reflectors spaced apart from each other. In one example, the die can have a single continuous p-side TCO in direct contact with one or more metal reflectors, and multiple n-side TCOs, each in direct contact with one or more bonding layers. That is, each of the n-side TCOs and p-side TCOs can be in direct contact with multiple or a single bonding layer and multiple or a single metal reflector, respectively. Each bonding layer can directly contact one or more n-side TCOs, with a total contact area smaller than the entire area of the corresponding bonding layer; the same is true for the metal reflectors contacting the p-side TCOs. The metal reflector / bonding layer can directly contact the p-side TCO / n-side TCO in multiple contact regions that are spaced apart from each other and discontinuous.
[0063] Figure 9 A die according to an embodiment of the present invention is shown. A metal reflector 838 extends from the pGaN surface 812 of the p-contact on the mesa to the nGaN surface 822 below the mesa. The metal reflector may extend on the n-side TCO 822, extending into the n-contact at the opening of the DBR 834, but may not extend on the n-contact itself. A portion of the metal reflector may extend horizontally to or above the edge of the mesa, and then slope downward toward the nGaN surface below the mesa. The downwardly sloped portion of the metal reflector may extend below the mesa, i.e., below the pGaN surface in the vertical direction. The metal reflector may not extend all the way to the nGaN surface.
[0064] Because the space occupied by the dielectric structure 842 may trap and / or absorb photons, extending a metal reflector in the space between the dielectric and the DBR can help reflect these photons, making them less likely to be absorbed and / or reach the quantum well. The metal reflector can be one of the most reflective elements in the die, and its extension can increase the optical efficiency of the system.
[0065] Figure 10 A die according to an embodiment of the present invention is shown. In addition to the DBR 834, a second DBR 846 can be deposited on the dielectric structure 842. This second DBR is more efficient in terms of reflectivity and therefore flux because, in this case, the second DBR is not sandwiched between the same material (i.e., two layers or structures of SiO2). The first dielectric structure 830 and the second dielectric structure 842 can be in direct contact with each other. However, they can be deposited in separate steps. In any case, they can each have a thickness for at least one wavelength of the emitted light from the die (i.e., the minimum thickness of the structure through which they are located), for example, from one wavelength to two wavelengths of the emitted light from the die (e.g., 300-600 nm for blue emitted light; 500-800 nm for red emitted light).
[0066] The disclosure provided in this specification is intended to illustrate, but not necessarily limit, the described embodiments. As used herein, the term "implementation" means an implementation that is illustrated by way of example rather than limitation. The techniques described in the foregoing text and figures may be mixed and matched as needed to produce alternative implementations. It will be apparent to those skilled in the art that many variations, changes, and substitutions can be made to the above embodiments without departing from the invention. Furthermore, it should be understood that all aspects of the invention are not limited to the specific descriptions, configurations, or relative proportions set forth herein, and are subject to various conditions and variables. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in carrying out the invention. Therefore, it is contemplated that the invention will also cover any such alternatives, modifications, variations, or equivalents. All such alternatives will be apparent to those skilled in the art based on this disclosure and are intended to fall within the scope of the appended claims.
Claims
1. A semiconductor structure, comprising: p-type doped semiconductor; One or more first transparent conductive oxide layers that directly contact the p-type doped semiconductor; One or more first metal layers in direct contact with the first transparent conductive oxide; An n-type doped semiconductor and an active layer, wherein the n-type doped semiconductor is coupled to the p-type doped semiconductor through the active layer; One or more second transparent conductive oxide layers are in direct contact with the n-type doped semiconductor; and One or more second metal layers that are in direct contact with the second transparent conductive oxide.
2. The semiconductor structure of claim 1, wherein the one or more first transparent conductive oxide layers and the one or more second transparent conductive oxide layers comprise the same material as each other.
3. The semiconductor structure according to claim 1, wherein the one or more first transparent conductive oxide layers and the one or more second transparent conductive oxide layers comprise materials different from each other.
4. The semiconductor structure according to claim 1 further includes a first dielectric structure disposed on the one or more first transparent conductive oxide layers and the one or more second transparent conductive oxide layers.
5. The semiconductor structure according to claim 4 further includes a distributed Bragg reflector (DBR) disposed on the first dielectric structure, the DBR overlapping the one or more first transparent conductive oxide layers and the one or more second transparent conductive oxide layers in the vertical direction.
6. The semiconductor structure according to claim 4, wherein the DBR is a first DBR, further comprising: A second DBR that is separated from the first DBR.
7. The semiconductor structure according to claim 4 further includes a second dielectric structure disposed on the one or more first metal layers.
8. The semiconductor structure of claim 1, wherein the one or more first metal layers comprise silver.
9. The semiconductor structure of claim 1, wherein one or more first metal layers overlap the surface of the n-type doped semiconductor.
10. The semiconductor structure of claim 1, wherein one or more first metal layers are in direct contact with the surface of the p-type doped semiconductor.
11. The semiconductor structure of claim 1, wherein the one or more second metal layers are one or more bonding layers disposed on the one or more first metal layers, the one or more bonding layers comprising at least one of Ag, Ni, Ti and Cu.
12. The semiconductor structure according to claim 1, wherein: Each of the one or more first metal layers directly contacts at least one of the one or more first transparent conductive oxide layers, and the total contact area is less than the entire area of the corresponding one of the one or more first metal layers. Each of the one or more second metal layers directly contacts at least one of the one or more second transparent conductive layers, and the total contact area is less than the entire area of the corresponding one of the one or more second metal layers.
13. The semiconductor structure according to claim 12, wherein: Each of the one or more first metal layers directly contacts the one or more first transparent conductive oxide layers in multiple contact regions that are discontinuous with each other, and Each of the one or more second metal layers directly contacts the one or more second transparent conductive oxide layers in multiple contact regions that are discontinuous with each other.
14. A method comprising: Provide semiconductor chips; The semiconductor wafer is etched to expose the surface of the n-type doped semiconductor and to form a mesa with the surface of the p-type doped semiconductor. A transparent conductive oxide structure is deposited on the n-type doped semiconductor and the p-type doped semiconductor; and The transparent conductive oxide structure is patterned to form one or more first transparent conductive oxide layers on the p-type doped semiconductor, and one or more second transparent conductive oxide layers spaced apart from the one or more first transparent conductive oxide layers are formed on the n-type doped semiconductor.
15. The method of claim 14, further comprising depositing a first dielectric structure on one or more first and second transparent conductive oxide layers.