Integrated circuit (IC) package with embedded power management integrated circuit (PMIC)

Abstract

In one aspect, an integrated circuit (IC) package includes: a package substrate, the package substrate including at least a first power node and a second power node; an interposer layer on the package substrate; and an IC die on the interposer layer. The interposer layer may include a dielectric layer and a power management integrated circuit (PMIC) embedded in the dielectric layer, wherein the PMIC includes a third power node and a fourth power node, and the third power node is electrically coupled to the first power node. The IC die may include a fifth power node and a sixth power node, wherein the fifth power node is electrically coupled to the fourth power node, and the sixth power node is electrically coupled to the second power node.

Description

Technical Field

[0001] This disclosure relates generally to an integrated circuit (IC) package, and more specifically to an IC package including an interposer having an embedded power management integrated circuit (PMIC). Background Technology

[0002] IC technology has made significant progress in improving computing power through the miniaturization of electronic components. An IC chip or IC die may include a set of circuits integrated thereon. In some specific implementations, an IC device can be formed by incorporating and protecting one or more IC dies in an IC package, wherein various power nodes and signal nodes of the one or more IC dies can be electrically coupled to corresponding conductive terminals of the IC package via electrical paths formed in one or more package substrates of the IC package.

[0003] Various packaging technologies are found in many electronic devices, including processors, servers, radio frequency (RF) ICs, and so on. Advanced packaging and processing technologies enable complex devices such as multi-die devices and system-on-a-chip (SoC) devices, which may include multiple functional blocks, each designed to perform a specific function, such as microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., Wi-Fi, Bluetooth, and other communications), etc.

[0004] For example, in a 3D IC (3DIC) packaging scheme, an interposer can be used within the IC package, on which one or more IC dies can be mounted, and the interposer can be further mounted on another IC die. The IC package can then be mounted on a circuit board (e.g., a printed circuit board, or PCB). In some examples, a power management integrated circuit (PMIC) (e.g., in the form of another IC package) can be mounted on the PCB and configured to manage one or more power distribution networks (PDNs) for supplying power to the IC dies within the IC package.

[0005] In some examples, the PMIC is configured to receive an external power supply at a higher voltage level (e.g., 5 volts (V) to 12 V) to an internal supply voltage at a lower voltage level (0.7 V to 1.0 V) for powering the IC die within the IC package (e.g., providing power for operating the IC die based on the voltage difference between the higher and lower voltage levels). However, the conductive path from the PMIC to the IC die, powered by the internal voltage supply, can cause a potential drop (also known as the IR drop) when the operating current (e.g., denoted as "I") passes through the resistance (e.g., denoted as "R") of the conductive path. This potential drop can be quite significant compared to the voltage level of the internal supply voltage.

[0006] Therefore, it may be necessary to arrange the IC die and the corresponding PMIC in order to reduce the IR voltage drop between the IC die and the PMIC. Summary of the Invention

[0007] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0008] In one aspect, an integrated circuit (IC) package includes: a package substrate including at least a first power node and a second power node; an interposer on the package substrate including a dielectric layer; a power management integrated circuit (PMIC) embedded in the dielectric layer, the PMIC including a third power node and a fourth power node, and the third power node being electrically coupled to the first power node; and an IC die on the interposer, the IC die including a fifth power node and a sixth power node, the fifth power node being electrically coupled to the fourth power node, and the sixth power node being electrically coupled to the second power node, wherein: the first power node and the third power node are configured to carry a first supply voltage having a first voltage level, the fourth power node and the fifth power node are configured to carry a second supply voltage having a second voltage level different from the first voltage level, the second power node and the sixth power node are configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first voltage level and the second voltage level, and the PMIC is configured to receive the first supply voltage at the third power node and output the second supply voltage at the fourth power node.

[0009] In one aspect, a method of manufacturing an integrated circuit (IC) package includes: disposing an interposer on a package substrate, the package substrate including at least a first power node and a second power node, and the interposer including: a dielectric layer; and a power management integrated circuit (PMIC) embedded in the dielectric layer, the PMIC including a third power node and a fourth power node, and the third power node being electrically coupled to the first power node; and disposing an IC die on the interposer, the IC die including a fifth power node and a sixth power node, the fifth power node being electrically coupled to the fourth power node, and the sixth power node being electrically coupled to the second power node, wherein: the first power node and the third power node are configured to carry a first supply voltage having a first voltage level, the fourth power node and the fifth power node are configured to carry a second supply voltage having a second voltage level different from the first voltage level, the second power node and the sixth power node are configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first voltage level and the second voltage level, and the PMIC is configured to receive the first supply voltage at the third power node and output the second supply voltage at the fourth power node.

[0010] In one aspect, an electronic device includes: an integrated circuit (IC) package, the IC package including: a package substrate including at least a first power node and a second power node; an interposer on the package substrate including: a dielectric layer; and a power management integrated circuit (PMIC) embedded in the dielectric layer, the PMIC including a third power node and a fourth power node, and the third power node being electrically coupled to the first power node; and an IC die on the interposer, the IC die including a fifth power node and a sixth power node, the fifth power node being electrically coupled to the fourth power node, and the sixth power node being electrically coupled to the second power node, wherein: the first power node and the third power node are configured to carry a first supply voltage having a first voltage level, the fourth power node and the fifth power node are configured to carry a second supply voltage having a second voltage level different from the first voltage level, the second power node and the sixth power node are configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first voltage level and the second voltage level, and the PMIC is configured to receive the first supply voltage at the third power node and output the second supply voltage at the fourth power node.

[0011] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0012] The accompanying drawings are provided to help describe various aspects of this disclosure, and are provided for illustrative purposes only and not to limit the aspects.

[0013] Figure 1A This is a cross-sectional view as part of a first circuit board assembly example according to various aspects of this disclosure.

[0014] Figure 1B This is a cross-sectional view as part of an example of a second circuit board assembly according to various aspects of this disclosure.

[0015] Figure 2 This is a cross-sectional view of a portion of an integrated circuit (IC) die according to various aspects of this disclosure.

[0016] Figure 3A This is a cross-sectional view of a first IC package example according to various aspects of this disclosure.

[0017] Figure 3B This is a cross-sectional view of a second IC package example according to various aspects of this disclosure.

[0018] Figures 4A to 4G The structures of various stages in manufacturing IC packages based on a first manufacturing process example are illustrated according to various aspects of this disclosure.

[0019] Figures 5A to 5H The structures of various stages in manufacturing IC packages based on a second manufacturing process example are illustrated according to various aspects of this disclosure.

[0020] Figure 6 Methods for manufacturing IC packages according to various aspects of this disclosure are illustrated.

[0021] Figure 7 Mobile devices according to various aspects of this disclosure are illustrated.

[0022] Figure 8 Various electronic devices that can be incorporated into IC packages as described herein are illustrated according to various aspects of this disclosure.

[0023] By convention, features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some figures in the drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0024] Various aspects of this disclosure are provided in the following description and accompanying drawings of various examples provided for illustrative purposes. Alternative aspects may be devised without departing from the scope of this disclosure. Additionally, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure the relevant details of this disclosure.

[0025] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as superior to or better than other aspects. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0026] In some of the described example implementations, instances are identified where various component structures and operational parts are derived from known conventional techniques and subsequently arranged according to one or more aspects. In such instances, internal details of known conventional component structures and / or operational parts may be omitted to help avoid potential confusion with the concepts illustrated in the exemplary aspects disclosed herein.

[0027] The terminology used herein is for descriptive purposes only and is not intended to be limiting. As used herein, the singular forms “a,” “some,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the term “comprising,” as used herein, indicates the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. Additionally, terms such as approximate and general indicate that the examples provided are not intended to be limited to precise numerical values ​​or geometries and include normal variations due to manufacturing tolerances and variations, material variations, and other design considerations.

[0028] As mentioned above, various aspects generally involve manufacturing integrated circuit (IC) packages that include an interposer layer with embedded power management integrated circuits (PMICs). Reducing the IR drop ("I" represents current and "R" represents resistance) with respect to the supply voltage can improve computing performance and reduce the power consumption of IC dies (e.g., IC dies with multiple processing cores).

[0029] Specific aspects of the subject matter described in this disclosure can be implemented to achieve one or more of the following potential advantages. In some aspects, by relying on a PMIC to provide power switching functionality for the IC die within the IC package, the IR drop caused by the supply voltage coupled vertically and vertically through the metallization of the IC die to the power switch of the IC die and then back to the power distribution network (PDN) of the IC die can be reduced or eliminated. Furthermore, by having a PMIC inside the IC package, the IR drop caused by the supply voltage coupled through the conductive path of the PCB can be eliminated. In some aspects, capacitor elements can increase the stability of the supply voltage. In some aspects, the IC package according to this application with reduced IR drop can improve the performance of the IC die (e.g., having multiple processing cores) by reducing the internal supply voltage, increasing the operating frequency, or both.

[0030] Figure 1A This is a cross-sectional view of a portion of a first circuit board assembly example 100A according to various aspects of this disclosure. In some aspects, Figure 1A This is a simplified cross-sectional view of the first circuit board assembly example 100A, and some details and components of the first circuit board assembly example 100A are available in... Figure 1A Simplified or omitted.

[0031] like Figure 1A As shown, a first circuit board assembly example 100A may include a PCB 110, an IC package 120A mounted on the PCB 110, and a PMIC (in the form of another IC package) 130 mounted on the PCB 110. In some aspects, the PCB 110 may include a conductive pattern layer (not shown) formed therein. In some aspects, the IC package 120A may be mounted on the PCB 110 via a terminal structure 122 (e.g., solder bumps based on the controlled collapse chip connection (C4) mounting method, also referred to as C4 bumps). In some aspects, the PMIC 130 may be mounted on the PCB 110 via a terminal structure 132 (e.g., C4 bumps).

[0032] In some aspects, IC package 120A may include a first package substrate 124, a first IC die 150 mounted on the first package substrate 124 via terminal structures 152 (e.g., solder bumps or copper pillar bumps), a second IC die 160 mounted on the first IC die 150 via terminal structures 162 (e.g., solder bumps or copper pillar bumps), a second package substrate 126 mounted on the first package substrate 124 via terminal structures 128 (e.g., solder bumps or copper pillar bumps together with conductive pillars), and a third IC die 180 mounted on the second package substrate 126 via terminal structures 182 (e.g., solder bumps or copper pillar bumps). In some aspects, the first IC die 150 may be a logic IC die, the second IC die may be a cache memory (e.g., last level cache (LLC) dynamic random access memory (DRAM)) die, and the third IC die 180 may be a DRAM die.

[0033] In some aspects, PMIC 130 may include a first power node configured to carry a first supply voltage (e.g., corresponding to terminal structure 132a in terminal structure 132), a second power node configured to carry a second supply voltage (e.g., corresponding to terminal structure 132b in terminal structure 132), and a third power node configured to carry a third supply voltage (e.g., corresponding to terminal structure 132c in terminal structure 132). In some aspects, the first supply voltage may have a first voltage level, the second supply voltage may have a second voltage level different from the first voltage level, and the third supply voltage may have a ground voltage level or a third voltage level different from the first and second voltage levels. In some aspects, the third supply voltage may be a ground voltage level, the second voltage level may be greater than the ground voltage level, and may be in the range of 0.7V to 1.0V. In some aspects, the first voltage level may be greater than the second voltage level, and may be in the range of 5V to 12V.

[0034] In some aspects, PMIC 130 may be configured to receive a first supply voltage at terminal structure 132a and output a second supply voltage at terminal structure 132b to terminal structure 122a in terminal structure 122 of IC package 120A via conductive path 112 formed by various conductive patterns in PCB 110. In some aspects, PMIC 130 may be configured to carry a third supply voltage at terminal structure 132c, which is also electrically shared by terminal structure 122b in terminal structure 122 of IC package 120A via conductive path 114 formed by various conductive patterns in PCB 110. In some respects, IC dies 150, 160 and 180 may be energized (e.g., provided with electrical power for operating the IC die) based on the voltage difference between a power node carrying a second supply voltage (from terminal structure 122a and at least through the corresponding conductive pattern of the first package substrate 124) and a power node carrying a third supply voltage (from terminal structure 122b and at least through the corresponding conductive pattern of the first package substrate 124).

[0035] In some aspects, the minimum distance D1 between the conductive paths 112 and 114 between the IC package 120A and the PMIC 130 can be at least 10 millimeters (mm) to 100 mm. In some aspects, the minimum distance D2 of the conductive path through one of the terminal structures in the terminal structure 122 and the first package substrate 124 can be at least 500 micrometers (µm) to 1000 µm. In some aspects, the conductive path from the PMIC 130 to the first IC die 150 can have a length at least the sum of distances D1 and D2, which may result in significant IR voltage drop and parasitic inductance along the conductive path.

[0036] Figure 1B This is a cross-sectional view of a portion of a second circuit board assembly example 100B according to various aspects of this disclosure. In some aspects, Figure 1B This is a simplified cross-sectional view of the second circuit board assembly example 100B, and some details and components of the second circuit board assembly example 100B are available in... Figure 1B Simplification or omission. In some respects, Figure 1B In and Figure 1A Components that are identical or similar to those in the figures are given the same reference numerals, and their detailed descriptions may be omitted.

[0037] like Figure 1BAs shown, the second circuit board assembly example 100B may include a PCB 110, a first IC package 120B mounted on the PCB 110, a second IC package 140 mounted on the PCB 110, and a PMIC (in the form of another IC package) 130 mounted on the PCB 110. In some aspects, the first IC package 120B may be mounted on the PCB 110 via a terminal structure 122 (e.g., a C4 bump). In some aspects, the PMIC 130 may be mounted on the PCB 110 via a terminal structure 132 (e.g., a C4 bump). In some aspects, the second IC package 140 may be mounted on the PCB 110 via a terminal structure 142 (e.g., a C4 bump).

[0038] In some aspects, the first IC package 120B may include a first package substrate 124, a first IC die 150 mounted on the first package substrate 124 via a terminal structure 152 (e.g., solder bumps or copper pillar bumps), and a second IC die 160 mounted on the first IC die 150 via a terminal structure 162 (e.g., solder bumps or copper pillar bumps). In some aspects, the second IC package 140 may include a second package substrate 144 mounted on the first package substrate 124 via a terminal structure 142, and a third IC die 180 mounted on the second package substrate 144 via a terminal structure 182 (e.g., solder bumps or copper pillar bumps). In some aspects, the first IC die 150 may be a logic IC die, the second IC die may be a cache memory (e.g., LLC DRAM) die, and the third IC die 180 may be a DRAM die.

[0039] In some aspects, PMIC 130 may include a first power node configured to carry a first supply voltage (e.g., corresponding to terminal structure 132a), a second power node configured to carry a second supply voltage (e.g., corresponding to terminal structure 132b), and a third power node configured to carry a third supply voltage (e.g., corresponding to terminal structure 132c), such as Figure 1AAs illustrated. In some aspects, PMIC 130 may be configured to receive a first supply voltage at terminal structure 132a and output a second supply voltage at terminal structure 132b to terminal structure 122a in terminal structure 122 of the first IC package 120B via conductive path 112 formed by various conductive patterns in PCB 110. In some aspects, PMIC 130 may be configured to carry a third supply voltage at terminal structure 132c, which is also electrically shared by terminal structure 122b in terminal structure 122 of the first IC package 120B via conductive path 114 formed by various conductive patterns in PCB 110. In some aspects, IC dies 150 and 160 may be energized based on the voltage difference between a power node carrying the second supply voltage (from terminal structure 122a and at least through the corresponding conductive pattern of the first package substrate 124) and a power node carrying the third supply voltage (from terminal structure 122b and at least through the corresponding conductive pattern of the first package substrate 124). In some respects, the second IC package 140 and the third IC die 180 can be configured and powered by the PMIC 130 in a manner similar to that of the first IC package 120B.

[0040] In some aspects, the minimum distance D3 of the conductive paths 112 and 114 between the first IC package 120B and the PMIC 130 can be at least 100 mm to 1000 mm. In some aspects, the minimum distance D4 of the conductive path through one of the terminal structures in the terminal structure 122 and the first package substrate 124 can be at least 500 µm to 1000 µm. In some aspects, the conductive path from the PMIC 130 to the first IC die 150 can have a length at least the sum of distances D3 and D4, which may result in significant IR voltage drop and parasitic inductance along the conductive path.

[0041] Figure 2 Based on all aspects of this disclosure Figure 1A or Figure 1B A cross-sectional view of a portion of the first IC die 150 and the corresponding terminal structure 152. In some respects, Figure 2 This is a simplified cross-sectional view of a portion of the first IC die 150, and some details and components of the first IC die 150 can be seen in... Figure 2 Simplification or omission. In some respects, Figure 2 In and Figure 1A and Figure 1B Components that are identical or similar to those in the figures are given the same reference numerals, and their detailed descriptions may be omitted. In some respects, it is assumed that... Figure 1A or Figure 1B The orientation of the first IC die 150 is defined relative to the first package substrate 124 ( Figure 2If the face not shown in the image is positioned upwards, then... Figure 2 The first IC die 150 depicted is positioned face down relative to the first package substrate 124. Of course, the orientations can be relative to each other, and are thus described in this disclosure for illustrative purposes.

[0042] In some aspects, the first IC die 150 may include a semiconductor substrate 210, a dielectric layer 220 on the semiconductor substrate 210, and a metallization structure 230 including multiple metallization layers. In some aspects, each of the metallization layers may include conductive traces and / or vias surrounded by a dielectric material. In some aspects, the first IC die 150 may also include a top metallization layer 240 on the metallization structure 230 and a passivation layer 250 on the top metallization layer 240. In some aspects, the top metallization layer 240 may include conductive pad structures 252a, 252b, 252c, and 252d. In some aspects, the first IC die 150 may also include terminal structures 152, including terminal structures 152a, 152b, 152c, and 152d on the conductive pad structures 252a, 252b, 252c, and 252d, respectively.

[0043] In some aspects, the first IC die 150 may include active devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) 262, 264, and 266. In some aspects, the terminal structure 152a may be configured to carry a supply voltage, such as a reference voltage. Figure 1A and Figure 1B The second supply voltage is described. In some aspects, MOSFET 262 may be configured as a power switch to electrically couple or decouple the supply voltage from terminal structure 152a to or from other electrical components in the first IC die 150. Therefore, in order to apply the supply voltage to an active device other than the power switch (e.g., MOSFET 262) (e.g., MOSFET 264), the supply voltage may need to be electrically coupled to MOSFET 262 via a first stack of conductive traces and vias 232, rather than via a second stack of conductive traces and vias 234 to the upper conductive pattern of the metallization structure 230 (because the PDN can be formed based on an upper conductive pattern with a low resistance per square in the first IC die 150), and then via a third stack of conductive traces and vias 236 to MOSFET 264. In some aspects, each stack of the conductive traces and vias 232, 234, and 236 may have a resistance of approximately 300 ohms.

[0044] In some respects, according to Figure 1A , Figure 1B and Figure 2The examples shown, such as circuit board assembly example 100A or circuit board assembly example 100B, may have an IR drop of approximately 10% to 15% of the voltage difference between the second and third supply voltages. In some aspects, the distances D1 and D2 or D3 and D4 of the conductive paths between the first IC die 150 and the PMIC 130 may cause an IR drop of approximately 60% to 80%; and the stacking of conductive traces and vias 232, 234, and 236 may cause an IR drop of approximately 20% to 40%.

[0045] In some respects, implementing the PDN based on the backside conductive structure can reduce a portion of the IR voltage drop caused by the stacking of conductive traces and vias 232, 234, and 236, but may still require three conductive stacks of conductive patterns to reach the power switch and then back to the PDN. In some respects, implementing the power switch near the PDN (such as on top of the metallization structure 230, at the top metallization layer 240, or as a backside active device) can help reduce the number of conductive pattern stacks required before the supply voltage reaches the active device (e.g., MOSFET 264) from three stacks to one stack in some examples. However, fabricating the active device on top of the metallization structure 230, at the top metallization layer 240, or on the backside of the semiconductor substrate 210 may correspond to increased semiconductor manufacturing complexity, which may lead to increased costs and / or reduced production yields.

[0046] In some respects, capacitor elements can be formed in the metallization structure 230 and electrically coupled to the PDN to reduce dynamic IR voltage drop (e.g., by providing stored charge for temporary current needs, rather than drawing all current from the PMIC). However, fabricating capacitor elements at the metallization structure 230 may still require increased semiconductor fabrication complexity.

[0047] In some aspects, IC dies may include multiple processing cores and can be configured to provide powerful computing capabilities while consuming significant power. In other aspects, to accommodate IR dropouts, IC dies may reduce their operating frequency to lower power consumption at the expense of reduced circuit performance. In still other aspects, to accommodate IR dropouts, IC dies may increase their internal voltage supply (e.g., Figure 1A and Figure 1B The second voltage supply illustrated in the figure increases the voltage level (from 80mV to 160mV in some cases) in order to ensure proper signal integrity at higher operating frequencies at the cost of increased power consumption or even increased heat generation.

[0048] Figure 3A This is a cross-sectional view of a first IC package example 300A according to various aspects of this disclosure. In some aspects, Figure 3AThis is a simplified cross-sectional view of a portion of the first IC package example 300A, and some details and components of the first IC package example 300A are available in... Figure 3A Simplified or omitted.

[0049] like Figure 3A As shown, the first IC package example 300A may include a package substrate 310, an interposer 320 on the package substrate 310, and an IC die 340 on the interposer 320. In some aspects, Figure 3A The orientation of the IC die 340 can be positioned face-up relative to the package substrate 310 and / or other components of the first IC package example 300A. Of course, the orientation can be defined in a relative manner and is incorporated herein for illustrative purposes.

[0050] In some aspects, the first IC package example 300A may include a molded portion 350 on a package substrate 310 and surrounding an interposer 320 and an IC die 340. In some aspects, the first IC package example 300A may also include a heat sink 360 on the IC die 340. In some aspects, the package substrate 310 may include terminal structures 312 (e.g., C4 bumps, including terminal structures 312a and 312b) formed on a lower surface of the package substrate 310. In some aspects, the terminal structures 312 may be configured to electrically couple the package substrate 310 to an external component, such as a PCB. In some aspects, the interposer 320 may be mounted on the package substrate 310 via terminal structures 322 (e.g., solder bumps, copper pillar bumps, or copper studs). In some aspects, the IC die 340 may be mounted on the interposer 320 via terminal structures 342 (e.g., solder bumps or copper pillar bumps, including terminal structures 342a to 342f). In some aspects, the underfill portion 343 may be disposed between the IC die 340 and the interposer 320 and surround the terminal structure 342. In some aspects, the molding portion 350 may extend between the interposer 320 and the package substrate 310 and surround the terminal structure 322. In some aspects, the thickness of the interposer 320 may be in the range of 30µm to 60µm.

[0051] In some aspects, the interposer 320 may include one or more conductive structures 326 (e.g., including conductive structures 326a and 326b) and a dielectric layer 324 surrounding the one or more conductive structures 326. In some aspects, the dielectric layer 324 may include a polymer material. In some aspects, the interposer 320 may include a first interposer metallization structure 328 on the side of the dielectric layer 324 facing the package substrate 310. In some aspects, the first interposer metallization structure 328 may include conductive patterns electrically coupled to terminal structures 322. In some aspects, at least a portion of the conductive patterns of the first interposer metallization structure 328 may be electrically coupled to one or more conductive structures 326. In some aspects, the interposer 320 may also include a second interposer metallization structure (not shown) on the other side of the dielectric layer 324 facing the IC die 340. In some aspects, the interposer 320 may include a PMIC 332 and a capacitor element 336 embedded in the dielectric layer.

[0052] In some aspects, the first interposer metallization structure may include at least one conductive pattern 329 beneath the PMIC 332. In some aspects, the at least one conductive pattern 329 beneath the PMIC 332 may be configured for heat dissipation of the PMIC 332.

[0053] In some aspects, based on the IC die 340 being positioned face-up relative to the package substrate 310, the IC die 340 may include a metallization portion 344 facing the interposer 320, a device portion 346 on the metallization portion 344, and a substrate portion 348 on the device portion 346. In some aspects, the metallization portion 344 may include conductive patterns, traces, and vias (e.g., including conductive patterns 345a to 345c) surrounded by a dielectric material. In some aspects, the device portion 346 may include various devices and components (e.g., transistors, diodes, resistors, capacitors, and / or inductors).

[0054] In some aspects, the package substrate 310 may include a first power node (e.g., corresponding to a terminal structure 312a and a conductive path 314 formed within the package substrate 310) and a second power node (e.g., corresponding to a terminal structure 312b and a conductive path 316 formed within the package substrate 310). In some aspects, the PMIC 332 may include a third power node (e.g., corresponding to a conductive terminal of the PMIC 332 electrically coupled to the terminal structure 342a) and a fourth power node (e.g., corresponding to a conductive terminal of the PMIC 332 electrically coupled to the terminal structure 342b). In some aspects, the IC die 340 may include a fifth power node (e.g., corresponding to a conductive pattern 345a in the metallization portion 344) and a sixth power node (e.g., corresponding to a conductive pattern 345b in the metallization portion 344). In some aspects, capacitor 336 may include a seventh power node (e.g., corresponding to a conductive terminal of capacitor 336 electrically coupled to terminal structure 342c) and an eighth power node (e.g., corresponding to a conductive terminal of capacitor 336 electrically coupled to terminal structure 342d).

[0055] In some aspects, the third power node may be electrically coupled to the first power node (and further electrically coupled to conductive path 314 and terminal structure 312a). In some aspects, the third power node may be electrically coupled to the first power node via conductive structure 326a in one or more conductive structures 326. In some aspects, the third power node may be further electrically coupled to the first power node via conductive pattern 345c of the metallization portion 344 of the IC die and terminal structures 342a and 342e.

[0056] In some aspects, the fifth power node can be electrically coupled to the fourth power node via, for example, conductive pattern 345a and terminal structure 342b. In some aspects, the sixth power node can be electrically coupled to the second power node (and further electrically coupled to conductive path 316 and terminal structure 312b) via, for example, conductive pattern 345b, terminal structure 342f and conductive structure 326b.

[0057] In some aspects, the first power node and the third power node may be configured to carry a first supply voltage having a first voltage level. In some aspects, the fourth power node and the fifth power node may be configured to carry a second supply voltage having a second voltage level different from the first voltage level. In some aspects, the second power node and the sixth power node may be configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first voltage level and the second voltage level.

[0058] In some aspects, IC die 340 may be configured to be energized based on the voltage difference between a fifth power node (carrying a second supply voltage) and a sixth power node (carrying a third supply voltage). In some aspects, PMIC 332 may include DC-DC conversion capability and may be configured to receive a first supply voltage at the third power node (and from conductive path 314 and terminal structure 312a) and output a second supply voltage at a fourth power node. In some aspects, the third supply voltage may be a ground voltage level, and the second voltage level may be greater than the ground voltage level and may be in the range of 0.7V to 1.0V. In some aspects, the first voltage level may be greater than the second voltage level and may be in the range of 5V to 12V.

[0059] In some aspects, PMIC 332 can be further configured to output a second supply voltage at the fourth power node based on PMIC 332 being in a powered-on mode, and to set the fourth power node to an open-circuit state based on PMIC 332 being in a powered-off mode. Therefore, in some aspects, IC die 340 can rely on PMIC 332 to provide a power switch (e.g., Figure 2 The functionality of MOSFET 262 in the IC package can be improved, and the IR drop caused by the supply voltage coupled vertically and vertically through the metallization portion 344 to the power switch at the device portion and then back to the PDN at the metallization portion can be reduced or eliminated in other examples. Furthermore, by connecting the PMIC 332 from outside the IC package (e.g., ...), Figure 1A and Figure 1B (The example shown) moves into the interior of the IC package (e.g., Figure 3A The example shown can eliminate the IR voltage drop caused by the supply voltage coupled through the conductive path of the PCB in other examples. In some respects, according to Figure 3A The IR drop of the second supply voltage in the example shown can be based on Figure 1A and Figure 1B The example shown has an IR drop of approximately 10% to 15% of the second supply voltage.

[0060] In some aspects, capacitor element 336 may include a deep trench capacitor structure, a metal-insulator-metal structure, a metal-oxide-metal structure, or a combination thereof. In some aspects, the seventh power node may be electrically coupled to the fourth and fifth power nodes via, for example, terminal structure 342c, conductive pattern 345a, and terminal structure 342b. In some aspects, the eighth power node may be electrically coupled to the second and sixth power nodes via, for example, terminal structure 342d, conductive pattern 345b, terminal structure 342f, and conductive structure 326b (and via conductive path 316 and terminal structure 312b). In some examples, capacitor element 336 may increase the stability of the voltage difference between the fifth and sixth power nodes.

[0061] Figure 3B This is a cross-sectional view of a second IC package example 300B according to various aspects of this disclosure. In some aspects, Figure 3B This is a simplified cross-sectional view of a portion of the second IC package example 300B, and some details and components of the second IC package example 300B are available in... Figure 3B Simplified or omitted. In some respects, the second IC package example 300B may be a variation of the first IC package example 300A, and Figure 3B In and Figure 3A Components that are identical or similar to those in the figures are given the same reference numerals, and their detailed descriptions may be simplified or omitted.

[0062] like Figure 3B As shown, the second IC package example 300B may include a package substrate 310, an interposer 320 on the package substrate 310, and an IC die 370 on the interposer 320. In some aspects, Figure 3B The orientation of the IC die 370 may be face-down relative to the package substrate 310 and / or other components of the second IC package example 300B. Of course, the orientation may be defined in a relative manner and is incorporated herein for illustrative purposes.

[0063] like Figure 3BAs shown, based on the IC die 370 being positioned face-down relative to the package substrate 310, the IC die 370 may include a substrate portion 372 facing the interposer 320, wherein the substrate portion 372 may include a back-side conductive structure 373 and conductive patterns formed therein (e.g., including conductive patterns 345a to 345c). In some aspects, the IC die 370 may include a device portion 374 on the substrate portion 372 and a metallization portion 376 on the device portion 374. In some aspects, the metallization portion 376 may include conductive patterns, traces, and vias surrounded by a dielectric material (e.g., conductive traces 377). In some aspects, the device portion 374 may include various devices and components (e.g., transistors, diodes, resistors, capacitors, and / or inductors). In some aspects, the back-side conductive structure 373 may extend through the device portion 374 and be electrically coupled to the conductive patterns of the metallization portion 376. Figure 3B As shown, the IC die 370 may also include a carrier substrate 378 on the metallized portion 376. In some aspects, the carrier substrate 378 may be omitted.

[0064] Similar to the first IC package example 300A, in some aspects, the package substrate 310 of the second IC package example 300B may include a first power node (e.g., corresponding to a terminal structure 312a and a conductive path 314 formed within the package substrate 310) and a second power node (e.g., corresponding to a terminal structure 312b and a conductive path 316 formed within the package substrate 310). In some aspects, the PMIC 332 may include a third power node (e.g., corresponding to a conductive terminal of the PMIC 332 electrically coupled to the terminal structure 342a) and a fourth power node (e.g., corresponding to a conductive terminal of the PMIC 332 electrically coupled to the terminal structure 342b). Furthermore, in some aspects, the IC die 370 may include a fifth power node (e.g., corresponding to a conductive pattern 345a in the substrate portion 372) and a sixth power node (e.g., corresponding to a conductive pattern 345b in the substrate portion 372). In some aspects, capacitor 336 may include a seventh power node (e.g., corresponding to a conductive terminal of capacitor 336 electrically coupled to terminal structure 342c) and an eighth power node (e.g., corresponding to a conductive terminal of capacitor 336 electrically coupled to terminal structure 342d).

[0065] In some respects, the electrical connections in the power node of the second IC package example 300B may be similar to the electrical connections in the power node of the first IC package example 300A, and a detailed description thereof is omitted.

[0066] In some aspects, the back-side conductive structure 373 can be used to form a PDN, and the IC die 370 can therefore have a reduced IR voltage drop between the device portion 374 and the PDN. Furthermore, in some aspects, the IC die 370 can rely on the PMIC 332 to provide a power switch (e.g., Figure 2 The functionality of MOSFET 262 in the IC is improved, and thus the IR voltage drop caused by the supply voltage of the power switch coupled vertically and vertically through the back-side conductive structure 373 to the device portion is further reduced. Furthermore, by connecting the PMIC332 from outside the IC package (e.g., ...), Figure 1A and Figure 1B (The example shown) moves into the interior of the IC package (e.g., Figure 3A The example shown can eliminate the IR voltage drop caused by the supply voltage coupled through the conductive path of the PCB in other examples. In some respects, according to Figure 3B The IR drop of the second supply voltage in the example shown can be based on Figure 1A and Figure 1B The example shown has an IR drop of approximately 10% to 15% of the second supply voltage.

[0067] In some aspects, capacitor element 336 may include a deep trench capacitor structure, a metal-insulator-metal structure, a metal-oxide-metal structure, or a combination thereof. In some aspects, the seventh power node may be electrically coupled to the fourth and fifth power nodes via, for example, terminal structure 342c, conductive pattern 345a, and terminal structure 342b. In some aspects, the eighth power node may be electrically coupled to the second and sixth power nodes via, for example, terminal structure 342dc, conductive pattern 345b, terminal structure 342f, and conductive structure 326b (and via conductive path 316 and terminal structure 312b). In some examples, capacitor element 336 may increase the stability of the voltage difference between the fifth and sixth power nodes.

[0068] Figures 4A to 4G Examples of manufacturing IC packages (such as...) based on a first manufacturing process example according to various aspects of this disclosure are illustrated. Figure 3A The structure of various stages of the first IC package example 300A. Figures 4A to 4G exemplified in Figure 3A Components that are identical or similar to those in the figures are given the same reference numerals, and their detailed descriptions may be omitted.

[0069] like Figure 4AAs shown, structure 400A can be formed by providing a PMIC 332 on a carrier substrate 412. In some aspects, structure 400A can be formed by further providing a capacitor element 336 on the carrier substrate 412. In some aspects, the carrier substrate 412 can be a glass substrate or a semiconductor substrate. In some aspects, the PMIC 332 and / or capacitor element 336 can be mounted on the carrier substrate 412 by tape or adhesive material layer. In some aspects, the conductive terminals (not shown) of the PMIC 332 and / or capacitor element 336 can be on the side of the PMIC 332 and / or capacitor element 336 that is not facing the carrier substrate 412.

[0070] like Figure 4B As shown, one or more conductive structures 326 can be formed on the carrier substrate 412 (in Figure 4B The diagram illustrates multiple conductive structures, including conductive structures 326a and 326b, to form structure 400B based on structure 400A. In some aspects, one or more conductive structures 326 may comprise a conductive material (e.g., copper, aluminum, tungsten, or combinations thereof). In some aspects, one or more conductive structures 326 may be one or more copper pillars or copper studs. In some aspects, one or more conductive structures 326 may be formed by first forming a patterned resist layer, setting copper based on a pattern defined by the patterned resist layer, and then removing the patterned resist layer. In some aspects, one or more conductive structures 326 may be formed based on a wire bonding process. In some aspects, one or more conductive structures 326 may be formed based on any other suitable process.

[0071] like Figure 4C As shown, structure 400C can be formed based on structure 400B by forming a dielectric layer 324 and a first interposer metallization structure 328 on a carrier substrate 412, wherein the dielectric layer 324 is located between the carrier substrate 412 and the first interposer metallization structure 328. In some aspects, the first interposer metallization structure 328 may include conductive patterns, and some of these conductive patterns may be electrically coupled to corresponding conductive structures in one or more conductive structures 326. In some aspects, the dielectric layer 324 may include a polymer material. In some aspects, the first interposer metallization structure 328 may be formed based on various operations including resist layer patterning, copper plating, resist layer removal, and / or dielectric deposition and robust lamination.

[0072] like Figure 4DAs shown, structure 400D can be formed based on structure 400C by separating carrier substrate 412 from an assembly including dielectric layer 324, PMIC 332, one or more conductive structures 326, first interposer metallization structure 328, and / or capacitor element 336. Structure 400D can be further formed by flipping the aforementioned assembly and placing it on a second carrier substrate 416. In some aspects, such as Figure 4D As shown, dielectric layer 324, one or more conductive structures 326, first interposer metallization structure 328, PMIC 332 and capacitor element 336 may constitute interposer layer 320.

[0073] like Figure 4D As shown, a first interposer metallization structure 328 is formed on the side of the dielectric layer 324 facing the second carrier substrate 416. In some aspects, at least one conductive pattern 329 of the first interposer metallization structure 328 may be located below the PMIC 332 and may be configured for heat dissipation of the PMIC 332. In some aspects, the interposer 320 may be further formed based on a second interposer metallization structure (not shown) formed on the other side of the dielectric layer 324 not facing the second carrier substrate 416, and may have conductive patterns that contact the conductive terminals of the PMIC 332 and / or the capacitor element 336.

[0074] like Figure 4E As shown, structure 400E can be formed based on structure 400D by providing IC die 340 on interposer layer 320. In some aspects, a plurality of terminal structures 342 (e.g., solder bumps or copper pillar bumps, including terminal structures 342a to 342f) can be formed on the underside of IC die 340, and IC die 340 can be mounted on interposer layer 320 through terminal structures 342. In some aspects, Figure 4E The IC die 340 can be positioned face up on the interposer layer 320.

[0075] In some aspects, the IC die 340 may include a metallization portion 344 facing the interposer 320, a device portion 346 on the metallization portion 344, and a substrate portion 348 on the device portion 346. In some aspects, the metallization portion 344 may include conductive patterns, traces, and vias (e.g., including conductive patterns 345a to 345c) surrounded by a dielectric material. Details regarding the various components of the IC die 340 and the interposer 320 and their electrical connections can be found in the references. Figure 3A The details of the discussion.

[0076] like Figure 4FAs shown, structure 400F can be formed based on structure 400E by providing an underfill portion 343 between IC die 340 and interposer 320 and around terminal structure 342, and separating second carrier substrate 416 from interposer 320. In some aspects, structure 400F can be further formed by forming molding portions 422 on the sidewalls of IC die 340, interposer 320, and underfill portion 343. In some aspects, the underfill portion 343 and molding portion 422 can be formed based on the same molding process. In some aspects, structure 400F can be further formed by forming terminal structure 322 (e.g., solder bump, copper pillar bump, or copper stud) on the underside of interposer 320.

[0077] like Figure 4G As shown, a structure 400G corresponding to IC package 300A can be formed. In some aspects, structure 400G can be formed based on a molding portion 350 (combined with molding portion 422) formed on package substrate 310 and surrounding interposer layer 320 and IC die 340, on which structure 400F is mounted on package substrate 310 via terminal structure 322. In some aspects, molding portion 350 may extend between interposer layer 320 and package substrate 310 and surround terminal structure 322. In some aspects, structure 400G can be further formed based on forming heat sink 360 on IC die 340. In some aspects, before or after mounting structure 400F on package substrate 310, structure 400G may include terminal structure 312 (e.g., C4 bump, including terminal structures 312a and 312b) formed on the underside of package substrate 310.

[0078] Although IC die 340 is Figures 4E to 4G The example shown is used to form such as Figure 3A The IC package 300A illustrated is a non-limiting example, but as... Figure 3B The illustrated IC die 370 can replace Figures 4E to 4G The IC die 340 is mounted on the interposer 320 for forming such a Figure 3B The illustrated IC package is 300B.

[0079] Figures 5A to 5H Examples of manufacturing IC packages (such as ICs) based on a second manufacturing process according to various aspects of this disclosure are illustrated. Figure 3A The structure of various stages of the first IC package example 300A. Figures 5A to 5H exemplified in Figure 3A Components that are identical or similar to those in the figures are given the same reference numerals, and their detailed descriptions may be omitted.

[0080] like Figure 5AAs shown, structure 500A can be formed by disposed of IC die 340 on carrier substrate 512. In some aspects, carrier substrate 512 may be a glass substrate or a semiconductor substrate. In some aspects, IC die 340 may include a metallization portion 344, a device portion 346, and a substrate portion 348. In some aspects, metallization portion 344 may include conductive patterns, traces, and vias (e.g., including conductive patterns 345a to 345c) surrounded by a dielectric material. Details regarding the various components of IC die 340 can be found in the reference. Figure 3A The details of the discussion. In some respects, Figure 5A The IC die 340 can be positioned face down on the carrier substrate 512.

[0081] In some aspects, structure 500A may also include a plurality of terminal structures 342 on IC die 340 (e.g., solder bumps or copper pillar bumps, including terminal structures 342a to 342f). In some aspects, terminal structures 342 may be formed on IC die 340 before or after IC die 340 is mounted on carrier substrate 512.

[0082] like Figure 5B As shown, it can be achieved by using IC die 340 (in Figure 5B In this configuration, IC die 340 is positioned face down on the underside of the terminal structure 342, and a bottom fill portion 343 is provided around the terminal structure 342 to form structure 500B. In some aspects, the bottom fill portion 343 can be formed by forming a molding material layer on the underside of IC die 340 and meshing the molding material layer to expose the terminal structure 342.

[0083] like Figure 5C As shown, one or more conductive structures 326 can be formed on the bottom filling portion 343 and the terminal structure 342 (in Figure 5C The diagram illustrates multiple conductive structures, including conductive structures 326a and 326b, to form structure 500C based on structure 500B, and the multiple conductive structures are electrically coupled to terminal structure 342. In some aspects, one or more conductive structures 326 may comprise a conductive material (e.g., copper, aluminum, tungsten, or combinations thereof). In some aspects, one or more conductive structures 326 may be one or more copper pillars or copper studs. In some aspects, one or more conductive structures 326 may be formed based on first forming a patterned resist layer, setting copper based on a pattern defined by the patterned resist layer, and then removing the patterned resist layer. In some aspects, one or more conductive structures 326 may be formed based on a wire bonding process. In some aspects, one or more conductive structures 326 may be formed based on any other suitable process.

[0084] In some aspects, prior to forming one or more conductive structures 326, an intermediate metallization layer (not shown) may be formed on the bottom fill portion 343 and the terminal structure 342, and then one or more conductive structures 326 may be disposed on the intermediate metallization layer.

[0085] like Figure 5D As shown, structure 500D can be formed based on structure 500C by providing PMIC 332 on the bottom fill portion 343 and terminal structure 342 (or on the interposer metallization layer, if applicable). In some aspects, structure 500D can be formed by further providing capacitor element 336 on the bottom fill portion 343 and terminal structure 342 (or on the interposer metallization layer, if applicable). In some aspects, PMIC 332 and / or capacitor element 336 may include conductive terminals (not shown) facing IC die 340, and PMIC 332 and / or capacitor element 336 can be mounted on IC die 340 by directly connecting the conductive terminals of PMIC 332 and / or capacitor element 336 to terminal structure 342 without interposer metallization layer, or indirectly connecting to terminal structure through interposer metallization layer when interposer metallization layer is formed.

[0086] like Figure 5E As shown, structure 500E can be formed based on structure 500D by forming a dielectric layer 324 on the bottom fill portion 343 (or on an interposer metallization layer where the PMIC 332 and / or capacitor element 336 are disposed, if available) and forming another interposer metallization structure 328 on the dielectric layer 324. In some aspects, the interposer metallization structure 328 may include conductive patterns, and some of these conductive patterns may be electrically coupled to corresponding conductive structures in one or more conductive structures 326. In some aspects, the dielectric layer 324 may include a polymer material. In some aspects, the interposer metallization structure 328 may be formed based on various operations including resist layer patterning, copper plating, resist layer removal, and / or dielectric deposition and robust lamination.

[0087] In some aspects, such as Figure 5E As shown, dielectric layer 324, one or more conductive structures 326, interposer metallization structure 328, PMIC 332 and capacitor element 336 may constitute interposer layer 320.

[0088] like Figure 5FAs shown, structure 500F can be formed based on structure 500E by forming terminal structures 322 (e.g., solder bumps, copper pillar bumps, or copper studs) on the underside of the interposer 320, and the terminal structures are electrically coupled to the interposer metallization structure 328 of the interposer 320. In some aspects, structure 500F can be further formed based on a molding portion 350 formed on the carrier substrate 512 and surrounding the interposer 320 and the IC die 340. In some aspects, the molding portion 350 may surround the terminal structure 322.

[0089] like Figure 5G As shown, structure 500G can be formed based on structure 500F by providing packaging substrate 310 on structure 500F. In some aspects, before or after mounting packaging substrate 310 on structure 500F, structure 500G may include terminal structures 312 (e.g., C4 bumps, including terminal structures 312a and 312b) formed on the underside of packaging substrate 310.

[0090] like Figure 5H As shown, a structure 500H corresponding to the IC package 300A can be formed. In some aspects, the structure 500H can be formed by separating the carrier substrate 512 from the molding portion 350 and the IC die 340. In some aspects, the structure 500H can be further formed by forming a heat sink 360 on the IC die 340 (on the side opposite to the interposer 320 and the package substrate 310).

[0091] Although IC die 340 is Figures 5A to 5H The example shown is used to form such as Figure 3A The IC package 300A illustrated is a non-limiting example, but as... Figure 3B The illustrated IC die 370 can replace Figures 5A to 5H The IC die 340 is mounted on the interposer 320 for forming such a Figure 3B The illustrated IC package is 300B.

[0092] Figure 6 Examples of methods for manufacturing IC packages (such as) according to various aspects of this disclosure are illustrated. Figure 3A Example of the first IC package 300A Figure 3B Example 300B of the second IC package Figure 4G The structure in 400G and / or Figure 5H The method 600 (structure 500H) in the middle. In some aspects, Figures 4A to 4G and Figures 5A to 5H The structure of IC packages at various stages of manufacturing according to method 600 can be described.

[0093] At operation 610, an interposer (e.g., interposer 320) may be disposed on a package substrate (e.g., package substrate 310). In some aspects, the package substrate may include at least a first power node (e.g., corresponding to terminal structure 312a) and a second power node (e.g., corresponding to terminal structure 312b). In some aspects, the interposer may include a dielectric layer (e.g., dielectric layer 324) and a PMIC (e.g., PMIC 332) embedded in the dielectric layer. In some aspects, the PMIC may include a third power node (e.g., corresponding to a contact terminal coupled to terminal structure 342a) and a fourth power node (e.g., corresponding to a contact terminal coupled to terminal structure 342b). In some aspects, the third power node may be electrically coupled to the first power node. In some aspects, the thickness of the interposer may be in the range of 30µm to 60µm.

[0094] At operation 620, an IC die (e.g., IC die 340 or IC die 370) may be disposed on the interposer. In some aspects, the IC die may include a fifth power node (e.g., corresponding to conductive pattern 345a) and a sixth power node (e.g., corresponding to conductive pattern 345b). In some aspects, the IC die may be configured to be energized at least based on the voltage difference between the fifth and sixth power nodes. In some aspects, the fifth power node may be electrically coupled to a fourth power node. In some aspects, the sixth power node may be electrically coupled to a second power node.

[0095] In some aspects, the first power node and the third power node may be configured to carry a first supply voltage having a first voltage level. In some aspects, the fourth power node and the fifth power node may be configured to carry a second supply voltage having a second voltage level different from the first voltage level. In some aspects, the second power node and the sixth power node may be configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first voltage level and the second voltage level.

[0096] In some aspects, the third supply voltage may be the ground voltage level, and the second voltage level may be greater than the ground voltage level and may be in the range of 0.7V to 1.0V. In some aspects, the first voltage level may be greater than the second voltage level and may be in the range of 5V to 12V. In some aspects, the PMIC may be configured to receive the first supply voltage at the third power node and output the second supply voltage at the fourth power node.

[0097] In some aspects, such as Figures 4A to 4CAs illustrated, method 600 may further include forming an interposer, including: disposing a PMIC on a carrier substrate (e.g., carrier substrate 412), forming one or more conductive structures (e.g., one or more conductive structures 326) on the carrier substrate, and forming a dielectric layer on the carrier substrate. In some aspects, the dielectric layer may cover the PMIC and may surround the one or more conductive structures. In some aspects, forming the interposer may further include separating the carrier substrate from the dielectric layer, the PMIC, and the one or more conductive structures.

[0098] In some aspects, such as Figures 5C to 5E As illustrated, the placement of an IC die on an interposer can be based on forming one or more conductive structures (e.g., one or more conductive structures 326) on one side of the IC die, placing a PMIC on one side of the IC die, forming a dielectric layer on the IC die, and forming an interposer metallization structure (e.g., interposer metallization structure 328) on the dielectric layer, such that the dielectric layer is between the interposer metallization structure and the IC die. In some aspects, the dielectric layer may cover the PMIC and surround one or more conductive structures.

[0099] In some respects, based on Figures 4A to 4G or Figures 5A to 5H Forming an interposer may include forming one or more conductive structures (e.g., one or more conductive structures 326) within the interposer, wherein a dielectric layer may surround one or more conductive structures. In some aspects, a third power node may be electrically coupled to a first power node via a first conductive structure (e.g., conductive structure 326a) in one or more conductive structures.

[0100] In some aspects, forming the interposer layer may also include providing capacitor elements (e.g., capacitor element 336) embedded in the dielectric layer. In some aspects, the capacitor element includes a seventh power node (e.g., corresponding to a contact terminal coupled to terminal structure 342c) and an eighth power node (e.g., corresponding to a contact terminal coupled to terminal structure 342d). In some aspects, the seventh power node may be electrically coupled to a fourth power node and a fifth power node. In some aspects, the eighth power node may be electrically coupled to a second power node and a sixth power node.

[0101] In some aspects, forming an interposer may include forming a first interposer metallization structure on one side of a dielectric layer on one side, forming a second interposer metallization structure on the other side of a dielectric layer on the other side, or a combination thereof.

[0102] The technical advantages of method 600 correspond to the manufacture of IC packages including an interposer with an embedded PMIC. In some aspects, by relying on the PMIC to provide power switching functionality for the IC die within the IC package, the IR drop caused by the supply voltage coupled vertically and horizontally through the metallization of the IC die to the power switch of the IC die and then back to the PDN of the IC die can be reduced or eliminated. Furthermore, by having the PMIC inside the IC package, the IR drop caused by the supply voltage coupled through the conductive path of the PCB can be eliminated. In some aspects, capacitors can increase the stability of the supply voltage.

[0103] Figure 7 A mobile device 700 according to various aspects of this disclosure is illustrated. In some aspects, the mobile device 700 may be implemented by including one or more IC devices, which include an intermediary layer having an embedded PMIC, as disclosed herein.

[0104] In some aspects, the mobile device 700 can be configured as a wireless communication device. As shown, the mobile device 700 includes a processor 701. The processor 701 is communicatively coupled to a memory 732 via a link, which can be a die-to-die or chip-to-chip link. The mobile device 700 also includes a display 728 and a display controller 726, wherein the display controller 726 is coupled to the processor 701 and the display 728. The mobile device 700 may include an input device 730 (e.g., a physical or virtual keyboard), a power supply 744 (e.g., a battery), a speaker 736, a microphone 738, and a wireless antenna 742. In some aspects, the power supply 744 may directly or indirectly provide the power supply voltage for some or all of the components of the mobile device 700.

[0105] In some respects, Figure 7 It may include a decoder / decoder (codec) 734 (e.g., an audio and / or voice codec) coupled to the processor 701; a speaker 736 and a microphone 738 coupled to the codec 734; and a wireless circuit 740 (which may include a modem, RF circuitry, filters, etc.) coupled to the wireless antenna 742 and the processor 701.

[0106] In some aspects, one or more of the processor 701 (e.g., SoC, application processor (AP)), display controller 726, memory 732, codec 734, and wireless circuit 740 (e.g., baseband interface) include an IC device packaged as an IC package and include an intermediary layer with an embedded PMIC according to the various aspects described in this disclosure.

[0107] It should be pointed out that, although Figure 7Mobile device 700 is described, but similar architectures can be used to implement devices including set-top boxes, music players, video players, entertainment units, navigation devices, personal digital assistants (PDAs), fixed location data units, computers, laptops, tablets, communication devices, mobile phones, or other similar devices.

[0108] Figure 8 Various electronic devices 810, 820 and 830 that can be incorporated with IC devices 812, 822 and 832 according to various aspects of this disclosure are illustrated, and these IC devices can be housed in IC packages as described herein.

[0109] For example, mobile phone device 810, laptop computer device 820, and fixed-location terminal device 830 can each generally be considered as user equipment (UE) and may include one or more IC devices (such as IC devices 812, 822, and 832) and a power supply for providing a supply voltage to power the IC devices. IC devices 812, 822, and 832 may, for example, correspond to IC devices packaged as IC packages having, based on the above references Figure 2 and Figure 3A The intermediate layer is fabricated as shown in the example in Figure 3E.

[0110] Figure 8 The devices 810, 820, and 830 illustrated herein are merely non-limiting examples. Other electronic devices may also feature ICs including semiconductor structures as described in this disclosure, including, but not limited to, a group of devices (e.g., electronic devices): mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed-location data units (such as instrument reading devices), communication devices, smartphones, tablet computers, computers, wearable devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), Internet of Things (IoT) devices, laptop computers, access points, base stations, or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0111] It should be understood that the various aspects disclosed herein can be described as functional equivalents of structures, materials, and / or devices as described and / or understood by those skilled in the art. For example, in one aspect, the apparatus may include components for performing the various functions discussed above. It should be understood that the foregoing aspects are provided by way of example only, and the claimed aspects are not limited to the specific references and / or illustrations cited as examples.

[0112] Figure 1 to Figure 8One or more of the components, processes, features, and / or functions illustrated herein may be rearranged and / or combined into a single component, process, feature, or function, or incorporated into several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. In some specific embodiments, Figures 1 to... Figure 8 The corresponding descriptions can be used to manufacture, create, provide, and / or produce integrated devices. In some specific implementations, the devices may include dies, integrated devices, die packages, ICs, device packages, IC packages, wafers, semiconductor devices, system-in-package (SiP), system-on-a-chip (SoC), and stacked-package (PoP) devices, etc.

[0113] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features than those explicitly mentioned in each clause. Rather, the various aspects of this disclosure may include fewer features than those in the individual example clauses disclosed. Therefore, the following clauses should be regarded accordingly as incorporated into the description, where each clause may serve as a separate example. Although each dependent clause may refer in the clause to a specific combination with one of the other clauses, the aspect of that dependent clause is not limited to that specific combination. It should be understood that other example clauses may also include combinations of aspects of a dependent clause with the subject matter of any other dependent or independent clause, or combinations of any feature with other dependent and independent clauses. The various aspects disclosed herein explicitly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of a clause may be included in any other independent clause, even if that clause does not directly depend on the independent clause.

[0114] Specific implementation examples are described in the following numbered clauses.

[0115] Clause 1. An integrated circuit (IC) package, the IC package comprising: a package substrate, the package substrate including at least a first power node and a second power node; an interposer on the package substrate, the interposer including: a dielectric layer; and a power management integrated circuit (PMIC) embedded in the dielectric layer, the PMIC including a third power node and a fourth power node, and the third power node being electrically coupled to the first power node; and an IC die on the interposer, the IC die including a fifth power node and a sixth power node, the fifth power node being electrically coupled to the fourth power node, and the... The sixth power node is electrically coupled to the second power node, wherein: the first power node and the third power node are configured to carry a first supply voltage having a first voltage level; the fourth power node and the fifth power node are configured to carry a second supply voltage having a second voltage level different from the first voltage level; the second power node and the sixth power node are configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first voltage level and the second voltage level; and the PMIC is configured to receive the first supply voltage at the third power node and output the second supply voltage at the fourth power node.

[0116] Clause 2. The IC package according to Clause 1, wherein: the PMIC is further configured to output the second supply voltage at the fourth power node based on the PMIC being in a power-on mode, and to set the fourth power node to an open circuit state based on the PMIC being in a power-off mode.

[0117] Clause 3. An IC package according to any one of Clauses 1 to 2, wherein: the interposer further comprises one or more conductive structures, the dielectric layer surrounds the one or more conductive structures, and the third power node is electrically coupled to the first power node through a first conductive structure of the one or more conductive structures.

[0118] Clause 4. The IC package as described in Clause 3, wherein: each of the one or more conductive structures comprises a copper stud.

[0119] Clause 5. An IC package according to any one of Clauses 1 to 4, wherein the interposer further comprises: a first interposer metallization structure on the side of the dielectric layer facing the package substrate, a second interposer metallization structure on the other side of the dielectric layer facing the IC die, or a combination thereof.

[0120] Clause 6. The IC package as described in Clause 5, wherein: the first interposer metallization structure includes at least one conductive pattern beneath the PMIC.

[0121] Clause 7. The IC package according to Clause 6, wherein the at least one conductive pattern beneath the PMIC is configured for heat dissipation of the PMIC.

[0122] Clause 8. An IC package according to any one of Clauses 1 to 7, wherein the dielectric layer comprises a polymer material.

[0123] Clause 9. An IC package according to any one of Clauses 1 to 8, wherein: the interposer further comprises a capacitor element, the capacitor element comprising a seventh power node and an eighth power node, the seventh power node being electrically coupled to the fourth power node and the fifth power node, and the eighth power node being electrically coupled to the second power node and the sixth power node.

[0124] Clause 10. The IC package as described in Clause 9, wherein the capacitor element includes: a deep trench capacitor structure, a metal-insulator-metal structure, a metal-oxide-metal structure, or a combination thereof.

[0125] Clause 11. An IC package according to any one of Clauses 1 to 10, wherein the IC die: is positioned face-up relative to the package substrate, comprising a metallized portion facing the interposer, a device portion on the metallized portion, and a substrate portion on the device portion; or is positioned face-down relative to the package substrate, comprising a substrate portion facing the interposer and including a back-side conductive structure formed therein, a device portion on the substrate portion, and a metallized portion on the device portion.

[0126] Clause 12. The IC package according to Clause 11, wherein: the third power node is electrically coupled to the first power node through a conductive pattern of the metallized portion of the IC die, a portion of the back-side conductive structure, or a combination thereof.

[0127] Clause 13. An IC package according to any one of Clauses 1 to 12, wherein the thickness of the interposer is in the range of 30 micrometers (µm) to 60 µm.

[0128] Clause 14. A method of manufacturing an integrated circuit (IC) package, the method comprising: disposing an interposer on a package substrate, the package substrate including at least a first power node and a second power node, and the interposer including: a dielectric layer; and a power management integrated circuit (PMIC) embedded in the dielectric layer, the PMIC including a third power node and a fourth power node, and the third power node being electrically coupled to the first power node; and disposing an IC die on the interposer, the IC die including a fifth power node and a sixth power node, the fifth power node being electrically coupled to the fourth power node, and the third power node being electrically coupled to the first power node; and disposing an IC die on the interposer, the IC die including a fifth power node and a sixth power node, the fifth power node being electrically coupled to the fourth power node, and the third power node being electrically coupled to the first power node; and disposing an IC die on the interposer layer ... Six power nodes are electrically coupled to the second power node, wherein: the first power node and the third power node are configured to carry a first supply voltage having a first voltage level; the fourth power node and the fifth power node are configured to carry a second supply voltage having a second voltage level different from the first voltage level; the second power node and the sixth power node are configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first voltage level and the second voltage level; and the PMIC is configured to receive the first supply voltage at the third power node and output the second supply voltage at the fourth power node.

[0129] Clause 15. The method according to Clause 14, the method further comprising forming the interposer layer, comprising: disposing the PMIC on a carrier substrate; forming one or more conductive structures on the carrier substrate; forming the dielectric layer on the carrier substrate, the dielectric layer covering the PMIC and surrounding the one or more conductive structures; and separating the carrier substrate from the dielectric layer, the PMIC and the one or more conductive structures.

[0130] Clause 16. The method according to Clause 14, wherein the IC die is disposed on the interposer based on the interposer being formed on one side of the IC die, comprising: forming one or more conductive structures on the one side of the IC die; disposing the PMIC on the one side of the IC die; forming the dielectric layer on the one side of the IC die, the dielectric layer covering the PMIC and surrounding the one or more conductive structures; and forming an interposer metallization structure on the dielectric layer such that the dielectric layer is between the interposer metallization structure and the IC die.

[0131] Clause 17. The method according to any one of Clauses 14 to 16, the method further comprising forming the interposer layer, comprising: forming one or more conductive structures in the interposer layer, the dielectric layer surrounding the one or more conductive structures, wherein the third power node is electrically coupled to the first power node through a first conductive structure in the one or more conductive structures.

[0132] Clause 18. The method according to any one of Clauses 14 to 17, the method further comprising forming the interposer layer, including: forming a first interposer metallization structure on the side of the dielectric layer facing the package substrate, forming a second interposer metallization structure on the other side of the dielectric layer facing the IC die, or a combination thereof.

[0133] Clause 19. The method according to Clause 18, wherein: the first interposer metallization structure includes at least one conductive pattern beneath the PMIC.

[0134] Clause 20. The method according to any one of Clauses 14 to 19, the method further comprising forming the interposer layer, comprising: providing a capacitor element embedded in the dielectric layer, the capacitor element including a seventh power node and an eighth power node, wherein: the seventh power node is electrically coupled to the fourth power node and the fifth power node, and the eighth power node is electrically coupled to the second power node and the sixth power node.

[0135] Clause 21. The method according to any one of Clauses 14 to 20, wherein the thickness of the interlayer is in the range of 30 micrometers (µm) to 60 µm.

[0136] Clause 22. An electronic device comprising: an integrated circuit (IC) package, the IC package comprising: a package substrate, the package substrate including at least a first power node and a second power node; an interposer layer on the package substrate, the interposer layer including: a dielectric layer; and a power management integrated circuit (PMIC) embedded in the dielectric layer, the PMIC including a third power node and a fourth power node, and the third power node being electrically coupled to the first power node; and an IC die on the interposer layer, the IC die including a fifth power node and a sixth power node, the fifth power node being electrically coupled to the fourth power node. The first and third power nodes are configured to carry a first supply voltage having a first voltage level, the fourth and fifth power nodes are configured to carry a second supply voltage having a second voltage level different from the first voltage level, the second and sixth power nodes are configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first and second voltage levels, and the PMIC is configured to receive the first supply voltage at the third power node and output the second supply voltage at the fourth power node.

[0137] Clause 23. The electronic device according to Clause 22, wherein: the PMIC is further configured to output the second supply voltage at the fourth power node based on the PMIC being in a power-on mode, and to set the fourth power node to an open circuit state based on the PMIC being in a power-off mode.

[0138] Clause 24. An electronic device according to any one of Clauses 22 to 23, wherein: the interposer further comprises one or more conductive structures, the dielectric layer surrounds the one or more conductive structures, and the third power node is electrically coupled to the first power node through a first conductive structure of the one or more conductive structures.

[0139] Clause 25. An electronic device according to any one of Clauses 22 to 24, wherein the interposer further comprises: a first interposer metallization structure on the side of the dielectric layer facing the package substrate, a second interposer metallization structure on the other side of the dielectric layer facing the IC die, or a combination thereof.

[0140] Clause 26. The electronic device according to Clause 25, wherein: the first interposer metallization structure includes at least one conductive pattern beneath the PMIC.

[0141] Clause 27. An electronic device according to any one of Clauses 22 to 26, wherein: the interposer further comprises a capacitor element, the capacitor element comprising a seventh power node and an eighth power node, the seventh power node being electrically coupled to the fourth power node and the fifth power node, and the eighth power node being electrically coupled to the second power node and the sixth power node.

[0142] Clause 28. An electronic device according to any one of Clauses 22 to 27, wherein the IC: is positioned face-up relative to the package substrate based on the IC die, including a metallized portion facing the interposer, a device portion on the metallized portion, and a substrate portion on the device portion; or is positioned face-down relative to the package substrate based on the IC die, including a substrate portion facing the interposer and including a back-side conductive structure formed therein, a device portion on the substrate portion, and a metallized portion on the device portion.

[0143] Clause 29. An electronic device according to any one of Clauses 22 to 28, wherein the thickness of the interposer is in the range of 30 micrometers (µm) to 60 µm.

[0144] Clause 30. An electronic device pursuant to any one of Clauses 22 to 29, wherein the electronic device includes at least one of the following: a music player, a video player, an entertainment unit; a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, or a device in a motor vehicle.

[0145] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0146] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0147] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using general-purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic elements, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but in alternatives, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0148] The methods, sequences, and / or algorithms described in conjunction with the aspects disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or a combination of both. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art. Example storage media are coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a user terminal (e.g., a UE). Alternatively, the processor and storage medium may reside as discrete components in the user terminal.

[0149] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. A computer-readable medium includes both computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. A storage medium may be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and is accessible to a computer. Furthermore, any connection is appropriately referred to as a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included within the definition of a medium. As used herein, disks and optical discs include: compact optical discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs. Disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0150] Furthermore, as used herein, the terms “set,” “group,” etc., are intended to include one or more of the stated elements. Additionally, as used herein, the terms “having,” “comprising,” “including,” etc., do not exclude the presence of one or more additional elements (e.g., element “having” A may also have B). Furthermore, the phrase “based on” is intended to mean “at least partially based on” unless otherwise explicitly stated. Moreover, as used herein, the term “or” is intended to be open-ended when used in a series and may be used interchangeably with “and / or” unless otherwise explicitly stated (e.g., if used in conjunction with “any” or “only one”), or these alternatives are mutually exclusive (e.g., “one or more” should not be interpreted as “one and more”). Furthermore, although components, functions, actions, and instructions may be described or claimed in the singular form, the plural form may also be considered unless explicitly stated to be limited to the singular. Therefore, as used herein, the articles “a,” “an,” “the,” and “described” are intended to include one or more of the stated elements. Additionally, as used herein, the terms “at least one” and “one or more” include performing or being able to perform “one” component, function, action or instruction of the described or claimed functionality, and also include performing or being able to perform “two or more” components, functions, actions or instructions of the described or claimed functionality in combination.

[0151] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. For example, the functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, no component, function, action, or instruction described or claimed herein should be construed as critical or essential unless explicitly described so.

Claims

1. An integrated circuit (IC) package, the integrated circuit (IC) package comprising: A packaging substrate, wherein the packaging substrate includes at least a first power node and a second power node; The interposer layer on the packaging substrate, the interposer layer comprising: Dielectric layer; and A power management integrated circuit (PMIC) embedded in the dielectric layer, the PMIC including a third power node and a fourth power node, the third power node being electrically coupled to the first power node; and The IC die on the interposer layer includes a fifth power node and a sixth power node, the fifth power node being electrically coupled to the fourth power node, and the sixth power node being electrically coupled to the second power node. in: The first power node and the third power node are configured to carry a first supply voltage having a first voltage level. The fourth power node and the fifth power node are configured to carry a second supply voltage having a second voltage level different from the first voltage level. The second power node and the sixth power node are configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first voltage level and the second voltage level, and The PMIC is configured to receive the first supply voltage at the third power node and output the second supply voltage at the fourth power node.

2. The IC package according to claim 1, wherein: The PMIC is further configured to output the second supply voltage at the fourth power node based on the PMIC being in a power-on mode, and to set the fourth power node to an open circuit state based on the PMIC being in a power-off mode.

3. The IC package according to claim 1, wherein: The interposer layer further includes one or more conductive structures, and the dielectric layer surrounds the one or more conductive structures. The third power node is electrically coupled to the first power node through the first conductive structure in one or more conductive structures.

4. The IC package according to claim 1, wherein the interposer layer further comprises: The first interposer metallization structure on the side of the dielectric layer facing the packaging substrate, The second interposer metallization structure on the other side of the dielectric layer facing the IC die, or Their combination.

5. The IC package according to claim 4, wherein: The first interposer metallization structure includes at least one conductive pattern beneath the PMIC.

6. The IC package according to claim 1, wherein: The interposer layer also includes capacitor components, which include a seventh power node and an eighth power node. The seventh power node is electrically coupled to the fourth power node and the fifth power node, and The eighth power node is electrically coupled to the second power node and the sixth power node.

7. The IC package of claim 6, wherein the capacitor comprises: Deep trench capacitor structure, Metal-insulator-metal structure Metal-oxide-metal structure, or Their combination.

8. The IC package according to claim 1, wherein the IC die: Based on the IC die being positioned face-up relative to the packaging substrate, it includes a metallized portion facing the interposer, a device portion on the metallized portion, and a substrate portion on the device portion; or Based on the IC die being positioned face-down relative to the packaging substrate, the substrate portion includes the substrate portion facing the interposer and including a back-side conductive structure formed therein, the device portion on the substrate portion, and the metallization portion on the device portion.

9. The IC package according to claim 8, wherein: The third power node is electrically coupled to the first power node via the conductive pattern of the metallized portion of the IC die, a portion of the back-side conductive structure, or a combination thereof.

10. The IC package of claim 1, wherein the thickness of the interposer is in the range of 30 micrometers (µm) to 60 µm.

11. A method for manufacturing an integrated circuit (IC) package, the method comprising: An interposer layer is disposed on a packaging substrate, the packaging substrate including at least a first power node and a second power node, and the interposer layer comprising: Dielectric layer; and A power management integrated circuit (PMIC) embedded in the dielectric layer, the PMIC including a third power node and a fourth power node, the third power node being electrically coupled to the first power node; and An IC die is disposed on the interposer layer. The IC die includes a fifth power node and a sixth power node. The fifth power node is electrically coupled to the fourth power node, and the sixth power node is electrically coupled to the second power node. in: The first power node and the third power node are configured to carry a first supply voltage having a first voltage level. The fourth power node and the fifth power node are configured to carry a second supply voltage having a second voltage level different from the first voltage level. The second power node and the sixth power node are configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first voltage level and the second voltage level, and The PMIC is configured to receive the first supply voltage at the third power node and output the second supply voltage at the fourth power node.

12. The method of claim 11, further comprising forming the intermediary layer, including: The PMIC is disposed on a carrier substrate; One or more conductive structures are formed on the carrier substrate; The dielectric layer is formed on the carrier substrate, the dielectric layer covering the PMIC and surrounding the one or more conductive structures; as well as The carrier substrate is separated from the dielectric layer, the PMIC, and the one or more conductive structures.

13. The method of claim 11, wherein the IC die is disposed on the interposer layer based on the interposer layer being formed on one side of the IC die, comprising: One or more conductive structures are formed on one side of the IC die; The PMIC is disposed on one side of the IC die; The dielectric layer is formed on one side of the IC die, the dielectric layer covering the PMIC and surrounding the one or more conductive structures; as well as An interlayer metallization structure is formed on the dielectric layer, such that the dielectric layer is between the interlayer metallization structure and the IC die.

14. The method of claim 11, further comprising forming the intermediary layer, including: One or more conductive structures are formed in the intermediate layer, and the dielectric layer surrounds the one or more conductive structures. The third power node is electrically coupled to the first power node through a first conductive structure in one or more conductive structures.

15. The method of claim 11, further comprising forming the intermediary layer, including: A first interposer metallization structure is formed on the side of the dielectric layer facing the packaging substrate. A second interposer metallization structure is formed on the other side of the dielectric layer facing the IC die, or Their combination.

16. The method of claim 11, further comprising forming the intermediary layer, including: A capacitor element is embedded in the dielectric layer, the capacitor element including a seventh power node and an eighth power node. in: The seventh power node is electrically coupled to the fourth power node and the fifth power node, and The eighth power node is electrically coupled to the second power node and the sixth power node.

17. An electronic device, the electronic device comprising: An integrated circuit (IC) package, the integrated circuit (IC) package comprising: A packaging substrate, wherein the packaging substrate includes at least a first power node and a second power node; The interposer layer on the packaging substrate, the interposer layer comprising: Dielectric layer; and A power management integrated circuit (PMIC) embedded in the dielectric layer, the PMIC including a third power node and a fourth power node, the third power node being electrically coupled to the first power node; and The IC die on the interposer layer includes a fifth power node and a sixth power node, the fifth power node being electrically coupled to the fourth power node, and the sixth power node being electrically coupled to the second power node. in: The first power node and the third power node are configured to carry a first supply voltage having a first voltage level. The fourth power node and the fifth power node are configured to carry a second supply voltage having a second voltage level different from the first voltage level. The second power node and the sixth power node are configured to carry a third supply voltage having a ground voltage level or a third voltage level different from the first voltage level and the second voltage level, and The PMIC is configured to receive the first supply voltage at the third power node and output the second supply voltage at the fourth power node.

18. The electronic device according to claim 17, wherein: The PMIC is further configured to output the second supply voltage at the fourth power node when the PMIC is in a power-on mode, and to set the fourth power node to an open circuit state when the PMIC is in a power-off mode.

19. The electronic device according to claim 17, wherein: The interposer layer further includes one or more conductive structures, and the dielectric layer surrounds the one or more conductive structures. The third power node is electrically coupled to the first power node through the first conductive structure in one or more conductive structures.

20. The electronic device of claim 17, wherein the intermediary layer further comprises: The first interposer metallization structure on the side of the dielectric layer facing the packaging substrate, The second interposer metallization structure on the other side of the dielectric layer facing the IC die, or Their combination.

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