Electronic devices and their manufacturing methods

Abstract

This invention improves the reliability of electrodes formed in openings. The electronic device has: an opening with an insulated inner surface; and electrodes formed on the inner surface of the opening. The electrodes are provided with metal laminated portions, wherein metals of different compositions or structures are laminated on the bottom surface of the opening. The metal laminated portions may include a sputtered layer, a chemically plated layer laminated on the sputtered layer, and an electrolytically plated layer laminated on the chemically plated layer. The metal laminated portions may be located on the bottom surface and side surfaces of the opening.

Description

Technical Field

[0001] This technology relates to an electronic device and a method for manufacturing the electronic device. Specifically, this technology relates to an electronic device having an opening in which electrodes are formed, and a method for manufacturing the electronic device. Background Technology

[0002] Through electrodes can be used to connect wiring in electronic devices. For example, a semiconductor package in which conductive pillars are formed through an electrolytic plating layer within an opening in a molding resin has been proposed (see, for example, Patent Document 1).

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2017-103426 Summary of the Invention

[0006] The problem the invention aims to solve

[0007] However, in the aforementioned conventional techniques, depending on the depth or shape of the opening, step coverage failures may occur in the seed layer used to form the coating, which could lead to the risk of hindering the formation of the electrode using the coating.

[0008] This technology was proposed in view of this situation, and its purpose is to improve the reliability of the electrodes formed in the opening portion.

[0009] Solution to the problem

[0010] This technology has been developed to solve the aforementioned problems, and its first aspect is an electronic device comprising: an opening having an insulating inner surface; and an electrode formed on the inner surface of the opening, wherein the electrode includes a metal stack, wherein metals with different compositions or microstructures are stacked on the bottom surface of the opening. Therefore, an effect of improving the coverage of the bottom surface of the opening is achieved.

[0011] Furthermore, in the first aspect, the metal stack portion can be located on the bottom surface and the side surface of the opening portion, and metal is stacked in the metal stack portion. Therefore, the effect of improving the coverage of the side surface of the opening portion is achieved.

[0012] Furthermore, in the first aspect, the microstructure can be grain-sized. Therefore, the effect of electrolytic plating being stacked on top of chemical plating is achieved.

[0013] Furthermore, in the first aspect, the metal stack may include a sputtered layer, a chemical plating layer stacked on the sputtered layer, and an electrolytic plating layer stacked on the chemical plating layer. Therefore, the effect of forming an electrolytic plating layer based on the sputtered layer and the chemical plating layer that have step-covering defects in the opening portion is achieved.

[0014] Furthermore, in the first aspect, the chemical plating layer can be selectively formed on the bottom surface of the opening via a sputtering layer. Therefore, the effect of avoiding the formation of a chemical plating layer on the entire surface of the sputtering layer is achieved.

[0015] Furthermore, in the first aspect, the chemical plating layer can be selectively formed on the bottom surface and the side surface of the opening via a sputtering layer. Therefore, the effect of avoiding the formation of a chemical plating layer on the entire surface of the sputtering layer is achieved.

[0016] Furthermore, in the first aspect, the sputtered layer on the bottom surface of the opening and the sputtered layer on the side surface of the opening can be separated from each other, and the chemical plating layer can be connected to the sputtered layer on the side surface of the opening via an electrolytic plating layer. Therefore, the effect of forming an electrolytic plating layer is achieved while compensating for step coverage defects in the sputtered layer of the opening through the chemical plating layer.

[0017] Furthermore, in the first aspect, the electronic device may also include wiring extending from the opening and connected to the electrode, wherein the wiring may include a sputtered layer and an electroplated layer stacked on the sputtered layer. Thus, the effect of configuring wiring connected to the electrode in the opening without using a chemical plating layer is achieved.

[0018] Furthermore, in the first aspect, the diameter of the bottom surface of the opening portion can be larger than the diameter of the opening surface of the opening portion. Therefore, the effect of determining the shape of the opening portion based on the notch on the bottom surface of the opening portion is achieved.

[0019] Furthermore, in the first aspect, the electronic device may further include: a first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate; a second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate, the second semiconductor chip being stacked on the first semiconductor chip such that the second wiring layer faces the first wiring layer; and a through electrode, wherein an electrode is formed, the through electrode penetrating the first semiconductor chip and being connected to the second wiring layer. Therefore, the effect of reducing connection failures of the through electrode penetrating the semiconductor chip and connecting to the wiring layer is achieved while accommodating an increase in via depth.

[0020] Furthermore, in the first aspect, the electronic device may further include: a first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate; a second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate, the second semiconductor chip being stacked on the first semiconductor chip such that the second wiring layer faces the first wiring layer; and a through electrode, wherein an electrode is formed, the through electrode penetrating the first semiconductor substrate and being connected to the first wiring layer. Therefore, the effect of reducing connection failures of the through electrode penetrating the semiconductor substrate and connecting to the wiring layer is achieved while accommodating an increase in via depth.

[0021] Furthermore, in the first aspect, the electronic device may further include: a first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate; a second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate, the second semiconductor chip being stacked on the first semiconductor chip such that the second wiring layer faces the first wiring layer; an embedding layer formed on the first semiconductor chip to embed the second semiconductor chip; a third semiconductor chip, wherein a third wiring layer is formed on a third semiconductor substrate, the third semiconductor chip being stacked on the embedding layer; and a through electrode, wherein an electrode is formed, the through electrode penetrating the third semiconductor chip and the second semiconductor chip and being connected to the first wiring layer. Therefore, the effect of reducing connection failures of through electrodes penetrating multiple semiconductor chips and connecting to the wiring layer is achieved while accommodating increased via depth.

[0022] Furthermore, in the first aspect, the electronic device may further include: a first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate; a second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate, the second semiconductor chip being stacked on the first semiconductor chip such that the second wiring layer faces the first wiring layer; an embedding layer formed on the first semiconductor chip to embed the second semiconductor chip; a third semiconductor chip, wherein a third wiring layer is formed on a third semiconductor substrate, the third semiconductor chip being stacked on the embedding layer; and a through electrode, wherein an electrode is formed, the through electrode penetrating the third semiconductor chip and the embedding layer and being connected to the first wiring layer. Therefore, the effect of reducing connection failures of the through electrode penetrating the semiconductor chip and the embedding layer and connecting to the wiring layer is achieved while accommodating an increase in via depth.

[0023] Furthermore, in the first aspect, the electronic device may also include a capacitor located in the opening and formed on an electrode. Thus, the effect of forming a capacitor in the opening is achieved while simultaneously improving the coverage of the bottom surface of the opening.

[0024] Furthermore, in the first aspect, the capacitor may include a first capacitor electrode formed on an electrode and a second capacitor electrode formed on the first capacitor electrode via a dielectric layer. Therefore, the effect of forming a capacitor in the opening portion is achieved while ensuring the selectivity of the capacitor electrode material.

[0025] Furthermore, in the first aspect, the capacitor may include a first capacitor electrode that also serves as an electrode and a second capacitor electrode formed on the first capacitor electrode via a dielectric layer. Therefore, the effect of forming a capacitor in the opening portion is achieved while simplifying the formation of the capacitor electrode.

[0026] Furthermore, in the first aspect, the electronic device may also include an insulating layer formed on the capacitor via a cavity in the opening. Thus, the capacitor formed in the opening is protected without being embedded inside the opening.

[0027] Furthermore, in the first aspect, the electronic device may also include an embedding layer formed on the capacitor to be embedded in the opening. Thus, the capacitor formed in the opening is covered by the embedding layer.

[0028] Furthermore, in a second aspect, the method for manufacturing an electronic device includes: a step of forming a sputtered layer on the inner surface of an opening; a step of forming an insulating layer on the sputtered layer; a step of removing the insulating layer on the sputtered layer on the bottom surface of the opening; a step of forming a chemical plating layer on the sputtered layer on the bottom surface of the opening; a step of removing the insulating layer in the opening after forming the chemical plating layer; and a step of forming an electrolytic plating layer on the sputtered layer and the chemical plating layer. Therefore, the effect of forming a three-layer structure comprising a sputtered layer, a chemical plating layer, and an electrolytic plating layer on the bottom surface of the opening is achieved.

[0029] Furthermore, in the second aspect, the sputtered layer on the side surface of the opening can be separated from the sputtered layer and the chemical plating layer on the bottom surface of the opening, and the chemical plating layer can be connected to the sputtered layer on the side surface of the opening via an electrolytic plating layer. Therefore, the effect of compensating for step coverage defects in the sputtered layer of the opening through the chemical plating layer while simultaneously forming the electrolytic plating layer is achieved. Attached Figure Description

[0030] Figure 1 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 1.

[0031] Figure 2 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 1.

[0032] Figure 3 This is a cross-sectional view showing yet another configuration example of the electronic device according to Embodiment 1.

[0033] Figure 4 This is a cross-sectional view showing yet another configuration example of the electronic device according to Embodiment 1.

[0034] Figure 5 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 1.

[0035] Figure 6 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 1.

[0036] Figure 7 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 1.

[0037] Figure 8 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 2.

[0038] Figure 9 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 2.

[0039] Figure 10 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 3.

[0040] Figure 11 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 3.

[0041] Figure 12 This is a cross-sectional view showing yet another configuration example of the electronic device according to Embodiment 3.

[0042] Figure 13 This is a cross-sectional view showing yet another configuration example of the electronic device according to Embodiment 3.

[0043] Figure 14 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 4.

[0044] Figure 15 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 5.

[0045] Figure 16 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 6.

[0046] Figure 17 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 6.

[0047] Figure 18 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 7.

[0048] Figure 19This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 8.

[0049] Figure 20 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 9.

[0050] Figure 21 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 10.

[0051] Figure 22 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 11.

[0052] Figure 23 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 12.

[0053] Figure 24 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 13.

[0054] Figure 25 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 14.

[0055] Figure 26 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 15.

[0056] Figure 27 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 16.

[0057] Figure 28 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 17.

[0058] Figure 29 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 17.

[0059] Figure 30 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 18.

[0060] Figure 31 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 18.

[0061] Figure 32 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 18.

[0062] Figure 33 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 18.

[0063] Figure 34 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 18.

[0064] Figure 35 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 19.

[0065] Figure 36 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 19.

[0066] Figure 37 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 20.

[0067] Figure 38 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 20.

[0068] Figure 39 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 21.

[0069] Figure 40 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 21.

[0070] Figure 41 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 22.

[0071] Figure 42 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 22.

[0072] Figure 43 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 23.

[0073] Figure 44 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 24.

[0074] Figure 45 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 24.

[0075] Figure 46 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 25.

[0076] Figure 47 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 25.

[0077] Figure 48 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 25.

[0078] Figure 49 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 26.

[0079] Figure 50 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 26.

[0080] Figure 51 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 26.

[0081] Figure 52 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 27.

[0082] Figure 53 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 27.

[0083] Figure 54 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 27.

[0084] Figure 55 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 28.

[0085] Figure 56 This is a schematic diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 28.

[0086] Figure 57 This is a schematic diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 28.

[0087] Figure 58 This is a schematic diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 28.

[0088] Figure 59 This is a schematic diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 28.

[0089] Figure 60 This is a schematic diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 28.

[0090] Figure 61 This is a schematic diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 28.

[0091] Figure 62 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 29.

[0092] Figure 63 This is a schematic diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 29.

[0093] Figure 64 This is a diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 29.

[0094] Figure 65 This is a diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 29.

[0095] Figure 66 This is a diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 29.

[0096] Figure 67 This is a diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 29.

[0097] Figure 68 This is a diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 29.

[0098] Figure 69 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 30.

[0099] Figure 70 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 31.

[0100] Figure 71 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 32.

[0101] Figure 72 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 33.

[0102] Figure 73 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 34.

[0103] Figure 74 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 35.

[0104] Figure 75 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 36.

[0105] Figure 76 This is a block diagram illustrating an example of a general configuration of a vehicle control system.

[0106] Figure 77 This is an explanatory diagram showing an example of the installation location of the external information detection unit and the camera unit. Detailed Implementation

[0107] The following describes the manner in which this technology is implemented (hereinafter referred to as embodiments). The descriptions are given in the following order.

[0108] 1. Example 1 (providing an example of a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked on the bottom surface of an opening)

[0109] 2. Example 2 (providing an example of a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked on the bottom surface of the opening via a barrier metal film)

[0110] 3. Example 3 (providing an example of a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked on the bottom surface of the opening, wherein the cross-sectional shape of the chemical plating layer is convex)

[0111] 4. Example 4 (providing an example of a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked on the bottom surface of the opening, wherein a portion of the sputtered layer is exposed during the formation of the chemical plating layer)

[0112] 5. Example 5 (providing an example of a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked on the bottom and side surfaces of an opening)

[0113] 6. Example 6 (providing an example of a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked on the bottom surface of an opening, wherein the entire opening is embedded with an electrolytic plating layer)

[0114] 7. Example 7 (where a through electrode in which a metal stack having a sputtered layer, a chemical plating layer and an electrolytic plating layer stacked sequentially on the bottom surface of the opening is connected to a lower chip via an upper chip)

[0115] 8. Example 8 (an example in which a through electrode of a metal stack having a sputtered layer, a chemical plating layer and an electrolytic plating layer stacked sequentially on the bottom surface of the opening is connected to a lower chip via an upper chip and the upper chip and the lower chip are joined based on hybrid bonding)

[0116] 9. Example 9 (An example in which a through electrode of a metal stack having a sputtered layer, a chemical plating layer and an electrolytic plating layer stacked sequentially on the bottom surface of the opening is connected to a lower chip via an upper chip and the upper chip and the lower chip are bonded via an adhesive layer)

[0117] 10. Example 10 (An example in which a through electrode in which a metal stack having a sputtered layer, a chemical plating layer and an electrolytic plating layer stacked sequentially are disposed on the bottom surface of an opening is connected to a lower chip via an upper chip, and the upper chip is stacked on the lower chip based on CoW (Chip on Wafer))

[0118] 11. Example 11 (An example in which a through electrode of a metal stack having a sputtered layer, a chemical plating layer and an electrolytic plating layer stacked sequentially on the bottom surface of the opening is connected to a lower chip via an upper chip, the upper chip is stacked on the lower chip based on CoW, and the upper chip and the lower chip are joined based on hybrid bonding)

[0119] 12. Example 12 (An example in which a through electrode of a metal stack portion having a sputtered layer, a chemical plating layer and an electrolytic plating layer stacked sequentially on the bottom surface of the opening portion is connected to a lower chip through an embedding layer surrounding the upper chip, and the upper chip is stacked on the lower chip based on CoW)

[0120] 13. Example 13 (An example in which a through electrode of a metal stack having a sputtered layer, a chemical plating layer and an electrolytic plating layer stacked sequentially on the bottom surface of the opening is connected to a lower chip through an embedding layer surrounding an upper chip, the upper chip is stacked on the lower chip based on CoW, and the upper chip and the lower chip are joined based on hybrid bonding)

[0121] 14. Example 14 (An example of wiring led out via a through electrode in which a metal stack having a sputtered layer, a chemical plating layer and an electrolytic plating layer stacked sequentially is provided on the bottom surface of the opening)

[0122] 15. Example 15 (An example in which a through electrode of a metal stack having a sputtered layer, a chemical plating layer and an electrolytic plating layer stacked sequentially on the bottom surface of the opening is connected to a lower chip via an upper chip and an intermediate chip)

[0123] 16. Example 16 (An example in which a through electrode of a metal stack having a sputtered layer, a chemical plating layer and an electrolytic plating layer stacked sequentially on the bottom surface of the opening is connected to a lower chip through an embedding layer in which an upper chip and an intermediate chip are embedded)

[0124] 17. Example 17 (An example of wiring being led out from a semiconductor chip on a sensor chip via a through electrode in which a sputtered layer, a chemical plating layer and an electrolytic plating layer are sequentially stacked on the bottom surface of the opening portion)

[0125] 18. Example 18 (An example of a capacitor being disposed on a metal stack in which a sputtered layer, a chemical plating layer, and an electrolytic plating layer are sequentially stacked in an opening)

[0126] 19. Example 19 (An example in which a capacitor is disposed on a metal stack in which a sputtered layer, a chemical plating layer and an electrolytic plating layer are sequentially stacked in the opening portion, and an insulating layer is formed along the surface of the capacitor)

[0127] 20. Example 20 (An example in which a capacitor is disposed on a metal stack in which a sputtered layer, a chemical plating layer and an electrolytic plating layer are sequentially stacked in an opening, and an embedding layer is formed on the capacitor so that it can be embedded in the opening)

[0128] 21. Example 21 (A capacitor is disposed on a metal stack in which a sputtered layer, a chemical plating layer and an electrolytic plating layer are sequentially stacked in the opening, and a through electrode is also used as the first capacitor electrode)

[0129] 22. Example 22 (providing a metal stack portion on the bottom surface of the opening portion in which a sputtered layer, a chemical plating layer and an electrolytic plating layer are sequentially stacked, and a skirt portion in which a photosensitive insulating film is embedded in the bottom surface of the opening portion)

[0130] 23. Example 23 (providing an example of a metal stack having a sputtered layer, a chemical plating layer and an electrolytic plating layer sequentially stacked on the bottom surface of an opening, and a barrier metal layer including an atomic layer deposition (ALD) film disposed below the sputtered layer)

[0131] 24. Example 24 (providing a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked on the bottom surface of the opening, and an example of adding chemical plating around the chemical plating layer)

[0132] 25. Example 25 (providing an example of a metal stack in which a sputtered layer, a chemical plating layer and an electrolytic plating layer are sequentially stacked in an opening, wherein multiple skirt portions are formed at different positions in the depth direction)

[0133] 26. Example 26 (provides an example of a metal stack in which a sputtered layer, a chemical plating layer and an electrolytic plating layer are sequentially stacked on the bottom surface of an opening, and a separation by an implanted oxygen (SIMOX) layer is provided over the entire substrate at a midpoint in the depth direction of the opening to surround the opening)

[0134] 27. Example 27 (providing a metal stack portion on the bottom surface of the opening portion in which a sputtered layer, a chemical plating layer and an electrolytic plating layer are sequentially stacked, and an SIMOX layer is provided in the portion of the substrate at the middle position in the depth direction of the opening portion to surround the opening portion)

[0135] 28. Example 28 (Provides a metal stack where a chemical plating layer, a sputtered layer, and an electrolytic plating layer are sequentially stacked on the bottom surface of an opening, the chemical plating layer is embedded in a wiring layer disposed below the opening, and there is no wiring below the chemical plating layer)

[0136] 29. Example 29 (Providing a metal stack where a chemical plating layer, a sputtering layer, and an electrolytic plating layer are sequentially stacked on the bottom surface of an opening, the chemical plating layer is embedded in a wiring layer disposed below the opening, and wiring is provided below the chemical plating layer)

[0137] 30. Example 30 (providing a metal stack portion on the bottom surface of the opening portion in which a chemical plating layer, a sputtered layer and an electrolytic plating layer are sequentially stacked, and the chemical plating layer is embedded in a wiring layer disposed below the opening portion and widened in the depth direction of the opening portion)

[0138] 31. Example 31 (Providing an example of a metal stack where a chemical plating layer and an electrolytic plating layer are sequentially stacked on the bottom surface of an opening to form a through-hole embedded in a semiconductor substrate below the chemical plating layer, and to form a sputtered film through-hole)

[0139] 32. Example 32 (providing a metal stack portion on the bottom surface of the opening portion in which a chemical plating layer and an electrolytic plating layer are sequentially stacked to form a through hole embedded in a semiconductor substrate below the chemical plating layer, and an example of forming a plated film and a sputtered film on the through hole)

[0140] 33. Example 33 (providing a metal stack portion on the bottom surface of the opening where a chemical plating layer and an electrolytic plating layer are sequentially stacked, and forming wiring embedded in a semiconductor substrate below the chemical plating layer)

[0141] 34. Example 34 (Provides a metal stack where a chemical plating layer, a sputtered layer, and an electrolytic plating layer are sequentially stacked on the bottom surface of the opening, the chemical plating layer is embedded in a wiring layer disposed below the opening, such that the chemical plating layer protrudes from the wiring layer, and there is no wiring below the chemical plating layer)

[0142] 35. Example 35 (Provides a metal stack portion on the bottom surface of an opening portion in which a chemical plating layer, a sputtering layer and an electrolytic plating layer are sequentially stacked, the chemical plating layer is embedded in a wiring layer disposed below the opening portion, such that the chemical plating layer protrudes from the wiring layer, and wiring is present below the chemical plating layer)

[0143] 36. Example 36 (Provides a metal stack portion on the bottom surface of an opening portion in which a chemical plating layer, a sputtering layer and an electrolytic plating layer are sequentially stacked, wherein the chemical plating layer is embedded in a wiring layer that is widened in the depth direction of the opening portion and disposed below the opening portion, such that the chemical plating layer protrudes from the wiring layer and wiring is present below the chemical plating layer)

[0144] 37. Examples of application to moving bodies

[0145] <1. Example 1>

[0146] Figure 1 This is a cross-sectional view illustrating an example configuration of an electronic device according to Embodiment 1. It should be noted that the scale, shape, etc., in the accompanying drawings used below may differ from the scale, shape, etc., of the actual structure in order to facilitate understanding of each configuration.

[0147] In the figure, the electronic device is provided with a through electrode TV1. The through electrode TV1 can be formed in a semiconductor substrate, an insulating substrate, a mounting substrate, or a wiring layer. The electronic device may include a semiconductor device, an optical device, a microelectromechanical system (MEMS), a display device, or an antenna element.

[0148] Semiconductor devices can house memory, processors, signal processing circuits, data processing circuits, or interface circuits. Hardware circuits such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) can be formed within them. The semiconductor materials used in semiconductor devices can be Si, GaAs, SiC, GaN, InGaAsP, etc.

[0149] Optical devices can be image sensors such as charge-coupled device (CCD) sensors, complementary metal-oxide-semiconductor (CMOS) sensors, or single-photon avalanche diode (SPAD) sensors. The light received by the image sensor can be visible light, near-infrared (NIR), short-wavelength infrared (SWIR), ultraviolet light, X-rays, etc. Optical devices can be light-receiving elements such as photodiodes (PD) or light-emitting elements such as laser diodes (LD), light-emitting diodes (LED), or vertical-cavity surface-emitting lasers (VCSELs). The optical materials used in optical devices can be semiconductors such as Si, GaAs, or InGaAs, or dielectrics such as LiNbO3, glass, or transparent resin.

[0150] MEMS can be optical switches, optical scanners, digital micromirror devices (DMDs), pressure sensors, flow sensors, or gyroscopes.

[0151] The display device can be a liquid crystal display, an organic electroluminescent (EL) display, or a miniature LED display.

[0152] Wiring layer 112 is formed on semiconductor substrate 111. Through electrode TV1 penetrates semiconductor substrate 111 and is connected to wiring layer 112. Wiring layer 112 has wiring 113 embedded in an insulating layer formed therein.

[0153] Furthermore, an opening 114 is formed in the semiconductor substrate 111. The opening 114 can penetrate the semiconductor substrate 111 and reach the wiring layer 112. The opening 114 can have a cylindrical shape. A through electrode TV1 can be formed along the inner surface of the opening 114. The through electrode TV1 includes a metal stack MT1 located on the bottom surface of the opening 114. In the metal stack MT1, metals with different compositions or microstructures are stacked therein. The microstructure is, for example, grain size. It should be noted that the through electrode TV1 is an example of the electrode described in the claims.

[0154] To insulate the through electrode TV1 from the semiconductor substrate 111, the inner surface of the opening 114 is insulated. In this case, an insulating layer 115 can be formed on the inner surface of the opening 114. The insulating layer 115 can be continuously formed from the side surface of the opening 114 to the rear surface of the semiconductor substrate 111.

[0155] A sputtered layer 116 can be formed on the bottom surface of the opening 114, and also via an insulating layer 115 above the side surfaces of the opening 114 and the rear surface of the semiconductor substrate 111. This sputtered layer 116 can be used as a seed layer for forming the electrolytic plating layer 119. A barrier metal layer can be disposed below the seed layer. The sputtered layer 116 on the bottom surface of the opening 114 can be separated from the sputtered layer 116 on the side surfaces of the opening 114.

[0156] On the bottom surface of the opening 114, a chemical plating layer 118 is formed on the sputtered layer 116. An insulating layer 117 is formed on the side surface of the chemical plating layer 118. It should be noted that the insulating layer 117 can be used to selectively form the chemical plating layer 118 on the sputtered layer 116 on the bottom surface of the opening 114. The insulating layer 117 can be formed on the side surface of the opening 114 before the formation of the chemical plating layer 118. After the formation of the chemical plating layer 118 and before the formation of the electrolytic plating layer 119, the insulating layer 117 on the side surface of the opening 114 can be removed. In this case, the insulating layer 117 can remain only on the side surface of the chemical plating layer 118.

[0157] An electrolytic plating layer 119 is formed on the chemical plating layer 118 and the insulating layer 117. In this case, the electrolytic plating layer 119 can be continuously formed on the chemical plating layer 118 and the insulating layer 117 to extend via the sputtering layer 116 to the side surface of the opening portion 114 and the rear surface of the semiconductor substrate 111.

[0158] The materials of insulating layers 115 and 117 can be, for example, inorganic materials (such as SiO2, SiN or SiCN) or organic materials (such as polyimide).

[0159] In this configuration, on the bottom surface of the opening 114, the metal stack MT1 can employ a three-layer structure consisting of a sputtered layer 116, a chemical plating layer 118, and an electrolytic plating layer 119. The composition of the sputtered layer 116, chemical plating layer 118, and electrolytic plating layer 119 can be Cu, Ni, Sn, Ag, Au, or a combination thereof. A single metal (such as Cu) can be used for the composition of the sputtered layer 116, chemical plating layer 118, and electrolytic plating layer 119. In this case, the grain sizes of the sputtered layer 116, chemical plating layer 118, and electrolytic plating layer 119 can be different from each other.

[0160] The material of the electroless plating layer 118 can be cobalt (Co). By using cobalt as the material of the electroless plating layer 118, electromigration resistance can be improved. In addition, the efficiency of electroplating can be improved and miscibility with Cu can be suppressed.

[0161] Here, a chemical plating layer 118 is formed on the sputtered layer 116 on the bottom surface of the opening 114, and then an electrolytic plating layer 119 is formed. Therefore, even if a step coverage failure of the sputtered layer 116 occurs due to the increased aspect ratio of the opening 114, the conductivity of the through electrode TV1 on the bottom surface of the opening 114 can be ensured, and open circuit defects can be reduced.

[0162] Figure 2 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 1.

[0163] In the same figure, the electronic device includes a through electrode TV2 and an insulating layer 125, instead of Figure 1 The through electrode TV1 and the insulating layer 115. Other configurations of this electronic device are similar. Figure 1 The configuration of electronic devices in the system.

[0164] In this configuration, an opening 124 is formed in the semiconductor substrate 111. The opening 124 can penetrate the semiconductor substrate 111 and reach the wiring layer 112. The opening 124 can have a shape that widens towards the bottom surface. In this configuration, the diameter of the bottom surface of the opening 124 can be larger than the diameter of the opening surface of the opening 124. For example, a notch can be formed at the bottom of the opening 124. A through electrode TV2 can be formed along the inner surface of the opening 124. The through electrode TV2 includes a metal stack MT2 located on the bottom surface of the opening 124. In the metal stack MT2, metals having different compositions or microstructures are stacked therein.

[0165] An insulating layer 125 is formed on the inner surface of the opening 124. The insulating layer 125 can be continuously formed from the side surface of the opening 124 to the rear surface of the semiconductor substrate 111.

[0166] The sputtered layer 126 can be formed on the bottom surface of the opening 124 and can also be formed above the side surface of the opening 124 and the rear surface of the semiconductor substrate 111 via the insulating layer 125. Here, the sputtered layer 126 can be separated between the bottom surface and the side surface of the opening 124. The sputtered layer 126 can be used as a seed layer for forming the electrolytic plating layer 129.

[0167] On the bottom surface of the opening 124, a chemical plating layer 128 is formed on the sputtered layer 126. The side surface of the chemical plating layer 128 may be warped. The chemical plating layer 128 may penetrate into the separation region of the sputtered layer 126 between the bottom surface and the side surface of the opening 124. In this case, the chemical plating layer 128 can be separated from the sputtered layer 126 on the side surface of the opening 124.

[0168] An electrolytic plating layer 129 is formed on the chemical plating layer 128. The electrolytic plating layer 129 can be continuously formed on the chemical plating layer 128 to extend via the sputtering layer 126 to the side surface of the opening portion 124 and the rear surface of the semiconductor substrate 111. Here, even if the chemical plating layer 128 and the sputtering layer 126 on the side surface of the opening portion 124 are separated from each other, the sputtering layer 126 can be used as a seed layer to form the electrolytic plating layer 129 on the sputtering layer 126 on the side surface of the opening portion 124. Then, as the electrolytic plating layer 129 grows, it can come into contact with the chemical plating layer 128 as its thickness increases. Therefore, the sputtering layer 126 and the electrolytic plating layer 129 on the bottom surface can be electrically connected to each other through the chemical plating layer 128. In this case, on the bottom surface of the opening portion 124, the metal stack portion MT2 can adopt a three-layer structure of sputtered layer 126, chemical plating layer 128 and electrolytic plating layer 129.

[0169] Here, a chemical plating layer 128 is formed on the sputtered layer 126 on the bottom surface of the opening 124, and then an electrolytic plating layer 129 is formed. Therefore, even in the event of a step coverage failure of the sputtered layer 126 due to the notch at the bottom of the opening 124, the conductivity of the through electrode TV2 on the bottom surface of the opening 124 can be ensured, and open circuit defects can be reduced.

[0170] Figure 3 This is a cross-sectional view showing yet another configuration example of the electronic device according to Embodiment 1.

[0171] In the same drawing, the electronic device includes a through electrode TV3, an opening 134, and an insulating layer 135, replacing... Figure 1 The through electrode TV1, the opening portion 114, and the insulating layer 115 are also present. Other configurations of this electronic device are similar. Figure 1 The configuration of electronic devices in the system.

[0172] The through electrode TV3 is embedded in the opening 134. The diameter of the opening 134 decreases towards the bottom. In this case, the side surface of the opening 134 can be inclined. For example, the three-dimensional shape of the opening 134 can be a cup shape or a flowerpot shape. The through electrode TV3 includes an insulating layer 137, a sputtered layer 136, a chemical plating layer 138, and an electrolytic plating layer 139, instead of Figure 1 The insulating layer 117, sputtering layer 116, chemical plating layer 118 and electrolytic plating layer 119.

[0173] An insulating layer 135 can be continuously formed from the side surface of the opening 134 to the rear surface of the semiconductor substrate 111. An insulating layer 137 is formed on the side surface of the chemical plating layer 138.

[0174] The sputtered layer 136 can be formed on the bottom surface of the opening 134 and can also be continuously formed above the side surface of the opening 134 and the rear surface of the semiconductor substrate 111 via the insulating layer 135.

[0175] A chemical plating layer 138 is formed on the sputtered layer 136 on the bottom surface of the opening 134. The three-dimensional shape of the chemical plating layer 138 can be, for example, an inverted truncated cone.

[0176] Electrolytic plating layer 139 is continuously formed on chemical plating layer 138 and insulating layer 137 to extend via sputtering layer 136 to the side surface of opening portion 134 and the rear surface of semiconductor substrate 111.

[0177] Figure 4 This is a cross-sectional view showing yet another example of the configuration of the electronic device according to Embodiment 1.

[0178] In this figure, the electronic device includes a through electrode TV4 instead of Figure 2 The through electrode TV2. Other configurations of this electronic device are similar to... Figure 2 The configurations of the electronic devices in the two systems are similar.

[0179] The through electrode TV4 includes a sputtered layer 146, a chemical plating layer 148, and an electrolytic plating layer 149 to replace Figure 2 The sputtered layer 126, the chemically plated layer 128, and the electrolytically plated layer 129 are also present. Furthermore, the through electrode TV4 has a directional... Figure 2 The electronic device has an added insulating layer 147. Other configurations of the through-electrode TV4 are similar to... Figure 2 The configuration of the through electrode TV2 in the middle is similar.

[0180] The sputtered layer 146 can be formed on the bottom surface of the opening 124, and can also be continuously formed on the side surface of the opening 124 and the rear surface of the semiconductor substrate 111 via the insulating layer 125.

[0181] A chemical plating layer 148 is formed on the sputtered layer 146 on the bottom surface of the opening portion 124. An insulating layer 147 is formed on the side surface of the chemical plating layer 148.

[0182] An electrolytic plating layer 149 is formed on the chemical plating layer 148 and the insulating layer 147 on the bottom surface of the opening portion 124. In this case, the electrolytic plating layer 149 can be formed continuously on the chemical plating layer 148 and the insulating layer 147 to extend to the side surface of the opening portion 124 and the rear surface of the semiconductor substrate 111 via the sputtering layer 146.

[0183] Figures 5 to 7 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 1. Note that in Figures 5 to 7 middle, Figure 2 The manufacturing method of the electronic device is used as an example, but this method can also be applied to... Figure 1 , Figure 3 or Figure 4 Methods for manufacturing electronic devices.

[0184] exist Figure 5 In (a), a wiring layer 112 is formed on a semiconductor substrate 111. Note that transistors, diodes, resistors, capacitors, etc., can be formed in the semiconductor substrate 111. Then, a resist pattern PA is formed on the back surface of the semiconductor substrate 111 using photolithography. In the resist pattern PA, an opening KA is formed at the location where the opening 124 is formed.

[0185] Next, as Figure 5 As shown in (b), the semiconductor substrate 111 is etched using a resist pattern PA as an etching mask, thereby forming an opening 124 in the semiconductor substrate 111. In this case, a notch may be formed at the bottom of the opening 124. For etching the semiconductor substrate 111, dry etching, such as reactive ion etching (RIE), may be used.

[0186] Next, as Figure 5 As shown in (c), an insulating layer 125 is formed on the bottom and side surfaces of the opening 124 and the rear surface of the semiconductor substrate 111 by a method such as chemical vapor deposition (CVD).

[0187] Next, as Figure 6 As shown in (a), the insulating layer 125 on the wiring layer 112 in the opening portion 124 is removed by selectively etching the bottom surface of the opening portion 124 via the opening portion 124.

[0188] Next, as Figure 6 As shown in (b), a sputtered layer 126 is formed by sputtering on the bottom surface of the opening 124, the side surface of the opening 124, and the rear surface of the semiconductor substrate 111. In this case, the sputtered layer 126 can be separated between the bottom surface and the side surface of the opening 124.

[0189] Next, as Figure 6 As shown in (c), an insulating layer 127 is formed on sputtered layer 126 by a method such as CVD. The insulating layer 127 may also be formed on insulating layer 125 exposed from sputtered layer 126 between bottom surface and side surface of opening 124.

[0190] Next, as Figure 7 As shown in (a), the insulating layer 127 on the sputtered layer 126 on the bottom surface of the opening portion 124 is removed by selectively etching the bottom surface of the opening portion 124 via the opening portion 124.

[0191] Next, as Figure 7 As shown in (b), a chemical plating layer 128 is selectively formed on the sputtered layer 126 on the bottom surface of the opening 124 based on electroless plating. The electroless plating layer 128 may extend beyond the sputtered layer 126 on the bottom surface of the opening 124. In this case, the electroless plating layer 128 may penetrate into the separation region of the sputtered layer 126 between the bottom surface and the side surface of the opening 124. The electroless plating layer 128 can be separated from the sputtered layer 126 on the side surface of the opening 124. In this case, the entire sputtered layer 126 on the side surface of the opening 124 can be covered by an insulating layer 127.

[0192] Next, as Figure 7 As shown in (c), the insulating layer 127 on the sputtered layer 126 is removed by a method such as plasma etching.

[0193] Next, as Figure 2 As shown, based on electrolytic plating using sputtered layer 126 as a seed layer, electrolytic plating layer 129 is continuously formed from electroless plating layer 128 to the side surface of opening portion 124 and the rear surface of semiconductor substrate 111. In this case, as the thickness of electrolytic plating layer 129 increases during the growth of electrolytic plating layer 129, electrolytic plating layer 129 can come into contact with electroless plating layer 128.

[0194] In this way, in Embodiment 1 described above, for example, a chemical plating layer 128 is formed on the bottom surface of the opening 124 between the sputtered layer 126 and the electroplated layer 129. Therefore, even in the event of a step coverage failure of the sputtered layer 126 at the bottom of the opening 124, the conductivity of the through electrode TV2 on the bottom surface of the opening 124 can be ensured, and open circuit defects can be reduced while miniaturizing the through electrode TV2.

[0195] <2. Example 2>

[0196] In Embodiment 1 described above, a chemical plating layer 128 is formed on the bottom surface of the opening portion 124 between the sputtered layer 126 and the electrolytic plating layer 129. In this Embodiment 2, a chemical plating layer 128 is formed on the bottom surface of the opening portion 124 between the sputtered layer 126 and the electrolytic plating layer 129, while a barrier metal film is formed below the sputtered layer 126.

[0197] Figure 8 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 2.

[0198] In this figure, the electronic device includes a through electrode TV5 instead of Figure 1 The through electrode TV1. Other configurations of this electronic device are... Figure 1 The configurations of the electronic devices in the two systems are similar.

[0199] The through electrode TV5 is configured to allow the through electrode TV5 to be directed towards Figure 1 A blocking metal film 120 is added to the through electrode TV1. Other configurations of the through electrode TV5 are the same as... Figure 1 The configuration of the through electrode TV1 is similar.

[0200] A barrier metal film 120 is formed beneath the sputtered layer 116. In this case, the barrier metal film 120 is located on the insulating layer 115 and the wiring layer 112 in the opening portion 114. The material of the barrier metal film 120 can be, for example, Ti, TiN, Ta, TaN, Ru, RuN, etc.

[0201] Figure 9 This is a cross-sectional view showing another example of the configuration of the electronic device according to Embodiment 2.

[0202] In this figure, the electronic device includes a through electrode TV6 instead of Figure 2 The through electrode TV2. Other configurations of this electronic device are similar to... Figure 2 The configurations of the electronic devices in the two systems are similar.

[0203] The through electrode TV6 is configured as follows: a blocking metal film 130 is added to... Figure 2 The through electrode TV2. Other configurations of the through electrode TV6 are similar to... Figure 2 The configuration of the through electrode TV2 in the middle is similar.

[0204] A barrier metal film 130 is formed beneath the sputtered layer 126. In this case, the barrier metal film 130 is located on the insulating layer 125 and the wiring layer 112 in the opening portion 124. The barrier metal film 130 may be discontinuous between the bottom surface and the side surface of the opening portion 124.

[0205] In this way, in Embodiment 2 described above, for example, a chemical plating layer 128 is formed between the sputtered layer 126 and the electroplated layer 129 on the bottom surface of the opening portion 124, and a barrier metal film is formed below the sputtered layer 126. Therefore, open-circuit defects can be reduced while miniaturizing the through electrode TV5, and the diffusion of metal contained in the sputtered layer 126 into the insulating layer 125 and the wiring layer 112 can be suppressed.

[0206] <3. Example 3>

[0207] In Embodiment 1 described above, a chemical plating layer 128 is formed between the sputtered layer 126 and the electroplated layer 129 on the bottom surface of the opening portion 124. In Embodiment 3, the cross-sectional shape of the chemical plating layer formed between the sputtered layer 126 and the electroplated layer on the bottom surface of the opening portion 124 is convex.

[0208] Figure 10 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 3.

[0209] In this figure, the electronic device includes a through electrode TV7, in place of... Figure 1 The through electrode TV1. Other configurations of this electronic device are... Figure 1 The configurations of the electronic devices in the two systems are similar.

[0210] The through electrode TV7 includes a chemical plating layer 158 and an electrolytic plating layer 159, to replace... Figure 1 The chemical plating layer 118 and the electrolytic plating layer 119. Other configurations of the through electrode TV7 are similar to... Figure 1 The configuration of the through electrode TV1 is similar.

[0211] The electroless plating layer 158 is formed on the sputtered layer 116 on the bottom surface of the opening portion 114. The cross-sectional shape of the electroless plating layer 158 can be convex. In this case, the upper surface shape of the electroless plating layer 158 can be a convex curved surface. For example, the three-dimensional shape of the electroless plating layer 158 can be a cap shape, a cup shape, or a bowl shape.

[0212] An electrolytic plating layer 159 is formed on the chemical plating layer 158 and the insulating layer 117 on the bottom surface of the opening portion 114. In this case, the electrolytic plating layer 159 is continuously formed on the chemical plating layer 158 and the insulating layer 117 to extend via the sputtering layer 116 to the side surface of the opening portion 114 and the rear surface of the semiconductor substrate 111. The electrolytic plating layer 159 is curved on the chemical plating layer 158 to follow the shape of the upper surface of the chemical plating layer 158.

[0213] Figure 11 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 3.

[0214] In this figure, the electronic device includes a through electrode TV8, in place of... Figure 2 The through electrode TV2. Other configurations of this electronic device are... Figure 2 The configurations of the electronic devices in the two systems are similar.

[0215] The through electrode TV8 includes a chemical plating layer 168 and an electrolytic plating layer 169, to replace... Figure 2 The chemical plating layer 128 and the electrolytic plating layer 129. Other configurations of the through electrode TV8 are similar to... Figure 2 The configuration of the through electrode TV2 in the middle is similar.

[0216] The electroless plating layer 168 is formed on the sputtered layer 126 on the bottom surface of the opening portion 124. The cross-sectional shape of the electroless plating layer 168 can be convex.

[0217] An electrolytic plating layer 169 is formed on a chemical plating layer 168 on the bottom surface of the opening portion 124. In this case, the electrolytic plating layer 169 is continuously formed on the chemical plating layer 168 to extend via the sputtering layer 126 to the side surface of the opening portion 124 and the rear surface of the semiconductor substrate 111. The electrolytic plating layer 169 is curved on the chemical plating layer 168 to follow the shape of the upper surface of the chemical plating layer 168.

[0218] Figure 12 This is a cross-sectional view showing yet another example of the configuration of the electronic device according to Embodiment 3.

[0219] In this figure, the electronic device includes a through electrode TV9, in place of... Figure 4 The through electrode TV4. Other configurations of this electronic device are... Figure 4 The configurations of the electronic devices in the two systems are similar.

[0220] The through electrode TV9 includes a chemical plating layer 178 and an electrolytic plating layer 179, to replace... Figure 4 The chemical plating layer 148 and the electrolytic plating layer 149. Other configurations of the through electrode TV9 are... Figure 4 The configuration of the through electrode TV4 in the middle is similar.

[0221] A chemical plating layer 178 is formed on the sputtered layer 146 on the bottom surface of the opening 124. The cross-sectional shape of the chemical plating layer 178 may be convex. An insulating layer 147 is formed on the side surface of the chemical plating layer 178.

[0222] An electrolytic plating layer 179 is formed on a chemical plating layer 178 and an insulating layer 147. In this case, the electrolytic plating layer 179 can be continuously formed on the chemical plating layer 178 and the insulating layer 147 to extend via the sputtering layer 146 to the side surface of the opening portion 124 and the rear surface of the semiconductor substrate 111. The electrolytic plating layer 179 is bent on the chemical plating layer 178 to follow the shape of the upper surface of the chemical plating layer 178.

[0223] Figure 13 This is a cross-sectional view showing yet another example of the configuration of the electronic device according to Embodiment 3.

[0224] In this figure, the electronic device includes a through electrode TV10, in place of... Figure 3 The through electrode TV3. Other configurations of this electronic device are... Figure 3 The configurations of the electronic devices in the two systems are similar.

[0225] The through electrode TV10 includes a chemical plating layer 188 and an electrolytic plating layer 189, to replace Figure 3 The chemical plating layer 138 and the electrolytic plating layer 139. Other configurations of the through electrode TV10 are similar to... Figure 3 The configuration of the through electrode TV10 is similar.

[0226] A chemical plating layer 188 is formed on the sputtered layer 136 on the bottom surface of the opening portion 134. The cross-sectional shape of the chemical plating layer 188 can be convex. An insulating layer 137 is formed on the side surface of the chemical plating layer 188.

[0227] An electrolytic plating layer 189 is formed on a chemical plating layer 188 and an insulating layer 137. In this case, the electrolytic plating layer 189 can be continuously formed on the chemical plating layer 188 and the insulating layer 137 to extend via the sputtering layer 136 to the side surface of the opening 134 and the rear surface of the semiconductor substrate 111. The electrolytic plating layer 189 is bent on the chemical plating layer 188 to follow the shape of the upper surface of the chemical plating layer 188.

[0228] In this way, in Embodiment 3 described above, for example, the cross-sectional shape of the electroless plating layer 168 formed between the sputtered layer 126 and the electrolytic plating layer 169 on the bottom surface of the opening portion 124 is convex. Therefore, the electroless plating layer 168 can be selectively formed on the sputtered layer 126 depending on the diameter or shape of the opening portion 124.

[0229] <4. Example 4>

[0230] In Embodiment 1 described above, a chemical plating layer 128 is selectively formed on the sputtered layer 126 on the bottom surface of the opening 124, and the entire sputtered layer 126 on the side surface of the opening 124 is covered by an insulating layer 127. In Embodiment 4, a chemical plating layer is selectively formed on the sputtered layer 126 on the bottom surface of the opening 124, wherein a portion of the sputtered layer on the side surface of the opening 124 is exposed from the insulating layer.

[0231] Figure 14This is a cross-sectional view illustrating an example configuration of an electronic device according to Embodiment 4. Note that this figure shows a configuration in which a chemical plating layer is selectively formed with a portion of the sputtered layer exposed from the insulating layer. Figure 2 This is an example of an electronic device, but the configuration can also be applied to other electronic devices.

[0232] In this figure, the electronic device includes a through electrode TV11 instead of Figure 2 The through electrode TV2. Other configurations of this electronic device are... Figure 2 The configurations of the electronic devices in the two systems are similar.

[0233] The through electrode TV11 includes a chemical plating layer 198 and an electrolytic plating layer 199 to replace Figure 2 The chemical plating layer 128 and the electrolytic plating layer 129. Other configurations of the through electrode TV11 are similar to... Figure 2 The configuration of the through electrode TV2 in the middle is similar.

[0234] On the side surface of the opening 124, the end of the sputtered layer 126 contacts the electroless plating layer 198. Here, to ensure that the end of the sputtered layer 126 contacts the electroless plating layer 198, in... Figure 7 In step b, the end of the sputtered layer 126 on the side surface of the opening portion 124 can be exposed from the insulating layer 127.

[0235] A chemical plating layer 198 is formed on the sputtered layer 126 on the bottom surface of the opening 124. Furthermore, the chemical plating layer 198 is formed on the side surfaces of the opening 124 and at the ends of the sputtered layer 126. In this case, the chemical plating layer 198 may protrude at the peripheral portion compared to the central portion.

[0236] An electrolytic plating layer 199 is formed on the chemical plating layer 198 on the bottom surface of the opening portion 124. In this case, the electrolytic plating layer 199 can be continuously formed on the chemical plating layer 198 via the sputtering layer 126 to extend to the side surface of the opening portion 124 and the rear surface of the semiconductor substrate 111.

[0237] Thus, in Embodiment 4 above, for example, a chemical plating layer 198 is selectively formed on a portion of the sputtered layer 126 on the side surface of the opening portion 124 while the insulating layer is exposed. Therefore, while achieving thinning of the chemical plating layer 198, the conductivity of the through electrode TV11 on the bottom surface of the opening portion 124 can be ensured, and while achieving miniaturization of the through electrode TV11, open-circuit defects can be reduced.

[0238] <5. Example 5>

[0239] In Embodiment 1 described above, a chemical plating layer 128 is formed between the sputtered layer 126 and the electroplated layer 129 on the bottom surface of the opening portion 124. In Embodiment 5, a chemical plating layer 128 is formed on the sputtered layer 126 on the bottom surface of the opening portion 124, and a chemical plating layer is also formed on the sputtered layer 126 on the side surface of the opening portion 124.

[0240] Figure 15 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 5. Note that this figure shows an application of a configuration in which a chemical plating layer 128' is formed on a sputtered layer 126 on the side surface of the opening portion 124. Figure 2 This is an example of an electronic device, but the configuration can also be applied to other electronic devices.

[0241] In Figure b, the electronic device includes a through electrode TV12 instead of Figure 2 The through electrode TV2. Other configurations of this electronic device are... Figure 2 The configurations of the electronic devices in the two systems are similar.

[0242] Through electrode TV12 includes an electrolytic plating layer 1009 to replace Figure 2 Electrolytic plating layer 129. Furthermore, the through electrode TV12 is configured such that chemical plating layer 128' is added to... Figure 2 The through electrode TV2. Other configurations of the through electrode TV12 are similar to... Figure 2 The configuration of the through electrode TV2 in the middle is similar.

[0243] A chemical plating layer 128' is formed on the side surface of the opening portion 124 above the sputtered layer 126. The chemical plating layer 128' can be selectively formed together with the chemical plating layer 128.

[0244] In this case, as shown in Figure a, before performing chemical plating, a resist pattern PB is formed on the sputtered layer 126 on the back surface of the semiconductor substrate 111 using photolithography. In the resist pattern PB, an opening KB is formed at a location exposing the side surface of the sputtered layer 126.

[0245] Then, chemical plating is performed using a resist pattern PB to form a chemical plating layer 128 on the sputtered layer 126 on the bottom surface of the opening portion 124, and a chemical plating layer 128' on the side surface of the opening portion 124 above the sputtered layer 126.

[0246] As shown in Figure b, an electrolytic plating layer 1009 is formed on the chemical plating layers 128 and 128'. In this case, the electrolytic plating layer 1009 can be formed continuously on the chemical plating layers 128 and 128' to extend to the rear surface of the semiconductor substrate 111 via the sputtering layer 126.

[0247] As described above, in Embodiment 5, a chemical plating layer 128 is formed on the sputtered layer 126 on the bottom surface of the opening 124, and a chemical plating layer 128' is also formed on the sputtered layer 126 on the side surface of the opening 124. Therefore, even if a step coverage failure of the sputtered layer 126 occurs at the bottom of the opening 124, the conductivity of the through electrode TV12 on the bottom surface of the opening 124 can be ensured, and open circuit defects can be reduced.

[0248] <6. Example 6>

[0249] In Embodiment 1 described above, a chemical plating layer 128 is formed between the sputtered layer 126 and the electroplated layer 129 on the bottom surface of the opening portion 124. In Embodiment 6, an electroplated layer is embedded in the opening portion 124 in which the chemical plating layer 128 is formed on the bottom surface via the sputtered layer 126.

[0250] Figure 16 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 6.

[0251] In this figure, the electronic device includes a through electrode TV12 instead of Figure 1 The through electrode TV1. Other configurations of this electronic device are... Figure 1 The configurations of the electronic devices in the two systems are similar.

[0252] Through electrode TV12 includes an electrolytic plating layer 1019 to replace Figure 1 The electrolytic plating layer 119. Other configurations of the through electrode TV12 are similar to... Figure 1 The configuration of the through electrode TV1 is similar.

[0253] An electrolytic plating layer 1019 is embedded in the opening portion 114 on the chemical plating layer 118 and the insulating layer 117. In this case, the electrolytic plating layer 1019 is continuously formed from the interior of the opening portion 114 to extend to the rear surface of the semiconductor substrate 111.

[0254] Figure 17 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 6.

[0255] In this figure, the electronic device includes a through electrode TV13 instead of Figure 2 The through electrode TV2. Other configurations of this electronic device are... Figure 2 The configurations of the electronic devices in the two systems are similar.

[0256] Through electrode TV13 includes an electrolytic plating layer 1029 to replace Figure 2 The electrolytic plating layer 129. Other configurations of the through electrode TV13 are similar to... Figure 2 The configuration of the through electrode TV2 in the middle is similar.

[0257] An electrolytic plating layer 1029 is embedded in the opening portion 124 on the chemical plating layer 128. In this case, the electrolytic plating layer 1029 is continuously formed from the interior of the opening portion 124 to extend to the rear surface of the semiconductor substrate 111.

[0258] In this way, in Embodiment 6 described above, for example, the electroplated layer 1029 is embedded in the opening portion 124, in which the chemically plated layer 128 is formed on the bottom surface via the sputtered layer 126. Therefore, even in the event of a step coverage failure of the sputtered layer 126 at the bottom of the opening portion 124, the conductivity of the through electrode TV13 on the bottom surface of the opening portion 124 can be ensured, and the stress applied to the through electrode TV13 can be adjusted.

[0259] The following text will describe it. Figure 2 The through electrode TV2 is used in an example of a stacked chip with multiple chips stacked together. For a stacked chip with multiple chips stacked together, any one of the through electrodes TV1 and TV3 to TV13, in addition to the through electrode TV2, can be applied.

[0260] <7. Example 7>

[0261] In Embodiment 1 above, the through electrode TV2, on which the sputtered layer 126, chemical plating layer 128, and electrolytic plating layer 129 are sequentially stacked on the bottom surface of the opening portion 124, is connected to the wiring layer 112 via the semiconductor substrate 111. In Embodiment 7, the through electrode TV2, on which the sputtered layer 126, chemical plating layer 128, and electrolytic plating layer 129 are sequentially stacked on the bottom surface of the opening portion 124, is connected to the lower chip via the upper chip.

[0262] Figure 18 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 7.

[0263] In this diagram, the electronic device includes chips P21 and P22. Chip P22 is stacked on top of chip P21. Chip P22 is directly bonded to chip P21.

[0264] For the direct bonding of chips P21 and P22, pressure bonding of oxides can be used. This pressure bonding can be performed, for example, at a temperature of 250°C or lower, with the bonding surfaces in a plasma-activated state. In this case, oxides can be formed on the bonding surfaces of each of chips P21 and P22.

[0265] For example, in the plasma activation of the bonding surfaces of chips P21 and P22 using SiO2, the bonding surfaces can be irradiated with oxygen or nitrogen plasma to hydrophilize them. Then, based on the hydrogen bonds between OH groups formed on the bonding surfaces as a result of moisture adsorption from the air, the bonding surfaces can be brought into close contact. The OH groups are then decomposed by heat treatment, and the generated hydrogen diffuses into the interface layer, thereby achieving direct bonding based on oxygen-mediated Si-O-Si bonding. Here, plasma activation of the bonding surfaces prior to heat treatment improves moisture adsorption on the bonding surfaces, and the necessary bonding strength to ensure the reliability of electronic devices can be obtained even with heat treatment at temperatures of 250°C or lower.

[0266] Each of chips P21 and P22 may include a semiconductor element, an optical element, or a MEMS. The substrate used for each of chips P21 and P22 may be a semiconductor substrate, a dielectric substrate, or an organic substrate.

[0267] Chip P21 includes a semiconductor substrate 211 and a wiring layer 261. The wiring layer 261 is formed on the front surface of the semiconductor substrate 211. The wiring layer 261 is provided with wirings 271 and pad electrodes 291, which are embedded in an insulating layer. In addition, the wiring layer 261 is provided with vias 281 for interlayer connections. The pad electrodes 291 can be used for connections through electrodes TV2.

[0268] Furthermore, the gate electrode 241 embedded in the insulating layer is formed on the front surface side of the semiconductor substrate 211 via the gate insulating film 231. In this case, the semiconductor substrate 211 may have a channel region located below the gate electrode 241 and impurity diffusion layers located on both sides of the channel region. Sidewalls 251 may be formed on both sides of the gate electrode 241. In addition, an impurity diffusion layer 221 connected to the wiring 271 is formed in the semiconductor substrate 211.

[0269] Chip P22 includes a semiconductor substrate 212 and a wiring layer 262. The wiring layer 262 is formed on the front surface side of the semiconductor substrate 212. The wiring layer 262 is provided with wirings 272 embedded in an insulating layer. In addition, the wiring layer 262 is provided with vias 282 for interlayer connections.

[0270] Furthermore, a through electrode TV2 is formed in the semiconductor substrate 212 and the wiring layer 262, penetrating the semiconductor substrate 212 and the wiring layer 262 in the depth direction. The through electrode TV2 penetrates the chip P22 to reach the chip P21 and connects to the pad electrode 291. A back surface wiring 214 is formed on the back surface side of the semiconductor substrate 212 via an insulating layer 125. The back surface wiring 214 is connected to the through electrode TV2. Here, the back surface wiring 214 may include a sputtered layer 126 and an electroplated layer 129. Therefore, the electroless plating layer 128 can be excluded from the back surface wiring 214, and the increase in thickness and resistance of the back surface wiring 214 can be suppressed.

[0271] Furthermore, the gate electrode 242 embedded in the insulating layer is formed on the front surface side of the semiconductor substrate 212 via the gate insulating film 232. In this case, the semiconductor substrate 212 may have a channel region located below the gate electrode 242 and impurity diffusion layers located on both sides of the channel region. Sidewalls 252 may be formed on both sides of the gate electrode 242. In addition, an impurity diffusion layer 222 connected to the wiring 272 is formed in the semiconductor substrate 212.

[0272] The stacked structure of chips P21 and P22 can constitute a wafer-level chip-scale package (WLCSP). In a WLCSP, the planar dimensions and shape of chip P22 can be equal to those of chip P21. In this case, the horizontal position of the end of chip P21 can be aligned with the horizontal position of the end of chip P22.

[0273] The materials used for the wiring layers 261 and 262, the gate insulating films 231 and 232, and the insulating layers for the sidewalls 251 and 252 can be, for example, SiO2, SiN, or SiCN. The materials used for wiring 271 and 272, the back surface wiring 214, the vias 281 and 282, and the pad electrodes 291 can be, for example, metals such as Al, Cu, AlCu, AlSiCu, or Co. The materials used for the gate electrodes 241 and 242 can be, for example, polysilicon.

[0274] In this way, in Embodiment 7 described above, the through electrode TV2, on the bottom surface of the opening 124, in which the sputtered layer 126, the chemical plating layer 128, and the electrolytic plating layer 129 are sequentially stacked, is disposed in chip P22 and connected to chip P21. Therefore, while chip P22 is stacked on chip P21, wiring can be led out from chip P21 to the outside, and open-circuit defects in the stacked structure of chips P21 and P22 can be reduced.

[0275] <8. Example 8>

[0276] In Embodiment 7 above, the through electrode TV2 is disposed in the stacked structure of chips P21 and P22 stacked based on direct oxide bonding. In Embodiment 8, the through electrode TV2 is disposed in the stacked structure of chips bonded based on hybrid bonding.

[0277] Figure 19 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 8.

[0278] In this figure, the electronic device includes chips P31 and P32 instead of chips P21 and P22 in the above embodiment 7.

[0279] Chip P31 is configured to add a bonding electrode 311 to chip P21 of embodiment 7. Chip P32 is configured to add a bonding electrode 312 to chip P22 of embodiment 7. The other configurations of each of chips P31 and P32 in embodiment 8 are similar to the configurations of each of chips P31 and P32 in embodiment 7.

[0280] Bonding electrode 311 is formed in wiring layer 261. Bonding electrode 312 is formed in wiring layer 262. Bonding electrodes 311 and 312 can be used for direct bonding between chips P31 and P32. For direct bonding between chips P31 and P32, hybrid bonding can be used. In this case, bonding electrodes 311 and 312 are arranged at opposite positions. Then, based on a metal bonding such as Cu-Cu bonding, bonding electrodes 311 and 312 can be bonded to each other.

[0281] In this way, in embodiment 8 above, the through electrode TV2 is disposed in the stacked structure of chips P31 and P32 based on hybrid bonding. Therefore, when chip P32 is stacked on chip P31, a connection between chips P31 and P32 can be achieved, and while reducing open circuit defects in the stacked structure of chips P31 and P32, wiring can be led out from chip P31 to the outside.

[0282] <9. Example 9>

[0283] In Embodiment 7 above, the through electrode TV2 is disposed in the stacked structure of chips P21 and P22 stacked based on direct oxide bonding. In Embodiment 9, the through electrode TV2 is disposed in the stacked structure of chips P21 and P22 bonded via an adhesive layer.

[0284] Figure 20 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 9.

[0285] In this figure, the electronic device includes an adhesive layer 321 added to the electronic device of Embodiment 7 described above. The other configurations of the electronic device of Embodiment 9 are similar to those of the electronic device of Embodiment 7 described above.

[0286] An adhesive layer 321 is disposed between chips P21 and P22 and bonds chips P21 and P22 together. In this case, a through electrode TV2 penetrates chip P21 and adhesive layer 321 and is connected to chip P22. As a material for adhesive layer 321, for example, a resin (such as epoxy resin) can be used.

[0287] In this way, in embodiment 9 described above, the through electrode TV2 is disposed in the stacked structure of chips P21 and P22 bonded via adhesive layer 321. Therefore, when chip P12 is stacked on chip P11, wiring can be led out from chip P11, and open circuit defects in the stacked structure of chips P11 and P12 can be reduced.

[0288] <10. Example 10>

[0289] In Embodiment 7 above, the through electrode TV2 is disposed in the stacked structure of chips P21 and P22 stacked based on oxide direct bonding. In Embodiment 10, the through electrode TV2 is disposed in the stacked structure of chips based on CoW stacking.

[0290] Figure 21 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 10.

[0291] In this figure, the electronic device includes chip P42, replacing chip P22 in Embodiment 7 described above. An embedding layer 411 is formed around chip P42. Chip P42, together with the embedding layer 411, is stacked on chip P21 based on CoW. Chip P42 is directly bonded to chip P21. For the direct bonding between chips P21 and P42, pressure bonding of oxides can be used. Other configurations of the electronic device in Embodiment 10 are similar to those of the electronic device in Embodiment 7 described above.

[0292] Chip P42 includes a semiconductor substrate 412 and a wiring layer 462. The wiring layer 462 is formed on the front surface of the semiconductor substrate 412. The wiring layer 462 is provided with wiring 472 embedded in an insulating layer. In addition, the wiring layer 462 is provided with vias 482 for interlayer connections.

[0293] Furthermore, a through electrode TV2 is formed in the semiconductor substrate 412 and the wiring layer 462, penetrating the semiconductor substrate 412 and the wiring layer 462 in the depth direction. The through electrode TV2 penetrates the chip P42 to reach the chip P21 and connects to the pad electrode 291. A back surface wiring 214 is formed on the back surface side of the semiconductor substrate 412 via the insulating layer 125. The back surface wiring 214 is connected to the through electrode TV2.

[0294] Furthermore, a gate electrode 442 embedded in an insulating layer is formed on the front surface side of the semiconductor substrate 412 via a gate insulating film 432. In this case, the semiconductor substrate 412 may have a channel region located below the gate electrode 442 and impurity diffusion layers located on both sides of the channel region. Sidewalls 452 may be formed on both sides of the gate electrode 442. In addition, an impurity diffusion layer 422 connected to the wiring 472 is formed in the semiconductor substrate 412.

[0295] A structure in which chip P42, having an embedding layer 411 formed around chip P42, is stacked on chip P21 can constitute a wafer-level packaged semiconductor wafer-level package (WLCSP). In the WLCSP, the planar dimensions and shape of chip P22 can be equal to the outer dimensions and shape of the embedding layer 411 formed around chip P42. In this case, the horizontal position of the end of chip P21 can be aligned with the horizontal position of the end of embedding layer 411. The height of embedding layer 411 can be equal to the height of chip P42. The material of embedding layer 411 can be a molding resin or an inorganic material such as SiO2 or SiN. After embedding chip P42 into embedding layer 411, embedding layer 411 can be planarized by methods such as chemical mechanical polishing (CMP) or post-surface grinding.

[0296] In this way, in the above embodiment 10, the through electrode TV2 is disposed in the stacked structure of chips P21 and P42 based on CoW stacking. Therefore, when stacking chips P21 and P42 with different sizes, wiring can be led out from chip P21, and open circuit defects in the stacked structure of chips P21 and P42 can be reduced.

[0297] <11. Example 11>

[0298] In Embodiment 10, the through electrode TV2 is disposed in the stacked structure of chips P21 and P42 based on CoW stacking. In Embodiment 11, the through electrode TV2 is disposed in the stacked structure of chips based on hybrid bonding.

[0299] Figure 22 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 11.

[0300] In this figure, the electronic device includes chips P31 and P52, replacing chips P21 and P42 in the above embodiment 10.

[0301] Chip P52 is configured such that bonding electrode 312 is added to chip P42 in Embodiment 10 described above. An embedding layer 411 is formed around chip P52. Chip P52, together with the embedding layer 411, is stacked on chip P31 based on CoW. Chip P52 is directly bonded to chip P31. Other configurations of chip P52 in Embodiment 11 are similar to the configuration of chip P42 in Embodiment 10 described above.

[0302] Bonding electrode 312 is formed in wiring layer 462. Bonding electrodes 311 and 312 can be used for direct bonding between chips P31 and P52. For direct bonding between chips P31 and P52, hybrid bonding can be used. Then, based on metal bonding such as Cu-Cu bonding, bonding electrodes 311 and 312 can be bonded to each other.

[0303] In this way, in the above embodiment 11, the through electrode TV2 is disposed in the stacked structure of chips P31 and P52 based on hybrid bonding. Therefore, when stacking chips P31 and P52 with different sizes, the connection between chips P31 and P52 can be realized, and while reducing open circuit defects in the stacked structure of chips P31 and P52, wiring can be led out from chip P31.

[0304] Note that the electronic devices of Embodiments 10 or 11 described above can be configured as fan-out wafer-level packages (FOWLP).

[0305] <12. Example 12>

[0306] In Embodiment 10, a through electrode TV2 is connected to chip P21 through chip P42, which is stacked on chip P21 based on CoW. In Embodiment 12, a through electrode TV2 is connected to chip P21 through the embedding layer 411 surrounding chip P42, which is stacked on chip P21 based on CoW.

[0307] Figure 23 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 12.

[0308] In this figure, in this electronic device, the through electrode TV2 penetrates the embedded layer 411 and is connected to the chip P21. Other configurations of this electronic device are similar to those of the electronic device in Embodiment 10 described above.

[0309] In this way, in embodiment 12 described above, a through electrode TV2 is connected to chip P21 by penetrating the embedding layer 411 surrounding chip P42, which is stacked on chip P21 based on CoW. Therefore, while stacking chips P21 and P42 with different sizes, wiring can be routed from chip P21 to the outside, and open-circuit defects in the stacked structure of chips P21 and P42 can be reduced. In this case, the through electrode TV2 formed in chip P42 is not required, and the size of chip P42 can be reduced.

[0310] <13. Example 13>

[0311] In Embodiment 11 described above, a through electrode TV2, which is bonded to chip P52 on chip P31 via a hybrid bonding method, is connected to chip P21. In Embodiment 13, a through electrode TV2, which is bonded to chip P31 via an embedding layer 411 surrounding chip P52 on chip P32 via a hybrid bonding method, is connected to chip P31.

[0312] Figure 24 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 13.

[0313] In this figure, in this electronic device, the through electrode TV2 penetrates the embedded layer 411 and is connected to the chip P31. Other configurations of this electronic device are similar to those of the electronic device in Embodiment 11 described above.

[0314] In this way, in embodiment 13 described above, a through electrode TV2 is connected to chip P31 by penetrating the embedded layer 411 surrounding chip P52, which is bonded to chip P31 based on a hybrid bonding method. Therefore, while stacking chips P31 and P52, which have different sizes, wiring can be routed from chip P31 to the outside, and open-circuit defects in the stacked structure of chips P31 and P52 can be reduced. In this case, the through electrode TV2 formed in chip P52 is not required, and the size of chip P52 can be reduced.

[0315] <14. Example 14>

[0316] In Embodiment 1 above, the through electrode TV2 penetrating chip P22 is connected to chip P21. In Embodiment 14, the through electrode TV2 penetrating the semiconductor substrate is connected to the wiring layer on the semiconductor substrate.

[0317] Figure 25 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 14.

[0318] In this figure, the electronic device includes chip P72, replacing chip P22 in embodiment 7. The other configurations of the electronic device in embodiment 14 are similar to those of the electronic device in embodiment 7.

[0319] Chip P72 is configured such that pad electrodes 292 are added to chip P22 of Embodiment 7 described above. Pad electrodes 292 are formed in wiring layer 262. Through-electrode TV2 is connected to pad electrodes 292. In this configuration, through-electrode TV2 can penetrate semiconductor substrate 212 and reach wiring layer 262. Other configurations of chip P72 in Embodiment 14 are similar to those of chip P22 in Embodiment 7 described above.

[0320] In this way, in the above embodiment 14, the through electrode TV2 penetrating the semiconductor substrate 212 is connected to the wiring layer 262 on the semiconductor substrate 212. Therefore, while stacking chip P72 on chip P21, wiring can be led out from chip P72 to the outside, and open circuit defects in the stacked structure of chips P21 and P72 can be reduced.

[0321] <15. Example 15>

[0322] In Embodiment 7 above, the through electrode TV2 is disposed in the stacked structure of chips P21 and P22 stacked based on direct oxide bonding. In Embodiment 15, the through electrode TV2, which penetrates the upper chip and the middle chip, is connected to the lower chip.

[0323] Figure 26 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 15.

[0324] In the accompanying drawings, the electronic device is configured such that chip P22 is added to the electronic device of Embodiment 11 described above. Chip P22 is stacked on the rear surface side of chip P52, which is embedded in the embedding layer 411. In this case, the embedding layer 411 may cover the rear surface side of chip P52. Furthermore, in this electronic device, the through electrode TV2 sequentially penetrates chips P22 and P52 and is connected to chip P31. Other configurations of this electronic device are similar to those of the electronic device of Embodiment 11 described above.

[0325] In this way, in embodiment 15 described above, the through electrode TV2, which passes through chips P22 and P52 sequentially, is connected to chip P31. Therefore, while stacking chip P22 on a stacked structure of chips P31 and P52, which have different sizes from each other, wiring can be led out from chip P31 to the outside, and open circuit defects in the stacked structure of chips P22, P31, and P52 can be reduced.

[0326] <16. Example 16>

[0327] In embodiment 15, the through electrode TV2, which sequentially penetrates chips P22 and P52, is connected to chip P31. In embodiment 16, the through electrode TV2, which sequentially penetrates the embedding layer 411 surrounding chips P22 and P52, is connected to chip P31.

[0328] Figure 27 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 16.

[0329] In this figure, in this electronic device, the through electrode TV2 sequentially penetrates the embedding layer 411 surrounding chips P22 and P52 and connects to chip P31. Other configurations of this electronic device are similar to those of the electronic device in Embodiment 15 described above.

[0330] In this way, in embodiment 16 described above, the through electrode TV2, which sequentially penetrates the embedding layer 411 surrounding chips P22 and P52, is connected to chip P31. Therefore, while stacking chip P22 on a stacked structure of chips P31 and P52, which have different sizes, wiring can be routed from chip P31 to the outside, and open-circuit defects in the stacked structure of chips P22, P31, and P52 can be reduced. In this case, the through electrode TV2 formed in chip P52 is unnecessary, and the size of chip P52 can be reduced.

[0331] <17. Example 17>

[0332] In Embodiment 14, the through electrode TV2 penetrating the semiconductor substrate 212 is connected to the wiring layer 262 on the semiconductor substrate 212. In Embodiment 17, the through electrode TV2 penetrating the semiconductor substrate of the semiconductor chip stacked on the sensor chip is connected to the wiring layer on the semiconductor substrate.

[0333] Figure 28 This is a cross-sectional view illustrating a configuration example of an electronic device according to Embodiment 17. Note that this figure shows a configuration example of an electronic device 600 cut from a stacked wafer STW.

[0334] In this figure, the electronic device 600 includes a sensor chip P61 and a semiconductor chip P62. The semiconductor chip P62 is stacked on top of the sensor chip P61. The sensor chip P61 is directly bonded to the semiconductor chip P62. For the direct bonding between the sensor chip P61 and the semiconductor chip P62, a hybrid bonding method can be used.

[0335] A back-illuminated image sensor is formed in a sensor chip P61. The sensor chip P61 includes a semiconductor substrate 611 and a wiring layer 661. The wiring layer 661 is formed on the front surface side of the semiconductor substrate 611. The wiring layer 661 is provided with wiring embedded in an insulating layer. In addition, the wiring layer is provided with vias for interlayer connections.

[0336] An interlayer insulating layer 621 is formed between the semiconductor substrate 611 and the wiring layer 661. In this case, a gate electrode embedded in the interlayer insulating layer 621 is formed on the front surface side of the semiconductor substrate 611. In the semiconductor substrate 611, a channel region located below the gate electrode and impurity diffusion layers located on both sides of the channel region can be formed. Sidewalls can be formed on both sides of the gate electrode.

[0337] Furthermore, a light-receiving region RA is disposed on the rear surface side of the semiconductor substrate 611. The light-receiving region RA detects light incident upon it. Pixels and pixel transistors are arranged in a matrix along the row and column directions within the light-receiving region RA.

[0338] A pixel isolation layer 631 for isolating pixels is formed in the light-receiving region RA. The pixel isolation layer 631 may be formed on the rear surface side of the semiconductor substrate 611 to be embedded in the semiconductor substrate 611 at the boundary of the pixel. In addition, a photodiode 641 is formed for each pixel in the light-receiving region RA.

[0339] Furthermore, a light-shielding film 651 is formed on the rear surface side of the semiconductor substrate 611. The light-shielding film 651 can minimize color mixing of light incident on each photodiode 641 via the color filter 681. The material of the light-shielding film 651 can be black resin or a metal such as Cr. A planarization film 671 is formed on the light-shielding film 651. As a material for the planarization film 671, for example, SiO2, SiN, etc., can be used.

[0340] A color filter 681 is formed for each pixel on the planarization film 671. A stress relief layer 691 is formed on the color filter 681. An opening portion KS for stress adjustment is formed in the stress relief layer 691 in the depth direction. The opening portion KS can penetrate the stress relief layer 691 and reach the semiconductor substrate 611. As a material for the stress relief layer 691, for example, SiO2, SiN, etc. can be used.

[0341] On-chip lenses 632 and 633 are formed for each pixel on the stress relief layer 691. In this case, on-chip lenses 632 and 633 can have a double-layer structure. As materials for color filters 681 and on-chip lenses 632 and 633, for example, insulating films such as SiO2, SiN, or SiCN, or transparent resins such as acrylic or polycarbonate can be used. In this case, the materials of on-chip lenses 632 and 633 can have different compositions, microstructures, etc., from each other. For example, the materials of on-chip lenses 632 and 633 can be selected to optimize optical properties and minimize degradation due to moisture absorption, etc. Color filter 681 can include pigments. For example, color filter 681 can be formed into a Bayer array or a quad Bayer array. Color filter 681 can include an RGB color filter, a complementary color filter, or a white color filter. Lenses, dichroists, or deflectors configured with metasurfaces can be formed on the light-receiving region RA.

[0342] A planarization film 634 is formed on the on-chip lens 633. For example, SiO2, SiN, etc., can be used as the material for the planarization film 634.

[0343] Logic circuitry is formed in a semiconductor chip P62. The semiconductor chip P62 includes a semiconductor substrate 612 and a wiring layer 662. The wiring layer 662 is formed on the front surface side of the semiconductor substrate 612. The wiring layer 662 has wiring embedded in an insulating layer. Furthermore, the wiring layer 662 has vias for interlayer connections. Additionally, inspection pads KPD are provided in the wiring layer 662. The inspection pads KPD can be used to inspect the semiconductor chip P62. In this case, the semiconductor chip P62 can be inspected by contacting the inspection pads KPD with a probe before embedding the transparent resin layer 602 into the opening portion KD.

[0344] An interlayer insulating layer 622 is formed between the semiconductor substrate 612 and the wiring layer 662. In this case, a gate electrode embedded in the interlayer insulating layer 622 is formed on the front surface side of the semiconductor substrate 612. A channel region located below the gate electrode and impurity diffusion layers located on both sides of the channel region can be formed in the semiconductor substrate 612. Sidewalls can be formed on both sides of the gate electrode. Furthermore, a pad electrode 692 embedded in the interlayer insulating layer 622 is formed on the front surface side of the semiconductor substrate 612. The pad electrode 692 can be used for the connection of the through electrode TV2.

[0345] Furthermore, a through electrode TV2 penetrating the semiconductor substrate 612 in the depth direction is formed in the semiconductor substrate 612. The through electrode TV2 penetrates the semiconductor substrate 612 and is connected to the pad electrode 692. A back surface wiring 214 is formed on the back surface side of the semiconductor substrate 612 via an insulating layer 125. The back surface wiring 214 is connected to the through electrode TV2.

[0346] An opening, KD, is formed in both the sensor chip P61 and the semiconductor chip P62. The opening KD is positioned where the inspection pad KPD is exposed. In this configuration, the opening KD penetrates the sensor chip P61 and reaches the surface of the inspection pad KPD.

[0347] Furthermore, the opening KB is formed in the sensor chip P61 and the semiconductor chip P62. The opening KB is arranged along the scribing line. In this case, the opening KB can penetrate the sensor chip P61 and the wiring layer 662.

[0348] The transparent substrate 601 is bonded to the rear surface of the sensor chip P61 via a transparent resin layer 602. In this case, the transparent resin layer 602 is embedded in the openings KB and KD.

[0349] The stacked structure of sensor chip P61 and semiconductor chip P62 can constitute a wafer-level packaged semiconductor chip spacer (WLCSP). In the WLCSP, the planar dimensions and shape of sensor chip P61 can be equal to the planar dimensions and shape of semiconductor chip P62. Furthermore, the planar dimensions and shape of sensor chip P61 can be equal to the planar dimensions and shape of transparent substrate 601. In this case, the horizontal position of the end of sensor chip P61 can be aligned with the horizontal position of the end of semiconductor chip P62. Furthermore, the horizontal position of the end of sensor chip P61 can be aligned with the horizontal position of the end of transparent substrate 601.

[0350] The transparent substrate 601 can be a glass substrate, a quartz substrate, or a transparent resin substrate such as acrylic or polycarbonate. The transparent substrate 601 can be made of materials such as Al2O3, CaF2, MgF2, or LiF, depending on the wavelength detected in the light-receiving region RA.

[0351] The transparent resin layer 602 can be a thermosetting resin or a UV-curable resin. For example, transparent resins such as siloxane resins, acrylic resins, or epoxy resins can be used as the material for the transparent resin layer 602. In this case, the material of the transparent resin layer 602 can be selected to ensure a refractive index difference with the on-chip lenses 632 and 633. The transparent resin layer 602 may contain fillers such as glass fibers to improve reliability. A resin material with adjusted optical properties (such as refractive index and extinction coefficient) can be selected for the transparent resin layer 602 to ensure good light reception in the pixel region RA.

[0352] Figure 29 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 17.

[0353] In this figure, the partitioned regions RE are set in the stacked wafer STW. The stacked wafer STW includes a transparent substrate wafer 601W and semiconductor wafers 612W and 622W stacked thereon. The transparent substrate 601 is cut from the transparent substrate wafer 601W for each partitioned region RE. The semiconductor substrate 612 is cut from the semiconductor wafer 612W for each partitioned region RE. The semiconductor substrate 622 is cut from the semiconductor wafer 622W for each partitioned region RE. The partitioned regions RE are divided along scribing lines SBL. Each scribing line SBL is formed at the location of the opening portion KB. The electronic device 600 is cut from each partitioned region RE. In this case, the stacked wafer STW can be divided into electronic devices 600 by cutting along the scribing lines SBL.

[0354] Thus, in embodiment 17 described above, the through electrode TV2, which penetrates the semiconductor substrate 612 through the semiconductor chip P62 stacked on the sensor chip P61, is connected to the wiring layer 662. Therefore, when the semiconductor chip P62 is stacked on the sensor chip P61, wiring can be led out from the semiconductor chip P62 to the outside, and open-circuit defects in the electronic device 600 can be reduced.

[0355] Note that in embodiment 17 above, an example is shown where semiconductor chip P62 is stacked on sensor chip P61. Besides this example, sensor chip P61 can be used as chip P21 in embodiments 7, 9, 10, 12, or 14 above, or sensor chip P61 can be used as chip P31 in embodiments 8, 11, 13, 15, or 16 above.

[0356] <18. Example 18>

[0357] In Embodiment 1 above, a metal stack portion having a sputtered layer, a chemical plating layer, and an electrolytic plating layer stacked sequentially is provided on the bottom surface of the opening portion. In Embodiment 18, a capacitor is provided on the metal stack portion, which has a sputtered layer, a chemical plating layer, and an electrolytic plating layer stacked sequentially in the opening portion.

[0358] Figure 30 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 18.

[0359] In the same accompanying drawing, the electronic device includes a setting... Figure 1 The capacitor CA1 is located on the through electrode TV1. Other configurations of this electronic device are similar. Figure 1 The configuration of electronic devices in the system.

[0360] The capacitor CA1 includes capacitor electrodes CD11 and CD12 and a dielectric layer ED1. The capacitor electrodes CD11 and CD12 are arranged opposite to each other via the dielectric layer ED1. The capacitor CA1 is located in the opening 114. In this case, the capacitor CA1 can be continuously formed on the metal stack MT1 to extend to the side surface of the opening 114 and the rear surface of the semiconductor substrate 111.

[0361] A capacitor electrode CD11 is formed on the through electrode TV1, a dielectric layer ED1 is formed on the capacitor electrode CD11, and a capacitor electrode CD12 is formed on the dielectric layer ED1. An insulating layer Z1 is formed on the capacitor CA1 to cover the opening 114. In this case, a cavity CAV1 can be formed in the opening 114 below the insulating layer Z1.

[0362] A portion of the capacitor electrode CD11 on the rear surface of the semiconductor substrate 111 is exposed from the dielectric layer ED1, the capacitor electrode CD12, and the insulating layer Z1. Then, the external electrode D1 is connected to the capacitor electrode CD11 via the insulating layer Z1. Furthermore, a portion of the capacitor electrode CD12 on the rear surface of the semiconductor substrate 111 is exposed from the insulating layer Z1. Then, the external electrode D2 is connected to the capacitor electrode CD12 via the insulating layer Z1.

[0363] Materials used as capacitor electrodes CD11 and CD12 can be, for example, Cu, Ti, Ta, Al, W, Ni, Ru, Co, TiN, TaN, or WN, and stacked structures of multiple materials can also be used.

[0364] As the material for the dielectric layer ED1, for example, SiO2, SiON, Si3N4, hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), tantalum oxide (Ta2O5), titanium oxide (TiO2), lanthanum oxide (LaO3), yttrium oxide (Y2O3), aluminum nitride (AlN), hafnium oxynitride (HfON) or aluminum oxynitride (AlON) can be used, and a stacked structure of multiple materials can also be used.

[0365] As the material for insulating layer Z1, organic materials with polyimide, acrylic, organosilicon, or epoxy groups as the backbone can be used, or materials containing fillers such as SiO2, Al2O3, AlN, or BN can be used. Insulating layer Z1 can be a chemical vapor deposition (CVD) film or a coating film.

[0366] Figure 31 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 18.

[0367] In the same accompanying drawing, the electronic device includes a setting... Figure 2The capacitor CA2 is located on the through electrode TV2. Other configurations of this electronic device are similar. Figure 2 The configuration of electronic devices in the system.

[0368] The capacitor CA2 includes capacitor electrodes CD21 and CD22 and a dielectric layer ED2. The capacitor electrodes CD21 and CD22 are arranged opposite to each other via the dielectric layer ED2. The capacitor CA2 is located in the opening 124. In this case, the capacitor CA2 can be continuously formed on the metal stack MT2 to extend to the side surface of the opening 124 and the rear surface of the semiconductor substrate 111.

[0369] A capacitor electrode CD21 is formed on the through electrode TV2, a dielectric layer ED2 is formed on the capacitor electrode CD21, and a capacitor electrode CD22 is formed on the dielectric layer ED2. An insulating layer Z2 is formed on the capacitor CA2 to cover the opening 124. In this case, a cavity CAV2 can be formed in the opening 124 below the insulating layer Z2.

[0370] A portion of the capacitor electrode CD21 on the rear surface of the semiconductor substrate 111 is exposed from the dielectric layer ED2, the capacitor electrode CD22, and the insulating layer Z2. Then, the external electrode D1 is connected to the capacitor electrode CD21 via the insulating layer Z2. Furthermore, a portion of the capacitor electrode CD22 on the rear surface of the semiconductor substrate 111 is exposed from the insulating layer Z2. Then, the external electrode D2 is connected to the capacitor electrode CD22 via the insulating layer Z2.

[0371] Figures 32 to 34 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 18. Note that in Figures 32 to 34 In the example, the method used for manufacturing is described. Figure 31 This method is applicable to the manufacture of electronic devices, but it can also be applied to the manufacture of electronic devices. Figure 30 Methods for electronic devices.

[0372] exist Figure 32 In (a), a capacitor electrode CD21 is formed on the electrolytic plating layer 129 by a method such as sputtering. In this case, the capacitor electrode CD21 can be formed not only on the back surface side of the semiconductor substrate 111, but also on the bottom surface and side surface of the opening portion 124.

[0373] Next, as Figure 32 As shown in (b), a dielectric layer ED2 is formed on the capacitor electrode CD21 by sputtering or the like. In this case, the dielectric layer ED2 can be formed not only on the rear surface of the semiconductor substrate 111, but also on the bottom and side surfaces of the opening portion 124.

[0374] Next, as Figure 32 As shown in (c), a capacitor electrode CD22 is formed on the dielectric layer ED2 by sputtering or the like. In this case, the capacitor electrode CD22 can be formed not only on the back surface of the semiconductor substrate 111, but also on the bottom surface and side surface of the opening portion 124.

[0375] Next, as Figure 33 As shown in (a), a resist pattern PC is formed on the capacitor electrode CD22 using photolithography to cover the opening portion 124. In this case, the resist pattern PC can be formed to correspond to the planar shape of the capacitor CA2.

[0376] Next, as Figure 33 As shown in (b), capacitor CA2 is formed by etching capacitor electrodes CD21, CD22 and dielectric layer ED2 using a resist pattern PC as an etching mask. Dry etching, such as RIE, can be used to etch the capacitor electrodes CD21, CD22 and dielectric layer ED2. The resist pattern PC is then removed by ashing or similar methods.

[0377] Next, as Figure 33 As shown in (c), a resist pattern PD is formed on the capacitor electrode CD22 using photolithography to cover the opening portion 124. In this case, a portion of the capacitor electrode CD22 on the rear surface side of the semiconductor substrate 111 can be exposed through the resist pattern PD.

[0378] Next, as Figure 34 As shown in (a), the capacitor electrode CD22 and the dielectric layer ED2 are etched using a resist pattern PD as an etching mask, thereby exposing a portion of the capacitor electrode CD21. For etching the capacitor electrode CD22 and the dielectric layer ED2, dry etching (such as RIE) can be used. The resist pattern PD is then removed by ashing or the like.

[0379] Next, as Figure 34 As shown in (b), an insulating layer Z2 is formed on capacitor CA2 by sputtering or the like to cover the opening 124. In this case, cavity CAV2 can be formed in the opening 124 below the insulating layer Z2. Then, openings KA1 and KA2 are formed in the insulating layer Z2 at positions corresponding to the positions of external electrodes D1 and D2.

[0380] Next, as Figure 31 As shown, external electrode D1 is connected to capacitor electrode CD21 via opening KA1, and external electrode D2 is connected to capacitor electrode CD22 via opening KA2.

[0381] In this way, in embodiment 18 described above, for example, capacitor CA1 is disposed on a metal stack MT1 having a sputtered layer 116, a chemical plating layer 118, and an electrolytic plating layer 119 sequentially stacked in the opening 114. Therefore, even in the event of a step coverage failure of the sputtered layer 116 at the bottom of the opening 114, the conductivity of the capacitor electrode CD11 on the bottom surface of the opening 114 can be ensured, and open-circuit defects can be reduced while miniaturizing capacitor CA1.

[0382] <19. Example 19>

[0383] In Embodiment 18, a capacitor is disposed on a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked on the bottom surface of the opening, and an insulating layer is formed on the capacitor to cover the upper part of the opening. In Embodiment 19, a capacitor is disposed on a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked in the opening, and an insulating layer is formed along the surface of the capacitor.

[0384] Figure 35 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 19.

[0385] In this figure, the electronic device includes an insulating layer Z3 instead of... Figure 30 The insulating layer Z1. Other configurations of this electronic device are similar. Figure 30 The configuration of electronic devices in the system.

[0386] An insulating layer Z3 is formed along the surface of the capacitor CA1. In this case, the insulating layer Z3 can be provided on the bottom surface of the opening 114, the side surface of the opening 114, and the rear surface of the semiconductor substrate 111. Then, the external electrode D1 on the rear surface side of the semiconductor substrate 111 is connected to the capacitor electrode CD11 via the insulating layer Z3. Furthermore, the external electrode D2 is connected to the capacitor electrode CD12 via the insulating layer Z3.

[0387] As the material for the insulating layer Z3, for example, inorganic materials such as SiO2, SiON, SiOC, Si3N4 or SiCO can be used, or organic materials with polyimide, acrylic acid, siloxane or epoxy groups as the backbone can be used, and a stacked structure of multiple materials can also be used.

[0388] Figure 36 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 19.

[0389] In this figure, the electronic device includes an insulating layer Z4 instead. Figure 31 The insulating layer Z2. Other configurations of this electronic device are similar. Figure 31 The configuration of electronic devices in the system.

[0390] An insulating layer Z4 is formed along the surface of capacitor CA2. In this case, the insulating layer Z4 can be provided on the bottom surface of opening 124, the side surface of opening 124, and the rear surface of semiconductor substrate 111. Then, the external electrode D1 on the rear surface side of semiconductor substrate 111 is connected to capacitor electrode CD21 via insulating layer Z4. Furthermore, the external electrode D2 is connected to capacitor electrode CD22 via insulating layer Z4.

[0391] In this way, in embodiment 19 described above, for example, capacitor CA1 is disposed on a metal stack MT1 having a sputtered layer 116, a chemical plating layer 118, and an electrolytic plating layer 119 sequentially stacked in the opening 114, and an insulating layer Z3 is formed along the surface of capacitor CA1. Therefore, even in the event of a step coverage failure of the sputtered layer 116 at the bottom of the opening 114, the conductivity of the capacitor electrode CD11 on the bottom surface of the opening 114 can be ensured, and capacitor CA1 can be protected.

[0392] <20. Example 20>

[0393] In Embodiment 18, a capacitor is disposed on a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked on the bottom surface of the opening, and an insulating layer is formed on the capacitor to cover the upper part of the opening. In Embodiment 20, a capacitor is disposed on a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked in the opening, and an embedding layer is formed on the capacitor to embed into the opening.

[0394] Figure 37 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 20.

[0395] In this figure, the electronic device includes an embedded layer Z5 instead. Figure 30 The insulating layer Z1. Other configurations of this electronic device are similar. Figure 30 The configuration of electronic devices in the system.

[0396] An embedding layer Z5 is formed on the capacitor CA1 in such a way that the opening portion 114 is embedded with the embedding layer Z5. In this case, the embedding layer Z5 can be disposed from inside the opening portion 114 to extend to the rear surface of the semiconductor substrate 111. Then, the external electrode D1 on the rear surface side of the semiconductor substrate 111 is connected to the capacitor electrode CD11 via the embedding layer Z5. Furthermore, the external electrode D2 is connected to the capacitor electrode CD12 via the embedding layer Z5.

[0397] As the material for the intercalation layer Z5, organic materials with polyimide, acrylic acid, siloxane, or epoxy groups as the backbone can be used, or materials containing fillers such as SiO2, Al2O3, AlN, or BN can be used. The insulating layer Z1 can be a chemical vapor deposition (CVD) film or a coating film.

[0398] Figure 38 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 20.

[0399] In this figure, the electronic device includes an embedded layer Z6 instead. Figure 31 The insulating layer Z2. Other configurations of this electronic device are similar. Figure 31 The configuration of electronic devices in the system.

[0400] An embedding layer Z6 is formed on the capacitor CA2 to be embedded in the opening 124. In this case, the embedding layer Z6 can be disposed from inside the opening 124 to extend to the rear surface of the semiconductor substrate 111. Then, the external electrode D1 on the rear surface side of the semiconductor substrate 111 is connected to the capacitor electrode CD21 via the embedding layer Z6. In addition, the external electrode D2 is connected to the capacitor electrode CD22 via the embedding layer Z6.

[0401] In this way, in embodiment 20 described above, for example, capacitor CA1 is disposed on a metal stack MT1 having a sputtered layer 116, a chemical plating layer 118, and an electrolytic plating layer 119 sequentially stacked in the opening 114, and an embedding layer Z5 is formed on capacitor CA1 to embed into the opening 114. Therefore, even in the event of a step coverage failure of the sputtered layer 116 at the bottom of the opening 114, the conductivity of the capacitor electrode CD11 on the bottom surface of the opening 114 can be ensured, and capacitor CA1 can be protected.

[0402] <Example 21>

[0403] In Embodiment 18 described above, a capacitor is disposed on a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked on the bottom surface of the opening, and an insulating layer is formed on the capacitor to cover the upper part of the opening. In Embodiment 21, a capacitor is disposed on a metal stack having a sputtered layer, a chemical plating layer, and an electrolytic plating layer sequentially stacked in the opening, and a through electrode also serves as a first capacitor electrode.

[0404] Figure 39 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 21.

[0405] In this diagram, in this electronic device, [the following was removed] Figure 30The capacitor electrode CD11. In this case, the through electrode TV1 can be used instead of the capacitor electrode CD11. Other configurations of the electronic device are... Figure 30 The configurations of the electronic devices in the two systems are similar.

[0406] The capacitor CA3 includes a through electrode TV1, a capacitance electrode CD12, and a dielectric layer ED1. The through electrode TV1 and the capacitance electrode CD12 are arranged opposite to each other via the dielectric layer ED1. The capacitor CA3 is located in the opening 114. In this case, the capacitor CA3 can be continuously formed from the bottom surface of the opening 114 to extend to the side surface of the opening 114 and the rear surface of the semiconductor substrate 111.

[0407] A dielectric layer ED1 is formed on the through electrode TV1, and a capacitor electrode CD12 is formed on the dielectric layer ED1. An insulating layer Z1 is formed on the capacitor CA3 to cover the opening portion 114.

[0408] A portion of the through electrode TV1 on the rear surface of the semiconductor substrate 111 is exposed from the dielectric layer ED1, the capacitor electrode CD12, and the insulating layer Z1. An external electrode D1 is then connected to the through electrode TV1 via the insulating layer Z1. Furthermore, a portion of the capacitor electrode CD12 on the rear surface of the semiconductor substrate 111 is exposed from the insulating layer Z1. An external electrode D2 is then connected to the capacitor electrode CD12 via the insulating layer Z1.

[0409] Figure 40 This is a cross-sectional view showing another configuration example of the electronic device according to Embodiment 21.

[0410] In this diagram, in this electronic device, [the following was removed] Figure 31 The capacitor electrode CD21. In this case, the through electrode TV2 can be used instead of the capacitor electrode CD21. Other configurations of the electronic device are similar to... Figure 31 The configurations of the electronic devices in the two systems are similar.

[0411] The capacitor CA4 includes a through electrode TV2, a capacitance electrode CD22, and a dielectric layer ED2. The through electrode TV2 and the capacitance electrode CD22 are arranged opposite to each other via the dielectric layer ED2. The capacitor CA4 is located in the opening 124. In this case, the capacitor CA4 can be continuously formed from the bottom surface of the opening 124 to extend to the side surface of the opening 124 and the rear surface of the semiconductor substrate 111.

[0412] A dielectric layer ED2 is formed on the through electrode TV2, and a capacitor electrode CD22 is formed on the dielectric layer ED2. An insulating layer Z2 is formed on the capacitor CA4 to cover the opening portion 124.

[0413] A portion of the through electrode TV2 on the rear surface of the semiconductor substrate 111 is exposed from the dielectric layer ED2, the capacitor electrode CD22, and the insulating layer Z2. Then, the external electrode D1 is connected to the through electrode TV2 via the insulating layer Z2. Furthermore, a portion of the capacitor electrode CD22 on the rear surface of the semiconductor substrate 111 is exposed from the insulating layer Z2. Then, the external electrode D2 is connected to the capacitor electrode CD22 via the insulating layer Z2.

[0414] In this way, in embodiment 21 described above, for example, capacitor CA3 is disposed on a metal stack MT1 having a sputtered layer 116, a chemical plating layer 118, and an electrolytic plating layer 119 sequentially stacked in the opening portion 114, and the through electrode TV1 also serves as the lower capacitor electrode. Therefore, even in the event of a step coverage failure of the sputtered layer 116 at the bottom of the opening portion 114, open-circuit defects can be reduced while minimizing the complexity of the capacitor CA3 configuration.

[0415] It should be noted that in the above embodiments 18 to 21, it is shown that... Figure 1 Through electrode TV1 or Figure 2 An example of forming a capacitor on the through electrode TV2. Besides these, capacitors can also be formed on... Figure 3 Through electrode TV3, Figure 4 Through electrode TV4, Figure 8 Through electrode TV5, Figure 9 Through electrode TV6, Figure 10 Through-electrode TV7, Figure 11 Through electrode TV8, Figure 12 Through electrode TV9, Figure 13 Through electrode TV10 or Figure 14 The through electrode TV11. Furthermore, capacitors can also be formed on... Figures 18 to 28 On the through electrode set in the electronic device.

[0416] <Example 22>

[0417] In one example of Embodiment 1 described above, a chemical plating layer 128 is selectively formed on the sputtered layer 126 on the bottom surface of the opening portion 124, and then an electrolytic plating layer 129 is formed. In Embodiment 22, after the photosensitive insulating film is embedded in the skirt portion at the bottom surface of the opening portion 124, a sputtered layer 116, a chemical plating layer 118, and an electrolytic plating layer 119 are sequentially formed on the bottom surface of the opening portion 124.

[0418] Figure 41 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 22.

[0419] In this figure, the electronic device includes a through electrode TV22, in place of... Figure 2 The through electrode TV2. Furthermore, this electronic device has a connection with... Figure 2 Compared to the electronic device, the photosensitive insulating film 2201 is added. Other configurations of this electronic device are similar to... Figure 2 The configurations of the electronic devices in the two systems are similar.

[0420] At the bottom portion of the opening 124, a skirt portion 2200 is formed due to a notch. The skirt portion 2200 is formed to widen towards the bottom portion of the opening 124.

[0421] The photosensitive insulating film 2201 has positive photosensitivity. Inorganic materials can be used as the material for the photosensitive insulating film 2201. In this case, a photosensitizer can be mixed into the inorganic material to impart photosensitivity to the inorganic material. The photosensitive insulating film 2201 is embedded in the skirt portion 2200 of the opening portion 124 via the insulating layer 125. In this case, the side surface of the opening portion 124 can be planarized by using the photosensitive insulating film 2201 in the depth direction.

[0422] The through electrode TV22 can be configured as similar to Figure 1 The through electrode TV1. In this case, the through electrode TV22 includes a sputtered layer 116, a chemical plating layer 118 and an electrolytic plating layer 119 sequentially formed on the bottom surface of the opening portion 124.

[0423] Figure 42 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 22.

[0424] exist Figure 42 In (a), Figure 5 Following step (c), a photosensitive inorganic solvent is applied to the insulating layer 125 by coating or the like. In this case, the photosensitive inorganic solvent can be embedded in the opening portion 124. Then, based on baking of the photosensitive inorganic solvent, the solvent on the photosensitive inorganic solvent evaporates, and a photosensitive insulating film 2201 is formed on the insulating layer 125.

[0425] Next, as Figure 42 As shown in (b), the exposed areas of the photosensitive insulating film 2201 are made soluble based on the exposure of the photosensitive insulating film 2201. In this case, the photosensitive insulating film 2201 can be exposed in the depth direction of the opening portion 124, and the photosensitive insulating film 2201 can be made soluble in the vertical direction. Then, based on the development of the exposed photosensitive insulating film 2201, the exposed areas of the photosensitive insulating film 2201 are removed. In this case, the photosensitive insulating film 2201 is embedded in the skirt portion 2200 of the opening portion 124 via the insulating layer 125.

[0426] Next, as Figure 42 As shown in Figure c, a sputtered layer 116 is formed by sputtering on the bottom surface of the opening portion 124, the side surface of the photosensitive insulating film 2201, and the rear surface of the semiconductor substrate 111. Thereafter, the following steps are performed: Figure 6 The steps after c.

[0427] In this way, in Embodiment 22 described above, after the photosensitive insulating film 2201 is embedded in the skirt portion 2200 at the bottom surface of the opening portion 124, a sputtered layer 116, a chemically plated layer 118, and an electrolytically plated layer 119 are sequentially formed on the bottom surface of the opening portion 124. Therefore, even if a notch occurs at the bottom of the opening portion 124, the conductivity of the through electrode TV22 on the bottom surface of the opening portion 124 can be ensured, and open-circuit defects can be reduced while miniaturizing the through electrode TV22.

[0428] <23. Example 23>

[0429] In one example of Embodiment 1 above, a chemical plating layer 128 is selectively formed on the sputtered layer 126 on the bottom surface of the opening 124, and then an electroplating layer 129 is formed. In Embodiment 23, the barrier metal layer formed below the seed layer for electroplating includes an ALD film.

[0430] Figure 43 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 23.

[0431] In this figure, the electronic device includes a replacement Figure 2 The through electrode TV2 and the through electrode TV23. Other configurations of this electronic device are similar. Figure 2 The configuration of electronic devices in the system.

[0432] Through electrode TV23 includes replacement Figure 2 The sputtered layer 126 includes a barrier metal layer 126A and a seed layer 126B. Other configurations of the through electrode TV23 are similar. Figure 2 The configuration of the through electrode TV2 in the middle.

[0433] A barrier metal layer 126A is formed on the bottom surface of the opening 124, and may also be formed on the side surface of the opening 124 and on the rear surface of the semiconductor substrate 111 via an insulating layer 125. The barrier metal layer 126A on the bottom surface of the opening 124 can be separated from the barrier metal layer 126A on the side surface of the opening 124. For example, titanium (Ti) can be used as the material for the barrier metal layer 126A. In this case, the barrier metal layer 126A may include an ALD film. In this case, the barrier metal layer 126A may be configured using only an ALD film, or it may be configured using an ALD film and a sputtered film.

[0434] A seed layer 126B can be formed on the barrier metal layer 126A. The seed layer 126B can be used to form the electrolytic plating layer 129. The seed layer 126B on the bottom surface of the opening 124 can be separated from the seed layer 126B on the side surface of the opening 124. For example, Cu can be used as the material for the seed layer 126B. A chemical plating layer 128 is formed on the seed layer 126B on the bottom surface of the opening 124. The electrolytic plating layer 129 is formed on the chemical plating layer 128 and on the seed layer 126B on the side surface of the opening 124.

[0435] In this way, in the above embodiment 23, the barrier metal layer 126A formed below the seed layer 126B for electroplating includes an ALD film. Therefore, even if a notch occurs at the bottom of the opening 124, the coverage of the barrier metal layer 126A at the bottom surface of the opening 124 can be improved, and open-circuit defects can be reduced while miniaturizing the through electrode TV23.

[0436] <24. Example 24>

[0437] In one example of Embodiment 1 above, a chemical plating layer 128 is selectively formed on the sputtered layer 126 on the bottom surface of the opening 124, and then an electrolytic plating layer 129 is formed. In Embodiment 24, after a chemical plating layer is selectively formed on the sputtered layer 126 on the bottom surface of the opening 124, an insulating layer around the chemical plating layer is removed to add chemical plating, and then an electrolytic plating layer is formed.

[0438] Figure 44 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 24.

[0439] In this figure, the electronic device includes a replacement Figure 2 The through electrode TV24 is the through electrode of TV2. Other configurations of this electronic device are similar. Figure 2 The configuration of electronic devices in the system.

[0440] Through electrode TV24 includes replacement Figure 2 The chemical plating layer 128 and the electrolytic plating layer 129 are chemical plating layers 128A, 128B, and 2429. Other configurations of the through electrode TV24 are similar. Figure 2 The configuration of the through electrode TV2 in the middle.

[0441] A chemical plating layer 128A is formed on the sputtered layer 126 on the bottom surface of the opening 124. Here, the chemical plating layer 128A may protrude in the opening 124. In this case, the outer peripheral surface of the chemical plating layer 128A may be separated from the sputtered layer 126.

[0442] A chemical plating layer 128B is formed on a chemical plating layer 128A. Here, the chemical plating layer 128B can cover the outer peripheral surface of the chemical plating layer 128A. In this case, the chemical plating layer 128B can penetrate into the gap between the chemical plating layer 128A and the sputtered layer 116, and can be formed from the side surface of the sputtered layer 126 to its upper surface.

[0443] Electrolytic plating layer 2429 is formed on electroless plating layer 128B. In this case, electrolytic plating layer 2429 can be formed on electroless plating layer 128A to extend from the side surface of electroless plating layer 128A to its upper surface.

[0444] Figure 45 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 24.

[0445] exist Figure 45 In a, Figure 7 Following step a, based on chemical plating, a chemical plating layer 128A is selectively formed on the sputtered layer 126 on the bottom surface of the opening portion 124.

[0446] Next, as Figure 45 As shown in b, the insulating layer 127 on the sputtered layer 126 is removed by a method such as plasma etching. In this case, a gap can be formed between the sputtered layer 126 and the outer peripheral surface of the chemical plating layer 128A.

[0447] Next, as Figure 45 As shown in c, a chemical plating layer 128B is formed on the chemical plating layer 128A. In this case, the chemical plating layer 128B can be embedded in the gap between the sputtered layer 126 and the outer peripheral surface of the chemical plating layer 128A. Then, as... Figure 44 As shown, an electrolytic plating layer 2429 is formed on a chemical plating layer 128B based on electrolytic plating using a sputtered layer 126 as a seed layer.

[0448] In this manner, in Embodiment 24 described above, a chemical plating layer 128A is selectively formed on the sputtered layer 126 on the bottom surface of the opening portion 124, and then the insulating layer 127 surrounding the chemical plating layer 128A is removed to form a chemical plating layer 128B, followed by the formation of an electrolytic plating layer 2429. Therefore, even in the case of a notch at the bottom of the opening portion 124, the conductivity of the through electrode TV22 on the bottom surface of the opening portion 124 can be ensured while improving the deposition efficiency of the electrolytic plating layer 2429.

[0449] <25. Example 25>

[0450] In one example of Embodiment 1 above, a chemical plating layer 128 is selectively formed on the sputtered layer 126 on the bottom surface of the opening 124, and then an electrolytic plating layer 129 is formed. In Embodiment 25, the sputtered layer, the chemical plating layer, and the electrolytic plating layer are sequentially stacked on the bottom surface of the opening, wherein a plurality of skirt portions with different positions in the depth direction are formed.

[0451] Figure 46 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 25.

[0452] In this figure, the electronic device includes a through electrode TV25 instead of Figure 2 The through electrode TV2 in the middle. Other configurations of this electronic device are similar to... Figure 2 The configurations of the electronic devices in the two systems are similar.

[0453] An opening 2524 is formed in a semiconductor substrate 111. The opening 2524 can penetrate the semiconductor substrate 111 and reach the wiring layer 112. Skirt portions 2501 and 2502 are formed in the opening 2524 at different positions in the depth direction. Skirt portion 2501 can be located on the bottom surface of the opening 2524, and skirt portion 2502 can be located at the middle portion of the opening 2524. In this case, a step corresponding to skirt portion 2502 is formed on the inner peripheral surface of the opening 2524. An insulating layer 2525 is formed on the inner surface of the opening 2524. A through electrode TV 25 can be formed along the inner surface of the opening 2524 via the insulating layer 2525.

[0454] The sputtering layer 2526 can be formed on the bottom surface of the opening 2524, and also on the side surface of the opening 2524 and the rear surface of the semiconductor substrate 111 via the insulating layer 2525. On the bottom surface of the opening 2524, a chemical plating layer 2528 is formed on the sputtering layer 2526.

[0455] An electrolytic plating layer 2529 is formed on a chemical plating layer 2528. In this case, the electrolytic plating layer 2529 can be continuously formed on the chemical plating layer 2528 to extend via the sputtering layer 2526 to the side surface of the opening 2524 and the rear surface of the semiconductor substrate 111. The steps of the opening 2524 are reflected in the insulating layer 2525, the sputtering layer 2526, and the chemical plating layer 2528.

[0456] Figure 47 and Figure 48 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 25.

[0457] exist Figure 47 In (a), a resist pattern RS1 is formed on a semiconductor substrate 111 using photolithography. An opening KA3 is provided in the resist pattern RS1. The opening KA3 is located at the position of the opening 2524.

[0458] Next, as Figure 47 As shown in (b), an opening 2524' is formed in the semiconductor substrate 111 based on anisotropic etching using a resist pattern RS1 as an etching mask. The depth of the opening 2524' can be shallower than the depth of the opening 2524. Here, a skirt portion 2502 is formed on the bottom surface of the opening 2524' due to a notch. In this case, by making the depth of the opening 2524' shallower than the depth of the opening 2524, the skirt portion 2502 can be smaller compared to the case where the depth of the opening 2524' is equal to the depth of the opening 2524.

[0459] Next, as Figure 47 As shown in (c), the resist pattern RS1 is removed by a method such as ashing. Then, a resist pattern RS2 is formed on the semiconductor substrate 111 using photolithography to cover the side surface of the opening 2524'. The resist pattern RS2 can be removed from the bottom of the opening 2524'.

[0460] Next, as Figure 48 As shown in (a), an opening 2524' is formed in the semiconductor substrate 111 based on anisotropic etching using a resist pattern RS2 as an etching mask. Here, a skirt portion 2501 is formed on the bottom surface of the opening 2524' due to a notch. In this case, the opening 2524 is formed via the opening 2524', while the opening 2524 is not formed via the opening 2524'. Figure 2 Compared to the case of the opening portion 124, the skirt portion 2501 can be smaller.

[0461] Next, as Figure 48As shown in (b), the resist pattern RS2 is removed by a method such as ashing. Then, by performing... Figure 5 The steps following (c) are used to form the through electrode TV25.

[0462] In this manner, in Embodiment 25 described above, the sputtered layer 2526, the chemical plating layer 2528, and the electrolytic plating layer 2529 are sequentially stacked on the bottom surface of the opening portion 2524, forming multiple skirt portions 2501 and 2502 with different positions in the depth direction. Therefore, even when the depth of the opening portion 2524 is large, the increase in the notch shape can be reduced, and open-circuit defects can be reduced while achieving miniaturization of the through electrode TV25.

[0463] <26. Example 26>

[0464] In one example of Embodiment 1 above, a chemical plating layer 128 is selectively formed on the sputtered layer 126 on the bottom surface of the opening 124, and then an electrolytic plating layer 129 is formed. In Embodiment 26, a SIMOX layer is disposed on the entire substrate at a midpoint in the depth direction of the opening to surround the periphery of the opening, and the sputtered layer, chemical plating layer, and electrolytic plating layer are sequentially stacked on the bottom surface of the opening.

[0465] Figure 49 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 26.

[0466] In this figure, the electronic device includes a through electrode TV26 instead of Figure 2 The through electrode TV2 in the middle. Other configurations of this electronic device are similar to... Figure 2 The configurations of the electronic devices in the two systems are similar.

[0467] A SIMOX layer 2611 is formed in a semiconductor substrate 111. The SIMOX layer 2611 may be disposed at the center in the depth direction of the semiconductor substrate 111. An opening 2624 is formed in the semiconductor substrate 111. The opening 2624 may penetrate the semiconductor substrate 111 and the SIMOX layer 2611 and reach the wiring layer 112. Skirt portions 2601 and 2602 are formed in the opening 2624 at different positions in the depth direction. Skirt portion 2601 may be located on the bottom surface of the opening 2624, and skirt portion 2602 may be located on the SIMOX layer 2611. An insulating layer 2625 is formed on the inner surface of the opening 2624. A through electrode TV 26 may be formed along the inner surface of the opening 2624 via the insulating layer 2625.

[0468] The sputtering layer 2626 can be formed on the bottom surface of the opening 2624, and also on the side surface of the opening 2624 and the rear surface of the semiconductor substrate 111 via the insulating layer 2625. On the bottom surface of the opening 2624, a chemical plating layer 2628 is formed on the sputtering layer 2626.

[0469] An electrolytic plating layer 2629 is formed on a chemical plating layer 2628. In this case, the electrolytic plating layer 2629 can be continuously formed on the chemical plating layer 2628 to extend via the sputtering layer 2626 to the side surface of the opening portion 2624 and the rear surface of the semiconductor substrate 111.

[0470] Figure 50 and Figure 51 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 26.

[0471] exist Figure 50 In (a), a wiring layer 112 is formed on a semiconductor substrate 111.

[0472] like Figure 50 As shown in (b), after oxygen ions are implanted into the semiconductor substrate 111, a SIMOX layer 2611 is formed in the semiconductor substrate 111 by heat treatment of the semiconductor substrate 111.

[0473] like Figure 50 As shown in (c), a resist pattern RS4 is formed on a semiconductor substrate 111 using photolithography. An opening KA6 is provided in the resist pattern RS4. The opening KA6 is located at the position of the opening 2624.

[0474] Next, as Figure 51 As shown in (a), an opening 2624' is formed in the semiconductor substrate 111 based on anisotropic etching using a resist pattern RS4 as an etching mask. The depth of the opening 2624' can be set to the position of the SIMOX layer 2611 in the depth direction. Here, a skirt portion 2602 is formed at the bottom surface of the opening 2624' due to a notch. In this case, by setting the depth of the opening 2624' to the position of the SIMOX layer 2611 in the depth direction, the skirt portion 2602 can be smaller compared to the case where the depth of the opening 2624' is equal to the depth of the opening 2624.

[0475] Next, as Figure 51As shown in (b), the opening portion 2624 is formed by anisotropic etching using a resist pattern RS4 as an etching mask. Here, due to the notch, a skirt portion 2601 is formed on the bottom surface of the opening portion 2624'. In this case, the opening portion 2624 is formed via the opening portion 2624', which is different from the case where there is no opening portion 2624' in between. Figure 2 Compared to the case of opening portion 124, skirt portion 2601 can be smaller.

[0476] Next, as Figure 51 As shown in (c), the resist pattern RS4 is removed by a method such as ashing. Then, by performing... Figure 5 The steps following (c) are used to form the through electrode TV26.

[0477] In this manner, in Embodiment 26 described above, the SIMOX layer 2611 is disposed on the entire semiconductor substrate 111 at the midpoint of the depth direction of the opening 2624, surrounding the periphery of the opening 2624, and the sputtered layer 2626, the chemical plating layer 2628, and the electrolytic plating layer 2629 are sequentially stacked on the bottom surface of the opening 2624. Therefore, even when the depth of the opening 2624 is large, the increase in the notch shape can be reduced, and open-circuit defects can be reduced while achieving miniaturization of the through electrode TV26.

[0478] <27. Example 27>

[0479] In Embodiment 26 described above, the SIMOX layer 2611 is disposed on the entire semiconductor substrate 111 at a midpoint in the depth direction of the opening 2624, surrounding the periphery of the opening 2624. In Embodiment 27, the SIMOX layer is disposed in a portion of the semiconductor substrate 111 at a midpoint in the depth direction of the opening 2624, surrounding the periphery of the opening 2624.

[0480] Figure 52 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 27.

[0481] In the same accompanying drawing, the electronic device includes a replacement Figure 49 The through electrode TV26 and the through electrode TV27. Other configurations of this electronic device are similar. Figure 49 The configuration of electronic devices in the system.

[0482] The through electrode TV27 can be configured to be similar to Figure 49The through electrode TV26. Meanwhile, a SIMOX layer 2711 is disposed in the semiconductor substrate 111 at a midpoint in the depth direction of the opening 2624, surrounding the periphery of the opening 2624. The SIMOX layer 2711 may be disposed only around the periphery of the opening 2624.

[0483] Figure 53 and Figure 54 This is a cross-sectional view illustrating an example of a method for manufacturing an electronic device according to Embodiment 27.

[0484] exist Figure 53 In (a), a resist pattern RS5 is formed on a semiconductor substrate 111 using photolithography. An opening KA7 is provided in the resist pattern RS5. The opening KA7 is located at a position overlapping with the SIMOX layer 2711.

[0485] Next, as Figure 53 As shown in (b), a SIMOX layer 2711 is formed in a semiconductor substrate 111 by ion implantation using a resist pattern RS5 as a mask.

[0486] Next, as Figure 53 As shown in (c), a resist pattern RS4 is formed on a semiconductor substrate 111 using photolithography. An opening KA6 is provided in the resist pattern RS4. The opening KA6 is located at the position of the opening 2624.

[0487] Next, as Figure 54 As shown, in performing something similar to Figure 51 After the steps, by executing Figure 5 The subsequent steps (c) are used to form the through electrode TV27.

[0488] In this way, in the above embodiment 27, the SIMOX layer 2711 is disposed in a portion of the semiconductor substrate 111 at the middle position in the depth direction of the opening 2624, surrounding the periphery of the opening 2624. Therefore, even when the depth of the opening 2624 is large, the increase in the notch shape can be reduced, and open-circuit defects can be reduced while achieving miniaturization of the through electrode TV27.

[0489] Note that any of the capacitors in Embodiments 18 to 21 can be formed on the through electrodes TV22 to TV27 of Embodiments 22 to 27. Furthermore, the through electrodes TV22 to TV27 of Embodiments 22 to 27 can be applied to the chips of Embodiments 7 to 17.

[0490] <28. Example 28>

[0491] In Embodiment 1 described above, a metal stack MT1, in which a sputtered layer 116, a chemical plating layer 118, and an electrolytic plating layer 119 are stacked, is provided in the opening portion 114. In Embodiment 28, a structure is adopted in which a metal stack containing a chemical plating layer, a sputtered layer, and an electrolytic plating layer is provided in the opening portion, the chemical plating layer is embedded in a wiring layer provided below the opening portion, and no wiring is provided below the chemical plating layer.

[0492] Figure 55 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 28.

[0493] In the same accompanying drawing, the electronic device includes a replacement Figure 8 The through electrode TV5 and the through electrode TV28 and the wiring layer 2812 of the wiring layer 112. Other configurations of this electronic device are similar. Figure 8 The configuration of electronic devices in the system.

[0494] Wiring layer 2812 is formed on semiconductor substrate 111. Wiring layer 2812 has wiring 2813 embedded in an insulating layer formed therein. Insulating layers 2814 and 2815 are sequentially stacked on wiring layer 2812. Insulating layer 2814 may be a pre-metal dielectric (PMD) layer. Insulating layer 2815 may be a shallow trench isolation (STI) layer. The materials of insulating layers 2814 and 2815 may be oxide films or nitride films.

[0495] Furthermore, wiring layer 2812 includes a recess KA. Recess KA is connected to opening portion 114 via insulating layers 2814 and 2815. In this configuration, wiring 2813 may be exposed on the side surface of recess KA. Alternatively, wiring 2813 may be configured not to be exposed on the bottom surface of recess KA. Additionally, a protective ring GR is formed around recess KA. The protective ring GR may surround the periphery of recess KA. The planar shape of the protective ring GR may be annular or rectangular.

[0496] An insulating layer 115 is formed on the inner surface of the opening 114. The insulating layer 115 can be continuously formed from the side surface of the opening 114 to the rear surface of the semiconductor substrate 111. In this case, the insulating layer 115 can contact the insulating layer 2814 via the insulating layer 2815.

[0497] The through electrode TV28 penetrates the semiconductor substrate 111 and connects to the wiring layer 2812. The through electrode TV28 includes a metal stack MT28. The metal stack MT28 is disposed at the end of the through electrode TV28. The end of the through electrode TV28 may be located at the bottom of the opening 114. The metal stack MT28 may use a stacked structure of a chemical plating layer 2818, a sputtering layer 116, and an electrolytic plating layer 2819. The metal stack MT28 may include a barrier metal layer 120 between the chemical plating layer 2818 and the sputtering layer 116.

[0498] The electroless plating layer 2818 is embedded in the recess KA. In this case, the electroless plating layer 2818 can be electrically connected to the guard ring GR. The barrier metal layer 120, the sputtered layer 116, and the electrolytic plating layer 2819 are sequentially stacked on the electroless plating layer 2818.

[0499] A barrier metal layer 120 can be continuously formed on the electroless plating layer 2818 to extend from the side surface of the insulating layer 115 to the upper surface of the insulating layer 115. A sputtered layer 116 can be continuously formed on the bottom surface of the barrier metal layer 120 to extend from the side surface of the barrier metal layer 120 to the upper surface of the barrier metal layer 120. An electrolytic plating layer 2819 can be continuously formed on the bottom surface of the sputtered layer 116 to extend from the side surface of the sputtered layer 116 to the upper surface of the sputtered layer 116. Note that a portion of the barrier metal layer 120 can be located in the recess KA, portions of the barrier metal layer 120 and the sputtered layer 116 can be located in the recess KA, or portions of the barrier metal layer 120, the sputtered layer 116, and the electrolytic plating layer 2819 can be located in the recess KA.

[0500] Figures 56 to 61 This is a diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 28. Note that... Figure 56 (a) to Figure 61 (a) is a cross-sectional view illustrating an example of a method for manufacturing the electronic device of Embodiment 28, and Figure 56 (b) to Figure 61 (b) is a plan view illustrating an example of a method for manufacturing the electronic device of Embodiment 28. Furthermore, in Figure 56 (b) to Figure 61 In (b), the planar shape of wiring 2813 is shown in perspective.

[0501] exist Figure 56In this configuration, an insulating layer 2815 is embedded in the semiconductor substrate 111. In this case, the insulating layer 2815 can be positioned around the location where a recess KA is to be formed in the semiconductor substrate 111. Then, an insulating layer 2814 is formed on the semiconductor substrate 111 and the insulating layer 2815 using a method such as CVD. Next, a wiring layer 2812 is formed on the insulating layer 2814. Wiring 2813, including a guard ring GR, is formed in the wiring layer 2812.

[0502] Next, as Figure 57 As shown, an opening 114 is formed in the semiconductor substrate 111 by selective etching from the rear surface side of the semiconductor substrate 111. For example, the etching of the semiconductor substrate 111 can be performed using anisotropic etching (such as reactive ion etching (RIE)).

[0503] Next, as Figure 58 As shown, an insulating layer 2814 is formed on a semiconductor substrate 111 and an insulating layer 2815 using a method such as CVD. In this case, the insulating layer 115 can cover the back surface of the semiconductor substrate 111.

[0504] Next, as Figure 59 As shown, a recess KA is formed in the wiring layer 2812 by selectively etching the insulating layer 2814 and the wiring layer 2812 via the opening portion 114. For example, the etching of the insulating layer 2814 and the wiring layer 2812 can be performed using anisotropic etching (such as reactive ion etching (RIE)). In this case, the recess KA can be arranged in a self-aligned manner relative to the opening portion 114. Furthermore, a portion of the wiring 2813 can be exposed at a side surface location of the recess KA.

[0505] Next, as Figure 60 As shown, a chemical plating layer 2818 is formed in the recess KA based on chemical plating.

[0506] Next, as Figure 61 As shown, a barrier metal layer 120 and a sputtered layer 116 are formed on a chemical plating layer 2818 by sputtering. Then, an electroplated layer 2819 is formed on the sputtered layer 116 based on electroplating using the sputtered layer 116 as a seed layer.

[0507] In this way, in the above embodiment 28, a metal stack portion MT28 in which a chemical plating layer 2818, a sputtered layer 116, and an electrolytic plating layer 2819 are stacked is provided in the opening portion 114. Therefore, even if a step coverage failure of the sputtered layer 116 occurs at the bottom of the opening portion 114, the conductivity of the through electrode TV28 on the bottom surface of the opening portion 114 can be ensured, and open circuit defects can be reduced while miniaturizing the through electrode TV28.

[0508] Furthermore, the electroless plating layer 2818 is embedded in the wiring layer 2812 located below the opening 114. In this case, a circuit design in which no wiring exists below the electroless plating layer 2818 can be adopted. The through electrode TV28 ensures conductivity through the electroless plating layer 2818 and the wiring layer 2812, while ensuring that the wiring 2813 does not exist below the opening 114. Therefore, the residue of etching products generated on the bottom and side surfaces of the opening 114 during etching of the insulating layer 115, the insulating layer 2814, and the wiring layer 2812 can be avoided, and yield and reliability can be improved.

[0509] <29. Example 29>

[0510] In embodiment 28 described above, a structure is adopted in which the chemical plating layer 2818 is embedded in the wiring layer 2812 provided below the opening portion 114 and no wiring 2813 is provided that contacts the area below the chemical plating layer 2818. In embodiment 29, the chemical plating layer 2818 is embedded in the wiring layer 2812 provided below the opening portion 114, and the wiring 2813 is located below the chemical plating layer 2818.

[0511] Figure 62 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 29.

[0512] In this figure, the electronic device includes wiring layer 2912, replacing... Figure 55 The wiring layer is 2812. Other configurations of this electronic device are similar. Figure 55 The configuration of electronic devices in the system.

[0513] Wiring layer 2912 is formed on semiconductor substrate 111. Wiring layer 2912 has wiring 2913 embedded in an insulating layer formed therein. Insulating layers 2814 and 2815 are deposited and formed between wiring layer 2912 and semiconductor substrate 111.

[0514] Furthermore, the wiring layer 2912 includes a recess KA. The recess KA is connected to the opening portion 114 via insulating layers 2814 and 2815. In this case, the wiring 2913 can be exposed from the bottom surface of the recess KA.

[0515] The through electrode TV28 penetrates the semiconductor substrate 111 and connects to the wiring layer 2912. In this case, the bottom surface of the chemical plating layer 2818 can be allowed to contact the wiring 2913.

[0516] Figures 63 to 68 This is a diagram illustrating an example of a method for manufacturing an electronic device according to Embodiment 29. Note that... Figure 63 (a) to Figure 68(a) is a cross-sectional view illustrating an example of a method for manufacturing the electronic device of Embodiment 29, and Figure 63 (b) to Figure 68 (b) is a plan view illustrating an example of a method for manufacturing the electronic device of Embodiment 29. Furthermore, in Figure 63 (b) to Figure 68 In (b), the planar shape of wiring 2813 is shown in perspective.

[0517] exist Figures 63 to 68 In this embodiment, except that the wiring layer 2812 in embodiment 28 is changed to wiring layer 2912, the manufacturing method of the electronic device according to embodiment 29 is the same as... Figures 56 to 61 The steps are similar. Meanwhile, in Figure 66 In the process, a recess KA is formed in the wiring layer 2912 by selectively etching the insulating layer 2814 and the wiring layer 2912 via the opening portion 114. In this case, a portion of the wiring 2913 is exposed at the bottom surface of the recess KA. Furthermore, in Figure 67 In the step, the chemical plating layer 2818 is embedded in the recess KA, allowing the bottom surface of the chemical plating layer 2818 to contact the wiring 2913.

[0518] In this way, in the above embodiment 29, the chemical plating layer 2818 is embedded in the wiring layer 2912 disposed below the opening portion 114, and the wiring 2813 exists below the chemical plating layer 2818. Therefore, the conductivity between the through electrode TV28 and the wiring layer 2912 can be ensured while reducing the contact resistance between the through electrode TV28 and the wiring layer 2912; thus, the electromigration resistance can be improved.

[0519] <30. Example 30>

[0520] In embodiment 28 described above, a structure is adopted in which the chemical plating layer 2818 is embedded in the wiring layer 2812 provided below the opening portion 114, and no wiring 2813 is provided below the chemical plating layer 2818. In embodiment 30, a structure is adopted in which the chemical plating layer 2818 is embedded in the wiring layer 2812 provided below the opening portion 124 that widens in the depth direction, and no wiring 2813 is provided that contacts the area below the chemical plating layer 2818.

[0521] Figure 69 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 30.

[0522] In this figure, the electronic device includes a through electrode TV30 and an opening 124, in place of... Figure 55 The through electrode TV28 and the opening portion 114 are located within it. Other configurations of this electronic device are... Figure 55 The configurations of the electronic devices in the two systems are similar.

[0523] The through electrode TV30 includes a barrier metal layer 3030, a sputtered layer 3026, and an electroplated layer 3029, to replace Figure 55 The barrier metal layer 120, sputtered layer 116, and electroplated layer 2819 are included. Other configurations of the through electrode TV30 are similar to... Figure 55 The configuration of the through electrode TV28 is similar.

[0524] A barrier metal layer 3030, a sputtered layer 3026, and an electroplated layer 3029 are sequentially stacked on a chemical plating layer 2818. The barrier metal layer 3030, sputtered layer 3026, and electroplated layer 3029 are formed in the depth direction along the shape of the opening 124. In this case, the barrier metal layer 3030, sputtered layer 3026, and electroplated layer 3029 may have a shape that widens in the depth direction of the opening 124. Note that a portion of the barrier metal layer 3030 may be located in the recess KA, a portion of the barrier metal layer 3030 and a portion of the sputtered layer 3026 may be located in the recess KA, or a portion of the barrier metal layer 3030, sputtered layer 3026, and electroplated layer 3029 may be located in the recess KA.

[0525] In this way, in the above embodiment 30, the electroless plating layer 2818 is embedded in the wiring layer 2812 disposed below the opening portion 124 which widens in the depth direction, and the wiring 2813 is not arranged below the electroless plating layer 2818. Therefore, the residue of etching products generated when etching the insulating layer 125, the insulating layer 2814 and the wiring layer 2812 on the bottom and side surfaces of the opening portion 124 can be avoided, and the conductivity between the through electrode TV30 and the wiring layer 2812 can be ensured.

[0526] Note that although the configuration of the through electrode TV30 being connected to the wiring layer 2812 has been shown in the above embodiment 30, the through electrode TV30 may also be connected to the wiring layer 2912.

[0527] <31. Example 31>

[0528] In embodiment 30 described above, the following structure is employed: a chemical plating layer 2818 is embedded in a wiring layer 2812 disposed below an opening portion 124 that widens in the depth direction, and wiring 2813 is not arranged below the chemical plating layer 2818. In embodiment 31, a chemical plating layer on which an electrolytic plating layer is stacked is disposed on the bottom surface of the opening portion, and a through-hole embedded in the semiconductor substrate 111 is formed below the chemical plating layer, and the through-hole is formed using a sputtered film.

[0529] Figure 70This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 31.

[0530] In this figure, a recess 3111 is formed in the semiconductor substrate 111. A via 3112 or wiring 3112 (hereinafter referred to as via 3112 for simplicity) is embedded in the recess 3111. In this case, an insulating layer 3113 is formed between the recess 3111 and the via 3112, so that the semiconductor substrate 111 and the via 3112 are insulated from each other. The via 3112 can be formed using a sputtered film. For example, Cu can be used as the material for the via 3112.

[0531] A wiring layer 112 is formed on a semiconductor substrate 111. A via 3112 may be located on the wiring layer 112. In this case, the via 3112 may protrude from the wiring layer 112. The via 3112 may be electrically connected to wiring 113.

[0532] Furthermore, an opening 3124 is formed in the semiconductor substrate 111. The opening 3124 may be disposed below the recess 3111. The opening 3124 may penetrate the semiconductor substrate 111 and reach the through hole 3112. The opening 3124 may have a shape that widens towards the bottom surface.

[0533] An insulating layer 3125 is formed on the inner surface of the opening 3124. The insulating layer 3125 can be continuously formed from the side surface of the opening 3124 to the rear surface of the semiconductor substrate 111.

[0534] A through electrode TV31 is formed in the opening portion 3124 via an insulating layer 3125. The through electrode TV31 is disposed on the through hole 3112. In this case, the through electrode TV31 can be electrically connected to the through hole 3112. The through electrode TV31 includes a chemical plating layer 3128, a sputtered layer 3126, and an electrolytic plating layer 3129.

[0535] A chemical plating layer 3128 is formed on the through hole 3112 in the opening portion 3124. In this case, the chemical plating layer 3128 can be electrically connected to the through hole 3112.

[0536] The sputtered layer 3126 can be formed on the side surface of the opening 3124 and the rear surface of the semiconductor substrate 111 via the insulating layer 3125. The sputtered layer 3126 can be used as a seed layer for forming the electrolytic plating layer 3129.

[0537] An electrolytic plating layer 3129 is formed on the electroless plating layer 3128 and the sputtering layer 3126. The electrolytic plating layer 3129 can be continuously formed on the electroless plating layer 3128 to extend via the sputtering layer 3126 to the side surface of the opening portion 3124 and the rear surface of the semiconductor substrate 111. The sputtering layer 3126 and the electrolytic plating layer 3129 are formed to conform to the shape of the opening portion 3124 in the depth direction. In this case, the sputtering layer 3126 and the electrolytic plating layer 3129 can have a shape that widens in the depth direction of the opening portion 3124.

[0538] In this manner, in embodiment 31 described above, a chemical plating layer 3128 on which an electrolytic plating layer 3129 is stacked is formed on the bottom surface of the opening portion 3124, and a through-hole 3112 embedded in the semiconductor substrate 111 is formed below the chemical plating layer 3128, and the through-hole 3112 is formed using a sputtered film. Therefore, the depth of the through electrode TV31 can be less than the thickness of the semiconductor substrate 111, and the filling performance of the electrolytic plating layer 3129 can be improved. Therefore, the miniaturization of the through electrode TV31 can be achieved while reducing open-circuit defects (step coverage failures).

[0539] <32. Example 32>

[0540] In Embodiment 31, a chemical plating layer 3128 on which an electrolytic plating layer 3129 is stacked is formed on the bottom surface of the opening portion 3124. A through-hole 3112 embedded in the semiconductor substrate 111 is formed below the chemical plating layer 3128, and the through-hole 3112 is formed using a sputtered film. In Embodiment 32, a chemical plating layer 3128 on which an electrolytic plating layer 3129 is stacked is formed on the bottom surface of the opening portion 3124. A through-hole 3112 embedded in the semiconductor substrate 111 is formed below the chemical plating layer 3128, and the through-hole includes a plating film and a sputtered film thereon.

[0541] Figure 71 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 32.

[0542] In this figure, the electronic device includes a through-hole 3212 or wiring 3212 (hereinafter referred to as through-hole 3212 for simplicity) instead of Figure 70 Through hole 3112 in the middle. Other configurations of this electronic device are similar to... Figure 70 The configurations of the electronic devices in the two systems are similar.

[0543] A through-hole 3212 is embedded in a recess 3111. An insulating layer 3113 is formed between the recess 3111 and the through-hole 3112. The through-hole 3212 can be formed using a deposited film 3212A and a sputtered film 3212B thereon. For example, Cu can be used as the material for the deposited film 3212A and the sputtered film 3212B. Here, by using the deposited film 3212A and the sputtered film 3212B to form the through-hole 3112, the embedding performance in the recess 3111 can be improved while using the sputtered film 3212B as a seed layer.

[0544] Furthermore, via 3212 can be provided on wiring layer 112. In this case, via 3212 can protrude from wiring layer 112. Via 3212 can be electrically connected to wiring 113.

[0545] In this manner, in embodiment 32 described above, a chemical plating layer 3128 on which an electrolytic plating layer 3129 is stacked is formed on the bottom surface of the opening portion 3124, and a through-hole 3212 embedded in the semiconductor substrate 111 is formed below the chemical plating layer 3128. The through-hole 3212 is composed of a plating film 3212A and a sputtered film 3212B thereon. Therefore, the depth of the through electrode TV31 can be less than the thickness of the semiconductor substrate 111, and the filling performance of the electrolytic plating layer 3129 can be improved. Thus, the miniaturization of the through electrode TV31 can be achieved while reducing open-circuit defects.

[0546] <33. Example 33>

[0547] In Embodiment 31 described above, a chemical plating layer 3128 on which an electrolytic plating layer 3129 is stacked is provided on the bottom surface of the opening portion 3124, and a through hole 3112 embedded in the semiconductor substrate 111 is formed below the chemical plating layer 3128, and the through hole 3112 is formed using a sputtered film. In Embodiment 33, a chemical plating layer on which an electrolytic plating layer is stacked is provided on the bottom surface of the opening portion, and wiring embedded in the semiconductor substrate is formed below the chemical plating layer.

[0548] Figure 72 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 33.

[0549] In this figure, a recess 3311 is formed in a semiconductor substrate 111. Wiring or vias 3312 and 3314 (hereinafter referred to as wirings 3312 and 3314 for simplicity) are embedded in the recess 3311. Wiring 3314 is stacked on wiring 3312. In this case, the width of wiring 3314 may be smaller than the width of wiring 3312. Furthermore, an insulating layer 3313 may be formed between the recess 3311 and wiring 3314 to insulate the semiconductor substrate 111 from wiring 3314. Wiring 3312 may include a CVD film. Wiring 3314 may include a sputtered film. For example, W can be used as the material for wiring 3312. For example, Cu can be used as the material for wiring 3314. For example, Ru can be used as the material for wiring 3312. By using Ru as the material for wiring 3312, the embedding performance of wiring 3312 can be improved, and by stacking wiring 3314 including Cu on wiring 3312, conductivity can be improved. Wiring 3312 and 3314 can be used, for example, in a rear surface power delivery network (PDN).

[0550] Wiring layer 112 is formed on semiconductor substrate 111. Wiring 3312 and 3314 may be disposed on wiring layer 112. In this case, wiring 3312 and 3314 may protrude from above wiring layer 112. Wiring 3312 and 3314 may be electrically connected to wiring 113.

[0551] Furthermore, an opening 3324 is formed in the semiconductor substrate 111. The opening 3324 may be disposed below the recess 3311. The opening 3324 penetrates the semiconductor substrate 111 and can reach wirings 3312 and 3314. The opening 3324 may have a shape that widens towards the bottom surface.

[0552] An insulating layer 3325 is formed on the inner surface of the opening 3324. The insulating layer 3325 can be continuously formed from the side surface of the opening 3324 to the rear surface of the semiconductor substrate 111.

[0553] A through electrode TV33 is formed in the opening portion 3324 via an insulating layer 3325. The through electrode TV33 is disposed on wirings 3312 and 3314. In this case, the through electrode TV33 can be electrically connected to wirings 3312 and 3314. The through electrode TV33 includes a chemical plating layer 3328, a sputtering layer 3326, and an electrolytic plating layer 3329.

[0554] A chemical plating layer 3328 is formed on wirings 3312 and 3314 in the opening portion 3324. In this case, the chemical plating layer 3328 can be electrically connected to wirings 3312 and 3314.

[0555] The sputtered layer 3326 can be formed on the side surface of the opening 3324 and the rear surface of the semiconductor substrate 111 via the insulating layer 3325. The sputtered layer 3326 can be used as a seed layer for forming the electrolytic plating layer 3329.

[0556] An electrolytic plating layer 3329 is formed on the electroless plating layer 3328 and the sputtering layer 3326. The electrolytic plating layer 3329 can be continuously formed on the electroless plating layer 3328 to extend via the sputtering layer 3326 to the side surface of the opening portion 3324 and the rear surface of the semiconductor substrate 111. The sputtering layer 3326 and the electrolytic plating layer 3329 are formed to follow the shape of the opening portion 3324 in the depth direction. In this case, the sputtering layer 3326 and the electrolytic plating layer 3329 can have a widened shape in the depth direction of the opening portion 3324.

[0557] In this manner, in embodiment 33 described above, a chemical plating layer 3328 on which an electrolytic plating layer 3329 is stacked is formed on the bottom surface of the opening portion 3324, and wirings 3312 and 3314 embedded in the semiconductor substrate 111 are formed below the chemical plating layer 3328. Therefore, the depth of the through electrode TV33 can be less than the thickness of the semiconductor substrate 111, improving the embedding performance of the electrolytic plating layer 3329 and reducing wiring resistance without increasing the planar dimensions of the wiring layer 112. Thus, miniaturization of the through electrode TV33 can be achieved while reducing open-circuit defects, and the potential of the electronic device can be stabilized during operation.

[0558] <34. Example 34>

[0559] In embodiment 29 described above, the following structure is adopted: the chemical plating layer 2818 is embedded in the wiring layer 2812 disposed below the opening portion 114, and the wiring 2813 disposed below the chemical plating layer 2818 is not provided. In embodiment 34, the chemical plating layer 2818 is embedded in the wiring layer 2812 disposed below the opening portion 114, so that the chemical plating layer 2818 protrudes into the opening portion 114, and the wiring 2813 in contact with the lower part of the chemical plating layer 2818 is removed.

[0560] Figure 73 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 34.

[0561] In this figure, the electronic device includes a through electrode TV34, replacing... Figure 55 The through-electrode TV28. Other configurations of this electronic device are similar to... Figure 55 The configuration of electronic devices in the system.

[0562] The through electrode TV34 includes a chemical plating layer 3418, a barrier metal layer 3420, a sputtering layer 3416, and an electrolytic plating layer 3419.

[0563] The chemical plating layer 3418 is embedded within the recess KA. In this case, the chemical plating layer 3418 can be electrically connected to the guard ring GR. The chemical plating layer 3418 protrudes into the opening 114. The lower surface of the chemical plating layer 3418 can be located below the surface of the semiconductor substrate 111. Note that the surface of the semiconductor substrate 111 is the interface between the semiconductor substrate 111 and the insulating layer 2815. The lower surface of the chemical plating layer 3418 can be located below the lower surface of the wiring layer 2812. Note that the lower surface of the wiring layer 2812 is the interface between the wiring layer 2812 and the insulating layer 2814.

[0564] A barrier metal layer 3420 is stacked on the electroless plating layer 3418. In this case, the barrier metal layer 3420 can be continuously formed on the electroless plating layer 3418 to extend through the side surface of the insulating layer 115 to the upper surface of the insulating layer 115.

[0565] The sputtered layer 3416 is stacked on the barrier metal layer 3420. In this case, the sputtered layer 3416 can be formed on the chemical plating layer 3418 to extend through the barrier metal layer 3420 to the side surface of the opening 114 and the rear surface of the semiconductor substrate 111.

[0566] An electrolytic plating layer 3419 is formed on a sputtering layer 3416. The electrolytic plating layer 3419 may be continuously formed on a chemical plating layer 3418 to extend via the sputtering layer 3416 to the side surface of the opening portion 114 and the rear surface of the semiconductor substrate 111.

[0567] Thus, in the above embodiment 34, the following structure is adopted: the chemical plating layer 3418 is embedded in the wiring layer 2812 disposed below the opening portion 114, so that the chemical plating layer 3418 protrudes into the opening portion 114, and no wiring 2813 is disposed below the chemical plating layer 3418. Therefore, the depth of the through electrode TV34 can be less than the thickness of the semiconductor substrate 111, and the filling performance of the electrolytic plating layer 3419 can be improved. In this way, while achieving miniaturization of the through electrode TV34, open circuit defects (step coverage faults) can be reduced, and stress can be alleviated.

[0568] It should be noted that the manufacturing method of Example 34 can be applied Figures 56 to 61 The steps are similar to the manufacturing method of Embodiment 28 described above. In this case, in Figure 60 In the process, the chemical plating layer 3418 can be made to protrude into the opening portion 114.

[0569] <35. Example 35>

[0570] Thus, in embodiment 34, the following structure is adopted: the chemical plating layer 3418 is embedded in the wiring layer 2812 disposed below the opening portion 114, so that the chemical plating layer 3418 protrudes into the opening portion 114, and no wiring 2813 is disposed below the chemical plating layer 3418. In embodiment 35, the chemical plating layer 3418 is embedded in the wiring layer 2812 disposed below the opening portion 114, so that the chemical plating layer 3418 protrudes into the opening portion 114, and the wiring 2813 is disposed below the chemical plating layer 3418.

[0571] Figure 74 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 35.

[0572] In the same figure, the electronic device includes wiring layer 2912, instead of Figure 55 Wiring layer 2812 is used. Here, the through electrode TV34 penetrates the semiconductor substrate 111 and connects to wiring layer 2912. In this case, the bottom surface of the chemical plating layer 3418 can be in contact with wiring 2913. Other configurations of this electronic device are similar. Figure 55 The configuration of electronic devices in the system.

[0573] Thus, in the above embodiment 35, the chemical plating layer 3418 is embedded in the wiring layer 2812 disposed below the opening portion 114, causing the chemical plating layer 3418 to protrude into the opening portion 114, and the wiring 2813 is disposed below the chemical plating layer 3418. Therefore, the depth of the through electrode TV34 can be less than the thickness of the semiconductor substrate 111, which can improve the embedding performance of the electrolytic plating layer 3419 and reduce the contact resistance between the through electrode TV34 and the wiring layer 2912. In this way, while achieving miniaturization of the through electrode TV34, open circuit defects can be reduced, and EM tolerance can be improved while reducing stress.

[0574] It should be noted that the manufacturing method of Example 35 can be applied Figures 63 to 68 The steps are similar to the manufacturing method of Embodiment 29 described above. In this case, in Figure 67 In the process, the chemical plating layer 3418 can be made to protrude into the opening portion 114.

[0575] <36. Example 36>

[0576] Thus, in embodiment 34, the following structure is adopted: the chemical plating layer 3418 is embedded in the wiring layer 2812 disposed below the opening portion 114, so that the chemical plating layer 3418 protrudes into the opening portion 114, and no wiring 2813 is disposed in contact with the lower part of the chemical plating layer 3418. In embodiment 36, the chemical plating layer is embedded in the wiring layer 2812 disposed below the opening portion 124 which widens in the depth direction, so that the chemical plating layer protrudes into the opening portion 124, and the wiring 2813 in contact with the lower part of the chemical plating layer is removed.

[0577] Figure 75 This is a cross-sectional view showing an example configuration of an electronic device according to Embodiment 36.

[0578] In the same figure, the electronic device includes a through electrode TV36, replacing... Figure 69 The through electrode TV30. Other configurations of this electronic device are similar. Figure 69 The configuration of electronic devices in the system.

[0579] The through electrode TV36 includes a chemical plating layer 3628, a barrier metal layer 3620, a sputtering layer 3626, and an electrolytic plating layer 3629.

[0580] The chemical plating layer 3628 is embedded within the recess KA. In this case, the chemical plating layer 3628 can be electrically connected to the guard ring GR. The chemical plating layer 3628 protrudes into the opening portion 124. In this case, the lower surface of the chemical plating layer 3628 can be located below the surface of the semiconductor substrate 111. Furthermore, the lower surface of the chemical plating layer 3628 can be located below the lower surface of the wiring layer 2812.

[0581] A barrier metal layer 3620 is stacked on the electroless plating layer 3628. In this case, the barrier metal layer 3620 can be continuously formed on the electroless plating layer 3628 to extend through the side surface of the insulating layer 125 to the upper surface of the insulating layer 125.

[0582] The sputtered layer 3626 is stacked on the barrier metal layer 3620. In this case, the sputtered layer 3626 can be formed on the chemical plating layer 3628 to extend through the barrier metal layer 3620 to the side surface of the opening 124 and the rear surface of the semiconductor substrate 111.

[0583] An electrolytic plating layer 3629 is formed on a sputtering layer 3626. In this case, the electrolytic plating layer 3629 can be continuously formed on a chemical plating layer 3628 to extend via the sputtering layer 3626 to the side surface of the opening portion 124 and the rear surface of the semiconductor substrate 111.

[0584] Thus, in the above embodiment 36, the following structure is adopted: the chemical plating layer 3628 is embedded in the wiring layer 2812 disposed below the opening portion 124 which widens in the depth direction, so that the chemical plating layer 3628 protrudes into the opening portion 124, and no wiring 2813 is disposed in contact with the bottom of the chemical plating layer 3628. Therefore, the depth of the through electrode TV36 can be less than the thickness of the semiconductor substrate 111, and the filling performance of the electrolytic plating layer 3629 can be improved. In this way, while achieving miniaturization of the through electrode TV36, open circuit defects (step coverage faults) can be reduced, and stress can be alleviated.

[0585] It should be noted that in the above embodiment 36, an example of the chemical plating layer 3628 being embedded in the wiring layer 2812 has been described; however, the chemical plating layer 3628 can be embedded in the wiring layer 2912 of the above embodiment 35.

[0586] <37. Examples of application to moving objects>

[0587] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can also be implemented as a device installed in any type of mobile body (such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, and robots).

[0588] Figure 76 This is a block diagram illustrating a schematic configuration example of a vehicle control system (which is an example of a mobile body control system to which the technology according to this disclosure can be applied).

[0589] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 76 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Additionally, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown as functional configurations of the integrated control unit 12050.

[0590] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for drive force generating devices (such as internal combustion engines, drive motors, etc.) that generate vehicle driving force, drive force transmission mechanisms that transmit driving force to the wheels, steering mechanisms that adjust the vehicle's steering angle, and braking devices that generate vehicle braking force.

[0591] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, rearview lights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches sent from a mobile device that serves as a substitute key can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0592] The exterior information detection unit 12030 detects information about the exterior of the vehicle, including the vehicle control system 12000. For example, the exterior information detection unit 12030 is connected to a camera unit 12031. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform processing such as detecting objects like people, vehicles, obstacles, signs, characters on the road surface, etc., or detecting their distance.

[0593] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output the electrical signal as an image, or it can output the electrical signal as information about the measured distance. Furthermore, the light received by the camera unit 12031 can be visible light or invisible light, such as infrared light.

[0594] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or the driver's level of concentration, or it can determine whether the driver is drowsy.

[0595] The microcomputer 12051 can calculate target control values ​​for the drive force generation device, steering mechanism, or braking device based on information about the exterior or interior of the vehicle obtained by the exterior information detection unit 12030 or the interior information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, distance-based following, speed maintenance, collision warning, lane departure warning, etc.

[0596] In addition, the microcomputer 12051 can control the drive force generation device, steering mechanism, braking device, etc., based on information about the exterior or interior of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040 to perform cooperative control aimed at achieving automation, which enables the vehicle to drive autonomously without relying on the driver's operation.

[0597] Additionally, the microcomputer 12051 can output control commands to the body system control unit 12020 based on information about the vehicle's exterior obtained from the exterior information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to switch from high beam to low beam (e.g., based on the position of the vehicle in front or oncoming vehicles detected by the exterior information detection unit 12030).

[0598] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or audibly notifying the occupants of the vehicle or the exterior of the vehicle. Figure 76 In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. The display unit 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0599] Figure 77 This is a view showing an example of the mounting location of the camera unit 12031.

[0600] exist Figure 77 In this, camera units 12101, 12102, 12103, 12104 and 12105 are included as camera unit 12031.

[0601] Cameras 12101, 12102, 12103, 12104, and 12105 are installed, for example, at the front end, side mirrors, rear bumper, and rear door of vehicle 12100, and at the upper part of the windshield inside the vehicle. Camera 12101 at the front end and camera 12105 at the upper part of the windshield inside the vehicle primarily acquire images of the front of vehicle 12100. Cameras 12102 and 12103 on the side mirrors primarily acquire images of the sides of vehicle 12100. Camera 12104 on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Camera 12105 at the upper part of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0602] It should be noted that, Figure 77Examples of the shooting ranges of camera units 12101 to 12104 are shown. Shooting range 12111 represents the shooting range of camera unit 12101 located at the front end. Shooting ranges 12112 and 12113 represent the shooting ranges of camera units 12102 and 12103 located on the side mirrors, respectively. Shooting range 12114 represents the shooting range of camera unit 12104 located on the rear bumper or rear door. For example, a bird's-eye view of vehicle 12100 viewed from above can be obtained by overlaying image data captured by camera units 12101 to 12104.

[0603] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0604] For example, the microcomputer 12051 can determine the distance and its time-varying distance (relative speed to the vehicle 12100) of each three-dimensional object within the shooting range 12111 to 12114 based on distance information obtained from the camera units 12101 to 12104. This allows it to extract the nearest three-dimensional object that is specifically present on the travel path of the vehicle 12100 and is traveling at a predetermined speed (e.g., equal to or greater than 0 km / h) in approximately the same direction as the vehicle 12100. Furthermore, the microcomputer 12051 can preset a following distance to be maintained in front of the vehicle and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Therefore, cooperative control aimed at enabling the vehicle to drive autonomously without relying on driver operation can be performed.

[0605] For example, microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that can be visually recognized by the driver of vehicle 12100 and obstacles that are difficult for the driver of vehicle 12100 to visually recognize. Then, microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and there is therefore a possibility of collision, microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and performs forced deceleration or evasive steering via drive system control unit 12010. Thus, microcomputer 12051 can assist driving to avoid collisions.

[0606] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. The microcomputer 12051 can, for example, identify a pedestrian by determining whether a pedestrian exists in the image captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, through a process of extracting feature points from the image captured by the imaging units 12101 to 12104 (which are infrared cameras) and a process of determining whether an object is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the image captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that an emphasized square outline is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 so that an icon representing the pedestrian, etc., is displayed at a desired location.

[0607] Examples of vehicle control systems that can be applied according to the technology disclosed herein have been described above. The technology according to this disclosure can be applied to the drive system control unit 12010, body system control unit 12020, external information detection unit 12030, internal information detection unit 12040, integrated control unit 12050, and imaging unit 12031 in the above configuration. Specifically, the electronic devices of the above embodiments can be applied to, for example, the drive system control unit 12010, body system control unit 12020, external information detection unit 12030, internal information detection unit 12040, integrated control unit 12050, and imaging unit 12031. By applying the technology according to this disclosure to the vehicle control system 12000, open-circuit defects can be reduced while miniaturizing the through electrodes and capacitors of the electronic devices.

[0608] Note that the above embodiments are examples illustrating the present technology, and the various aspects in the embodiments correspond to the various aspects of the invention as defined in the claims. Similarly, the various aspects of the invention as defined in the claims correspond to the aspects of the same name in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and various modifications can be made to embody the embodiments without departing from the spirit of the present technology. Furthermore, the effects described in this specification are merely illustrative and not restrictive, and other effects may also occur.

[0609] Note that this technology can also have the following configurations.

[0610] (1) An electronic device, comprising:

[0611] An opening portion having an insulating inner surface; and

[0612] Electrodes formed on the inner surface of the opening, wherein,

[0613] The electrode includes a metal stack in which metals with different compositions or microstructures are stacked on the bottom surface of the opening.

[0614] (2) The electronic device according to (1), wherein,

[0615] The metal stack, on which the metal is stacked, is located on the bottom surface of the opening and the side surface of the opening.

[0616] (3) The electronic device according to (1) or (2), wherein,

[0617] Each microstructure is a grain size.

[0618] (4) The electronic device according to any one of (1) to (3) further comprises:

[0619] A wiring layer disposed below the opening portion, the wiring layer having wiring electrically connected to the electrode.

[0620] (5) The electronic device according to (4), wherein,

[0621] At least a portion of the metal stack is embedded in the wiring layer.

[0622] (6) The electronic device according to (5), wherein,

[0623] The metal stack includes a chemical plating layer embedded in the wiring layer.

[0624] (7) The electronic device according to any one of (4) to (6), wherein,

[0625] In the wiring layer, there are no wirings that contact the lower surface of the metal stack.

[0626] (8) The electronic device according to any one of (4) to (6), wherein,

[0627] In the wiring layer, there are wirings that are in contact with the lower surface of the metal stack.

[0628] (9) The electronic device according to any one of (4) to (8), wherein,

[0629] A portion of the wiring serves as a protective ring around the metal stack.

[0630] (10) The electronic device according to any one of (4) to (9), wherein,

[0631] The metal stack protrudes above the wiring layer.

[0632] (11) The electronic device according to any one of (1) to (10) further comprises:

[0633] The semiconductor substrate in which the opening portion is formed.

[0634] (12) The electronic device according to (11), wherein,

[0635] The bottom surface of the metal stack is located below the lower surface of the semiconductor substrate.

[0636] (13) The electronic device according to (11) or (12), wherein,

[0637] The top surface of the metal stack is located above the lower surface of the semiconductor substrate.

[0638] (14) The electronic device according to any one of (1) to (10) further comprises:

[0639] Through-holes or embedded wirings are disposed below the opening and embedded in the semiconductor substrate.

[0640] (15) The electronic device according to (14), wherein the through-hole or the embedded wiring comprises:

[0641] The sputtered film formed beneath the metal stack, and

[0642] A coating or chemical vapor deposition (CVD) film formed beneath the sputtered film.

[0643] (16) The electronic device according to any one of (1) to (15), wherein the metal stack comprises:

[0644] Chemical plating;

[0645] The sputtered layer stacked on the chemical plating layer; and

[0646] An electroplated layer stacked on the sputtered layer.

[0647] (17) The electronic device according to any one of (1) to (15), wherein the metal stack comprises:

[0648] Sputtered layer;

[0649] The chemical plating layer stacked on the sputtered layer; and

[0650] An electrolytic plating layer stacked on top of the chemical plating layer.

[0651] (18) The electronic device according to (17), wherein,

[0652] The chemical plating layer is selectively formed on the bottom surface of the opening via the sputtering layer.

[0653] (19) The electronic device according to (17), wherein,

[0654] The chemical plating layer is selectively formed on the bottom surface of the opening and the side surface of the opening via the sputtering layer.

[0655] (20) The electronic device according to any one of (17) to (19), wherein,

[0656] The sputtered layer on the bottom surface of the opening and the sputtered layer on the side surface of the opening are separated from each other, and

[0657] The chemical plating layer is connected to the sputtered layer on the side surface of the opening portion via the electrolytic plating layer.

[0658] (21) The electronic device according to any one of (17) to (20) further comprises:

[0659] Wiring extending from the opening and connected to the electrode, wherein...

[0660] The wiring includes:

[0661] The sputtered layer; and

[0662] An electroplated layer stacked on the sputtered layer.

[0663] (22) The electronic device according to any one of (1) to (21), wherein,

[0664] The diameter of the bottom surface of the opening is greater than the diameter of the opening surface of the opening.

[0665] (23) The electronic device according to any one of (1) to (22) further includes:

[0666] A first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate;

[0667] A second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate, and the second semiconductor chip is stacked on the first semiconductor chip with the second wiring layer facing the first wiring layer; and

[0668] A through electrode is formed therein, the through electrode penetrating the first semiconductor chip and connected to the second wiring layer.

[0669] (24) The electronic device according to any one of (1) to (22) further includes:

[0670] A first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate;

[0671] A second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate, and the second semiconductor chip is stacked on the first semiconductor chip such that the second wiring layer faces the first wiring layer; and

[0672] A through electrode is formed therein, the through electrode penetrating a first semiconductor substrate and connected to a first wiring layer.

[0673] (25) The electronic device according to any one of (1) to (22) further comprises:

[0674] A first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate;

[0675] The second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate, and the second semiconductor chip is stacked on a first semiconductor chip such that the second wiring layer faces the first wiring layer;

[0676] An embedding layer is formed on a first semiconductor chip to embed a second semiconductor chip;

[0677] A third semiconductor chip, wherein a third wiring layer is formed on a third semiconductor substrate, and the third semiconductor chip is stacked on an embedding layer; and

[0678] A through electrode is formed therein, the through electrode penetrating a third semiconductor chip and a second semiconductor chip and being connected to a first wiring layer.

[0679] (26) The electronic device according to any one of (1) to (22) further comprises:

[0680] A first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate;

[0681] The second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate, and the second semiconductor chip is stacked on a first semiconductor chip such that the second wiring layer faces the first wiring layer;

[0682] An embedding layer is formed on a first semiconductor chip to embed a second semiconductor chip;

[0683] A third semiconductor chip, wherein a third wiring layer is formed on a third semiconductor substrate, and the third semiconductor chip is stacked on an embedding layer; and

[0684] A through electrode is formed therein, the through electrode penetrating the third semiconductor chip and the embedding layer and connecting to the first wiring layer.

[0685] (27) The electronic device according to any one of (1) to (26) further includes

[0686] A capacitor located in the opening and formed on the electrode.

[0687] (28) The electronic device according to (27), wherein the capacitor includes

[0688] The first capacitor electrode formed on the electrode, and

[0689] A second capacitor electrode is formed on the first capacitor electrode via a dielectric layer.

[0690] (29) The electronic device according to (27), wherein the capacitor includes

[0691] Also used as the first capacitor electrode, and

[0692] A second capacitor electrode is formed on the first capacitor electrode via a dielectric layer.

[0693] (30) The electronic device according to any one of (27) to (29) further includes

[0694] An insulating layer is formed on the capacitor through the cavity in the opening.

[0695] (31) The electronic device according to any one of (27) to (30) further includes

[0696] An embedding layer is formed on the capacitor to be embedded in the opening portion.

[0697] (32) The electronic device according to any one of (1) to (31) further includes

[0698] A photosensitive insulating film embedded in the skirt portion of the bottom surface of the opening.

[0699] (33) The electronic device according to any one of (1) to (32), wherein the electrodes include a barrier metal layer.

[0700] (34) The electronic device according to (33) wherein the blocking metal layer comprises an atomic layer deposition (ALD) film.

[0701] (35) The electronic device according to (32) or (33), wherein

[0702] The barrier metal layer includes at least one of Ti, TiN, Ta, TaN, Ru, and RuN.

[0703] (36) The electronic device according to any one of (1) to (35), wherein

[0704] The electrode includes a cobalt-containing chemical plating layer.

[0705] (37) The electronic device according to any one of (1) to (36), wherein the metal stack comprises

[0706] Seed layer,

[0707] A first chemical plating layer stacked on the seed layer and separated from the inner circumferential surface of the opening.

[0708] A second chemical plating layer is formed around the first chemical plating layer, and

[0709] An electrolytic plating layer is formed on the second chemical plating layer.

[0710] (38) The electronic device according to any one of (1) to (37), wherein

[0711] The opening includes multiple skirt sections located at different positions in the depth direction.

[0712] (39) The electronic device according to any one of (1) to (38) further includes

[0713] A separation of the implanted oxygen (SIMOX) layer is set at the midpoint of the depth direction of the opening to surround the opening.

[0714] (40) A method of manufacturing an electronic device, the method comprising:

[0715] The step of forming a sputtered layer on the inner surface of the opening;

[0716] The step of forming an insulating layer on the sputtered layer;

[0717] The step of removing the insulating layer on the sputtered layer on the bottom surface of the opening portion;

[0718] The step of forming a chemical plating layer on the sputtered layer on the bottom surface of the opening;

[0719] The step of removing the insulating layer from the opening after the formation of the chemical plating layer; and

[0720] The step of forming an electrolytic plating layer on a sputtered layer and a chemical plating layer.

[0721] (41) The method of manufacturing an electronic device according to (40), wherein

[0722] The sputtered layer on the side surface of the opening is separate from the sputtered layer and chemical plating layer on the bottom surface of the opening, and

[0723] The chemical plating layer is attached to the sputtered layer on the side surface of the opening via an electrolytic plating layer.

[0724] (42) The method of manufacturing an electronic device according to (40) or (41) further includes

[0725] The step of embedding a photosensitive insulating film in the skirt portion of the bottom surface of the opening portion before forming the sputtered layer.

[0726] (43) The method of manufacturing an electronic device according to any one of (40) to (42) further includes

[0727] After the insulating layer in the opening is removed following the formation of the chemical plating layer, the area where the insulating layer has been removed is re-embedded by chemical plating.

[0728] (44) A method of manufacturing an electronic device according to any one of (40) to (43), wherein

[0729] The etching used to form the opening was performed multiple times.

[0730] (45) The method of manufacturing an electronic device according to any one of (40) to (44) further comprises:

[0731] The step of forming a SIMOX layer in the substrate where the opening is to be formed; and

[0732] The step of forming an opening in the substrate by etching at the location of the SIMOX layer. Attached Figure Description

[0734] TV1 Through Electrode

[0735] MT1 Metal Stacking Section

[0736] 111 Semiconductor substrate

[0737] 112 Wiring Layer

[0738] 113 Wiring

[0739] 114 Opening section

[0740] Insulation layers 115 and 117

[0741] 116 sputtering layer

[0742] 118 Chemical plating

[0743] 119 Electrolytic plating

Claims

1. An electronic device, comprising: An opening portion having an insulating inner surface; as well as Electrodes formed on the inner surface of the opening, wherein The electrode includes a metal stack in which metals with different compositions or microstructures are stacked on the bottom surface of the opening.

2. The electronic device according to claim 1, wherein The metal stack, on which the metal is stacked, is located on the bottom surface of the opening and the side surface of the opening.

3. The electronic device according to claim 1, wherein Each microstructure is a grain size.

4. The electronic device of claim 1, wherein the metal stack comprises sputtered layer, The chemical plating layer stacked on the sputtered layer, and An electrolytic plating layer stacked on top of the chemical plating layer.

5. The electronic device according to claim 4, wherein The chemical plating layer is selectively formed on the bottom surface of the opening via the sputtering layer.

6. The electronic device according to claim 4, wherein The chemical plating layer is selectively formed on the bottom surface of the opening and the side surface of the opening via the sputtering layer.

7. The electronic device according to claim 4, wherein... The sputtered layer on the bottom surface of the opening and the sputtered layer on the side surface of the opening are separated from each other, and The chemical plating layer is connected to the sputtered layer on the side surface of the opening via the electrolytic plating layer.

8. The electronic device according to claim 4, further comprising: Wiring extending from the opening and connected to the electrode, wherein The wiring includes the sputtered layer and an electroplated layer stacked on the sputtered layer.

9. The electronic device according to claim 1, wherein The diameter of the bottom surface of the opening is larger than the diameter of the opening surface of the opening.

10. The electronic device according to claim 1, further comprising: A first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate; A second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate such that the second semiconductor chip is stacked on a first semiconductor chip such that the second wiring layer faces the first wiring layer; and Through electrode, wherein an electrode is formed, the through electrode penetrates the first semiconductor chip and is connected to the second wiring layer.

11. The electronic device according to claim 1, further comprising: A first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate; A second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate such that the second semiconductor chip is stacked on a first semiconductor chip such that the second wiring layer faces the first wiring layer; and A through electrode is formed therein, the through electrode penetrates the first semiconductor substrate and is connected to the first wiring layer.

12. The electronic device according to claim 1, further comprising: A first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate; The second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate, and the second semiconductor chip is stacked on a first semiconductor chip such that the second wiring layer faces the first wiring layer. An embedding layer is formed on the first semiconductor chip to embed the second semiconductor chip; A third semiconductor chip, wherein a third wiring layer is formed on a third semiconductor substrate, and the third semiconductor chip is stacked on an embedding layer; as well as Through electrode, wherein an electrode is formed, the through electrode penetrates the third semiconductor chip and the second semiconductor chip and is connected to the first wiring layer.

13. The electronic device according to claim 1, further comprising: A first semiconductor chip, wherein a first wiring layer is formed on a first semiconductor substrate; The second semiconductor chip, wherein a second wiring layer is formed on a second semiconductor substrate, and the second semiconductor chip is stacked on a first semiconductor chip such that the second wiring layer faces the first wiring layer. An embedding layer is formed on the first semiconductor chip to embed the second semiconductor chip; A third semiconductor chip, wherein a third wiring layer is formed on a third semiconductor substrate, and the third semiconductor chip is stacked on an embedding layer; as well as Through electrode, wherein an electrode is formed, the through electrode penetrates the third semiconductor chip and the embedding layer and is connected to the first wiring layer.

14. The electronic device of claim 1, further comprising: A capacitor, located in an open portion and formed on electrodes.

15. The electronic device according to claim 14, wherein, Capacitors include The first capacitor electrode formed on the electrode, and A second capacitor electrode is formed on the first capacitor electrode through a dielectric layer.

16. The electronic device according to claim 14, wherein, Capacitors include Also used as the first capacitor electrode, and A second capacitor electrode is formed on the first capacitor electrode via a dielectric layer.

17. The electronic device of claim 14, further comprising: An insulating layer is formed on the capacitor through a cavity in the opening.

18. The electronic device of claim 14, further comprising: An embedded layer is formed on the capacitor to be embedded in the opening portion.

19. A method of manufacturing an electronic device, the method comprising: The step of forming a sputtered layer on the inner surface of the opening; The step of forming an insulating layer on the sputtered layer; The step of removing the insulating layer on the sputtered layer on the bottom surface of the opening portion; The step of forming a chemical plating layer on the sputtered layer on the bottom surface of the opening; The step of removing the insulating layer from the opening after the chemical plating layer has been formed; as well as The step of forming an electrolytic plating layer on a sputtered layer and a chemical plating layer.

20. The method of manufacturing an electronic device according to claim 19, wherein... The sputtered layer on the side surface of the opening is separated from the sputtered layer and chemical plating layer on the bottom surface of the opening, and The chemical plating layer is attached to the sputtered layer on the side surface of the opening via electrolytic plating.

Images